Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48342	1			T2	124		T8	284		T9	104
access_err	62270	1			T1	96		T2	4		T3	26
write_blank_err	454	1			T6	9		T13	3		T14	2
ecc_uncorr_err	70126	1			T10	6		T12	505		T101	117
ecc_corr_err	1398	1			T10	2		T12	8		T101	11
no_err	90073	1			T1	136		T2	20		T3	20

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	663	1			T6	11		T13	4		T14	6
secret2	26816	1			T1	14		T2	1		T3	2
secret1	27972	1			T1	23		T2	6		T3	9
secret0	37280	1			T1	13		T3	3		T4	6
hw_cfg1	37027	1			T1	14		T4	11		T5	11
hw_cfg0	25289	1			T1	31		T2	4		T3	5
rot_creator_auth_state	21747	1			T1	10		T2	3		T3	2
rot_creator_auth_codesign	21601	1			T1	27		T2	4		T3	9
owner_sw_cfg	20813	1			T1	21		T3	4		T4	3
creator_sw_cfg	20278	1			T1	32		T2	1		T3	8
vendor_test	33177	1			T1	47		T2	129		T3	4

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3545	1			T9	104		T190	517		T205	90
fsm_err	secret1	3124	1			T200	247		T324	1		T325	224
fsm_err	secret0	4412	1			T159	168		T326	36		T327	237
fsm_err	hw_cfg1	4365	1			T16	193		T217	118		T248	126
fsm_err	hw_cfg0	3462	1			T16	45		T218	192		T208	82
fsm_err	rot_creator_auth_state	3844	1			T158	376		T84	419		T328	301
fsm_err	rot_creator_auth_codesign	3335	1			T100	252		T191	36		T145	2
fsm_err	owner_sw_cfg	3635	1			T102	9		T124	149		T329	29
fsm_err	creator_sw_cfg	3092	1			T12	75		T101	71		T102	9
fsm_err	vendor_test	15528	1			T2	124		T8	284		T12	75
access_err	life_cycle	663	1			T6	11		T13	4		T14	6
access_err	secret2	10902	1			T1	12		T2	1		T3	1
access_err	secret1	6025	1			T1	13		T3	4		T9	121
access_err	secret0	4656	1			T1	7		T3	3		T9	63
access_err	hw_cfg1	1226	1			T1	3		T9	7		T97	1
access_err	hw_cfg0	2275	1			T1	15		T2	2		T9	54
access_err	rot_creator_auth_state	5873	1			T1	3		T3	2		T5	6
access_err	rot_creator_auth_codesign	8222	1			T1	12		T3	8		T5	10
access_err	owner_sw_cfg	7189	1			T1	5		T5	10		T9	110
access_err	creator_sw_cfg	7680	1			T1	16		T2	1		T3	5
access_err	vendor_test	7559	1			T1	10		T3	3		T5	7
write_blank_err	secret2	18	1			T140	1		T122	1		T241	1
write_blank_err	secret1	22	1			T96	1		T225	1		T312	1
write_blank_err	secret0	44	1			T6	2		T248	1		T224	1
write_blank_err	hw_cfg1	79	1			T6	1		T13	3		T14	1
write_blank_err	hw_cfg0	26	1			T141	1		T330	2		T331	1
write_blank_err	rot_creator_auth_state	145	1			T6	4		T96	2		T224	2
write_blank_err	rot_creator_auth_codesign	55	1			T141	3		T19	4		T302	1
write_blank_err	owner_sw_cfg	23	1			T6	2		T241	1		T332	3
write_blank_err	creator_sw_cfg	13	1			T141	1		T333	1		T233	1
write_blank_err	vendor_test	29	1			T14	1		T334	2		T335	1
ecc_uncorr_err	secret2	6897	1			T140	319		T122	234		T153	9
ecc_uncorr_err	secret1	9475	1			T10	6		T12	75		T102	5
ecc_uncorr_err	secret0	19513	1			T12	74		T102	17		T6	702
ecc_uncorr_err	hw_cfg1	20676	1			T102	4		T13	461		T14	105
ecc_uncorr_err	hw_cfg0	7370	1			T12	74		T87	53		T141	212
ecc_uncorr_err	rot_creator_auth_state	3195	1			T12	71		T87	48		T225	27
ecc_uncorr_err	rot_creator_auth_codesign	941	1			T12	68		T101	44		T102	11
ecc_uncorr_err	owner_sw_cfg	1001	1			T12	73		T101	73		T102	9
ecc_uncorr_err	creator_sw_cfg	1058	1			T12	70		T87	44		T183	57
ecc_corr_err	secret2	73	1			T62	2		T129	2		T174	1
ecc_corr_err	secret1	150	1			T101	2		T62	5		T87	1
ecc_corr_err	secret0	143	1			T101	1		T62	3		T87	1
ecc_corr_err	hw_cfg1	292	1			T101	1		T62	1		T6	1
ecc_corr_err	hw_cfg0	264	1			T10	1		T12	1		T101	3
ecc_corr_err	rot_creator_auth_state	128	1			T12	3		T101	1		T62	4
ecc_corr_err	rot_creator_auth_codesign	115	1			T101	1		T62	4		T176	1
ecc_corr_err	owner_sw_cfg	124	1			T10	1		T12	1		T101	2
ecc_corr_err	creator_sw_cfg	109	1			T12	3		T62	1		T49	2
no_err	secret2	5381	1			T1	2		T3	1		T4	10
no_err	secret1	9176	1			T1	10		T2	6		T3	5
no_err	secret0	8512	1			T1	6		T4	6		T5	10
no_err	hw_cfg1	10389	1			T1	11		T4	11		T5	11
no_err	hw_cfg0	11892	1			T1	16		T2	2		T3	5
no_err	rot_creator_auth_state	8562	1			T1	7		T2	3		T5	5
no_err	rot_creator_auth_codesign	8933	1			T1	15		T2	4		T3	1
no_err	owner_sw_cfg	8841	1			T1	16		T3	4		T4	3
no_err	creator_sw_cfg	8326	1			T1	16		T3	3		T4	14
no_err	vendor_test	10061	1			T1	37		T2	5		T3	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded