Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
lc_prog_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_lc_esc 2 0 2 100.00 100 1 1 0
lc_prog_req_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_prog_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26984 1 T2 6 T4 4 T6 8
auto[1] 832 1 T13 1 T107 2 T41 2



Summary for Variable lc_prog_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26834 1 T2 6 T4 4 T6 8
auto[1] 982 1 T13 2 T107 2 T41 4



Summary for Variable lc_prog_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lc_prog_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 27784 1 T2 6 T4 4 T6 8
lc_esc_on 32 1 T16 1 T390 1 T252 1



Summary for Variable lc_prog_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26126 1 T2 6 T4 4 T6 8
auto[1] 1690 1 T13 2 T107 3 T41 4



Summary for Variable lc_prog_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14848 1 T2 3 T4 2 T6 4
auto[1] 12968 1 T2 3 T4 2 T6 4



Summary for Variable lc_prog_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26218 1 T2 6 T4 3 T6 8
auto[1] 1598 1 T4 1 T13 1 T107 3



Summary for Variable lc_prog_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26243 1 T2 6 T4 3 T6 8
auto[1] 1573 1 T4 1 T13 2 T107 4

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