Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
otbn_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
otbn_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
otbn_req_during_lc_esc 2 0 2 100.00 100 1 1 0
otbn_req_during_otp_idle 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable otbn_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12060 1 T4 10 T5 2 T6 6
auto[1] 988 1 T4 2 T13 3 T41 9



Summary for Variable otbn_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12095 1 T4 10 T5 2 T6 6
auto[1] 953 1 T4 2 T13 2 T41 10



Summary for Variable otbn_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for otbn_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13017 1 T4 12 T5 2 T6 6
lc_esc_on 31 1 T106 1 T215 1 T391 1



Summary for Variable otbn_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2274 1 T4 6 T13 4 T106 1
auto[1] 10774 1 T4 6 T5 2 T6 6



Summary for Variable otbn_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12025 1 T4 12 T5 2 T6 6
auto[1] 1023 1 T13 4 T41 9 T8 33



Summary for Variable otbn_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12698 1 T4 12 T5 2 T6 6
auto[1] 350 1 T13 3 T8 12 T99 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%