SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 48267 | 1 | T10 | 54 | T11 | 53 | T106 | 264 | ||||
access_err | 60523 | 1 | T2 | 49 | T10 | 10 | T4 | 22 | ||||
write_blank_err | 476 | 1 | T7 | 4 | T8 | 8 | T97 | 2 | ||||
ecc_uncorr_err | 67685 | 1 | T6 | 150 | T7 | 444 | T112 | 112 | ||||
ecc_corr_err | 1420 | 1 | T6 | 3 | T11 | 30 | T112 | 4 | ||||
no_err | 90348 | 1 | T2 | 64 | T10 | 43 | T4 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 786 | 1 | T7 | 4 | T8 | 15 | T9 | 20 | ||||
secret2 | 22471 | 1 | T2 | 6 | T10 | 2 | T4 | 12 | ||||
secret1 | 24518 | 1 | T2 | 11 | T10 | 63 | T4 | 5 | ||||
secret0 | 33088 | 1 | T2 | 11 | T10 | 2 | T4 | 2 | ||||
hw_cfg1 | 43575 | 1 | T2 | 9 | T10 | 6 | T4 | 6 | ||||
hw_cfg0 | 26445 | 1 | T2 | 13 | T10 | 7 | T6 | 1 | ||||
rot_creator_auth_state | 22953 | 1 | T2 | 14 | T10 | 2 | T11 | 12 | ||||
rot_creator_auth_codesign | 20907 | 1 | T2 | 20 | T10 | 5 | T4 | 14 | ||||
owner_sw_cfg | 20620 | 1 | T2 | 6 | T10 | 5 | T4 | 15 | ||||
creator_sw_cfg | 21512 | 1 | T2 | 8 | T10 | 8 | T4 | 10 | ||||
vendor_test | 31844 | 1 | T2 | 15 | T10 | 7 | T4 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 3178 | 1 | T109 | 192 | T186 | 150 | T339 | 22 | ||||
fsm_err | secret1 | 2884 | 1 | T10 | 54 | T215 | 321 | T340 | 1 | ||||
fsm_err | secret0 | 4015 | 1 | T217 | 341 | T186 | 273 | T235 | 251 | ||||
fsm_err | hw_cfg1 | 2951 | 1 | T131 | 330 | T182 | 60 | T229 | 133 | ||||
fsm_err | hw_cfg0 | 6142 | 1 | T106 | 264 | T221 | 195 | T254 | 239 | ||||
fsm_err | rot_creator_auth_state | 4268 | 1 | T9 | 20 | T256 | 146 | T322 | 24 | ||||
fsm_err | rot_creator_auth_codesign | 2827 | 1 | T18 | 26 | T341 | 329 | T148 | 60 | ||||
fsm_err | owner_sw_cfg | 3337 | 1 | T282 | 165 | T131 | 260 | T255 | 117 | ||||
fsm_err | creator_sw_cfg | 4366 | 1 | T9 | 176 | T149 | 63 | T164 | 257 | ||||
fsm_err | vendor_test | 14299 | 1 | T11 | 53 | T112 | 63 | T58 | 8 | ||||
access_err | life_cycle | 786 | 1 | T7 | 4 | T8 | 15 | T9 | 20 | ||||
access_err | secret2 | 10847 | 1 | T2 | 6 | T10 | 2 | T4 | 3 | ||||
access_err | secret1 | 5554 | 1 | T2 | 8 | T11 | 5 | T13 | 35 | ||||
access_err | secret0 | 4267 | 1 | T4 | 1 | T11 | 7 | T13 | 27 | ||||
access_err | hw_cfg1 | 1184 | 1 | T2 | 4 | T11 | 1 | T13 | 4 | ||||
access_err | hw_cfg0 | 2147 | 1 | T13 | 1 | T30 | 12 | T17 | 10 | ||||
access_err | rot_creator_auth_state | 5864 | 1 | T2 | 6 | T11 | 3 | T13 | 17 | ||||
access_err | rot_creator_auth_codesign | 7779 | 1 | T2 | 10 | T10 | 3 | T4 | 5 | ||||
access_err | owner_sw_cfg | 6974 | 1 | T2 | 1 | T10 | 1 | T4 | 6 | ||||
access_err | creator_sw_cfg | 7613 | 1 | T2 | 7 | T10 | 4 | T4 | 4 | ||||
access_err | vendor_test | 7508 | 1 | T2 | 7 | T4 | 3 | T11 | 13 | ||||
write_blank_err | secret2 | 8 | 1 | T221 | 1 | T19 | 1 | T230 | 1 | ||||
write_blank_err | secret1 | 21 | 1 | T8 | 1 | T103 | 1 | T19 | 2 | ||||
write_blank_err | secret0 | 53 | 1 | T8 | 1 | T9 | 1 | T218 | 2 | ||||
write_blank_err | hw_cfg1 | 86 | 1 | T7 | 1 | T97 | 1 | T9 | 1 | ||||
write_blank_err | hw_cfg0 | 23 | 1 | T103 | 1 | T198 | 1 | T342 | 1 | ||||
write_blank_err | rot_creator_auth_state | 148 | 1 | T8 | 4 | T9 | 7 | T103 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 66 | 1 | T7 | 3 | T9 | 1 | T103 | 1 | ||||
write_blank_err | owner_sw_cfg | 28 | 1 | T9 | 1 | T103 | 1 | T186 | 1 | ||||
write_blank_err | creator_sw_cfg | 26 | 1 | T9 | 1 | T218 | 2 | T343 | 2 | ||||
write_blank_err | vendor_test | 17 | 1 | T8 | 2 | T97 | 1 | T9 | 1 | ||||
ecc_uncorr_err | secret2 | 3268 | 1 | T112 | 53 | T95 | 40 | T221 | 324 | ||||
ecc_uncorr_err | secret1 | 6724 | 1 | T8 | 489 | T95 | 46 | T103 | 467 | ||||
ecc_uncorr_err | secret0 | 16186 | 1 | T6 | 46 | T8 | 436 | T95 | 114 | ||||
ecc_uncorr_err | hw_cfg1 | 28449 | 1 | T7 | 444 | T112 | 59 | T97 | 699 | ||||
ecc_uncorr_err | hw_cfg0 | 5700 | 1 | T148 | 56 | T198 | 671 | T207 | 42 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4216 | 1 | T141 | 12 | T148 | 63 | T207 | 82 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1249 | 1 | T6 | 104 | T95 | 52 | T267 | 3 | ||||
ecc_uncorr_err | owner_sw_cfg | 912 | 1 | T238 | 35 | T267 | 3 | T148 | 121 | ||||
ecc_uncorr_err | creator_sw_cfg | 981 | 1 | T95 | 42 | T238 | 32 | T207 | 48 | ||||
ecc_corr_err | secret2 | 82 | 1 | T69 | 4 | T59 | 3 | T42 | 3 | ||||
ecc_corr_err | secret1 | 113 | 1 | T11 | 1 | T69 | 1 | T59 | 1 | ||||
ecc_corr_err | secret0 | 150 | 1 | T112 | 2 | T95 | 1 | T141 | 1 | ||||
ecc_corr_err | hw_cfg1 | 249 | 1 | T6 | 1 | T11 | 15 | T112 | 2 | ||||
ecc_corr_err | hw_cfg0 | 251 | 1 | T6 | 1 | T11 | 9 | T103 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 137 | 1 | T11 | 3 | T95 | 1 | T103 | 1 | ||||
ecc_corr_err | rot_creator_auth_codesign | 121 | 1 | T11 | 1 | T95 | 1 | T141 | 1 | ||||
ecc_corr_err | owner_sw_cfg | 147 | 1 | T11 | 1 | T95 | 1 | T65 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 170 | 1 | T6 | 1 | T95 | 4 | T65 | 1 | ||||
no_err | secret2 | 5088 | 1 | T4 | 9 | T11 | 2 | T13 | 25 | ||||
no_err | secret1 | 9222 | 1 | T2 | 3 | T10 | 9 | T4 | 5 | ||||
no_err | secret0 | 8417 | 1 | T2 | 11 | T10 | 2 | T4 | 1 | ||||
no_err | hw_cfg1 | 10656 | 1 | T2 | 5 | T10 | 6 | T4 | 6 | ||||
no_err | hw_cfg0 | 12182 | 1 | T2 | 13 | T10 | 7 | T11 | 11 | ||||
no_err | rot_creator_auth_state | 8320 | 1 | T2 | 8 | T10 | 2 | T11 | 6 | ||||
no_err | rot_creator_auth_codesign | 8865 | 1 | T2 | 10 | T10 | 2 | T4 | 9 | ||||
no_err | owner_sw_cfg | 9222 | 1 | T2 | 5 | T10 | 4 | T4 | 9 | ||||
no_err | creator_sw_cfg | 8356 | 1 | T2 | 1 | T10 | 4 | T4 | 6 | ||||
no_err | vendor_test | 10020 | 1 | T2 | 8 | T10 | 7 | T4 | 6 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |