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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.96 93.86 96.30 95.59 92.36 96.91 96.34 93.35


Total test records in report: 1323
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T1264 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1018778677 Jul 07 07:03:59 PM PDT 24 Jul 07 07:04:01 PM PDT 24 86083840 ps
T1265 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3712002863 Jul 07 07:04:00 PM PDT 24 Jul 07 07:04:02 PM PDT 24 739271568 ps
T1266 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3519073866 Jul 07 07:03:34 PM PDT 24 Jul 07 07:03:35 PM PDT 24 65691569 ps
T1267 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.4057383041 Jul 07 07:04:12 PM PDT 24 Jul 07 07:04:13 PM PDT 24 133875042 ps
T1268 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1177675025 Jul 07 07:03:29 PM PDT 24 Jul 07 07:03:31 PM PDT 24 557227614 ps
T352 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4240817385 Jul 07 07:03:53 PM PDT 24 Jul 07 07:04:04 PM PDT 24 616745528 ps
T1269 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1493159544 Jul 07 07:03:44 PM PDT 24 Jul 07 07:03:47 PM PDT 24 1123178066 ps
T353 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2419158085 Jul 07 07:03:31 PM PDT 24 Jul 07 07:03:52 PM PDT 24 2306520726 ps
T1270 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1391562979 Jul 07 07:03:31 PM PDT 24 Jul 07 07:03:39 PM PDT 24 3073697211 ps
T1271 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.4172309279 Jul 07 07:04:05 PM PDT 24 Jul 07 07:04:06 PM PDT 24 42047878 ps
T1272 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4106524232 Jul 07 07:03:49 PM PDT 24 Jul 07 07:03:53 PM PDT 24 1169348731 ps
T1273 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3639255042 Jul 07 07:03:33 PM PDT 24 Jul 07 07:03:34 PM PDT 24 38638556 ps
T1274 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1399216340 Jul 07 07:04:00 PM PDT 24 Jul 07 07:04:07 PM PDT 24 2406279860 ps
T1275 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.261448508 Jul 07 07:03:40 PM PDT 24 Jul 07 07:03:42 PM PDT 24 48473127 ps
T1276 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1200809137 Jul 07 07:03:55 PM PDT 24 Jul 07 07:03:58 PM PDT 24 49935099 ps
T1277 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2439916387 Jul 07 07:03:39 PM PDT 24 Jul 07 07:03:42 PM PDT 24 154601175 ps
T1278 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3371695433 Jul 07 07:04:06 PM PDT 24 Jul 07 07:04:08 PM PDT 24 41319214 ps
T1279 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.858336883 Jul 07 07:03:52 PM PDT 24 Jul 07 07:03:58 PM PDT 24 900281639 ps
T1280 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.40496813 Jul 07 07:04:05 PM PDT 24 Jul 07 07:04:09 PM PDT 24 215705706 ps
T1281 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1454311574 Jul 07 07:03:40 PM PDT 24 Jul 07 07:03:42 PM PDT 24 65671382 ps
T311 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.810207177 Jul 07 07:03:58 PM PDT 24 Jul 07 07:04:00 PM PDT 24 44166832 ps
T1282 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2011269646 Jul 07 07:03:58 PM PDT 24 Jul 07 07:04:00 PM PDT 24 563263517 ps
T1283 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.492021371 Jul 07 07:04:05 PM PDT 24 Jul 07 07:04:08 PM PDT 24 91423070 ps
T1284 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.941393062 Jul 07 07:04:06 PM PDT 24 Jul 07 07:04:08 PM PDT 24 138944181 ps
T1285 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.789073427 Jul 07 07:03:41 PM PDT 24 Jul 07 07:03:45 PM PDT 24 131408340 ps
T312 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2096689828 Jul 07 07:03:34 PM PDT 24 Jul 07 07:03:36 PM PDT 24 51191488 ps
T1286 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2574111328 Jul 07 07:03:43 PM PDT 24 Jul 07 07:03:46 PM PDT 24 70073499 ps
T1287 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3478457999 Jul 07 07:03:24 PM PDT 24 Jul 07 07:03:31 PM PDT 24 147057444 ps
T1288 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1516033639 Jul 07 07:04:02 PM PDT 24 Jul 07 07:04:04 PM PDT 24 46419766 ps
T1289 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3857211153 Jul 07 07:04:01 PM PDT 24 Jul 07 07:04:08 PM PDT 24 2695269746 ps
T1290 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.738061745 Jul 07 07:04:10 PM PDT 24 Jul 07 07:04:12 PM PDT 24 129847756 ps
T1291 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3786669991 Jul 07 07:04:05 PM PDT 24 Jul 07 07:04:07 PM PDT 24 39600066 ps
T1292 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1989157434 Jul 07 07:03:55 PM PDT 24 Jul 07 07:04:01 PM PDT 24 1742594702 ps
T1293 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1117237729 Jul 07 07:03:29 PM PDT 24 Jul 07 07:03:31 PM PDT 24 124818815 ps
T1294 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2069604530 Jul 07 07:03:56 PM PDT 24 Jul 07 07:03:58 PM PDT 24 569910095 ps
T1295 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1847874784 Jul 07 07:03:42 PM PDT 24 Jul 07 07:03:49 PM PDT 24 572763640 ps
T1296 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.660754384 Jul 07 07:04:06 PM PDT 24 Jul 07 07:04:08 PM PDT 24 71740597 ps
T1297 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1313668195 Jul 07 07:03:29 PM PDT 24 Jul 07 07:03:31 PM PDT 24 45121989 ps
T1298 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1932294283 Jul 07 07:03:30 PM PDT 24 Jul 07 07:03:33 PM PDT 24 106386660 ps
T1299 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2885086461 Jul 07 07:03:42 PM PDT 24 Jul 07 07:03:45 PM PDT 24 101889898 ps
T1300 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.926354286 Jul 07 07:03:24 PM PDT 24 Jul 07 07:03:25 PM PDT 24 40682031 ps
T1301 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3848220080 Jul 07 07:03:44 PM PDT 24 Jul 07 07:03:45 PM PDT 24 73712776 ps
T1302 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.4264568681 Jul 07 07:03:32 PM PDT 24 Jul 07 07:03:42 PM PDT 24 2631438118 ps
T354 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1260326643 Jul 07 07:03:43 PM PDT 24 Jul 07 07:03:54 PM PDT 24 1442882728 ps
T1303 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1992189074 Jul 07 07:04:01 PM PDT 24 Jul 07 07:04:04 PM PDT 24 158598375 ps
T313 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.750710993 Jul 07 07:03:25 PM PDT 24 Jul 07 07:03:28 PM PDT 24 254089872 ps
T1304 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3782852372 Jul 07 07:04:07 PM PDT 24 Jul 07 07:04:10 PM PDT 24 567291598 ps
T1305 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3401145091 Jul 07 07:04:00 PM PDT 24 Jul 07 07:04:06 PM PDT 24 285461185 ps
T1306 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.726758999 Jul 07 07:03:25 PM PDT 24 Jul 07 07:03:44 PM PDT 24 6986280592 ps
T1307 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.380357042 Jul 07 07:04:09 PM PDT 24 Jul 07 07:04:11 PM PDT 24 71765998 ps
T1308 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1367172755 Jul 07 07:03:49 PM PDT 24 Jul 07 07:03:51 PM PDT 24 64810077 ps
T1309 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3273628490 Jul 07 07:03:30 PM PDT 24 Jul 07 07:03:33 PM PDT 24 591568617 ps
T278 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2983954291 Jul 07 07:04:00 PM PDT 24 Jul 07 07:04:21 PM PDT 24 1749969258 ps
T1310 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1233726855 Jul 07 07:04:09 PM PDT 24 Jul 07 07:04:11 PM PDT 24 53244545 ps
T355 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3056887728 Jul 07 07:03:43 PM PDT 24 Jul 07 07:04:02 PM PDT 24 1321050782 ps
T349 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1968711115 Jul 07 07:03:59 PM PDT 24 Jul 07 07:04:10 PM PDT 24 856043901 ps
T1311 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.4185033001 Jul 07 07:03:59 PM PDT 24 Jul 07 07:04:05 PM PDT 24 177473707 ps
T1312 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2013008656 Jul 07 07:03:41 PM PDT 24 Jul 07 07:03:45 PM PDT 24 129186782 ps
T1313 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.476959361 Jul 07 07:04:01 PM PDT 24 Jul 07 07:04:05 PM PDT 24 224414652 ps
T350 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1887006537 Jul 07 07:03:55 PM PDT 24 Jul 07 07:04:18 PM PDT 24 4964735920 ps
T1314 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4115631283 Jul 07 07:03:32 PM PDT 24 Jul 07 07:03:39 PM PDT 24 659478419 ps
T1315 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2380020135 Jul 07 07:03:31 PM PDT 24 Jul 07 07:03:34 PM PDT 24 135076633 ps
T1316 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3662647095 Jul 07 07:03:43 PM PDT 24 Jul 07 07:03:45 PM PDT 24 50758011 ps
T1317 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3933778706 Jul 07 07:03:37 PM PDT 24 Jul 07 07:03:39 PM PDT 24 1000850949 ps
T356 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.874263516 Jul 07 07:03:38 PM PDT 24 Jul 07 07:03:58 PM PDT 24 5274259239 ps
T345 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2306222052 Jul 07 07:03:45 PM PDT 24 Jul 07 07:03:58 PM PDT 24 2451603372 ps
T1318 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1050535972 Jul 07 07:03:25 PM PDT 24 Jul 07 07:03:27 PM PDT 24 69358424 ps
T1319 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2130327262 Jul 07 07:03:52 PM PDT 24 Jul 07 07:03:55 PM PDT 24 140003009 ps
T1320 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3749842882 Jul 07 07:03:58 PM PDT 24 Jul 07 07:04:00 PM PDT 24 96256124 ps
T1321 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.692538013 Jul 07 07:04:06 PM PDT 24 Jul 07 07:04:08 PM PDT 24 79197713 ps
T314 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3870777294 Jul 07 07:03:44 PM PDT 24 Jul 07 07:03:46 PM PDT 24 118314380 ps
T1322 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1791484801 Jul 07 07:04:01 PM PDT 24 Jul 07 07:04:04 PM PDT 24 258472039 ps
T1323 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2342718618 Jul 07 07:04:07 PM PDT 24 Jul 07 07:04:09 PM PDT 24 136315025 ps

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.3433137004
Short name T11
Test name
Test status
Simulation time 980894799 ps
CPU time 15.79 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 243088 kb
Host smart-988f4a1d-11bf-43ea-bcd2-267bd690d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433137004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3433137004
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3855344030
Short name T8
Test name
Test status
Simulation time 35607008942 ps
CPU time 260.31 seconds
Started Jul 07 07:05:43 PM PDT 24
Finished Jul 07 07:10:04 PM PDT 24
Peak memory 273448 kb
Host smart-b7fb69b7-5832-4c84-9510-99ec44647374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855344030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3855344030
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.1508273987
Short name T9
Test name
Test status
Simulation time 16943367856 ps
CPU time 233.71 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:08:34 PM PDT 24
Peak memory 274880 kb
Host smart-2a061e7b-c97e-4c4a-aa7f-cfc6018d4eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508273987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
1508273987
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3183734819
Short name T13
Test name
Test status
Simulation time 981342950 ps
CPU time 23.43 seconds
Started Jul 07 07:06:20 PM PDT 24
Finished Jul 07 07:06:44 PM PDT 24
Peak memory 242268 kb
Host smart-77103919-572f-46ab-8925-3a5da8dc989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183734819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3183734819
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1262902056
Short name T252
Test name
Test status
Simulation time 1434507623435 ps
CPU time 4671.61 seconds
Started Jul 07 07:08:12 PM PDT 24
Finished Jul 07 08:26:04 PM PDT 24
Peak memory 537072 kb
Host smart-8d9533b4-b1c0-4f48-9287-39fc13ecf6c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262902056 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.1262902056
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.883631337
Short name T146
Test name
Test status
Simulation time 350941859 ps
CPU time 3.26 seconds
Started Jul 07 07:09:27 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 242156 kb
Host smart-18386d1e-d632-4c7c-8798-d4c324e4cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883631337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.883631337
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.3729888371
Short name T25
Test name
Test status
Simulation time 42679807663 ps
CPU time 199.52 seconds
Started Jul 07 07:04:15 PM PDT 24
Finished Jul 07 07:07:34 PM PDT 24
Peak memory 278508 kb
Host smart-86181c9b-41c7-4527-b405-98dc3f368785
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729888371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3729888371
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.145678584
Short name T218
Test name
Test status
Simulation time 16438998563 ps
CPU time 182.69 seconds
Started Jul 07 07:06:55 PM PDT 24
Finished Jul 07 07:09:58 PM PDT 24
Peak memory 268528 kb
Host smart-12cecde0-dfbd-4e1e-9e11-2616de7a220e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145678584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.
145678584
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1717947775
Short name T26
Test name
Test status
Simulation time 321803812 ps
CPU time 4.35 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:08:59 PM PDT 24
Peak memory 242060 kb
Host smart-be2778be-1cd7-446a-964b-a49c6855e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717947775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1717947775
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.522870326
Short name T274
Test name
Test status
Simulation time 20153515883 ps
CPU time 19.55 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:19 PM PDT 24
Peak memory 246152 kb
Host smart-b58a5320-9624-4e12-b18b-66478ae5b3b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522870326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in
tg_err.522870326
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.4195273928
Short name T21
Test name
Test status
Simulation time 295023974281 ps
CPU time 3704.53 seconds
Started Jul 07 07:05:25 PM PDT 24
Finished Jul 07 08:07:10 PM PDT 24
Peak memory 273796 kb
Host smart-0936cce3-e051-4a53-acf4-60f4c7d9af04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195273928 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.4195273928
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.796548600
Short name T66
Test name
Test status
Simulation time 626543519 ps
CPU time 4.78 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 241912 kb
Host smart-635bb0a1-b314-4c98-b9d7-2c31b6305d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796548600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.796548600
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.445636621
Short name T77
Test name
Test status
Simulation time 26843046891 ps
CPU time 57.78 seconds
Started Jul 07 07:07:09 PM PDT 24
Finished Jul 07 07:08:07 PM PDT 24
Peak memory 257096 kb
Host smart-36520d51-d762-4332-8faa-08ed01763bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445636621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.445636621
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3958798790
Short name T14
Test name
Test status
Simulation time 1964939463946 ps
CPU time 2982.45 seconds
Started Jul 07 07:07:02 PM PDT 24
Finished Jul 07 07:56:45 PM PDT 24
Peak memory 356144 kb
Host smart-e172fab3-7b62-4328-9498-5ffa0f3d48f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958798790 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3958798790
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.1692861786
Short name T221
Test name
Test status
Simulation time 18562030974 ps
CPU time 89.81 seconds
Started Jul 07 07:06:03 PM PDT 24
Finished Jul 07 07:07:34 PM PDT 24
Peak memory 257032 kb
Host smart-85b1e501-08fc-4018-8de4-a2377a73bb8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692861786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.1692861786
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.1866822620
Short name T39
Test name
Test status
Simulation time 2900390290 ps
CPU time 5.89 seconds
Started Jul 07 07:09:09 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242212 kb
Host smart-1375d31b-1fc9-4046-8d7e-22b42dfed554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866822620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1866822620
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.3812470644
Short name T200
Test name
Test status
Simulation time 3406978584 ps
CPU time 37.74 seconds
Started Jul 07 07:07:24 PM PDT 24
Finished Jul 07 07:08:02 PM PDT 24
Peak memory 244036 kb
Host smart-3486f864-2f44-4cfe-85fc-779774de0496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812470644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3812470644
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.2579336446
Short name T49
Test name
Test status
Simulation time 164846897 ps
CPU time 4.74 seconds
Started Jul 07 07:09:06 PM PDT 24
Finished Jul 07 07:09:11 PM PDT 24
Peak memory 241868 kb
Host smart-476a80fd-d1f2-4632-8620-b1664fcdf0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579336446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2579336446
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.579189555
Short name T131
Test name
Test status
Simulation time 10512771509 ps
CPU time 119.82 seconds
Started Jul 07 07:07:34 PM PDT 24
Finished Jul 07 07:09:34 PM PDT 24
Peak memory 249656 kb
Host smart-3c10d6d9-3760-4f6a-b002-0c9fba30fe70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579189555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
579189555
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1460164287
Short name T3
Test name
Test status
Simulation time 492011258 ps
CPU time 5.15 seconds
Started Jul 07 07:08:59 PM PDT 24
Finished Jul 07 07:09:05 PM PDT 24
Peak memory 242188 kb
Host smart-a69f86e5-8457-447e-9464-c8035f44e71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460164287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1460164287
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.259511498
Short name T440
Test name
Test status
Simulation time 97073166 ps
CPU time 2.01 seconds
Started Jul 07 07:04:16 PM PDT 24
Finished Jul 07 07:04:18 PM PDT 24
Peak memory 240428 kb
Host smart-98f45c22-fe61-4a1a-92b0-cfe7c82df41f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259511498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.259511498
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2109927311
Short name T59
Test name
Test status
Simulation time 17938607652 ps
CPU time 43 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:05:22 PM PDT 24
Peak memory 243424 kb
Host smart-f6d05652-d90b-48db-9494-a1d3f53d2349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109927311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2109927311
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.3245643531
Short name T62
Test name
Test status
Simulation time 3119952411 ps
CPU time 9.43 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:35 PM PDT 24
Peak memory 242220 kb
Host smart-ef7c9539-1a44-4d6a-aa1b-d22e90abc449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245643531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3245643531
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3745242066
Short name T125
Test name
Test status
Simulation time 469749483 ps
CPU time 4.95 seconds
Started Jul 07 07:04:46 PM PDT 24
Finished Jul 07 07:04:51 PM PDT 24
Peak memory 242064 kb
Host smart-d083a19e-ec04-4bba-a0d4-617bcb5d3dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745242066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3745242066
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1582945262
Short name T142
Test name
Test status
Simulation time 185852057 ps
CPU time 4.09 seconds
Started Jul 07 07:08:19 PM PDT 24
Finished Jul 07 07:08:24 PM PDT 24
Peak memory 242332 kb
Host smart-6e749f67-4c2e-4624-9d35-ac7a30e435bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582945262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1582945262
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.4125310418
Short name T384
Test name
Test status
Simulation time 115744191886 ps
CPU time 964.8 seconds
Started Jul 07 07:07:44 PM PDT 24
Finished Jul 07 07:23:49 PM PDT 24
Peak memory 290976 kb
Host smart-0ca4230b-1a56-4023-a203-909fbdc87bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125310418 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.4125310418
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.4290583287
Short name T56
Test name
Test status
Simulation time 142222732 ps
CPU time 5.3 seconds
Started Jul 07 07:08:42 PM PDT 24
Finished Jul 07 07:08:48 PM PDT 24
Peak memory 242368 kb
Host smart-9744baf8-bf47-4d8c-a404-e296949f133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290583287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.4290583287
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3939511141
Short name T12
Test name
Test status
Simulation time 324011154 ps
CPU time 5.02 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242064 kb
Host smart-072044ac-e63d-4c2e-aa34-d66feb499e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939511141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3939511141
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.164702931
Short name T34
Test name
Test status
Simulation time 146393560 ps
CPU time 4.18 seconds
Started Jul 07 07:09:24 PM PDT 24
Finished Jul 07 07:09:28 PM PDT 24
Peak memory 241900 kb
Host smart-a7d9778c-e7fd-4395-8850-eb6e2d44afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164702931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.164702931
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.306791718
Short name T536
Test name
Test status
Simulation time 55070896930 ps
CPU time 321.7 seconds
Started Jul 07 07:06:55 PM PDT 24
Finished Jul 07 07:12:17 PM PDT 24
Peak memory 279572 kb
Host smart-1411d51d-9a88-49b1-beb8-3f5b3e2137b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306791718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.
306791718
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.1115186589
Short name T235
Test name
Test status
Simulation time 2650499620 ps
CPU time 15.43 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:13 PM PDT 24
Peak memory 241884 kb
Host smart-d917b47e-b1c6-4429-92a3-8801f0e9c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115186589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1115186589
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.1417826376
Short name T27
Test name
Test status
Simulation time 600815266 ps
CPU time 4.77 seconds
Started Jul 07 07:08:37 PM PDT 24
Finished Jul 07 07:08:42 PM PDT 24
Peak memory 241792 kb
Host smart-649e71b0-8121-47da-a4ef-d5ba79c56e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417826376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1417826376
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.1496177960
Short name T124
Test name
Test status
Simulation time 364075768 ps
CPU time 9.64 seconds
Started Jul 07 07:06:59 PM PDT 24
Finished Jul 07 07:07:09 PM PDT 24
Peak memory 242300 kb
Host smart-0565c1cf-f6d6-48a8-bf3a-f432d6575bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496177960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1496177960
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.2821819710
Short name T112
Test name
Test status
Simulation time 597133512 ps
CPU time 12.13 seconds
Started Jul 07 07:04:46 PM PDT 24
Finished Jul 07 07:04:58 PM PDT 24
Peak memory 242524 kb
Host smart-50ebecec-bc49-46dc-b32f-8b0b80befc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821819710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.2821819710
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1578780040
Short name T293
Test name
Test status
Simulation time 38375192 ps
CPU time 1.64 seconds
Started Jul 07 07:03:23 PM PDT 24
Finished Jul 07 07:03:25 PM PDT 24
Peak memory 241304 kb
Host smart-4ce8c2f6-2c5d-42d7-9cb7-675ddf617f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578780040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1578780040
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.1505936479
Short name T81
Test name
Test status
Simulation time 14743151414 ps
CPU time 44.5 seconds
Started Jul 07 07:04:46 PM PDT 24
Finished Jul 07 07:05:31 PM PDT 24
Peak memory 245216 kb
Host smart-935f6ff3-b51f-4015-a373-04865b9dcb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505936479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.1505936479
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.3521446208
Short name T103
Test name
Test status
Simulation time 23870417881 ps
CPU time 250.84 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:08:49 PM PDT 24
Peak memory 289744 kb
Host smart-52fae7c9-cd38-497f-85a4-fa4b863d5154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521446208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
3521446208
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.2478684936
Short name T214
Test name
Test status
Simulation time 286335244 ps
CPU time 6.37 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:40 PM PDT 24
Peak memory 241884 kb
Host smart-8b8fb180-d9b6-4847-b6cd-ecf40662dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478684936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2478684936
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.1359244578
Short name T1
Test name
Test status
Simulation time 126946070 ps
CPU time 4.62 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:03 PM PDT 24
Peak memory 241916 kb
Host smart-a0b4b242-343a-475b-b8fc-fb451285a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359244578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.1359244578
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2680809777
Short name T227
Test name
Test status
Simulation time 638084562 ps
CPU time 19.32 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:36 PM PDT 24
Peak memory 241928 kb
Host smart-d838b8ce-4744-490d-8c3c-c7e0315a3ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680809777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2680809777
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.878740246
Short name T207
Test name
Test status
Simulation time 2563279015 ps
CPU time 31.68 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:05:10 PM PDT 24
Peak memory 243304 kb
Host smart-782af494-40c5-4fba-bde6-06e69ec8b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878740246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.878740246
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.2084569038
Short name T31
Test name
Test status
Simulation time 1002484637 ps
CPU time 22.27 seconds
Started Jul 07 07:05:22 PM PDT 24
Finished Jul 07 07:05:44 PM PDT 24
Peak memory 244096 kb
Host smart-8b84e2fb-df3f-409a-ac9a-79edae007e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084569038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2084569038
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.2883492102
Short name T29
Test name
Test status
Simulation time 597639160 ps
CPU time 6.11 seconds
Started Jul 07 07:08:14 PM PDT 24
Finished Jul 07 07:08:21 PM PDT 24
Peak memory 242024 kb
Host smart-52ef6235-e29c-4f06-b1af-b636c7aaf042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883492102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2883492102
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.2021110800
Short name T54
Test name
Test status
Simulation time 10653069099 ps
CPU time 12.91 seconds
Started Jul 07 07:05:40 PM PDT 24
Finished Jul 07 07:05:53 PM PDT 24
Peak memory 243748 kb
Host smart-d5d5c808-db2c-4036-af2a-3d815d0887e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021110800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2021110800
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.1226663398
Short name T79
Test name
Test status
Simulation time 170035747 ps
CPU time 3.82 seconds
Started Jul 07 07:08:19 PM PDT 24
Finished Jul 07 07:08:23 PM PDT 24
Peak memory 242192 kb
Host smart-f7111d40-0262-4fb2-a6e2-abef31318283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226663398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1226663398
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1438138530
Short name T175
Test name
Test status
Simulation time 157432208 ps
CPU time 4.38 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:30 PM PDT 24
Peak memory 242152 kb
Host smart-31e56bbb-472b-4a20-b76a-cb14d10c0140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438138530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1438138530
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1073307265
Short name T96
Test name
Test status
Simulation time 286330744 ps
CPU time 11.07 seconds
Started Jul 07 07:04:44 PM PDT 24
Finished Jul 07 07:04:56 PM PDT 24
Peak memory 242064 kb
Host smart-d8764f26-9f01-4b10-9983-56fc92f076af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073307265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1073307265
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2983954291
Short name T278
Test name
Test status
Simulation time 1749969258 ps
CPU time 20.42 seconds
Started Jul 07 07:04:00 PM PDT 24
Finished Jul 07 07:04:21 PM PDT 24
Peak memory 244444 kb
Host smart-01e7c7ce-fdf1-45b0-9ab0-feeea738a6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983954291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.2983954291
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2195297148
Short name T229
Test name
Test status
Simulation time 1608216272 ps
CPU time 11.81 seconds
Started Jul 07 07:08:19 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 241896 kb
Host smart-a01fa19c-dde7-4556-8175-4ac42e8a9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195297148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2195297148
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.442307366
Short name T132
Test name
Test status
Simulation time 8666053434 ps
CPU time 50.54 seconds
Started Jul 07 07:05:34 PM PDT 24
Finished Jul 07 07:06:25 PM PDT 24
Peak memory 247108 kb
Host smart-1d2ea8ee-eb08-41c3-beb4-1194fa5d422b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442307366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
442307366
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.230980761
Short name T253
Test name
Test status
Simulation time 19140181204 ps
CPU time 182.05 seconds
Started Jul 07 07:04:12 PM PDT 24
Finished Jul 07 07:07:15 PM PDT 24
Peak memory 261668 kb
Host smart-2ca5f453-f7db-43c7-a343-3c2e275a696b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230980761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.230980761
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.591635110
Short name T197
Test name
Test status
Simulation time 542855871 ps
CPU time 13.84 seconds
Started Jul 07 07:04:49 PM PDT 24
Finished Jul 07 07:05:03 PM PDT 24
Peak memory 241824 kb
Host smart-28a69b09-8c33-45f7-b891-ea17aba50747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591635110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
591635110
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.3263378395
Short name T71
Test name
Test status
Simulation time 493898573 ps
CPU time 7.22 seconds
Started Jul 07 07:08:15 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 242220 kb
Host smart-764b03f4-1190-4769-9b0e-71c8cd49fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263378395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3263378395
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.1970255996
Short name T190
Test name
Test status
Simulation time 584432100 ps
CPU time 15.15 seconds
Started Jul 07 07:08:13 PM PDT 24
Finished Jul 07 07:08:29 PM PDT 24
Peak memory 242304 kb
Host smart-c5c3f237-ecd4-4fc1-8b23-5f9d5504a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970255996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.1970255996
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.593877511
Short name T84
Test name
Test status
Simulation time 285845129 ps
CPU time 4.66 seconds
Started Jul 07 07:08:24 PM PDT 24
Finished Jul 07 07:08:29 PM PDT 24
Peak memory 241864 kb
Host smart-ff07980d-f4b0-4be2-b8b2-5d10b8cee4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593877511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.593877511
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.4123691687
Short name T234
Test name
Test status
Simulation time 633294508 ps
CPU time 16.53 seconds
Started Jul 07 07:08:26 PM PDT 24
Finished Jul 07 07:08:43 PM PDT 24
Peak memory 242292 kb
Host smart-9054ec38-08d2-43bf-a27e-b263d5a15223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123691687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.4123691687
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.758804565
Short name T223
Test name
Test status
Simulation time 244352372 ps
CPU time 6.14 seconds
Started Jul 07 07:05:08 PM PDT 24
Finished Jul 07 07:05:14 PM PDT 24
Peak memory 241896 kb
Host smart-2e864d4c-fca4-42bd-9d71-83199dc18c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758804565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.758804565
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2363210620
Short name T92
Test name
Test status
Simulation time 1705934391 ps
CPU time 4.1 seconds
Started Jul 07 07:08:34 PM PDT 24
Finished Jul 07 07:08:39 PM PDT 24
Peak memory 242048 kb
Host smart-cda67e51-0477-4820-a45c-5d2bee8355ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363210620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2363210620
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1474990850
Short name T130
Test name
Test status
Simulation time 308840194 ps
CPU time 8.05 seconds
Started Jul 07 07:05:39 PM PDT 24
Finished Jul 07 07:05:48 PM PDT 24
Peak memory 241944 kb
Host smart-55382c2c-ecb1-4fe2-a760-99106f8a3959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474990850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1474990850
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2227190847
Short name T728
Test name
Test status
Simulation time 4352815265 ps
CPU time 14.92 seconds
Started Jul 07 07:05:53 PM PDT 24
Finished Jul 07 07:06:08 PM PDT 24
Peak memory 242064 kb
Host smart-867d1f41-450e-436e-8c20-f7efd2e395e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227190847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2227190847
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.3442855179
Short name T42
Test name
Test status
Simulation time 10981850020 ps
CPU time 21.12 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:06:37 PM PDT 24
Peak memory 243780 kb
Host smart-8a5d1e2c-918e-4ec9-b307-fa0d15cf8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442855179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3442855179
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3018285197
Short name T273
Test name
Test status
Simulation time 711112889 ps
CPU time 9.98 seconds
Started Jul 07 07:03:25 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 244112 kb
Host smart-5812dce9-298e-46a2-a41c-6abbb2994988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018285197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3018285197
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2606728033
Short name T20
Test name
Test status
Simulation time 181954388410 ps
CPU time 2594.06 seconds
Started Jul 07 07:04:20 PM PDT 24
Finished Jul 07 07:47:35 PM PDT 24
Peak memory 363616 kb
Host smart-ec29c9dc-33d4-411f-8f12-681f72647cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606728033 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2606728033
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3339106158
Short name T376
Test name
Test status
Simulation time 764308529 ps
CPU time 19.03 seconds
Started Jul 07 07:06:41 PM PDT 24
Finished Jul 07 07:07:01 PM PDT 24
Peak memory 248788 kb
Host smart-b3d527fa-3c56-4906-a059-80b9ed8b9d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339106158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3339106158
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1626291883
Short name T357
Test name
Test status
Simulation time 3751397130 ps
CPU time 9.36 seconds
Started Jul 07 07:07:07 PM PDT 24
Finished Jul 07 07:07:16 PM PDT 24
Peak memory 248816 kb
Host smart-56899d43-c3c0-4b54-9338-40a02979a08e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626291883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1626291883
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3714524144
Short name T85
Test name
Test status
Simulation time 22318269343 ps
CPU time 45.97 seconds
Started Jul 07 07:04:20 PM PDT 24
Finished Jul 07 07:05:06 PM PDT 24
Peak memory 245192 kb
Host smart-133ac3cf-d629-4616-97b8-b67b59158941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714524144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3714524144
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.1667169488
Short name T257
Test name
Test status
Simulation time 888106959 ps
CPU time 18.76 seconds
Started Jul 07 07:07:00 PM PDT 24
Finished Jul 07 07:07:19 PM PDT 24
Peak memory 242032 kb
Host smart-6a52198a-45ce-4b51-9713-cf7964680721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667169488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1667169488
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2821082053
Short name T121
Test name
Test status
Simulation time 1496730206 ps
CPU time 16.62 seconds
Started Jul 07 07:05:20 PM PDT 24
Finished Jul 07 07:05:37 PM PDT 24
Peak memory 241580 kb
Host smart-4083ba5d-151b-472e-bce0-94f990f9fe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821082053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2821082053
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2599423364
Short name T91
Test name
Test status
Simulation time 118363637 ps
CPU time 4.15 seconds
Started Jul 07 07:08:53 PM PDT 24
Finished Jul 07 07:08:58 PM PDT 24
Peak memory 241816 kb
Host smart-d40ed9f6-1430-4df3-b04b-07006648045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599423364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2599423364
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3395345366
Short name T209
Test name
Test status
Simulation time 93216146 ps
CPU time 3.6 seconds
Started Jul 07 07:08:13 PM PDT 24
Finished Jul 07 07:08:17 PM PDT 24
Peak memory 241912 kb
Host smart-d972bb90-be23-490d-91c7-f7d03729aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395345366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3395345366
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1344571466
Short name T80
Test name
Test status
Simulation time 1689116498 ps
CPU time 6.08 seconds
Started Jul 07 07:05:13 PM PDT 24
Finished Jul 07 07:05:20 PM PDT 24
Peak memory 242108 kb
Host smart-e14e4e33-9c1a-4a51-9e74-245f24761fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344571466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1344571466
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.1066010748
Short name T267
Test name
Test status
Simulation time 12469390694 ps
CPU time 19.92 seconds
Started Jul 07 07:05:46 PM PDT 24
Finished Jul 07 07:06:07 PM PDT 24
Peak memory 243400 kb
Host smart-21f46003-80f2-44d0-9e56-e93576989460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066010748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1066010748
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3600641055
Short name T111
Test name
Test status
Simulation time 376173671 ps
CPU time 13.43 seconds
Started Jul 07 07:07:04 PM PDT 24
Finished Jul 07 07:07:17 PM PDT 24
Peak memory 242372 kb
Host smart-2174ecd4-12b2-4b66-a8ee-86105d21020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600641055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3600641055
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.3779662763
Short name T367
Test name
Test status
Simulation time 268654952 ps
CPU time 8.17 seconds
Started Jul 07 07:06:41 PM PDT 24
Finished Jul 07 07:06:49 PM PDT 24
Peak memory 242108 kb
Host smart-c5de9c70-dc2e-4953-b046-26a39a4982d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779662763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3779662763
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.337551957
Short name T237
Test name
Test status
Simulation time 56127913 ps
CPU time 1.72 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:20 PM PDT 24
Peak memory 240092 kb
Host smart-33cae57d-1873-426c-9d08-8a8a536df636
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=337551957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.337551957
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.762723433
Short name T272
Test name
Test status
Simulation time 974476284 ps
CPU time 9.95 seconds
Started Jul 07 07:03:48 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 244028 kb
Host smart-d261dcd9-45c2-4a8d-a5f9-9caa8e6fce71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762723433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in
tg_err.762723433
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1887006537
Short name T350
Test name
Test status
Simulation time 4964735920 ps
CPU time 23.42 seconds
Started Jul 07 07:03:55 PM PDT 24
Finished Jul 07 07:04:18 PM PDT 24
Peak memory 245032 kb
Host smart-ce3d642f-ea6e-445f-9892-0e3b2745eb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887006537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.1887006537
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.22965762
Short name T370
Test name
Test status
Simulation time 491164073 ps
CPU time 9.19 seconds
Started Jul 07 07:05:05 PM PDT 24
Finished Jul 07 07:05:14 PM PDT 24
Peak memory 242020 kb
Host smart-bd60ca59-21c9-445b-97c5-4216315e59b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22965762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.22965762
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1879683597
Short name T395
Test name
Test status
Simulation time 106345131565 ps
CPU time 1471.37 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:29:36 PM PDT 24
Peak memory 333316 kb
Host smart-141e6f7c-6a73-4eb0-a36a-e9657b62c99d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879683597 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.1879683597
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1365482979
Short name T304
Test name
Test status
Simulation time 321354639 ps
CPU time 6.36 seconds
Started Jul 07 07:03:25 PM PDT 24
Finished Jul 07 07:03:32 PM PDT 24
Peak memory 239096 kb
Host smart-7f57bd2e-021b-4994-b94e-15545e677fcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365482979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1365482979
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.822593211
Short name T83
Test name
Test status
Simulation time 382879407 ps
CPU time 4.25 seconds
Started Jul 07 07:08:20 PM PDT 24
Finished Jul 07 07:08:24 PM PDT 24
Peak memory 242008 kb
Host smart-d6a42dc7-21d5-46c2-8458-29aa413a84b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822593211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.822593211
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.419018321
Short name T90
Test name
Test status
Simulation time 452655493 ps
CPU time 4.55 seconds
Started Jul 07 07:07:46 PM PDT 24
Finished Jul 07 07:07:51 PM PDT 24
Peak memory 241932 kb
Host smart-a8d54871-b33c-431b-928b-d34ff657977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419018321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.419018321
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.857180626
Short name T924
Test name
Test status
Simulation time 732129871340 ps
CPU time 1595.23 seconds
Started Jul 07 07:04:48 PM PDT 24
Finished Jul 07 07:31:23 PM PDT 24
Peak memory 432792 kb
Host smart-2e9393f0-802b-4064-b71a-b8aec1bcabe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857180626 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.857180626
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.2263849283
Short name T429
Test name
Test status
Simulation time 11502324563 ps
CPU time 29.51 seconds
Started Jul 07 07:06:54 PM PDT 24
Finished Jul 07 07:07:24 PM PDT 24
Peak memory 242984 kb
Host smart-c0257614-0f0f-4348-9a8c-2307cec066be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263849283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2263849283
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.4248240213
Short name T269
Test name
Test status
Simulation time 340466458 ps
CPU time 4 seconds
Started Jul 07 07:07:32 PM PDT 24
Finished Jul 07 07:07:36 PM PDT 24
Peak memory 241936 kb
Host smart-c17a2110-300f-4801-b4ed-94045c4893ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248240213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.4248240213
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.434485786
Short name T264
Test name
Test status
Simulation time 18937293649 ps
CPU time 131.73 seconds
Started Jul 07 07:06:50 PM PDT 24
Finished Jul 07 07:09:02 PM PDT 24
Peak memory 248788 kb
Host smart-c6762112-3723-4e71-a769-eca69d11516c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434485786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.
434485786
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3948134970
Short name T134
Test name
Test status
Simulation time 384617562 ps
CPU time 3.94 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:08 PM PDT 24
Peak memory 241576 kb
Host smart-1b172567-a333-4a81-80a0-3c5814ca74a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948134970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3948134970
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.4269712763
Short name T262
Test name
Test status
Simulation time 244119660581 ps
CPU time 946.96 seconds
Started Jul 07 07:07:43 PM PDT 24
Finished Jul 07 07:23:31 PM PDT 24
Peak memory 300220 kb
Host smart-5e0e9423-22af-474a-a753-dc592fa736bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269712763 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.4269712763
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.504393008
Short name T199
Test name
Test status
Simulation time 312649613 ps
CPU time 10.16 seconds
Started Jul 07 07:06:13 PM PDT 24
Finished Jul 07 07:06:24 PM PDT 24
Peak memory 242164 kb
Host smart-9cc826ce-05cb-4a60-9cc7-08fb69a1fe7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504393008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.504393008
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.1931400358
Short name T88
Test name
Test status
Simulation time 282229595 ps
CPU time 3.87 seconds
Started Jul 07 07:08:38 PM PDT 24
Finished Jul 07 07:08:43 PM PDT 24
Peak memory 242084 kb
Host smart-b32d42e0-1f17-46d8-8a89-dc572c6e4976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931400358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1931400358
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.763224789
Short name T102
Test name
Test status
Simulation time 1537544735 ps
CPU time 29.36 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:34 PM PDT 24
Peak memory 242332 kb
Host smart-08aa0611-73e9-486d-893a-d85efb93c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763224789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.763224789
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.726758999
Short name T1306
Test name
Test status
Simulation time 6986280592 ps
CPU time 18.63 seconds
Started Jul 07 07:03:25 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 239272 kb
Host smart-d6f5d45c-12c7-403c-9639-0eabc769cd60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726758999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.726758999
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.750710993
Short name T313
Test name
Test status
Simulation time 254089872 ps
CPU time 1.85 seconds
Started Jul 07 07:03:25 PM PDT 24
Finished Jul 07 07:03:28 PM PDT 24
Peak memory 241320 kb
Host smart-05c570bc-f8cf-48f2-b685-cecd8f348f56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750710993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.750710993
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3467462081
Short name T1260
Test name
Test status
Simulation time 408043552 ps
CPU time 2.97 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:34 PM PDT 24
Peak memory 247472 kb
Host smart-35e371aa-a1f2-4782-80c9-19367aeda97f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467462081 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3467462081
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.926354286
Short name T1300
Test name
Test status
Simulation time 40682031 ps
CPU time 1.36 seconds
Started Jul 07 07:03:24 PM PDT 24
Finished Jul 07 07:03:25 PM PDT 24
Peak memory 231024 kb
Host smart-1f47085e-8770-4672-95f4-c909495d0bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926354286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.926354286
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2955921794
Short name T1210
Test name
Test status
Simulation time 120142228 ps
CPU time 1.34 seconds
Started Jul 07 07:03:23 PM PDT 24
Finished Jul 07 07:03:25 PM PDT 24
Peak memory 230192 kb
Host smart-57947d21-a34d-4233-9199-493de6af95d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955921794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.2955921794
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1050535972
Short name T1318
Test name
Test status
Simulation time 69358424 ps
CPU time 1.35 seconds
Started Jul 07 07:03:25 PM PDT 24
Finished Jul 07 07:03:27 PM PDT 24
Peak memory 229968 kb
Host smart-301faafe-6aed-4646-96dd-54a90d5f8b58
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050535972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.1050535972
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.467685638
Short name T275
Test name
Test status
Simulation time 81483378 ps
CPU time 2.17 seconds
Started Jul 07 07:03:30 PM PDT 24
Finished Jul 07 07:03:32 PM PDT 24
Peak memory 242284 kb
Host smart-7a197a58-26ed-4cb0-a0e0-109abd34ef0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467685638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct
rl_same_csr_outstanding.467685638
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3478457999
Short name T1287
Test name
Test status
Simulation time 147057444 ps
CPU time 6.06 seconds
Started Jul 07 07:03:24 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 247236 kb
Host smart-79c9bd46-85d8-469b-ac7d-0edae4285191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478457999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3478457999
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2652779644
Short name T324
Test name
Test status
Simulation time 177142992 ps
CPU time 3.26 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 239256 kb
Host smart-a412c180-c224-4bf6-9839-687bcf49618e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652779644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.2652779644
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1391562979
Short name T1270
Test name
Test status
Simulation time 3073697211 ps
CPU time 7.16 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:39 PM PDT 24
Peak memory 231092 kb
Host smart-b09116c8-08cd-4057-b29a-1b0f8812b205
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391562979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.1391562979
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3637186714
Short name T1259
Test name
Test status
Simulation time 1556503568 ps
CPU time 2.92 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:34 PM PDT 24
Peak memory 241528 kb
Host smart-2a1f38b5-9e8c-46b6-a920-1acbdfbf3a91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637186714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3637186714
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1932294283
Short name T1298
Test name
Test status
Simulation time 106386660 ps
CPU time 3.12 seconds
Started Jul 07 07:03:30 PM PDT 24
Finished Jul 07 07:03:33 PM PDT 24
Peak memory 247452 kb
Host smart-5089edc7-c70d-45a9-95fe-457b301920b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932294283 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1932294283
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3480083382
Short name T277
Test name
Test status
Simulation time 43288998 ps
CPU time 1.55 seconds
Started Jul 07 07:03:30 PM PDT 24
Finished Jul 07 07:03:32 PM PDT 24
Peak memory 240968 kb
Host smart-da077f49-e198-4a9b-abf7-ec8771d7d85a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480083382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3480083382
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3273628490
Short name T1309
Test name
Test status
Simulation time 591568617 ps
CPU time 1.96 seconds
Started Jul 07 07:03:30 PM PDT 24
Finished Jul 07 07:03:33 PM PDT 24
Peak memory 230376 kb
Host smart-dda37a04-7642-4b06-bbf8-95a3037be525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273628490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3273628490
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1117237729
Short name T1293
Test name
Test status
Simulation time 124818815 ps
CPU time 1.32 seconds
Started Jul 07 07:03:29 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 230204 kb
Host smart-3b0485bc-bd22-40ed-8fd3-8d7b28157f67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117237729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.1117237729
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1177675025
Short name T1268
Test name
Test status
Simulation time 557227614 ps
CPU time 2.03 seconds
Started Jul 07 07:03:29 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 229964 kb
Host smart-4d8e4162-6e53-4a9c-854a-99a8b862adda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177675025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1177675025
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2380020135
Short name T1315
Test name
Test status
Simulation time 135076633 ps
CPU time 2.41 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:34 PM PDT 24
Peak memory 239300 kb
Host smart-30437d3e-1289-4361-bb33-40a572c2dd91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380020135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2380020135
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4115631283
Short name T1314
Test name
Test status
Simulation time 659478419 ps
CPU time 6.5 seconds
Started Jul 07 07:03:32 PM PDT 24
Finished Jul 07 07:03:39 PM PDT 24
Peak memory 246504 kb
Host smart-204e6a5a-b83d-46d4-8dde-e50661eb529c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115631283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.4115631283
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2419158085
Short name T353
Test name
Test status
Simulation time 2306520726 ps
CPU time 20.11 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:52 PM PDT 24
Peak memory 244628 kb
Host smart-fb612cc7-ed92-4637-bd7a-cf7550d400f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419158085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2419158085
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2130327262
Short name T1319
Test name
Test status
Simulation time 140003009 ps
CPU time 3.03 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:55 PM PDT 24
Peak memory 246580 kb
Host smart-03d2aeb4-f7cd-4edb-ba64-3f578b24d7a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130327262 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2130327262
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2395881330
Short name T319
Test name
Test status
Simulation time 134657409 ps
CPU time 1.49 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 240788 kb
Host smart-365ac44f-d29e-41b2-833c-b3c832b9e522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395881330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2395881330
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.451028289
Short name T1199
Test name
Test status
Simulation time 114067358 ps
CPU time 1.59 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:54 PM PDT 24
Peak memory 231128 kb
Host smart-16151494-bcf0-486f-880d-24a6dcead8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451028289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.451028289
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1765596736
Short name T1258
Test name
Test status
Simulation time 249653466 ps
CPU time 2.37 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 239236 kb
Host smart-e070d00f-87a1-4f1f-b3da-0ce9db2986b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765596736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1765596736
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3631791225
Short name T1251
Test name
Test status
Simulation time 1018361343 ps
CPU time 6.11 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 246504 kb
Host smart-f71de514-5465-454b-a30d-36dae5f98902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631791225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3631791225
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3543176851
Short name T1202
Test name
Test status
Simulation time 127964188 ps
CPU time 2.23 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:54 PM PDT 24
Peak memory 247492 kb
Host smart-795e5fc0-7360-4ab4-bcac-fe99a3b3b684
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543176851 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3543176851
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3882336882
Short name T295
Test name
Test status
Simulation time 86090745 ps
CPU time 1.59 seconds
Started Jul 07 07:03:51 PM PDT 24
Finished Jul 07 07:03:52 PM PDT 24
Peak memory 241008 kb
Host smart-57e2f59f-278f-473b-93d2-d272baf626c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882336882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3882336882
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2329972715
Short name T1232
Test name
Test status
Simulation time 560911314 ps
CPU time 1.69 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:54 PM PDT 24
Peak memory 230296 kb
Host smart-888efd1b-777b-412f-ac02-ba9de8b85dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329972715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2329972715
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2233086025
Short name T1230
Test name
Test status
Simulation time 260358488 ps
CPU time 2.72 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:55 PM PDT 24
Peak memory 239068 kb
Host smart-b1f80f46-c226-4d85-96e2-05fa36387fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233086025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.2233086025
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2436075187
Short name T1219
Test name
Test status
Simulation time 63599528 ps
CPU time 3.42 seconds
Started Jul 07 07:03:48 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 246400 kb
Host smart-48f5413f-9660-43e9-83b4-42616874fb11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436075187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2436075187
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4240817385
Short name T352
Test name
Test status
Simulation time 616745528 ps
CPU time 10.49 seconds
Started Jul 07 07:03:53 PM PDT 24
Finished Jul 07 07:04:04 PM PDT 24
Peak memory 239400 kb
Host smart-9493e737-5d2a-45de-af9c-c4a80e2ebf56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240817385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.4240817385
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1330582615
Short name T1203
Test name
Test status
Simulation time 141765569 ps
CPU time 2.19 seconds
Started Jul 07 07:03:55 PM PDT 24
Finished Jul 07 07:03:57 PM PDT 24
Peak memory 245772 kb
Host smart-c0c1f47d-5046-4db4-930d-a515641d6de2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330582615 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1330582615
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.810207177
Short name T311
Test name
Test status
Simulation time 44166832 ps
CPU time 1.56 seconds
Started Jul 07 07:03:58 PM PDT 24
Finished Jul 07 07:04:00 PM PDT 24
Peak memory 239248 kb
Host smart-2afa76fe-3b05-4213-b503-dca00432b088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810207177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.810207177
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.395201266
Short name T1214
Test name
Test status
Simulation time 40740269 ps
CPU time 1.44 seconds
Started Jul 07 07:03:56 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 230284 kb
Host smart-cde6acfe-8a18-41ef-a375-99a73dc8ee80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395201266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.395201266
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1464616996
Short name T321
Test name
Test status
Simulation time 1007938258 ps
CPU time 3.18 seconds
Started Jul 07 07:03:56 PM PDT 24
Finished Jul 07 07:03:59 PM PDT 24
Peak memory 239188 kb
Host smart-00f968b1-602a-4f05-9edc-ba21e2a9be10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464616996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1464616996
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.858336883
Short name T1279
Test name
Test status
Simulation time 900281639 ps
CPU time 5.26 seconds
Started Jul 07 07:03:52 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 246304 kb
Host smart-3f8cc683-1102-4fc6-b685-c6a743014869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858336883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.858336883
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1989157434
Short name T1292
Test name
Test status
Simulation time 1742594702 ps
CPU time 5.19 seconds
Started Jul 07 07:03:55 PM PDT 24
Finished Jul 07 07:04:01 PM PDT 24
Peak memory 247512 kb
Host smart-158d5a73-a315-43ab-8def-b4dbaa78478d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989157434 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1989157434
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3864424293
Short name T306
Test name
Test status
Simulation time 562680189 ps
CPU time 2.26 seconds
Started Jul 07 07:03:58 PM PDT 24
Finished Jul 07 07:04:00 PM PDT 24
Peak memory 241108 kb
Host smart-9dfbfade-b82a-4291-a48f-ffdb03bdcf8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864424293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3864424293
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3749842882
Short name T1320
Test name
Test status
Simulation time 96256124 ps
CPU time 1.44 seconds
Started Jul 07 07:03:58 PM PDT 24
Finished Jul 07 07:04:00 PM PDT 24
Peak memory 231040 kb
Host smart-5268825e-8c0e-4a63-bfe4-db7bc4ff6d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749842882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3749842882
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1723690486
Short name T1249
Test name
Test status
Simulation time 1666648077 ps
CPU time 5.53 seconds
Started Jul 07 07:03:56 PM PDT 24
Finished Jul 07 07:04:01 PM PDT 24
Peak memory 242364 kb
Host smart-33dea58a-8253-486e-8c08-9db916a17737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723690486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1723690486
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1200809137
Short name T1276
Test name
Test status
Simulation time 49935099 ps
CPU time 2.9 seconds
Started Jul 07 07:03:55 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 246396 kb
Host smart-8e234eaf-7a76-4a30-8b45-dfaa9d3a5330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200809137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1200809137
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1435228230
Short name T1243
Test name
Test status
Simulation time 757331753 ps
CPU time 10.31 seconds
Started Jul 07 07:03:54 PM PDT 24
Finished Jul 07 07:04:05 PM PDT 24
Peak memory 243948 kb
Host smart-5aa0e144-f7c6-4372-ae75-283c9af62ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435228230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1435228230
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2116843241
Short name T1261
Test name
Test status
Simulation time 282226424 ps
CPU time 4.01 seconds
Started Jul 07 07:03:54 PM PDT 24
Finished Jul 07 07:03:59 PM PDT 24
Peak memory 247484 kb
Host smart-4ed25991-15a1-44ef-8aa7-3f568e22b24a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116843241 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2116843241
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2011269646
Short name T1282
Test name
Test status
Simulation time 563263517 ps
CPU time 1.48 seconds
Started Jul 07 07:03:58 PM PDT 24
Finished Jul 07 07:04:00 PM PDT 24
Peak memory 239228 kb
Host smart-733c245f-ff41-4987-a1bc-ec3de86ebdd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011269646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2011269646
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1649228107
Short name T1227
Test name
Test status
Simulation time 77314415 ps
CPU time 1.37 seconds
Started Jul 07 07:03:55 PM PDT 24
Finished Jul 07 07:03:57 PM PDT 24
Peak memory 230336 kb
Host smart-b06df8f1-9b77-446e-bd48-dcaaf80a25eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649228107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1649228107
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.716788187
Short name T1247
Test name
Test status
Simulation time 72912273 ps
CPU time 2.23 seconds
Started Jul 07 07:03:54 PM PDT 24
Finished Jul 07 07:03:57 PM PDT 24
Peak memory 242080 kb
Host smart-690d2f0e-5091-429a-b3a5-55ec8c906eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716788187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c
trl_same_csr_outstanding.716788187
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3401145091
Short name T1305
Test name
Test status
Simulation time 285461185 ps
CPU time 5.92 seconds
Started Jul 07 07:04:00 PM PDT 24
Finished Jul 07 07:04:06 PM PDT 24
Peak memory 246420 kb
Host smart-84d53cb5-1322-47b6-9b41-ea8019b371b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401145091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3401145091
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2779759903
Short name T1236
Test name
Test status
Simulation time 106698350 ps
CPU time 3.57 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:03 PM PDT 24
Peak memory 247364 kb
Host smart-91908e5b-548c-4bcc-80bb-5a90ea3d10d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779759903 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2779759903
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3106247306
Short name T305
Test name
Test status
Simulation time 122252282 ps
CPU time 1.81 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:01 PM PDT 24
Peak memory 241656 kb
Host smart-d21d4ee7-980a-4dbe-9515-bf72ed59919f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106247306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3106247306
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.4083074766
Short name T1223
Test name
Test status
Simulation time 38142279 ps
CPU time 1.4 seconds
Started Jul 07 07:03:58 PM PDT 24
Finished Jul 07 07:04:00 PM PDT 24
Peak memory 231024 kb
Host smart-d72fff34-683a-458b-9776-010bec0aed16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083074766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.4083074766
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3328565426
Short name T1229
Test name
Test status
Simulation time 145150216 ps
CPU time 2.24 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:04 PM PDT 24
Peak memory 239216 kb
Host smart-e821500c-629e-4baa-9bfb-b8d0a05ae4b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328565426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.3328565426
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.4185033001
Short name T1311
Test name
Test status
Simulation time 177473707 ps
CPU time 5.14 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:05 PM PDT 24
Peak memory 246572 kb
Host smart-40b7ee92-2345-4b15-925d-ea27cb0699d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185033001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.4185033001
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1968711115
Short name T349
Test name
Test status
Simulation time 856043901 ps
CPU time 11.21 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 239368 kb
Host smart-b43fe705-f315-4634-8e01-87b99a861fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968711115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.1968711115
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1791484801
Short name T1322
Test name
Test status
Simulation time 258472039 ps
CPU time 3.02 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:04 PM PDT 24
Peak memory 247720 kb
Host smart-393a9bd6-1770-49d5-87e2-77f649116f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791484801 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1791484801
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2549785221
Short name T1244
Test name
Test status
Simulation time 118429941 ps
CPU time 1.82 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:01 PM PDT 24
Peak memory 239228 kb
Host smart-319928d8-a1d3-4636-9bca-21c2e8ed999b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549785221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2549785221
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2069604530
Short name T1294
Test name
Test status
Simulation time 569910095 ps
CPU time 1.55 seconds
Started Jul 07 07:03:56 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 231052 kb
Host smart-7a0a7db6-8010-4816-a333-77980df6dea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069604530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2069604530
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3712002863
Short name T1265
Test name
Test status
Simulation time 739271568 ps
CPU time 2.34 seconds
Started Jul 07 07:04:00 PM PDT 24
Finished Jul 07 07:04:02 PM PDT 24
Peak memory 242420 kb
Host smart-fbb950ee-3343-43fe-98e9-925d66c2bfae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712002863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.3712002863
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1372428984
Short name T1224
Test name
Test status
Simulation time 62520935 ps
CPU time 3.56 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:05 PM PDT 24
Peak memory 245812 kb
Host smart-68055b51-a691-480b-85b7-3c1940503dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372428984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1372428984
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3701522813
Short name T348
Test name
Test status
Simulation time 773134707 ps
CPU time 10.95 seconds
Started Jul 07 07:03:58 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 244144 kb
Host smart-85662ce3-c30e-4a41-84af-dc8ab43b166e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701522813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3701522813
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1593625810
Short name T1231
Test name
Test status
Simulation time 215039602 ps
CPU time 2.81 seconds
Started Jul 07 07:04:02 PM PDT 24
Finished Jul 07 07:04:06 PM PDT 24
Peak memory 245432 kb
Host smart-c5fb0682-d952-44e8-841c-3ac6f6baf6df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593625810 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.1593625810
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2126943676
Short name T1262
Test name
Test status
Simulation time 165811875 ps
CPU time 1.91 seconds
Started Jul 07 07:04:04 PM PDT 24
Finished Jul 07 07:04:06 PM PDT 24
Peak memory 241396 kb
Host smart-904faea0-5fe2-4338-9bf3-c20f584db322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126943676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2126943676
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1018778677
Short name T1264
Test name
Test status
Simulation time 86083840 ps
CPU time 1.35 seconds
Started Jul 07 07:03:59 PM PDT 24
Finished Jul 07 07:04:01 PM PDT 24
Peak memory 230600 kb
Host smart-1e4169dd-3285-40af-b043-a552db6e7efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018778677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1018778677
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1992189074
Short name T1303
Test name
Test status
Simulation time 158598375 ps
CPU time 2.95 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:04 PM PDT 24
Peak memory 239128 kb
Host smart-fc7421f2-17c0-473b-a629-1b10df61d42a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992189074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1992189074
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3857211153
Short name T1289
Test name
Test status
Simulation time 2695269746 ps
CPU time 6.9 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 246524 kb
Host smart-411f01d1-415b-4528-8fe5-1f9bec3be2af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857211153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3857211153
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.40496813
Short name T1280
Test name
Test status
Simulation time 215705706 ps
CPU time 3.29 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 246568 kb
Host smart-e69f2f10-6585-41cd-8155-dc544bb8daba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40496813 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.40496813
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.660754384
Short name T1296
Test name
Test status
Simulation time 71740597 ps
CPU time 1.49 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 239204 kb
Host smart-10f55cb0-5a9a-4c12-9e14-20203ce5febe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660754384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.660754384
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2283290118
Short name T1221
Test name
Test status
Simulation time 547560602 ps
CPU time 1.85 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 230204 kb
Host smart-5d9b5283-d178-4c78-a11e-d172e4eeb6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283290118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2283290118
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.492021371
Short name T1283
Test name
Test status
Simulation time 91423070 ps
CPU time 2 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 239176 kb
Host smart-f432defe-53f5-4295-8e9a-8cfb3db1713f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492021371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c
trl_same_csr_outstanding.492021371
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1399216340
Short name T1274
Test name
Test status
Simulation time 2406279860 ps
CPU time 6.8 seconds
Started Jul 07 07:04:00 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 246728 kb
Host smart-6ab2a5c1-76be-49a7-b270-761013539038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399216340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1399216340
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1443111557
Short name T279
Test name
Test status
Simulation time 2451045605 ps
CPU time 19.01 seconds
Started Jul 07 07:04:04 PM PDT 24
Finished Jul 07 07:04:23 PM PDT 24
Peak memory 244664 kb
Host smart-ffa1c2ff-0909-4c86-8ae4-cb90e851db64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443111557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1443111557
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.4275389084
Short name T1200
Test name
Test status
Simulation time 427780072 ps
CPU time 3.16 seconds
Started Jul 07 07:04:04 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 247456 kb
Host smart-1b806a79-18f4-43d1-832a-1100cf4bfedd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275389084 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.4275389084
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1516033639
Short name T1288
Test name
Test status
Simulation time 46419766 ps
CPU time 1.82 seconds
Started Jul 07 07:04:02 PM PDT 24
Finished Jul 07 07:04:04 PM PDT 24
Peak memory 241508 kb
Host smart-eae3b21f-c3b7-4a7d-9ef1-0969b929f6c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516033639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1516033639
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3786669991
Short name T1291
Test name
Test status
Simulation time 39600066 ps
CPU time 1.4 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 230980 kb
Host smart-7327a4a1-cc23-43dd-9f25-9977aa63a361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786669991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3786669991
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3009499796
Short name T320
Test name
Test status
Simulation time 80491358 ps
CPU time 2.81 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 239440 kb
Host smart-0f8004b0-0f8e-47ca-8389-be3e5124b2ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009499796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.3009499796
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.476959361
Short name T1313
Test name
Test status
Simulation time 224414652 ps
CPU time 3.65 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:05 PM PDT 24
Peak memory 246364 kb
Host smart-66d3791b-3b5c-490b-9315-bc6cb89c1a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476959361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.476959361
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.659719777
Short name T344
Test name
Test status
Simulation time 1316138607 ps
CPU time 9.06 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:16 PM PDT 24
Peak memory 244076 kb
Host smart-308b80eb-face-4285-ac95-a880bc5489a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659719777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_in
tg_err.659719777
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4175489476
Short name T276
Test name
Test status
Simulation time 65893090 ps
CPU time 3.08 seconds
Started Jul 07 07:03:34 PM PDT 24
Finished Jul 07 07:03:38 PM PDT 24
Peak memory 239260 kb
Host smart-227b2f20-4e2a-4758-abdc-af7d137e4ab4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175489476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.4175489476
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2960128897
Short name T1239
Test name
Test status
Simulation time 1226645681 ps
CPU time 4.9 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:50 PM PDT 24
Peak memory 238736 kb
Host smart-66086099-fc72-453e-9154-8b25d47c6378
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960128897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2960128897
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3933778706
Short name T1317
Test name
Test status
Simulation time 1000850949 ps
CPU time 2.19 seconds
Started Jul 07 07:03:37 PM PDT 24
Finished Jul 07 07:03:39 PM PDT 24
Peak memory 239204 kb
Host smart-dea49aa7-d7b3-4a3c-be33-ca76afb99255
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933778706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.3933778706
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1809840469
Short name T1217
Test name
Test status
Simulation time 223874879 ps
CPU time 2.85 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:48 PM PDT 24
Peak memory 247328 kb
Host smart-54cd05e6-0dea-455e-bd5d-e3679becfd9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809840469 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1809840469
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2096689828
Short name T312
Test name
Test status
Simulation time 51191488 ps
CPU time 1.76 seconds
Started Jul 07 07:03:34 PM PDT 24
Finished Jul 07 07:03:36 PM PDT 24
Peak memory 241396 kb
Host smart-0f7cfab1-6561-4fce-a7c5-dac58193ba4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096689828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2096689828
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3859989296
Short name T1201
Test name
Test status
Simulation time 39108337 ps
CPU time 1.4 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:33 PM PDT 24
Peak memory 230284 kb
Host smart-304a2e07-cf40-42ab-aa24-3f03553a5810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859989296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3859989296
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3639255042
Short name T1273
Test name
Test status
Simulation time 38638556 ps
CPU time 1.33 seconds
Started Jul 07 07:03:33 PM PDT 24
Finished Jul 07 07:03:34 PM PDT 24
Peak memory 229876 kb
Host smart-ae7036b1-12b5-4870-b770-fb967f0028cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639255042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3639255042
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1313668195
Short name T1297
Test name
Test status
Simulation time 45121989 ps
CPU time 1.32 seconds
Started Jul 07 07:03:29 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 229964 kb
Host smart-f398e17f-b815-4fe2-bcfb-fda7ded6be76
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313668195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.1313668195
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3634479884
Short name T318
Test name
Test status
Simulation time 79483897 ps
CPU time 2.39 seconds
Started Jul 07 07:03:33 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 242360 kb
Host smart-fab70c6e-8faa-4315-86da-528315d41c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634479884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3634479884
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3059078375
Short name T1237
Test name
Test status
Simulation time 191474412 ps
CPU time 4.66 seconds
Started Jul 07 07:03:31 PM PDT 24
Finished Jul 07 07:03:37 PM PDT 24
Peak memory 247196 kb
Host smart-41d3f26a-f744-4a01-88f8-14ac5ef13cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059078375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3059078375
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1952638586
Short name T346
Test name
Test status
Simulation time 9802837350 ps
CPU time 14.69 seconds
Started Jul 07 07:03:29 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 244488 kb
Host smart-f0a1dafd-8921-4695-902d-0030d2a82d82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952638586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.1952638586
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.168046807
Short name T1206
Test name
Test status
Simulation time 613072195 ps
CPU time 2.26 seconds
Started Jul 07 07:04:01 PM PDT 24
Finished Jul 07 07:04:04 PM PDT 24
Peak memory 230312 kb
Host smart-6c7d4bcb-5db8-4072-a0a8-f371c8aa0a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168046807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.168046807
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.381901880
Short name T1208
Test name
Test status
Simulation time 133800339 ps
CPU time 1.38 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 230504 kb
Host smart-fd024798-d80f-42ce-b8e6-bfa80f9c40a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381901880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.381901880
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2342718618
Short name T1323
Test name
Test status
Simulation time 136315025 ps
CPU time 1.49 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 230356 kb
Host smart-4cbaeb3a-ce12-41d7-873c-9249c14bcaeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342718618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2342718618
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1497353767
Short name T1245
Test name
Test status
Simulation time 39878485 ps
CPU time 1.44 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 231080 kb
Host smart-d9983e99-959b-4053-8383-546bcffaa900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497353767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1497353767
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3371695433
Short name T1278
Test name
Test status
Simulation time 41319214 ps
CPU time 1.55 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 230300 kb
Host smart-55a72c0e-847b-4536-a0a3-cfe3bd3880f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371695433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3371695433
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.2090988831
Short name T1255
Test name
Test status
Simulation time 70239601 ps
CPU time 1.48 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 231044 kb
Host smart-f4ff0d41-1fc6-4692-a4fb-197f52b92419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090988831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2090988831
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1647046881
Short name T1196
Test name
Test status
Simulation time 42590010 ps
CPU time 1.42 seconds
Started Jul 07 07:04:08 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 230572 kb
Host smart-160097fc-19e7-4b9c-9889-29a592e806ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647046881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1647046881
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1682344364
Short name T1253
Test name
Test status
Simulation time 95721654 ps
CPU time 1.54 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 231088 kb
Host smart-af0c56b5-63be-4549-855c-eaf1336a7572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682344364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1682344364
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2265629798
Short name T1225
Test name
Test status
Simulation time 46120243 ps
CPU time 1.39 seconds
Started Jul 07 07:04:09 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 230580 kb
Host smart-1a6600af-40b1-4157-a9cb-38f3897b3868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265629798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2265629798
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2486628156
Short name T1212
Test name
Test status
Simulation time 89191165 ps
CPU time 1.39 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 230336 kb
Host smart-c5970c51-87d6-4b74-af7e-5fddd609cb04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486628156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2486628156
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2117431332
Short name T294
Test name
Test status
Simulation time 81415229 ps
CPU time 5.27 seconds
Started Jul 07 07:03:36 PM PDT 24
Finished Jul 07 07:03:41 PM PDT 24
Peak memory 239272 kb
Host smart-986675af-ceda-45e2-9cee-adb7ac2d8e0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117431332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2117431332
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.775124213
Short name T325
Test name
Test status
Simulation time 4108292339 ps
CPU time 11.68 seconds
Started Jul 07 07:03:35 PM PDT 24
Finished Jul 07 07:03:46 PM PDT 24
Peak memory 239208 kb
Host smart-da932c59-6580-4060-8463-6c965fcfd6a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775124213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.775124213
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1371969282
Short name T309
Test name
Test status
Simulation time 201206461 ps
CPU time 1.99 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:47 PM PDT 24
Peak memory 239140 kb
Host smart-a01f0145-4798-4344-ba71-201f828259e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371969282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.1371969282
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.482894909
Short name T1240
Test name
Test status
Simulation time 186447410 ps
CPU time 4.4 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:49 PM PDT 24
Peak memory 247448 kb
Host smart-92dc5020-6b92-4809-acad-5aca06157e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482894909 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.482894909
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.641572258
Short name T317
Test name
Test status
Simulation time 41070900 ps
CPU time 1.52 seconds
Started Jul 07 07:03:33 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 241144 kb
Host smart-e70db1a3-02bc-4947-b953-4fc0e9428431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641572258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.641572258
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1908808298
Short name T1228
Test name
Test status
Simulation time 45845931 ps
CPU time 1.49 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:46 PM PDT 24
Peak memory 230624 kb
Host smart-31a842a6-ebde-4949-9cb2-2ba670f42fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908808298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1908808298
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3519073866
Short name T1266
Test name
Test status
Simulation time 65691569 ps
CPU time 1.42 seconds
Started Jul 07 07:03:34 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 230160 kb
Host smart-140b48ac-6480-4d6b-a2a6-57a062a6ba2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519073866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.3519073866
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2890902351
Short name T1209
Test name
Test status
Simulation time 109943211 ps
CPU time 1.37 seconds
Started Jul 07 07:03:34 PM PDT 24
Finished Jul 07 07:03:36 PM PDT 24
Peak memory 229980 kb
Host smart-f310a629-798a-48a9-ae1f-0f3efa61dabb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890902351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2890902351
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2574111328
Short name T1286
Test name
Test status
Simulation time 70073499 ps
CPU time 2.47 seconds
Started Jul 07 07:03:43 PM PDT 24
Finished Jul 07 07:03:46 PM PDT 24
Peak memory 239100 kb
Host smart-7f5e4844-2c1a-4bfb-b5de-edef1a904091
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574111328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.2574111328
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1554027831
Short name T1205
Test name
Test status
Simulation time 97455676 ps
CPU time 2.73 seconds
Started Jul 07 07:03:32 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 245992 kb
Host smart-a100c1a6-4550-4916-a843-5d945bfd22c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554027831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1554027831
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3101966813
Short name T1215
Test name
Test status
Simulation time 1323916400 ps
CPU time 9.71 seconds
Started Jul 07 07:03:34 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 244248 kb
Host smart-1382861a-d3ec-4cee-aff8-f18fc4e82040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101966813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3101966813
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.692538013
Short name T1321
Test name
Test status
Simulation time 79197713 ps
CPU time 1.41 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 231112 kb
Host smart-80b39fcf-4cbb-426c-8c8a-b802dcd8d540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692538013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.692538013
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.4172309279
Short name T1271
Test name
Test status
Simulation time 42047878 ps
CPU time 1.42 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:06 PM PDT 24
Peak memory 231092 kb
Host smart-3fc957ff-6141-459c-84db-e4a0e2bb900f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172309279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.4172309279
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.529840216
Short name T1198
Test name
Test status
Simulation time 589145299 ps
CPU time 1.67 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 230324 kb
Host smart-ef153699-9097-412e-bd12-ecd0ea15a67f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529840216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.529840216
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2041985756
Short name T1204
Test name
Test status
Simulation time 141245580 ps
CPU time 1.39 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 231048 kb
Host smart-c2f7c1d0-995a-46ce-9195-934ba463304e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041985756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2041985756
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.4173485020
Short name T1248
Test name
Test status
Simulation time 66799787 ps
CPU time 1.46 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 231060 kb
Host smart-00fc92af-aa60-4855-8ed0-08170c62ef07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173485020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.4173485020
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3286859266
Short name T1252
Test name
Test status
Simulation time 148607549 ps
CPU time 1.57 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 231084 kb
Host smart-3057e98d-e583-4fcc-8ba8-cb8f0df061fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286859266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3286859266
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1056794469
Short name T1238
Test name
Test status
Simulation time 42358994 ps
CPU time 1.41 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:07 PM PDT 24
Peak memory 230300 kb
Host smart-156f96e0-a6e7-4845-8396-acfb638c01ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056794469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1056794469
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.941393062
Short name T1284
Test name
Test status
Simulation time 138944181 ps
CPU time 1.47 seconds
Started Jul 07 07:04:06 PM PDT 24
Finished Jul 07 07:04:08 PM PDT 24
Peak memory 230268 kb
Host smart-fae10084-3e7a-4560-9d48-b620d65a9718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941393062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.941393062
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.427392761
Short name T1195
Test name
Test status
Simulation time 139827174 ps
CPU time 1.57 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:09 PM PDT 24
Peak memory 230324 kb
Host smart-e77ce0e7-009e-4a24-9b1b-94bb7298b265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427392761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.427392761
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.458218310
Short name T1263
Test name
Test status
Simulation time 40533978 ps
CPU time 1.42 seconds
Started Jul 07 07:04:05 PM PDT 24
Finished Jul 07 07:04:06 PM PDT 24
Peak memory 230628 kb
Host smart-c11c84f2-7be8-4510-942e-3603be7b5576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458218310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.458218310
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2201783335
Short name T308
Test name
Test status
Simulation time 1175296674 ps
CPU time 5.16 seconds
Started Jul 07 07:03:36 PM PDT 24
Finished Jul 07 07:03:41 PM PDT 24
Peak memory 239204 kb
Host smart-b696707c-5616-42ea-99ea-c2801745f71e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201783335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.2201783335
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1991557055
Short name T296
Test name
Test status
Simulation time 500318270 ps
CPU time 7.43 seconds
Started Jul 07 07:03:36 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 239216 kb
Host smart-66546d2d-0139-4dcf-9f2f-1d105a8421e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991557055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.1991557055
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2444620560
Short name T307
Test name
Test status
Simulation time 383047750 ps
CPU time 2.69 seconds
Started Jul 07 07:03:37 PM PDT 24
Finished Jul 07 07:03:40 PM PDT 24
Peak memory 241032 kb
Host smart-408abc1c-bebb-49a0-9a51-bdce7d8502bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444620560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.2444620560
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2439916387
Short name T1277
Test name
Test status
Simulation time 154601175 ps
CPU time 3.07 seconds
Started Jul 07 07:03:39 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 247484 kb
Host smart-e24b71c0-0d11-40b8-8a7c-898a58524438
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439916387 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.2439916387
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1454311574
Short name T1281
Test name
Test status
Simulation time 65671382 ps
CPU time 1.65 seconds
Started Jul 07 07:03:40 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 241096 kb
Host smart-de68017f-6570-43a5-ac3c-2ed1d698ecb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454311574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1454311574
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3621699388
Short name T1207
Test name
Test status
Simulation time 39928088 ps
CPU time 1.47 seconds
Started Jul 07 07:03:36 PM PDT 24
Finished Jul 07 07:03:38 PM PDT 24
Peak memory 230612 kb
Host smart-ea242ca3-9115-4fb5-a8e5-01ecfdb7a746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621699388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3621699388
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3440905003
Short name T1213
Test name
Test status
Simulation time 133986500 ps
CPU time 1.36 seconds
Started Jul 07 07:03:38 PM PDT 24
Finished Jul 07 07:03:40 PM PDT 24
Peak memory 230736 kb
Host smart-f21f6faa-e2d1-4fe9-afbb-535aaf231246
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440905003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.3440905003
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2671510367
Short name T1197
Test name
Test status
Simulation time 78653911 ps
CPU time 1.43 seconds
Started Jul 07 07:03:36 PM PDT 24
Finished Jul 07 07:03:38 PM PDT 24
Peak memory 229892 kb
Host smart-556b7e0f-b676-4539-b418-b6533f144434
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671510367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2671510367
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3801062229
Short name T1254
Test name
Test status
Simulation time 678144574 ps
CPU time 1.94 seconds
Started Jul 07 07:03:37 PM PDT 24
Finished Jul 07 07:03:39 PM PDT 24
Peak memory 239192 kb
Host smart-5e115f60-ffa5-459e-9136-cac4599c16aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801062229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3801062229
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.4264568681
Short name T1302
Test name
Test status
Simulation time 2631438118 ps
CPU time 9.04 seconds
Started Jul 07 07:03:32 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 247168 kb
Host smart-26d49df2-2967-466e-b8d1-3882e4cd6c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264568681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.4264568681
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.874263516
Short name T356
Test name
Test status
Simulation time 5274259239 ps
CPU time 19.65 seconds
Started Jul 07 07:03:38 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 245984 kb
Host smart-e40776c0-50c4-4ddf-851e-172262b7e802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874263516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.874263516
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3782852372
Short name T1304
Test name
Test status
Simulation time 567291598 ps
CPU time 2.05 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 230304 kb
Host smart-576f9361-c3b3-488b-9aca-3b0dd13ae0e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782852372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3782852372
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3436838405
Short name T1220
Test name
Test status
Simulation time 554474726 ps
CPU time 1.96 seconds
Started Jul 07 07:04:07 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 230616 kb
Host smart-7992e0be-4471-4c43-97ad-7e63458f83dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436838405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3436838405
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2511462830
Short name T1235
Test name
Test status
Simulation time 149069851 ps
CPU time 1.6 seconds
Started Jul 07 07:04:09 PM PDT 24
Finished Jul 07 07:04:11 PM PDT 24
Peak memory 230328 kb
Host smart-14fdf8c0-91ef-4936-90ef-2db1baa24255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511462830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2511462830
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.235967924
Short name T1211
Test name
Test status
Simulation time 126763346 ps
CPU time 1.52 seconds
Started Jul 07 07:04:08 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 230248 kb
Host smart-713fcc68-fcea-4d1b-aca6-24b1bd298eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235967924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.235967924
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.1932923299
Short name T1250
Test name
Test status
Simulation time 562525846 ps
CPU time 1.69 seconds
Started Jul 07 07:04:08 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 231080 kb
Host smart-70997227-d98d-4841-90b1-43f4fc368a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932923299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.1932923299
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.4057383041
Short name T1267
Test name
Test status
Simulation time 133875042 ps
CPU time 1.38 seconds
Started Jul 07 07:04:12 PM PDT 24
Finished Jul 07 07:04:13 PM PDT 24
Peak memory 230344 kb
Host smart-7c305f62-63ae-43c6-852a-6581e2100eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057383041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.4057383041
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1233726855
Short name T1310
Test name
Test status
Simulation time 53244545 ps
CPU time 1.51 seconds
Started Jul 07 07:04:09 PM PDT 24
Finished Jul 07 07:04:11 PM PDT 24
Peak memory 231088 kb
Host smart-1969908a-83c4-4b2c-8ff7-1a31631e0766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233726855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1233726855
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.380357042
Short name T1307
Test name
Test status
Simulation time 71765998 ps
CPU time 1.44 seconds
Started Jul 07 07:04:09 PM PDT 24
Finished Jul 07 07:04:11 PM PDT 24
Peak memory 230284 kb
Host smart-d40eca14-de1c-4b10-9103-e9e8ae75646d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380357042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.380357042
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.738061745
Short name T1290
Test name
Test status
Simulation time 129847756 ps
CPU time 1.47 seconds
Started Jul 07 07:04:10 PM PDT 24
Finished Jul 07 07:04:12 PM PDT 24
Peak memory 230360 kb
Host smart-228614e8-e317-4a01-815f-27b70d7430f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738061745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.738061745
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.250822170
Short name T1256
Test name
Test status
Simulation time 41300566 ps
CPU time 1.57 seconds
Started Jul 07 07:04:09 PM PDT 24
Finished Jul 07 07:04:10 PM PDT 24
Peak memory 230996 kb
Host smart-634eab44-4f15-4593-9e4d-2d55fa34d36a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250822170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.250822170
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3652898370
Short name T1233
Test name
Test status
Simulation time 76637261 ps
CPU time 2.89 seconds
Started Jul 07 07:03:39 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 247488 kb
Host smart-234e47ac-b930-41d1-ab64-a9a6a243c2c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652898370 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3652898370
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2542340164
Short name T316
Test name
Test status
Simulation time 80013058 ps
CPU time 1.8 seconds
Started Jul 07 07:03:40 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 241684 kb
Host smart-1209ede1-9ce3-42ad-8922-4b98cfa1cd46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542340164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2542340164
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.261448508
Short name T1275
Test name
Test status
Simulation time 48473127 ps
CPU time 1.37 seconds
Started Jul 07 07:03:40 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 230328 kb
Host smart-782414f7-0121-4540-b926-9a7a9b0646b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261448508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.261448508
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3611163937
Short name T1234
Test name
Test status
Simulation time 2126984914 ps
CPU time 5.08 seconds
Started Jul 07 07:03:40 PM PDT 24
Finished Jul 07 07:03:45 PM PDT 24
Peak memory 239196 kb
Host smart-9a413194-9c9b-4a7e-874f-a09b2c471c98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611163937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3611163937
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2013008656
Short name T1312
Test name
Test status
Simulation time 129186782 ps
CPU time 3.94 seconds
Started Jul 07 07:03:41 PM PDT 24
Finished Jul 07 07:03:45 PM PDT 24
Peak memory 239408 kb
Host smart-2bd0604e-d671-4d73-8d70-8578c595ca68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013008656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2013008656
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1260326643
Short name T354
Test name
Test status
Simulation time 1442882728 ps
CPU time 11.17 seconds
Started Jul 07 07:03:43 PM PDT 24
Finished Jul 07 07:03:54 PM PDT 24
Peak memory 244024 kb
Host smart-8e825a9b-5414-4619-a552-c47ae13cc24f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260326643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1260326643
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4237216059
Short name T1226
Test name
Test status
Simulation time 204873453 ps
CPU time 3.02 seconds
Started Jul 07 07:03:41 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 247496 kb
Host smart-f4b32c05-3b85-455d-b1ad-b875b5676498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237216059 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.4237216059
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.40338201
Short name T1257
Test name
Test status
Simulation time 586403948 ps
CPU time 1.85 seconds
Started Jul 07 07:03:41 PM PDT 24
Finished Jul 07 07:03:43 PM PDT 24
Peak memory 239092 kb
Host smart-2c01a3af-83f4-488f-8ede-6dc3dfb643c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40338201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.40338201
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1486540387
Short name T1242
Test name
Test status
Simulation time 38496308 ps
CPU time 1.36 seconds
Started Jul 07 07:03:40 PM PDT 24
Finished Jul 07 07:03:42 PM PDT 24
Peak memory 230996 kb
Host smart-73bc4611-7cb1-4a71-858e-ba6c82b7f6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486540387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1486540387
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2885086461
Short name T1299
Test name
Test status
Simulation time 101889898 ps
CPU time 3.06 seconds
Started Jul 07 07:03:42 PM PDT 24
Finished Jul 07 07:03:45 PM PDT 24
Peak memory 242292 kb
Host smart-727d0c87-4d87-4a33-a5cf-42656fc3f7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885086461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.2885086461
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3765981022
Short name T1218
Test name
Test status
Simulation time 758706415 ps
CPU time 3.08 seconds
Started Jul 07 07:03:41 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 239424 kb
Host smart-f683f8ce-3e6a-43c5-bb66-a0eb8a3fb87d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765981022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3765981022
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.55524825
Short name T351
Test name
Test status
Simulation time 4877941577 ps
CPU time 21.52 seconds
Started Jul 07 07:03:39 PM PDT 24
Finished Jul 07 07:04:01 PM PDT 24
Peak memory 246056 kb
Host smart-c62a2de0-8721-4685-af05-0bf509f92fae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55524825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg
_err.55524825
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1493159544
Short name T1269
Test name
Test status
Simulation time 1123178066 ps
CPU time 2.23 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:47 PM PDT 24
Peak memory 245032 kb
Host smart-ab6ef226-5484-41b6-a2bd-7158df68e8ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493159544 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1493159544
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3287796256
Short name T303
Test name
Test status
Simulation time 171366681 ps
CPU time 1.73 seconds
Started Jul 07 07:03:42 PM PDT 24
Finished Jul 07 07:03:44 PM PDT 24
Peak memory 241476 kb
Host smart-ddc306b6-7ea4-4b41-ba5e-9a8ba67b08f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287796256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3287796256
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3662647095
Short name T1316
Test name
Test status
Simulation time 50758011 ps
CPU time 1.49 seconds
Started Jul 07 07:03:43 PM PDT 24
Finished Jul 07 07:03:45 PM PDT 24
Peak memory 231352 kb
Host smart-f0647414-5034-4b0a-8a39-9b78f122df21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662647095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3662647095
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.789073427
Short name T1285
Test name
Test status
Simulation time 131408340 ps
CPU time 3.34 seconds
Started Jul 07 07:03:41 PM PDT 24
Finished Jul 07 07:03:45 PM PDT 24
Peak memory 242380 kb
Host smart-89942367-1a18-4f34-a245-91863b5187c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789073427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.789073427
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1847874784
Short name T1295
Test name
Test status
Simulation time 572763640 ps
CPU time 6.45 seconds
Started Jul 07 07:03:42 PM PDT 24
Finished Jul 07 07:03:49 PM PDT 24
Peak memory 239316 kb
Host smart-71eaff44-3613-4d34-9429-0ff466d69e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847874784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1847874784
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3056887728
Short name T355
Test name
Test status
Simulation time 1321050782 ps
CPU time 18.94 seconds
Started Jul 07 07:03:43 PM PDT 24
Finished Jul 07 07:04:02 PM PDT 24
Peak memory 244440 kb
Host smart-f9b823cb-3ac9-4d6f-b574-e958e5c52af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056887728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3056887728
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3711293441
Short name T1222
Test name
Test status
Simulation time 302940972 ps
CPU time 2.78 seconds
Started Jul 07 07:03:48 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 247428 kb
Host smart-d3ee1eb3-1283-4060-b421-299c91f3e7ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711293441 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3711293441
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3870777294
Short name T314
Test name
Test status
Simulation time 118314380 ps
CPU time 1.7 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:46 PM PDT 24
Peak memory 241480 kb
Host smart-6aca1ddb-6dd4-4385-b5c7-32106a1829b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870777294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3870777294
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3848220080
Short name T1301
Test name
Test status
Simulation time 73712776 ps
CPU time 1.45 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:45 PM PDT 24
Peak memory 230640 kb
Host smart-c59d3e13-3463-40e7-a052-1f729e6a5983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848220080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3848220080
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3406313633
Short name T315
Test name
Test status
Simulation time 2089448780 ps
CPU time 5.01 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:55 PM PDT 24
Peak memory 239160 kb
Host smart-8718a98b-99f1-4c8a-80b0-828558d8f770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406313633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.3406313633
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1385249721
Short name T1246
Test name
Test status
Simulation time 133253410 ps
CPU time 4.94 seconds
Started Jul 07 07:03:44 PM PDT 24
Finished Jul 07 07:03:50 PM PDT 24
Peak memory 246528 kb
Host smart-2e2c35e3-37c3-4081-ab28-40f4663b001c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385249721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.1385249721
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2306222052
Short name T345
Test name
Test status
Simulation time 2451603372 ps
CPU time 12.62 seconds
Started Jul 07 07:03:45 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 244396 kb
Host smart-55073bcc-81ba-4cbf-a64d-15e38caf433e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306222052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2306222052
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4106524232
Short name T1272
Test name
Test status
Simulation time 1169348731 ps
CPU time 4.16 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:53 PM PDT 24
Peak memory 246856 kb
Host smart-0f068f0e-c95f-41ea-997f-3978ce2d5263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106524232 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.4106524232
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.117619838
Short name T310
Test name
Test status
Simulation time 679347650 ps
CPU time 1.87 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 240968 kb
Host smart-2c3365fc-f7f2-4f4a-b497-97b548fcc781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117619838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.117619838
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1367172755
Short name T1308
Test name
Test status
Simulation time 64810077 ps
CPU time 1.47 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 231056 kb
Host smart-c59c7b31-5e4c-4e68-9ddc-e6eece878c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367172755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1367172755
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3389362189
Short name T1241
Test name
Test status
Simulation time 134526345 ps
CPU time 2.39 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:52 PM PDT 24
Peak memory 239256 kb
Host smart-4f1de5ff-bcef-4c2f-acbb-4a1833ba0091
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389362189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3389362189
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.4102945343
Short name T1216
Test name
Test status
Simulation time 112409528 ps
CPU time 4.33 seconds
Started Jul 07 07:03:49 PM PDT 24
Finished Jul 07 07:03:54 PM PDT 24
Peak memory 246320 kb
Host smart-d39a3075-62fc-404c-8ebb-9c4c299500f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102945343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.4102945343
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2717173116
Short name T347
Test name
Test status
Simulation time 823810208 ps
CPU time 11.49 seconds
Started Jul 07 07:03:50 PM PDT 24
Finished Jul 07 07:04:02 PM PDT 24
Peak memory 239240 kb
Host smart-7c5aa258-26d7-4cf2-bb5f-939a378432da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717173116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2717173116
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3285888519
Short name T486
Test name
Test status
Simulation time 734878558 ps
CPU time 15.26 seconds
Started Jul 07 07:04:11 PM PDT 24
Finished Jul 07 07:04:27 PM PDT 24
Peak memory 242532 kb
Host smart-f46fe42f-20d4-4659-b95f-de999a5a3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285888519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3285888519
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3657484194
Short name T44
Test name
Test status
Simulation time 21544090935 ps
CPU time 50.14 seconds
Started Jul 07 07:04:16 PM PDT 24
Finished Jul 07 07:05:06 PM PDT 24
Peak memory 245920 kb
Host smart-9748f56c-8adf-4c08-a198-165affaf8e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657484194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3657484194
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.435522908
Short name T782
Test name
Test status
Simulation time 1043490575 ps
CPU time 27.26 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:45 PM PDT 24
Peak memory 243272 kb
Host smart-b860e345-98e4-46c6-afca-519aa24819c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435522908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.435522908
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.264657769
Short name T1118
Test name
Test status
Simulation time 2094718746 ps
CPU time 28.48 seconds
Started Jul 07 07:04:11 PM PDT 24
Finished Jul 07 07:04:40 PM PDT 24
Peak memory 242964 kb
Host smart-138aa0d5-de0f-433c-ab5e-179d2aea03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264657769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.264657769
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.1702208059
Short name T890
Test name
Test status
Simulation time 418463286 ps
CPU time 3.48 seconds
Started Jul 07 07:04:10 PM PDT 24
Finished Jul 07 07:04:13 PM PDT 24
Peak memory 242116 kb
Host smart-04753aca-fddd-4441-b415-81553bbff111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702208059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1702208059
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3103823269
Short name T524
Test name
Test status
Simulation time 7587468062 ps
CPU time 11.59 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:29 PM PDT 24
Peak memory 241592 kb
Host smart-c2269ece-edba-411b-848d-d0d440d72da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103823269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3103823269
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.4116936221
Short name T300
Test name
Test status
Simulation time 2093734719 ps
CPU time 18.94 seconds
Started Jul 07 07:04:16 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 242568 kb
Host smart-09a41919-51cd-41d0-ad8b-6e175d012d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116936221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.4116936221
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.3110774779
Short name T806
Test name
Test status
Simulation time 3309148472 ps
CPU time 8.6 seconds
Started Jul 07 07:04:14 PM PDT 24
Finished Jul 07 07:04:23 PM PDT 24
Peak memory 242424 kb
Host smart-f8d273eb-d596-400b-9299-9a3d0d1f4fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110774779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3110774779
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2610707678
Short name T644
Test name
Test status
Simulation time 430730465 ps
CPU time 4.58 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:22 PM PDT 24
Peak memory 241944 kb
Host smart-3b55261d-6921-49b8-a6dd-7d379484e6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610707678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2610707678
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3249404525
Short name T851
Test name
Test status
Simulation time 1314287584 ps
CPU time 18.14 seconds
Started Jul 07 07:04:10 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 242684 kb
Host smart-7bf33c3a-ca1f-49d5-8038-bb1d3109a994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249404525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3249404525
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.574952448
Short name T531
Test name
Test status
Simulation time 11659070945 ps
CPU time 23.11 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:41 PM PDT 24
Peak memory 241456 kb
Host smart-f02d777a-2eaa-4d20-9414-12a5704f5721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574952448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.574952448
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1522499981
Short name T680
Test name
Test status
Simulation time 560032251 ps
CPU time 12.18 seconds
Started Jul 07 07:04:12 PM PDT 24
Finished Jul 07 07:04:24 PM PDT 24
Peak memory 242352 kb
Host smart-36ba090b-98ed-4d17-a741-e489bb504f9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522499981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1522499981
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.13623004
Short name T242
Test name
Test status
Simulation time 156050052078 ps
CPU time 175.37 seconds
Started Jul 07 07:04:12 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 275964 kb
Host smart-1c785b1c-b995-448f-939c-a3435ff447ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13623004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.13623004
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.885179992
Short name T479
Test name
Test status
Simulation time 6518479746 ps
CPU time 17.39 seconds
Started Jul 07 07:04:10 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 242932 kb
Host smart-509b946e-6aec-4a46-bec2-b4a2af579f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885179992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.885179992
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3332951042
Short name T902
Test name
Test status
Simulation time 114119641147 ps
CPU time 1549.94 seconds
Started Jul 07 07:04:12 PM PDT 24
Finished Jul 07 07:30:03 PM PDT 24
Peak memory 305728 kb
Host smart-eb243754-f014-48cf-9ce3-a2408e3fd1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332951042 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3332951042
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3910108544
Short name T162
Test name
Test status
Simulation time 1036477883 ps
CPU time 13.58 seconds
Started Jul 07 07:04:15 PM PDT 24
Finished Jul 07 07:04:29 PM PDT 24
Peak memory 242068 kb
Host smart-1f006a21-db51-4d90-88a6-78817d720b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910108544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3910108544
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3321002441
Short name T251
Test name
Test status
Simulation time 169663920 ps
CPU time 1.64 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:04:21 PM PDT 24
Peak memory 240428 kb
Host smart-c5823de1-139e-4bf2-b1ea-86c1099e7f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321002441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3321002441
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1971180956
Short name T1016
Test name
Test status
Simulation time 819723424 ps
CPU time 17.76 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:04:36 PM PDT 24
Peak memory 241952 kb
Host smart-e02a3b38-9c24-44be-95fd-f72faf036913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971180956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1971180956
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1458488506
Short name T87
Test name
Test status
Simulation time 106536092 ps
CPU time 5.11 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:04:24 PM PDT 24
Peak memory 242124 kb
Host smart-6435a07a-77eb-4bfb-9676-21d1a37abd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458488506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1458488506
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.289421357
Short name T857
Test name
Test status
Simulation time 1492233802 ps
CPU time 23.21 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:04:42 PM PDT 24
Peak memory 242444 kb
Host smart-302959ac-f50e-44bb-8412-6a9edf8e05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289421357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.289421357
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1577825800
Short name T936
Test name
Test status
Simulation time 1939981215 ps
CPU time 23.57 seconds
Started Jul 07 07:04:16 PM PDT 24
Finished Jul 07 07:04:40 PM PDT 24
Peak memory 243008 kb
Host smart-e69f2f61-0a64-49ee-8eb1-27a80e8c2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577825800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1577825800
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.2468445777
Short name T399
Test name
Test status
Simulation time 2085788842 ps
CPU time 5.65 seconds
Started Jul 07 07:04:15 PM PDT 24
Finished Jul 07 07:04:21 PM PDT 24
Peak memory 241864 kb
Host smart-9b9b1343-6a4d-494a-8344-33ae027df6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468445777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2468445777
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.1740202079
Short name T201
Test name
Test status
Simulation time 4032171293 ps
CPU time 49.31 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:05:07 PM PDT 24
Peak memory 257088 kb
Host smart-f34bc70c-ff20-47cd-b40b-c0a1b9117604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740202079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1740202079
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3521866560
Short name T565
Test name
Test status
Simulation time 2964759149 ps
CPU time 20.59 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:04:40 PM PDT 24
Peak memory 242036 kb
Host smart-195a4217-9fd2-4749-80fc-a6d859c70341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521866560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3521866560
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.1307010877
Short name T862
Test name
Test status
Simulation time 1714853494 ps
CPU time 13.03 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:04:31 PM PDT 24
Peak memory 248728 kb
Host smart-a1b3e02f-e337-4a34-ad90-7350fc18f494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307010877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1307010877
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3204976389
Short name T1192
Test name
Test status
Simulation time 212322617 ps
CPU time 3.8 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:04:23 PM PDT 24
Peak memory 242124 kb
Host smart-7971665a-5beb-410e-9134-3f18abf5f482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204976389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3204976389
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.505794322
Short name T338
Test name
Test status
Simulation time 422385779 ps
CPU time 6.78 seconds
Started Jul 07 07:04:13 PM PDT 24
Finished Jul 07 07:04:20 PM PDT 24
Peak memory 242080 kb
Host smart-7d69b7a8-b7c9-447a-b08b-d23349d35742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505794322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.505794322
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3922843684
Short name T187
Test name
Test status
Simulation time 9833722742 ps
CPU time 16.26 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 242252 kb
Host smart-faeb5b24-5864-4403-a28d-2398674de2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922843684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3922843684
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.129761950
Short name T40
Test name
Test status
Simulation time 191748353810 ps
CPU time 2326.99 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:43:05 PM PDT 24
Peak memory 265288 kb
Host smart-51d3bce4-cb10-4892-b0fd-97d8dbe14280
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129761950 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.129761950
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3294706762
Short name T647
Test name
Test status
Simulation time 486729618 ps
CPU time 19.14 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:04:38 PM PDT 24
Peak memory 242292 kb
Host smart-aadfc453-dfaf-4abe-b7d0-2b32ea7aded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294706762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3294706762
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.568434138
Short name T758
Test name
Test status
Simulation time 48770611 ps
CPU time 1.72 seconds
Started Jul 07 07:04:50 PM PDT 24
Finished Jul 07 07:04:52 PM PDT 24
Peak memory 240244 kb
Host smart-9e42a246-22c4-46c7-a525-3f14e8f86744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568434138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.568434138
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1544049110
Short name T575
Test name
Test status
Simulation time 1708506437 ps
CPU time 28.36 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:05:12 PM PDT 24
Peak memory 242220 kb
Host smart-2064fa3a-4f90-4e5a-96cc-5f54b3a89a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544049110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1544049110
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2321028698
Short name T388
Test name
Test status
Simulation time 602868208 ps
CPU time 14.57 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:04:57 PM PDT 24
Peak memory 242200 kb
Host smart-c013a995-d248-488b-a37f-abc5e853275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321028698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2321028698
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.671049489
Short name T208
Test name
Test status
Simulation time 2515882514 ps
CPU time 53.26 seconds
Started Jul 07 07:04:44 PM PDT 24
Finished Jul 07 07:05:37 PM PDT 24
Peak memory 257072 kb
Host smart-509b60f0-2acc-4313-a798-f9a97f3c973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671049489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.671049489
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1213784646
Short name T1040
Test name
Test status
Simulation time 2282377835 ps
CPU time 20.16 seconds
Started Jul 07 07:04:44 PM PDT 24
Finished Jul 07 07:05:05 PM PDT 24
Peak memory 242344 kb
Host smart-c85e0bbb-5fdd-4372-8630-787ee0f98cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213784646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1213784646
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2538745113
Short name T560
Test name
Test status
Simulation time 965711070 ps
CPU time 23.34 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:05:07 PM PDT 24
Peak memory 242192 kb
Host smart-e1ec8e7f-2da7-47af-93fd-6a35063c3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538745113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2538745113
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2058573988
Short name T105
Test name
Test status
Simulation time 659458439 ps
CPU time 20.35 seconds
Started Jul 07 07:04:45 PM PDT 24
Finished Jul 07 07:05:06 PM PDT 24
Peak memory 242260 kb
Host smart-c9499d80-5b04-44a8-b75a-daa205439787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058573988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2058573988
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1800995130
Short name T360
Test name
Test status
Simulation time 346953371 ps
CPU time 6.73 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 242436 kb
Host smart-dcd1035d-4b6b-4bc8-ac51-565a2439acca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800995130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1800995130
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.889615530
Short name T417
Test name
Test status
Simulation time 678106640 ps
CPU time 7.13 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 241932 kb
Host smart-52182d19-ccb7-47e6-8b18-c30e4c16286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889615530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.889615530
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2364407389
Short name T110
Test name
Test status
Simulation time 14213740322 ps
CPU time 26.94 seconds
Started Jul 07 07:04:47 PM PDT 24
Finished Jul 07 07:05:14 PM PDT 24
Peak memory 242616 kb
Host smart-1cb4a597-777e-4c1a-84ea-09eb123b3ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364407389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2364407389
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.2700152980
Short name T476
Test name
Test status
Simulation time 90616248 ps
CPU time 2.83 seconds
Started Jul 07 07:08:12 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 242168 kb
Host smart-efd9895a-2ac4-436e-8d9a-656b2b1b28c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700152980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2700152980
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.3157922343
Short name T959
Test name
Test status
Simulation time 9495234983 ps
CPU time 25.97 seconds
Started Jul 07 07:08:13 PM PDT 24
Finished Jul 07 07:08:39 PM PDT 24
Peak memory 241948 kb
Host smart-6b2b2e96-f371-4c2b-aaf9-a27d07736b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157922343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3157922343
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.707438820
Short name T807
Test name
Test status
Simulation time 301986226 ps
CPU time 4.55 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 241888 kb
Host smart-c53114f8-3542-49f3-8217-da3add4854a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707438820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.707438820
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3803644149
Short name T753
Test name
Test status
Simulation time 308431217 ps
CPU time 4.01 seconds
Started Jul 07 07:08:13 PM PDT 24
Finished Jul 07 07:08:17 PM PDT 24
Peak memory 241928 kb
Host smart-6112dc4b-566f-44f1-99ab-23a2a38b23f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803644149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3803644149
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.4126760140
Short name T470
Test name
Test status
Simulation time 2256047120 ps
CPU time 7.44 seconds
Started Jul 07 07:08:13 PM PDT 24
Finished Jul 07 07:08:21 PM PDT 24
Peak memory 242028 kb
Host smart-538f4715-9338-45fc-bc46-218ff4d74669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126760140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.4126760140
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.2811246125
Short name T437
Test name
Test status
Simulation time 122714321 ps
CPU time 3.32 seconds
Started Jul 07 07:08:15 PM PDT 24
Finished Jul 07 07:08:19 PM PDT 24
Peak memory 242108 kb
Host smart-46f0268e-5142-4d82-97c6-0a4e48995aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811246125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2811246125
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.738059741
Short name T1128
Test name
Test status
Simulation time 4632106944 ps
CPU time 13.95 seconds
Started Jul 07 07:08:17 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 242012 kb
Host smart-4a3d868e-2a7c-4da3-8633-d3a1d7f310ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738059741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.738059741
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.624845536
Short name T1150
Test name
Test status
Simulation time 1532879444 ps
CPU time 3.79 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:20 PM PDT 24
Peak memory 242160 kb
Host smart-abab9627-713c-4c0f-beef-18682ce9b578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624845536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.624845536
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.4066008776
Short name T611
Test name
Test status
Simulation time 1525341937 ps
CPU time 5.94 seconds
Started Jul 07 07:08:14 PM PDT 24
Finished Jul 07 07:08:20 PM PDT 24
Peak memory 241720 kb
Host smart-9f57942a-fd26-4b79-a8b1-abad620a0c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066008776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.4066008776
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.418514756
Short name T50
Test name
Test status
Simulation time 238322865 ps
CPU time 4.4 seconds
Started Jul 07 07:08:14 PM PDT 24
Finished Jul 07 07:08:19 PM PDT 24
Peak memory 242148 kb
Host smart-6047ecb8-7a4b-40f4-9346-7667459c4a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418514756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.418514756
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.1851356255
Short name T1014
Test name
Test status
Simulation time 2083982122 ps
CPU time 7.92 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:24 PM PDT 24
Peak memory 242152 kb
Host smart-b8ac77e2-6a71-4989-a66e-ab4f303523d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851356255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1851356255
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.1460778830
Short name T888
Test name
Test status
Simulation time 263339024 ps
CPU time 7.64 seconds
Started Jul 07 07:08:17 PM PDT 24
Finished Jul 07 07:08:25 PM PDT 24
Peak memory 241784 kb
Host smart-b93b3074-e6b5-446b-ad70-d0e13401effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460778830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1460778830
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.820821439
Short name T1173
Test name
Test status
Simulation time 481287903 ps
CPU time 6.27 seconds
Started Jul 07 07:08:14 PM PDT 24
Finished Jul 07 07:08:21 PM PDT 24
Peak memory 242372 kb
Host smart-008e804a-d0c7-4638-9405-bbd3f579f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820821439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.820821439
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.776059590
Short name T123
Test name
Test status
Simulation time 330691515 ps
CPU time 6.24 seconds
Started Jul 07 07:08:15 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 241804 kb
Host smart-5552f37c-2946-44a7-a08e-97c46b9bd31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776059590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.776059590
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.244202062
Short name T859
Test name
Test status
Simulation time 300240620 ps
CPU time 4.15 seconds
Started Jul 07 07:08:19 PM PDT 24
Finished Jul 07 07:08:24 PM PDT 24
Peak memory 242144 kb
Host smart-9ce9fc00-b6ed-43fc-b107-975c78882128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244202062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.244202062
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.3219135344
Short name T457
Test name
Test status
Simulation time 172637231 ps
CPU time 1.71 seconds
Started Jul 07 07:04:53 PM PDT 24
Finished Jul 07 07:04:55 PM PDT 24
Peak memory 240452 kb
Host smart-87a4e15c-3801-431d-9981-505c1694a4cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219135344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3219135344
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3757921172
Short name T721
Test name
Test status
Simulation time 2397405839 ps
CPU time 30.78 seconds
Started Jul 07 07:04:55 PM PDT 24
Finished Jul 07 07:05:26 PM PDT 24
Peak memory 244404 kb
Host smart-eb754f5b-b85f-4e87-9823-14ecd6e52261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757921172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3757921172
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.815300720
Short name T917
Test name
Test status
Simulation time 779102601 ps
CPU time 9.7 seconds
Started Jul 07 07:04:52 PM PDT 24
Finished Jul 07 07:05:02 PM PDT 24
Peak memory 242472 kb
Host smart-1aa22f1c-b934-43f9-8aeb-2949dcd757d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815300720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.815300720
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.1321133710
Short name T701
Test name
Test status
Simulation time 2450330394 ps
CPU time 27.82 seconds
Started Jul 07 07:04:52 PM PDT 24
Finished Jul 07 07:05:21 PM PDT 24
Peak memory 248852 kb
Host smart-1e7aa0c7-d908-4452-8fde-e80742d9511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321133710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1321133710
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1258820609
Short name T989
Test name
Test status
Simulation time 300420128 ps
CPU time 5.02 seconds
Started Jul 07 07:04:52 PM PDT 24
Finished Jul 07 07:04:57 PM PDT 24
Peak memory 242156 kb
Host smart-86caae2a-29bd-44a9-a141-4409a2a2dc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258820609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1258820609
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.394543122
Short name T141
Test name
Test status
Simulation time 152642489 ps
CPU time 3.9 seconds
Started Jul 07 07:04:54 PM PDT 24
Finished Jul 07 07:04:58 PM PDT 24
Peak memory 241976 kb
Host smart-3d161744-f6ef-487c-9b65-9650e6bd4ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394543122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.394543122
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.3178789807
Short name T99
Test name
Test status
Simulation time 18141224854 ps
CPU time 54.34 seconds
Started Jul 07 07:04:54 PM PDT 24
Finished Jul 07 07:05:49 PM PDT 24
Peak memory 243260 kb
Host smart-3e6cdbb9-13c4-4fb1-984d-419c9d64eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178789807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3178789807
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.1692891845
Short name T391
Test name
Test status
Simulation time 653954553 ps
CPU time 5.55 seconds
Started Jul 07 07:04:50 PM PDT 24
Finished Jul 07 07:04:56 PM PDT 24
Peak memory 242240 kb
Host smart-73d71f6c-e189-4a44-bf50-7a583eead08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692891845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1692891845
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.2016609794
Short name T601
Test name
Test status
Simulation time 1624644859 ps
CPU time 21 seconds
Started Jul 07 07:04:53 PM PDT 24
Finished Jul 07 07:05:14 PM PDT 24
Peak memory 241976 kb
Host smart-291e9c1f-360b-4727-8120-e323c007e968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016609794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2016609794
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.1899185687
Short name T1106
Test name
Test status
Simulation time 537295249 ps
CPU time 10.18 seconds
Started Jul 07 07:04:53 PM PDT 24
Finished Jul 07 07:05:04 PM PDT 24
Peak memory 242184 kb
Host smart-1432c791-2313-4838-9f32-20c5f04cc44b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899185687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1899185687
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1909792831
Short name T1074
Test name
Test status
Simulation time 786255619 ps
CPU time 6.29 seconds
Started Jul 07 07:04:48 PM PDT 24
Finished Jul 07 07:04:54 PM PDT 24
Peak memory 242168 kb
Host smart-fa8533d2-1f35-4f9a-82b8-178a6eeb1f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909792831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1909792831
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.4267954035
Short name T1024
Test name
Test status
Simulation time 9517119987 ps
CPU time 18.21 seconds
Started Jul 07 07:04:55 PM PDT 24
Finished Jul 07 07:05:13 PM PDT 24
Peak memory 241812 kb
Host smart-e45d7397-67da-4bfc-8fa4-cbd48431e75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267954035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.4267954035
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.1841841882
Short name T794
Test name
Test status
Simulation time 7762439075 ps
CPU time 15.68 seconds
Started Jul 07 07:04:53 PM PDT 24
Finished Jul 07 07:05:09 PM PDT 24
Peak memory 243496 kb
Host smart-3f79929b-a461-4f45-8af0-39faa559c6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841841882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1841841882
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2752744401
Short name T117
Test name
Test status
Simulation time 385011951 ps
CPU time 4.46 seconds
Started Jul 07 07:08:14 PM PDT 24
Finished Jul 07 07:08:19 PM PDT 24
Peak memory 242056 kb
Host smart-45dc2e6f-4784-491b-937c-3c7594b1b61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752744401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2752744401
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.444981882
Short name T270
Test name
Test status
Simulation time 332400337 ps
CPU time 7.81 seconds
Started Jul 07 07:08:15 PM PDT 24
Finished Jul 07 07:08:23 PM PDT 24
Peak memory 242164 kb
Host smart-2baf0be8-2c7d-4df3-9244-ce3d07e2b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444981882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.444981882
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.2179665678
Short name T211
Test name
Test status
Simulation time 254708777 ps
CPU time 3.98 seconds
Started Jul 07 07:08:14 PM PDT 24
Finished Jul 07 07:08:18 PM PDT 24
Peak memory 241796 kb
Host smart-3653663e-cc1e-4d77-be3b-58ec0f52345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179665678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2179665678
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.4134315712
Short name T1170
Test name
Test status
Simulation time 171487983 ps
CPU time 4.68 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:21 PM PDT 24
Peak memory 248544 kb
Host smart-f73b6241-9692-4aec-a79a-a689c07753fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134315712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.4134315712
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.3293998546
Short name T213
Test name
Test status
Simulation time 141413890 ps
CPU time 3.88 seconds
Started Jul 07 07:08:15 PM PDT 24
Finished Jul 07 07:08:19 PM PDT 24
Peak memory 241900 kb
Host smart-241dfbea-073c-454d-8924-d9a25514bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293998546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3293998546
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.1704753095
Short name T750
Test name
Test status
Simulation time 449302254 ps
CPU time 5.64 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:24 PM PDT 24
Peak memory 242632 kb
Host smart-63a6b81a-700d-4d87-87ca-04c1f96f71d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704753095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1704753095
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.699166558
Short name T562
Test name
Test status
Simulation time 99439187 ps
CPU time 3.3 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 242204 kb
Host smart-9cefa29f-beef-44a7-943c-286616f7b39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699166558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.699166558
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.13120777
Short name T189
Test name
Test status
Simulation time 251757601 ps
CPU time 3.32 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:20 PM PDT 24
Peak memory 241992 kb
Host smart-9ad19ce5-fe36-49a1-93c5-917e95b3a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13120777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.13120777
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.3792959665
Short name T1028
Test name
Test status
Simulation time 194276551 ps
CPU time 5.67 seconds
Started Jul 07 07:08:17 PM PDT 24
Finished Jul 07 07:08:23 PM PDT 24
Peak memory 242308 kb
Host smart-b6e5e718-b3cd-431a-9149-60a4f0e7ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792959665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3792959665
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.3536464682
Short name T866
Test name
Test status
Simulation time 146061355 ps
CPU time 3.57 seconds
Started Jul 07 07:08:17 PM PDT 24
Finished Jul 07 07:08:21 PM PDT 24
Peak memory 242204 kb
Host smart-58a5c876-77a4-4d89-a990-60dfe5901bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536464682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3536464682
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.1025408482
Short name T215
Test name
Test status
Simulation time 328511486 ps
CPU time 13.49 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:30 PM PDT 24
Peak memory 242348 kb
Host smart-ae2bfea2-a755-49ea-a9b8-0c2799b1ad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025408482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1025408482
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.3270171124
Short name T756
Test name
Test status
Simulation time 146004914 ps
CPU time 3.78 seconds
Started Jul 07 07:08:17 PM PDT 24
Finished Jul 07 07:08:21 PM PDT 24
Peak memory 242476 kb
Host smart-fdeb4845-772d-4066-9d6e-e2775fc0ef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270171124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3270171124
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.179147460
Short name T941
Test name
Test status
Simulation time 149541696 ps
CPU time 4.45 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 241892 kb
Host smart-5a582130-f9fd-4980-840b-10007415b36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179147460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.179147460
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.1203911687
Short name T1159
Test name
Test status
Simulation time 916091503 ps
CPU time 16.26 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:32 PM PDT 24
Peak memory 242148 kb
Host smart-2ca35cca-9e4c-4225-bfd4-cdef3bd1f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203911687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1203911687
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.915027564
Short name T178
Test name
Test status
Simulation time 134634237 ps
CPU time 3.41 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:20 PM PDT 24
Peak memory 242072 kb
Host smart-adadd5b4-f44c-4eeb-9574-f720c8e2e8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915027564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.915027564
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.4212424263
Short name T569
Test name
Test status
Simulation time 901099463 ps
CPU time 13.53 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:32 PM PDT 24
Peak memory 241768 kb
Host smart-db13802e-9196-4862-918a-b0ec242988ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212424263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.4212424263
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.1582707664
Short name T28
Test name
Test status
Simulation time 119185109 ps
CPU time 4.31 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 242164 kb
Host smart-12e526a9-a98e-439f-b096-145eb00684b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582707664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1582707664
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.2400869627
Short name T1103
Test name
Test status
Simulation time 171631944 ps
CPU time 4.53 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 241996 kb
Host smart-b5fd1bc8-dffd-4882-a529-3f83dc961f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400869627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2400869627
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.620156148
Short name T549
Test name
Test status
Simulation time 184926391 ps
CPU time 1.92 seconds
Started Jul 07 07:05:00 PM PDT 24
Finished Jul 07 07:05:02 PM PDT 24
Peak memory 240228 kb
Host smart-3822a159-32c6-4177-979e-d921dbb5528c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620156148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.620156148
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.882803890
Short name T32
Test name
Test status
Simulation time 1042328329 ps
CPU time 17.27 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:20 PM PDT 24
Peak memory 242432 kb
Host smart-a60e8316-1cf7-4482-8cd6-ffcc3757311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882803890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.882803890
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.2246510045
Short name T97
Test name
Test status
Simulation time 6102857350 ps
CPU time 55.31 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:58 PM PDT 24
Peak memory 257416 kb
Host smart-c18618b8-a2d4-4353-856b-a88e93630862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246510045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2246510045
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.373640881
Short name T570
Test name
Test status
Simulation time 8821015142 ps
CPU time 13.12 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:15 PM PDT 24
Peak memory 248848 kb
Host smart-4b58a5ee-486b-4f72-8bd5-9e3b31a26f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373640881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.373640881
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.4281494310
Short name T682
Test name
Test status
Simulation time 248250849 ps
CPU time 4.54 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:06 PM PDT 24
Peak memory 242084 kb
Host smart-92ebbed1-07d8-470e-aa37-732b1a806159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281494310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.4281494310
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.718685789
Short name T894
Test name
Test status
Simulation time 3111161828 ps
CPU time 20.21 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:25 PM PDT 24
Peak memory 243340 kb
Host smart-6eb29d08-cbac-421c-947f-db3afb3374aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718685789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.718685789
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.583407733
Short name T1174
Test name
Test status
Simulation time 2780122878 ps
CPU time 39.49 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:42 PM PDT 24
Peak memory 243316 kb
Host smart-4db66852-615d-4627-9243-a448b0b67bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583407733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.583407733
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.4123269949
Short name T265
Test name
Test status
Simulation time 4726834705 ps
CPU time 15.52 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:20 PM PDT 24
Peak memory 242228 kb
Host smart-f48c7510-ca93-49a1-9726-e508eeb6b2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123269949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.4123269949
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.3936037233
Short name T430
Test name
Test status
Simulation time 457568764 ps
CPU time 13.81 seconds
Started Jul 07 07:04:58 PM PDT 24
Finished Jul 07 07:05:12 PM PDT 24
Peak memory 248736 kb
Host smart-92983df5-9815-477d-be33-3bcdfb4b229a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936037233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3936037233
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1112805768
Short name T1030
Test name
Test status
Simulation time 534388760 ps
CPU time 9.64 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:12 PM PDT 24
Peak memory 242052 kb
Host smart-47335a18-2608-4581-b284-44cb705662a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112805768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1112805768
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3481842020
Short name T927
Test name
Test status
Simulation time 4103525372 ps
CPU time 8.75 seconds
Started Jul 07 07:05:02 PM PDT 24
Finished Jul 07 07:05:11 PM PDT 24
Peak memory 242144 kb
Host smart-66ca09f4-adae-4f36-938f-7ff8b542bd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481842020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3481842020
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2143904449
Short name T1132
Test name
Test status
Simulation time 15935533783 ps
CPU time 167.59 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:07:52 PM PDT 24
Peak memory 250488 kb
Host smart-52708f4c-bad4-48a2-a87a-488e999b3b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143904449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2143904449
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1577568044
Short name T1111
Test name
Test status
Simulation time 1661974541247 ps
CPU time 2853.4 seconds
Started Jul 07 07:05:03 PM PDT 24
Finished Jul 07 07:52:38 PM PDT 24
Peak memory 315520 kb
Host smart-b0d87293-8754-43f2-9bf8-b81616bfd05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577568044 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1577568044
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.3155165353
Short name T903
Test name
Test status
Simulation time 178097404 ps
CPU time 4.36 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:24 PM PDT 24
Peak memory 242060 kb
Host smart-d8c64ab8-8291-411c-8c54-9af243589ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155165353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3155165353
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2940329330
Short name T930
Test name
Test status
Simulation time 775048798 ps
CPU time 10.02 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:28 PM PDT 24
Peak memory 241876 kb
Host smart-a8f75d57-1688-4196-9b5b-403bf4e845bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940329330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2940329330
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.4256704191
Short name T702
Test name
Test status
Simulation time 209495044 ps
CPU time 3.04 seconds
Started Jul 07 07:08:16 PM PDT 24
Finished Jul 07 07:08:19 PM PDT 24
Peak memory 242348 kb
Host smart-103821bc-7e5b-47da-b0ef-426e49dd4bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256704191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.4256704191
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.93719026
Short name T168
Test name
Test status
Simulation time 435941011 ps
CPU time 4.12 seconds
Started Jul 07 07:08:18 PM PDT 24
Finished Jul 07 07:08:23 PM PDT 24
Peak memory 241828 kb
Host smart-6fa55955-bb68-4438-a93e-e9b625521a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93719026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.93719026
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3936623744
Short name T609
Test name
Test status
Simulation time 154463336 ps
CPU time 3.12 seconds
Started Jul 07 07:08:19 PM PDT 24
Finished Jul 07 07:08:22 PM PDT 24
Peak memory 241920 kb
Host smart-d9bd5fce-6947-4fb0-b6ba-e683fd5199c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936623744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3936623744
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3707581948
Short name T1058
Test name
Test status
Simulation time 145548054 ps
CPU time 3.79 seconds
Started Jul 07 07:08:22 PM PDT 24
Finished Jul 07 07:08:26 PM PDT 24
Peak memory 242152 kb
Host smart-55294d3a-349f-4313-ba8b-c381a99b50fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707581948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3707581948
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.3812681642
Short name T799
Test name
Test status
Simulation time 255196844 ps
CPU time 3.96 seconds
Started Jul 07 07:08:22 PM PDT 24
Finished Jul 07 07:08:27 PM PDT 24
Peak memory 241916 kb
Host smart-5efa653f-6b49-457f-b56b-9bd0fa6b6a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812681642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3812681642
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3394253935
Short name T537
Test name
Test status
Simulation time 802756546 ps
CPU time 6.09 seconds
Started Jul 07 07:08:21 PM PDT 24
Finished Jul 07 07:08:28 PM PDT 24
Peak memory 241908 kb
Host smart-98f42fd1-2a94-4b2e-a2bf-4614cc2e0de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394253935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3394253935
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3094863838
Short name T546
Test name
Test status
Simulation time 105747520 ps
CPU time 4.11 seconds
Started Jul 07 07:08:22 PM PDT 24
Finished Jul 07 07:08:26 PM PDT 24
Peak memory 242184 kb
Host smart-bf26ad95-7e96-4584-a727-797ca3c557e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094863838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3094863838
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.3971950130
Short name T1060
Test name
Test status
Simulation time 4550506752 ps
CPU time 11.25 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 242340 kb
Host smart-3c870033-deca-4649-8e60-e6370af7168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971950130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3971950130
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3537966266
Short name T978
Test name
Test status
Simulation time 2217277527 ps
CPU time 5.82 seconds
Started Jul 07 07:08:22 PM PDT 24
Finished Jul 07 07:08:28 PM PDT 24
Peak memory 242120 kb
Host smart-4c7a0ec8-a4ef-4553-8a8f-50dbc1daac67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537966266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3537966266
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.2769007516
Short name T1108
Test name
Test status
Simulation time 1778112726 ps
CPU time 5.08 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:30 PM PDT 24
Peak memory 241968 kb
Host smart-0c07bbf6-59fd-4483-8f89-6cc34f279500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769007516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2769007516
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.4170695510
Short name T761
Test name
Test status
Simulation time 1864901681 ps
CPU time 7.19 seconds
Started Jul 07 07:08:21 PM PDT 24
Finished Jul 07 07:08:28 PM PDT 24
Peak memory 242148 kb
Host smart-f1b87bb4-07c4-413e-bcb2-8d5a5669c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170695510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.4170695510
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.1692601090
Short name T140
Test name
Test status
Simulation time 342721629 ps
CPU time 4.55 seconds
Started Jul 07 07:08:22 PM PDT 24
Finished Jul 07 07:08:27 PM PDT 24
Peak memory 242116 kb
Host smart-7ee9b6af-2399-4dc4-bdae-4542e092100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692601090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1692601090
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3418109851
Short name T642
Test name
Test status
Simulation time 1774875011 ps
CPU time 14.27 seconds
Started Jul 07 07:08:20 PM PDT 24
Finished Jul 07 07:08:34 PM PDT 24
Peak memory 242228 kb
Host smart-7db7d8ea-f80f-4364-bd99-bacde2f0065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418109851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3418109851
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3572730338
Short name T792
Test name
Test status
Simulation time 187174870 ps
CPU time 4.85 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:32 PM PDT 24
Peak memory 242144 kb
Host smart-36e050ea-55e2-408e-a99e-991e1c7c0b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572730338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3572730338
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3286350916
Short name T953
Test name
Test status
Simulation time 325118745 ps
CPU time 9.54 seconds
Started Jul 07 07:08:23 PM PDT 24
Finished Jul 07 07:08:33 PM PDT 24
Peak memory 241892 kb
Host smart-3b3fb847-a2fd-40ed-8265-35fb02f7ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286350916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3286350916
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1497215594
Short name T832
Test name
Test status
Simulation time 201582060 ps
CPU time 3.05 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 242384 kb
Host smart-bc4d701a-f38c-4aa0-aa0a-8af486c1c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497215594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1497215594
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2130208630
Short name T390
Test name
Test status
Simulation time 752464487 ps
CPU time 7.24 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:35 PM PDT 24
Peak memory 241828 kb
Host smart-e6fb3bec-6463-4a00-8c2d-a63528e72faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130208630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2130208630
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.1924935517
Short name T588
Test name
Test status
Simulation time 241691292 ps
CPU time 2.22 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:07 PM PDT 24
Peak memory 240388 kb
Host smart-5953d212-1337-473a-b05c-f7e091c823ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924935517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1924935517
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.782775635
Short name T120
Test name
Test status
Simulation time 1121663149 ps
CPU time 13.84 seconds
Started Jul 07 07:05:03 PM PDT 24
Finished Jul 07 07:05:17 PM PDT 24
Peak memory 244044 kb
Host smart-6f2d38c8-0bb1-40fe-9c51-d28b840059ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782775635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.782775635
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.597463367
Short name T744
Test name
Test status
Simulation time 4335664329 ps
CPU time 21.41 seconds
Started Jul 07 07:05:05 PM PDT 24
Finished Jul 07 07:05:27 PM PDT 24
Peak memory 241992 kb
Host smart-0da440d9-0dfe-4d9a-b95e-e52de48530bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597463367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.597463367
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.499539258
Short name T30
Test name
Test status
Simulation time 1316451641 ps
CPU time 17.09 seconds
Started Jul 07 07:05:03 PM PDT 24
Finished Jul 07 07:05:21 PM PDT 24
Peak memory 242424 kb
Host smart-5159d59b-7dc1-44b7-a171-11e92b7d07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499539258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.499539258
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.828813538
Short name T491
Test name
Test status
Simulation time 327996211 ps
CPU time 3.98 seconds
Started Jul 07 07:05:01 PM PDT 24
Finished Jul 07 07:05:05 PM PDT 24
Peak memory 241928 kb
Host smart-d906f75b-21cb-4d1f-baab-f54eade00599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828813538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.828813538
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.4105583624
Short name T720
Test name
Test status
Simulation time 149007464 ps
CPU time 4.73 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:10 PM PDT 24
Peak memory 242080 kb
Host smart-124ddc70-046e-4c6a-bc50-f94c3c5a24aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105583624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.4105583624
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.876528569
Short name T757
Test name
Test status
Simulation time 579254247 ps
CPU time 24.51 seconds
Started Jul 07 07:05:03 PM PDT 24
Finished Jul 07 07:05:28 PM PDT 24
Peak memory 242680 kb
Host smart-c6fad4bb-cfc4-4670-a823-3000db31c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876528569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.876528569
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1589062658
Short name T637
Test name
Test status
Simulation time 1755672024 ps
CPU time 17.08 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:21 PM PDT 24
Peak memory 241956 kb
Host smart-03bd6553-4acd-41cb-b3a2-127f763c479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589062658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1589062658
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2981916735
Short name T167
Test name
Test status
Simulation time 10342881448 ps
CPU time 21.96 seconds
Started Jul 07 07:05:00 PM PDT 24
Finished Jul 07 07:05:22 PM PDT 24
Peak memory 248788 kb
Host smart-47316eae-565d-4d91-9942-adc73f550309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981916735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2981916735
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.634306537
Short name T979
Test name
Test status
Simulation time 2811131096 ps
CPU time 5.45 seconds
Started Jul 07 07:05:01 PM PDT 24
Finished Jul 07 07:05:07 PM PDT 24
Peak memory 242208 kb
Host smart-4a5c54d6-5481-4688-9593-55c460de7b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634306537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.634306537
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3943039534
Short name T892
Test name
Test status
Simulation time 7422603583 ps
CPU time 39.35 seconds
Started Jul 07 07:05:04 PM PDT 24
Finished Jul 07 07:05:44 PM PDT 24
Peak memory 248828 kb
Host smart-00aee6cc-05fb-4c70-9082-9298828e0796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943039534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3943039534
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3674563843
Short name T2
Test name
Test status
Simulation time 754980169 ps
CPU time 8.28 seconds
Started Jul 07 07:05:07 PM PDT 24
Finished Jul 07 07:05:16 PM PDT 24
Peak memory 242276 kb
Host smart-4348e6fa-77fe-4fa6-82ce-65f5f908b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674563843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3674563843
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.694486096
Short name T696
Test name
Test status
Simulation time 765873057 ps
CPU time 5.6 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 241900 kb
Host smart-0f1cf876-ccad-47ad-a480-8ff23bb21007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694486096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.694486096
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.992000080
Short name T1094
Test name
Test status
Simulation time 1505634673 ps
CPU time 6.58 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:33 PM PDT 24
Peak memory 241912 kb
Host smart-8a1cf97d-f7c4-4342-9958-63a4673fca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992000080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.992000080
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.1200276516
Short name T972
Test name
Test status
Simulation time 324963621 ps
CPU time 19.25 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:44 PM PDT 24
Peak memory 241956 kb
Host smart-5a07a7be-2d9a-442e-a8e5-41c3be1779bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200276516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1200276516
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2011451985
Short name T1021
Test name
Test status
Simulation time 512086846 ps
CPU time 5.7 seconds
Started Jul 07 07:08:24 PM PDT 24
Finished Jul 07 07:08:30 PM PDT 24
Peak memory 241904 kb
Host smart-fd6cb76f-2396-4291-8143-c661c9456500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011451985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2011451985
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.864043752
Short name T624
Test name
Test status
Simulation time 2750543305 ps
CPU time 7.56 seconds
Started Jul 07 07:08:26 PM PDT 24
Finished Jul 07 07:08:34 PM PDT 24
Peak memory 241888 kb
Host smart-adacb44a-3fcb-42fb-bd1a-f4b5b9d12e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864043752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.864043752
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.5728440
Short name T492
Test name
Test status
Simulation time 170693220 ps
CPU time 5.07 seconds
Started Jul 07 07:08:26 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 241888 kb
Host smart-f0dbbb96-c203-49f1-8802-2980391e5295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5728440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.5728440
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1796275503
Short name T1051
Test name
Test status
Simulation time 1471248180 ps
CPU time 6.77 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:33 PM PDT 24
Peak memory 241940 kb
Host smart-404621c7-f2e3-4542-b630-a3c10a85a194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796275503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1796275503
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.1969694254
Short name T542
Test name
Test status
Simulation time 219950264 ps
CPU time 6.19 seconds
Started Jul 07 07:08:26 PM PDT 24
Finished Jul 07 07:08:33 PM PDT 24
Peak memory 241840 kb
Host smart-34694576-9e8d-4de1-abd1-3eaa4dfa531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969694254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1969694254
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2218401663
Short name T534
Test name
Test status
Simulation time 109644402 ps
CPU time 3.84 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 241868 kb
Host smart-c11f29a9-4584-48c6-a492-9c764f8f9e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218401663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2218401663
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2697955829
Short name T389
Test name
Test status
Simulation time 583581514 ps
CPU time 13.23 seconds
Started Jul 07 07:08:25 PM PDT 24
Finished Jul 07 07:08:40 PM PDT 24
Peak memory 242028 kb
Host smart-c7b4da1d-62dc-41be-a3f3-9549bf8c3196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697955829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2697955829
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1285910713
Short name T666
Test name
Test status
Simulation time 1398105427 ps
CPU time 15.36 seconds
Started Jul 07 07:08:26 PM PDT 24
Finished Jul 07 07:08:42 PM PDT 24
Peak memory 241864 kb
Host smart-6d6ffae3-7c29-4150-8a8b-2d33040e86ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285910713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1285910713
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.855607529
Short name T669
Test name
Test status
Simulation time 295073458 ps
CPU time 4.81 seconds
Started Jul 07 07:08:29 PM PDT 24
Finished Jul 07 07:08:35 PM PDT 24
Peak memory 242072 kb
Host smart-7bf54e5e-9012-4771-a999-64a5a5557f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855607529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.855607529
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2556103973
Short name T567
Test name
Test status
Simulation time 166887571 ps
CPU time 8.34 seconds
Started Jul 07 07:08:30 PM PDT 24
Finished Jul 07 07:08:39 PM PDT 24
Peak memory 241892 kb
Host smart-e0b137d5-271f-4a94-878f-971664b136c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556103973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2556103973
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.1013270447
Short name T670
Test name
Test status
Simulation time 238902662 ps
CPU time 4.54 seconds
Started Jul 07 07:08:26 PM PDT 24
Finished Jul 07 07:08:32 PM PDT 24
Peak memory 241916 kb
Host smart-c4309b1b-1a62-4d6a-9364-f09eba3d2681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013270447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.1013270447
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2487180046
Short name T1038
Test name
Test status
Simulation time 235571814 ps
CPU time 5.38 seconds
Started Jul 07 07:08:30 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 241860 kb
Host smart-ebebdb17-1dcb-4795-b8f3-8262457a8e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487180046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2487180046
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2159955561
Short name T733
Test name
Test status
Simulation time 186775577 ps
CPU time 3.98 seconds
Started Jul 07 07:08:29 PM PDT 24
Finished Jul 07 07:08:33 PM PDT 24
Peak memory 242148 kb
Host smart-a59a5249-affb-4d01-8fd0-c12a0c56079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159955561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2159955561
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.1621045759
Short name T462
Test name
Test status
Simulation time 48299000 ps
CPU time 1.68 seconds
Started Jul 07 07:05:15 PM PDT 24
Finished Jul 07 07:05:17 PM PDT 24
Peak memory 240256 kb
Host smart-6507479d-2da7-45d9-96af-a5f73f075adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621045759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1621045759
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2281014757
Short name T1104
Test name
Test status
Simulation time 4706048234 ps
CPU time 30.41 seconds
Started Jul 07 07:05:10 PM PDT 24
Finished Jul 07 07:05:41 PM PDT 24
Peak memory 248200 kb
Host smart-e3f2660d-1726-4430-a39b-266d95460b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281014757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2281014757
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.587663924
Short name T778
Test name
Test status
Simulation time 3153731785 ps
CPU time 15.8 seconds
Started Jul 07 07:05:08 PM PDT 24
Finished Jul 07 07:05:24 PM PDT 24
Peak memory 242336 kb
Host smart-a380dbdc-820c-4635-9501-7c9e11f9b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587663924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.587663924
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.3389810992
Short name T737
Test name
Test status
Simulation time 6519950075 ps
CPU time 18.18 seconds
Started Jul 07 07:05:09 PM PDT 24
Finished Jul 07 07:05:28 PM PDT 24
Peak memory 243128 kb
Host smart-103f4665-1883-45b9-98d4-998f6757b4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389810992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.3389810992
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.3608389220
Short name T481
Test name
Test status
Simulation time 384424894 ps
CPU time 3.78 seconds
Started Jul 07 07:05:10 PM PDT 24
Finished Jul 07 07:05:14 PM PDT 24
Peak memory 242012 kb
Host smart-2334ec28-ebc9-4340-bd56-c0219f6c4dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608389220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3608389220
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.891381244
Short name T194
Test name
Test status
Simulation time 14453385630 ps
CPU time 24.84 seconds
Started Jul 07 07:05:09 PM PDT 24
Finished Jul 07 07:05:35 PM PDT 24
Peak memory 248116 kb
Host smart-e9977739-b602-40e5-b709-7ffc6f6a0ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891381244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.891381244
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.2761683907
Short name T703
Test name
Test status
Simulation time 3310848438 ps
CPU time 21.6 seconds
Started Jul 07 07:05:11 PM PDT 24
Finished Jul 07 07:05:33 PM PDT 24
Peak memory 242028 kb
Host smart-6af80270-dfa9-4204-95d9-df601a8cd68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761683907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2761683907
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.355942271
Short name T527
Test name
Test status
Simulation time 1320417883 ps
CPU time 18.63 seconds
Started Jul 07 07:05:09 PM PDT 24
Finished Jul 07 07:05:28 PM PDT 24
Peak memory 242228 kb
Host smart-a0f99594-9b89-4277-8282-f19d909c8e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355942271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.355942271
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2340025644
Short name T371
Test name
Test status
Simulation time 867400348 ps
CPU time 6.74 seconds
Started Jul 07 07:05:08 PM PDT 24
Finished Jul 07 07:05:15 PM PDT 24
Peak memory 241996 kb
Host smart-fadd960d-c333-4082-bedc-884efcee6d2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340025644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2340025644
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1123306652
Short name T1193
Test name
Test status
Simulation time 1558855092 ps
CPU time 12.23 seconds
Started Jul 07 07:05:07 PM PDT 24
Finished Jul 07 07:05:19 PM PDT 24
Peak memory 242188 kb
Host smart-89ad713a-4759-4add-b95c-3b4a81a0e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123306652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1123306652
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.2091746308
Short name T1187
Test name
Test status
Simulation time 54523170879 ps
CPU time 287.48 seconds
Started Jul 07 07:05:09 PM PDT 24
Finished Jul 07 07:09:57 PM PDT 24
Peak memory 310444 kb
Host smart-d2160f34-60ea-4d8c-bb49-4f6094a0f7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091746308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.2091746308
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.326840986
Short name T261
Test name
Test status
Simulation time 39106546767 ps
CPU time 320.77 seconds
Started Jul 07 07:05:09 PM PDT 24
Finished Jul 07 07:10:31 PM PDT 24
Peak memory 257068 kb
Host smart-334bae58-da9d-460b-b32a-1bfddd4261ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326840986 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.326840986
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2984902453
Short name T512
Test name
Test status
Simulation time 4891338694 ps
CPU time 34.48 seconds
Started Jul 07 07:05:10 PM PDT 24
Finished Jul 07 07:05:45 PM PDT 24
Peak memory 248816 kb
Host smart-01095528-c852-49f9-ac84-977e16d5b41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984902453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2984902453
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2307677733
Short name T1181
Test name
Test status
Simulation time 116461101 ps
CPU time 4.09 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:32 PM PDT 24
Peak memory 242080 kb
Host smart-4b3580b6-f125-4eef-8ab8-80ffae5ab4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307677733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2307677733
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.2497752838
Short name T522
Test name
Test status
Simulation time 1019328740 ps
CPU time 22.28 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:50 PM PDT 24
Peak memory 241984 kb
Host smart-75318433-68af-470e-8b4d-6561b917240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497752838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.2497752838
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.722396474
Short name T660
Test name
Test status
Simulation time 511593751 ps
CPU time 3.89 seconds
Started Jul 07 07:08:27 PM PDT 24
Finished Jul 07 07:08:32 PM PDT 24
Peak memory 242164 kb
Host smart-dfbec047-512d-4d7e-b50f-fb9d5fee111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722396474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.722396474
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2922361495
Short name T1009
Test name
Test status
Simulation time 1904532891 ps
CPU time 7.24 seconds
Started Jul 07 07:08:34 PM PDT 24
Finished Jul 07 07:08:42 PM PDT 24
Peak memory 242020 kb
Host smart-21212ba7-0c64-40e3-97fd-8cb1d8c7ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922361495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2922361495
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.4107115202
Short name T172
Test name
Test status
Simulation time 147860078 ps
CPU time 3.73 seconds
Started Jul 07 07:08:32 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 242048 kb
Host smart-d60febf8-fc05-46a1-80d1-5eaeb926dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107115202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.4107115202
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2865812841
Short name T1017
Test name
Test status
Simulation time 1197231329 ps
CPU time 8.82 seconds
Started Jul 07 07:08:33 PM PDT 24
Finished Jul 07 07:08:42 PM PDT 24
Peak memory 241852 kb
Host smart-d6f288cc-e54a-4e5a-b152-9062ade12714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865812841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2865812841
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.4174481953
Short name T550
Test name
Test status
Simulation time 489965859 ps
CPU time 3.88 seconds
Started Jul 07 07:08:32 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 242380 kb
Host smart-c8c3c87b-2b57-4229-8d4d-b8b33ed7d651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174481953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.4174481953
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.48256191
Short name T825
Test name
Test status
Simulation time 9634330667 ps
CPU time 22.5 seconds
Started Jul 07 07:08:33 PM PDT 24
Finished Jul 07 07:08:57 PM PDT 24
Peak memory 241900 kb
Host smart-16deb5df-0a7f-4541-a8a3-ba490e889602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48256191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.48256191
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.244734917
Short name T151
Test name
Test status
Simulation time 1910558456 ps
CPU time 4.7 seconds
Started Jul 07 07:08:33 PM PDT 24
Finished Jul 07 07:08:39 PM PDT 24
Peak memory 242056 kb
Host smart-83362eef-2ccc-4012-bac3-3bd5874d37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244734917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.244734917
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.3192020015
Short name T422
Test name
Test status
Simulation time 2052563045 ps
CPU time 7 seconds
Started Jul 07 07:08:32 PM PDT 24
Finished Jul 07 07:08:39 PM PDT 24
Peak memory 241904 kb
Host smart-bdc0f061-1a79-4423-9e20-7fb791bffd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192020015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3192020015
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.436209467
Short name T822
Test name
Test status
Simulation time 257486990 ps
CPU time 4.18 seconds
Started Jul 07 07:08:33 PM PDT 24
Finished Jul 07 07:08:39 PM PDT 24
Peak memory 242232 kb
Host smart-ada82b2f-d8af-40ac-aba9-e19f416b3f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436209467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.436209467
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.505113150
Short name T1148
Test name
Test status
Simulation time 1763512108 ps
CPU time 13.36 seconds
Started Jul 07 07:08:32 PM PDT 24
Finished Jul 07 07:08:46 PM PDT 24
Peak memory 241956 kb
Host smart-7c224042-2661-4585-8e06-34b943d2b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505113150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.505113150
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2054333779
Short name T1112
Test name
Test status
Simulation time 2736588122 ps
CPU time 6.39 seconds
Started Jul 07 07:08:33 PM PDT 24
Finished Jul 07 07:08:41 PM PDT 24
Peak memory 242248 kb
Host smart-4092b09a-d09e-45b5-9adb-0a4bebede447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054333779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2054333779
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.4285681340
Short name T635
Test name
Test status
Simulation time 329865459 ps
CPU time 7.96 seconds
Started Jul 07 07:08:32 PM PDT 24
Finished Jul 07 07:08:40 PM PDT 24
Peak memory 242336 kb
Host smart-e643f45d-8eea-42b2-a754-a6f3d98ccebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285681340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.4285681340
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3913156425
Short name T1082
Test name
Test status
Simulation time 146908068 ps
CPU time 3.78 seconds
Started Jul 07 07:08:31 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 241940 kb
Host smart-d34be499-1ac3-464f-9bc0-453e5d826474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913156425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3913156425
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.195696933
Short name T618
Test name
Test status
Simulation time 398445088 ps
CPU time 4.5 seconds
Started Jul 07 07:08:30 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 241872 kb
Host smart-2b306f9a-ac5f-473c-bc4a-904dcd901220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195696933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.195696933
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.184567371
Short name T673
Test name
Test status
Simulation time 690628876 ps
CPU time 5.2 seconds
Started Jul 07 07:08:31 PM PDT 24
Finished Jul 07 07:08:37 PM PDT 24
Peak memory 242440 kb
Host smart-f129f3dd-3fd1-4456-9f85-f816f50c1759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184567371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.184567371
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2763629570
Short name T897
Test name
Test status
Simulation time 1172140058 ps
CPU time 9.77 seconds
Started Jul 07 07:08:30 PM PDT 24
Finished Jul 07 07:08:41 PM PDT 24
Peak memory 241824 kb
Host smart-b3731e44-98a5-4d0c-ac3e-b3873d40e4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763629570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2763629570
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.835781965
Short name T1007
Test name
Test status
Simulation time 432928705 ps
CPU time 12.7 seconds
Started Jul 07 07:08:35 PM PDT 24
Finished Jul 07 07:08:49 PM PDT 24
Peak memory 242256 kb
Host smart-d9d5be79-f48c-4e8a-82ed-54da1db7e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835781965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.835781965
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.3372648791
Short name T552
Test name
Test status
Simulation time 86262031 ps
CPU time 1.73 seconds
Started Jul 07 07:05:16 PM PDT 24
Finished Jul 07 07:05:18 PM PDT 24
Peak memory 240384 kb
Host smart-c941d9d3-9e1d-4f36-9318-87f7a9a954ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372648791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3372648791
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.4255388180
Short name T86
Test name
Test status
Simulation time 4977346258 ps
CPU time 23.01 seconds
Started Jul 07 07:05:11 PM PDT 24
Finished Jul 07 07:05:34 PM PDT 24
Peak memory 248880 kb
Host smart-f148c911-c631-49f6-a93e-3346e15a96fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255388180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.4255388180
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2097185674
Short name T920
Test name
Test status
Simulation time 909544848 ps
CPU time 15.49 seconds
Started Jul 07 07:05:14 PM PDT 24
Finished Jul 07 07:05:29 PM PDT 24
Peak memory 242056 kb
Host smart-1464d78d-d24e-44d4-8c06-362ac43df91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097185674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2097185674
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.909628453
Short name T987
Test name
Test status
Simulation time 583034585 ps
CPU time 10.89 seconds
Started Jul 07 07:05:12 PM PDT 24
Finished Jul 07 07:05:23 PM PDT 24
Peak memory 242544 kb
Host smart-40ea6283-6d2d-47f5-8310-3398c79f0ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909628453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.909628453
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.92976175
Short name T148
Test name
Test status
Simulation time 12472822292 ps
CPU time 27.03 seconds
Started Jul 07 07:05:12 PM PDT 24
Finished Jul 07 07:05:39 PM PDT 24
Peak memory 245948 kb
Host smart-8e7ebc7b-ff4d-424b-937b-3065981c2816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92976175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.92976175
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.3282959385
Short name T379
Test name
Test status
Simulation time 13988290048 ps
CPU time 33.32 seconds
Started Jul 07 07:05:14 PM PDT 24
Finished Jul 07 07:05:48 PM PDT 24
Peak memory 242276 kb
Host smart-3c650a61-fb21-46fa-8727-a34e1e862278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282959385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3282959385
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.2882968684
Short name T726
Test name
Test status
Simulation time 428128221 ps
CPU time 11.32 seconds
Started Jul 07 07:05:14 PM PDT 24
Finished Jul 07 07:05:26 PM PDT 24
Peak memory 248280 kb
Host smart-a44a0248-7c6a-4ca2-8130-9107c340c3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882968684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2882968684
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.2653416529
Short name T968
Test name
Test status
Simulation time 8596945388 ps
CPU time 22.47 seconds
Started Jul 07 07:05:14 PM PDT 24
Finished Jul 07 07:05:37 PM PDT 24
Peak memory 242156 kb
Host smart-1457153b-d466-44be-8a7e-6376f609e4c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653416529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2653416529
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.1963431046
Short name T718
Test name
Test status
Simulation time 449483283 ps
CPU time 3.23 seconds
Started Jul 07 07:05:12 PM PDT 24
Finished Jul 07 07:05:15 PM PDT 24
Peak memory 248592 kb
Host smart-59d5c7e6-0602-4170-b91a-c34a3f4e997f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963431046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1963431046
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.4195498734
Short name T712
Test name
Test status
Simulation time 223067387 ps
CPU time 5.5 seconds
Started Jul 07 07:05:14 PM PDT 24
Finished Jul 07 07:05:20 PM PDT 24
Peak memory 242268 kb
Host smart-50335df5-d844-4c2c-ba9b-2d6c5c994b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195498734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.4195498734
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2494515079
Short name T981
Test name
Test status
Simulation time 9570713398 ps
CPU time 162.04 seconds
Started Jul 07 07:05:13 PM PDT 24
Finished Jul 07 07:07:55 PM PDT 24
Peak memory 257072 kb
Host smart-2cdf579b-a319-49e1-8924-51ea172e48ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494515079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2494515079
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.85999288
Short name T1066
Test name
Test status
Simulation time 2729198297 ps
CPU time 20.91 seconds
Started Jul 07 07:05:10 PM PDT 24
Finished Jul 07 07:05:32 PM PDT 24
Peak memory 243328 kb
Host smart-6d08205a-59b4-47be-91fe-27c1e867b363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85999288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.85999288
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.1309188941
Short name T1027
Test name
Test status
Simulation time 331097677 ps
CPU time 4.72 seconds
Started Jul 07 07:08:35 PM PDT 24
Finished Jul 07 07:08:40 PM PDT 24
Peak memory 242156 kb
Host smart-febe9cbd-597c-46e2-a51e-347f976c57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309188941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1309188941
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.219368575
Short name T1019
Test name
Test status
Simulation time 224430971 ps
CPU time 12.1 seconds
Started Jul 07 07:08:36 PM PDT 24
Finished Jul 07 07:08:49 PM PDT 24
Peak memory 248640 kb
Host smart-c5fbc061-ff32-4f7d-bb04-bc1b34754fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219368575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.219368575
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.2879366301
Short name T450
Test name
Test status
Simulation time 564816495 ps
CPU time 4.02 seconds
Started Jul 07 07:08:33 PM PDT 24
Finished Jul 07 07:08:38 PM PDT 24
Peak memory 242252 kb
Host smart-bd291cfa-6acf-4bfb-b6ae-bad1e591a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879366301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2879366301
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.276005749
Short name T977
Test name
Test status
Simulation time 146094144 ps
CPU time 6.9 seconds
Started Jul 07 07:08:38 PM PDT 24
Finished Jul 07 07:08:45 PM PDT 24
Peak memory 241948 kb
Host smart-6c656a25-8e8e-464e-b76b-bde16a19cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276005749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.276005749
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1509965986
Short name T466
Test name
Test status
Simulation time 323394284 ps
CPU time 5.12 seconds
Started Jul 07 07:08:38 PM PDT 24
Finished Jul 07 07:08:44 PM PDT 24
Peak memory 242084 kb
Host smart-5df72724-9829-458a-a413-9b468de92404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509965986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1509965986
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.1191496982
Short name T446
Test name
Test status
Simulation time 522008744 ps
CPU time 8.86 seconds
Started Jul 07 07:08:40 PM PDT 24
Finished Jul 07 07:08:50 PM PDT 24
Peak memory 242312 kb
Host smart-7caaf0f1-79b4-40d8-8af6-95f785e83b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191496982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1191496982
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.174894675
Short name T610
Test name
Test status
Simulation time 138552201 ps
CPU time 3.65 seconds
Started Jul 07 07:08:40 PM PDT 24
Finished Jul 07 07:08:45 PM PDT 24
Peak memory 241912 kb
Host smart-fc99d483-7286-4096-9fc1-fe225a94d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174894675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.174894675
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2604586323
Short name T458
Test name
Test status
Simulation time 462888681 ps
CPU time 12.53 seconds
Started Jul 07 07:08:39 PM PDT 24
Finished Jul 07 07:08:52 PM PDT 24
Peak memory 241828 kb
Host smart-87063ffb-28f8-4795-bced-ee591a3393cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604586323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2604586323
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1373489521
Short name T1061
Test name
Test status
Simulation time 616073904 ps
CPU time 4.71 seconds
Started Jul 07 07:08:38 PM PDT 24
Finished Jul 07 07:08:43 PM PDT 24
Peak memory 242244 kb
Host smart-770b6ed6-cb3d-4c05-b8be-ab9ab2c46048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373489521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1373489521
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.630433890
Short name T781
Test name
Test status
Simulation time 245768278 ps
CPU time 3.41 seconds
Started Jul 07 07:08:40 PM PDT 24
Finished Jul 07 07:08:44 PM PDT 24
Peak memory 242284 kb
Host smart-2979a881-18f0-4ee4-9780-c77adcd2412a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630433890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.630433890
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.22331782
Short name T766
Test name
Test status
Simulation time 143244383 ps
CPU time 4.09 seconds
Started Jul 07 07:08:40 PM PDT 24
Finished Jul 07 07:08:45 PM PDT 24
Peak memory 241920 kb
Host smart-bf675b6c-9491-45c5-b9cf-1ac3214a1f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22331782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.22331782
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.282389625
Short name T1117
Test name
Test status
Simulation time 134978688 ps
CPU time 4.58 seconds
Started Jul 07 07:08:38 PM PDT 24
Finished Jul 07 07:08:44 PM PDT 24
Peak memory 242124 kb
Host smart-47ba968f-feed-4667-b1e0-41e007b2b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282389625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.282389625
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.913048482
Short name T1072
Test name
Test status
Simulation time 339912394 ps
CPU time 3.6 seconds
Started Jul 07 07:08:43 PM PDT 24
Finished Jul 07 07:08:47 PM PDT 24
Peak memory 242412 kb
Host smart-b0017954-7486-40eb-b446-bb0fa1036132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913048482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.913048482
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.1295951990
Short name T1101
Test name
Test status
Simulation time 963371231 ps
CPU time 22.9 seconds
Started Jul 07 07:08:45 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 241816 kb
Host smart-7408662c-d4a3-45ba-88b5-c3f7199df104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295951990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1295951990
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.1713673574
Short name T915
Test name
Test status
Simulation time 369091876 ps
CPU time 2.94 seconds
Started Jul 07 07:08:45 PM PDT 24
Finished Jul 07 07:08:49 PM PDT 24
Peak memory 242212 kb
Host smart-14766998-eb99-4ac3-8854-c409a84b770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713673574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1713673574
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.4232758334
Short name T589
Test name
Test status
Simulation time 243911418 ps
CPU time 5.23 seconds
Started Jul 07 07:08:44 PM PDT 24
Finished Jul 07 07:08:50 PM PDT 24
Peak memory 241820 kb
Host smart-1e7d1e53-0a8e-468e-9a39-0db04dddd331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232758334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.4232758334
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1568306451
Short name T535
Test name
Test status
Simulation time 1840582250 ps
CPU time 5.07 seconds
Started Jul 07 07:08:43 PM PDT 24
Finished Jul 07 07:08:48 PM PDT 24
Peak memory 242044 kb
Host smart-799da424-ef44-4fb3-a502-ab7b0a372b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568306451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1568306451
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.3805925517
Short name T819
Test name
Test status
Simulation time 659256930 ps
CPU time 4.7 seconds
Started Jul 07 07:08:44 PM PDT 24
Finished Jul 07 07:08:49 PM PDT 24
Peak memory 242216 kb
Host smart-a583772b-920f-4867-8ce0-fa20911b74e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805925517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3805925517
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.2670993924
Short name T419
Test name
Test status
Simulation time 48755241 ps
CPU time 1.63 seconds
Started Jul 07 07:05:16 PM PDT 24
Finished Jul 07 07:05:18 PM PDT 24
Peak memory 240324 kb
Host smart-8c23aff6-8cc0-4e17-abba-7981c879acd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670993924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2670993924
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.388570634
Short name T1168
Test name
Test status
Simulation time 397120821 ps
CPU time 9.09 seconds
Started Jul 07 07:05:14 PM PDT 24
Finished Jul 07 07:05:24 PM PDT 24
Peak memory 242036 kb
Host smart-6b13c05c-f5a8-467c-bede-dcea4879cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388570634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.388570634
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.3875094373
Short name T507
Test name
Test status
Simulation time 1027265958 ps
CPU time 15.27 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:36 PM PDT 24
Peak memory 242268 kb
Host smart-f2999659-9f44-4f8a-b682-e246f0f5c186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875094373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3875094373
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2359746125
Short name T743
Test name
Test status
Simulation time 1951899911 ps
CPU time 6.59 seconds
Started Jul 07 07:05:20 PM PDT 24
Finished Jul 07 07:05:27 PM PDT 24
Peak memory 241900 kb
Host smart-f03bc54b-bca2-47c4-9fc2-e799a73befb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359746125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2359746125
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.3390876355
Short name T594
Test name
Test status
Simulation time 16053172532 ps
CPU time 24.99 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:05:42 PM PDT 24
Peak memory 245296 kb
Host smart-cd3db265-3ba4-4ae6-a8f1-c4e7393c5568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390876355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3390876355
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2432993693
Short name T526
Test name
Test status
Simulation time 1849068212 ps
CPU time 21.18 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:05:39 PM PDT 24
Peak memory 242356 kb
Host smart-1a98da22-f2b3-4ff5-bf80-c1e601abca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432993693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2432993693
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.2993010292
Short name T672
Test name
Test status
Simulation time 1337095701 ps
CPU time 12.35 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:05:29 PM PDT 24
Peak memory 241892 kb
Host smart-acd2f129-dd80-490e-9ad7-5ac6e2eef138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993010292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2993010292
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2768920
Short name T407
Test name
Test status
Simulation time 606653609 ps
CPU time 10.61 seconds
Started Jul 07 07:05:16 PM PDT 24
Finished Jul 07 07:05:27 PM PDT 24
Peak memory 241900 kb
Host smart-493f6689-a0bd-4db1-b216-b565947948b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2768920
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.886894660
Short name T369
Test name
Test status
Simulation time 418779812 ps
CPU time 8.15 seconds
Started Jul 07 07:05:18 PM PDT 24
Finished Jul 07 07:05:27 PM PDT 24
Peak memory 242032 kb
Host smart-40ee9492-8c47-4850-b750-57f8116b4726
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886894660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.886894660
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.519370887
Short name T945
Test name
Test status
Simulation time 543040887 ps
CPU time 12.04 seconds
Started Jul 07 07:05:16 PM PDT 24
Finished Jul 07 07:05:28 PM PDT 24
Peak memory 242024 kb
Host smart-63ecb3bb-2ae1-4e42-b5de-5bdb2f9ed1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519370887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.519370887
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.80738714
Short name T375
Test name
Test status
Simulation time 3957658841 ps
CPU time 54.61 seconds
Started Jul 07 07:05:16 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 254984 kb
Host smart-f4e16aa8-0ef9-4eff-9342-7694b390e1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80738714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.80738714
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1939674315
Short name T821
Test name
Test status
Simulation time 12009141632 ps
CPU time 341.88 seconds
Started Jul 07 07:05:15 PM PDT 24
Finished Jul 07 07:10:57 PM PDT 24
Peak memory 257112 kb
Host smart-050b4afd-82b1-4bf2-900d-7f37ecdcd7bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939674315 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1939674315
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.2545250964
Short name T652
Test name
Test status
Simulation time 934497877 ps
CPU time 20.71 seconds
Started Jul 07 07:05:15 PM PDT 24
Finished Jul 07 07:05:36 PM PDT 24
Peak memory 242232 kb
Host smart-00196754-6506-4572-8335-123eef2e2ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545250964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2545250964
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.3712091298
Short name T420
Test name
Test status
Simulation time 111726235 ps
CPU time 4.37 seconds
Started Jul 07 07:08:42 PM PDT 24
Finished Jul 07 07:08:47 PM PDT 24
Peak memory 242120 kb
Host smart-8552791a-a62e-418f-b9a8-3dfdf466a711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712091298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3712091298
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3499548419
Short name T976
Test name
Test status
Simulation time 381781184 ps
CPU time 3.4 seconds
Started Jul 07 07:08:45 PM PDT 24
Finished Jul 07 07:08:50 PM PDT 24
Peak memory 241928 kb
Host smart-d82920e6-4dd2-4e3a-9272-519241a7912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499548419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3499548419
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3187160558
Short name T217
Test name
Test status
Simulation time 666674200 ps
CPU time 17.29 seconds
Started Jul 07 07:08:45 PM PDT 24
Finished Jul 07 07:09:03 PM PDT 24
Peak memory 242312 kb
Host smart-19e10fd5-4d0f-4207-8bbe-e3db69e2a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187160558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3187160558
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.318589632
Short name T60
Test name
Test status
Simulation time 139483037 ps
CPU time 4.97 seconds
Started Jul 07 07:08:45 PM PDT 24
Finished Jul 07 07:08:51 PM PDT 24
Peak memory 242068 kb
Host smart-032478a8-1442-4881-b056-a213f5dfb9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318589632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.318589632
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2297143812
Short name T428
Test name
Test status
Simulation time 2247223106 ps
CPU time 22.07 seconds
Started Jul 07 07:08:50 PM PDT 24
Finished Jul 07 07:09:12 PM PDT 24
Peak memory 242044 kb
Host smart-fbcfd341-098f-480e-afe8-14e0feafa4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297143812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2297143812
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3033628615
Short name T773
Test name
Test status
Simulation time 1770883360 ps
CPU time 6.63 seconds
Started Jul 07 07:08:49 PM PDT 24
Finished Jul 07 07:08:56 PM PDT 24
Peak memory 242068 kb
Host smart-8bebf51b-23c3-4fa7-87fe-fc33689f2b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033628615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3033628615
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2602344384
Short name T271
Test name
Test status
Simulation time 2418482052 ps
CPU time 17.83 seconds
Started Jul 07 07:08:52 PM PDT 24
Finished Jul 07 07:09:10 PM PDT 24
Peak memory 242372 kb
Host smart-1cd52cbf-dba5-4f6f-832c-7866c3304493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602344384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2602344384
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2879031573
Short name T89
Test name
Test status
Simulation time 2040978040 ps
CPU time 3.65 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:08:58 PM PDT 24
Peak memory 242384 kb
Host smart-e05775b3-9030-4c76-971f-e81390ea2637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879031573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2879031573
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.3416107764
Short name T254
Test name
Test status
Simulation time 434526838 ps
CPU time 11.45 seconds
Started Jul 07 07:08:53 PM PDT 24
Finished Jul 07 07:09:05 PM PDT 24
Peak memory 241828 kb
Host smart-5057e6f1-8f1c-4fa5-9404-326b9ab66967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416107764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3416107764
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.509662821
Short name T183
Test name
Test status
Simulation time 476041675 ps
CPU time 3.85 seconds
Started Jul 07 07:08:50 PM PDT 24
Finished Jul 07 07:08:54 PM PDT 24
Peak memory 241920 kb
Host smart-edd10a82-1aff-4563-ae1a-7c8e146f6282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509662821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.509662821
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.4234591027
Short name T485
Test name
Test status
Simulation time 1144966732 ps
CPU time 11.07 seconds
Started Jul 07 07:08:51 PM PDT 24
Finished Jul 07 07:09:03 PM PDT 24
Peak memory 242276 kb
Host smart-8caeb38d-20bf-48fb-98e7-2e409f821816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234591027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.4234591027
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.1210701665
Short name T967
Test name
Test status
Simulation time 229318902 ps
CPU time 4.21 seconds
Started Jul 07 07:08:50 PM PDT 24
Finished Jul 07 07:08:54 PM PDT 24
Peak memory 242124 kb
Host smart-67eccb23-9e67-40a4-b505-9b41f3cdec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210701665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1210701665
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.4172000655
Short name T1068
Test name
Test status
Simulation time 946965252 ps
CPU time 21.11 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 241896 kb
Host smart-4dbd9acd-fe32-4cce-b23b-5c9c9d0cdb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172000655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.4172000655
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.896185528
Short name T879
Test name
Test status
Simulation time 196792811 ps
CPU time 4.33 seconds
Started Jul 07 07:08:50 PM PDT 24
Finished Jul 07 07:08:54 PM PDT 24
Peak memory 241916 kb
Host smart-c0218375-478a-4d3e-866a-2f19414dfb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896185528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.896185528
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2030078530
Short name T646
Test name
Test status
Simulation time 201543257 ps
CPU time 6.01 seconds
Started Jul 07 07:08:48 PM PDT 24
Finished Jul 07 07:08:54 PM PDT 24
Peak memory 242020 kb
Host smart-5dc91917-a124-411b-b30f-0e5856947f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030078530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2030078530
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.2592755327
Short name T965
Test name
Test status
Simulation time 194179648 ps
CPU time 3.46 seconds
Started Jul 07 07:08:47 PM PDT 24
Finished Jul 07 07:08:51 PM PDT 24
Peak memory 241840 kb
Host smart-f88a9e5d-1d70-4d14-86a5-804ade708645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592755327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2592755327
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.4096513758
Short name T109
Test name
Test status
Simulation time 255927645 ps
CPU time 12.53 seconds
Started Jul 07 07:08:51 PM PDT 24
Finished Jul 07 07:09:04 PM PDT 24
Peak memory 241652 kb
Host smart-06a43b29-0948-40a8-8f40-e8cc2a4fe8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096513758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.4096513758
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3579857923
Short name T403
Test name
Test status
Simulation time 435427036 ps
CPU time 5.21 seconds
Started Jul 07 07:08:49 PM PDT 24
Finished Jul 07 07:08:55 PM PDT 24
Peak memory 242064 kb
Host smart-f5eb84ba-104a-4a94-85a3-b2b128b2a53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579857923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3579857923
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2200735114
Short name T1162
Test name
Test status
Simulation time 1652586922 ps
CPU time 7.12 seconds
Started Jul 07 07:08:49 PM PDT 24
Finished Jul 07 07:08:56 PM PDT 24
Peak memory 241760 kb
Host smart-62097883-6661-4f69-8f8a-218642dd7cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200735114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2200735114
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.2771964079
Short name T471
Test name
Test status
Simulation time 229893603 ps
CPU time 2.21 seconds
Started Jul 07 07:05:18 PM PDT 24
Finished Jul 07 07:05:20 PM PDT 24
Peak memory 240612 kb
Host smart-6d0b2ed5-b5f4-491d-b01d-e92cad7977f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771964079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2771964079
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1121527678
Short name T899
Test name
Test status
Simulation time 1371106703 ps
CPU time 16.77 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:38 PM PDT 24
Peak memory 248824 kb
Host smart-3844e4e9-5816-4171-a6f5-8c3d37f358a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121527678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1121527678
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1934069803
Short name T443
Test name
Test status
Simulation time 1221193176 ps
CPU time 13.66 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:05:31 PM PDT 24
Peak memory 242252 kb
Host smart-71a18162-643c-44cc-a71d-fe4d3111f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934069803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1934069803
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.3769032643
Short name T993
Test name
Test status
Simulation time 793307463 ps
CPU time 20.21 seconds
Started Jul 07 07:05:19 PM PDT 24
Finished Jul 07 07:05:40 PM PDT 24
Peak memory 248756 kb
Host smart-14525db7-932b-44b1-974c-ffed2e4436c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769032643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3769032643
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3856215109
Short name T996
Test name
Test status
Simulation time 252914572 ps
CPU time 3.42 seconds
Started Jul 07 07:05:19 PM PDT 24
Finished Jul 07 07:05:23 PM PDT 24
Peak memory 242164 kb
Host smart-6a76b671-986d-4afd-8986-53cb1e9dd84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856215109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3856215109
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3753068774
Short name T616
Test name
Test status
Simulation time 2191104269 ps
CPU time 19.81 seconds
Started Jul 07 07:05:22 PM PDT 24
Finished Jul 07 07:05:42 PM PDT 24
Peak memory 246084 kb
Host smart-e572e112-1a60-4e26-8e06-319dc4bc8cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753068774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3753068774
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.761048831
Short name T503
Test name
Test status
Simulation time 2887746275 ps
CPU time 30.68 seconds
Started Jul 07 07:05:19 PM PDT 24
Finished Jul 07 07:05:50 PM PDT 24
Peak memory 242712 kb
Host smart-3ac78d0e-2ed2-4357-8ff1-9495c1d01e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761048831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.761048831
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3773909412
Short name T876
Test name
Test status
Simulation time 1090859505 ps
CPU time 23.26 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:45 PM PDT 24
Peak memory 241788 kb
Host smart-51489fe3-4a49-4709-a122-25b50152f8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773909412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3773909412
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3038314371
Short name T754
Test name
Test status
Simulation time 1632168880 ps
CPU time 17.76 seconds
Started Jul 07 07:05:20 PM PDT 24
Finished Jul 07 07:05:38 PM PDT 24
Peak memory 248692 kb
Host smart-3758b522-60af-48fa-ab7d-d1000360958f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038314371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3038314371
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.526715839
Short name T606
Test name
Test status
Simulation time 756272466 ps
CPU time 7.39 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:05:25 PM PDT 24
Peak memory 242172 kb
Host smart-4d82b817-746a-4325-add3-eeb814b56db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526715839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.526715839
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2633668601
Short name T299
Test name
Test status
Simulation time 2297313653 ps
CPU time 5.74 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:05:23 PM PDT 24
Peak memory 242192 kb
Host smart-5fbb94c1-6ed1-4e6a-80f9-4eaee1561d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633668601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2633668601
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.1903354069
Short name T377
Test name
Test status
Simulation time 16064948660 ps
CPU time 106.24 seconds
Started Jul 07 07:05:17 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 270156 kb
Host smart-557a5a67-cae2-4aa1-83e0-8a805811a4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903354069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.1903354069
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.272412521
Short name T629
Test name
Test status
Simulation time 41627395458 ps
CPU time 905.73 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:20:27 PM PDT 24
Peak memory 411972 kb
Host smart-2f020eed-73b4-40c6-90f7-9f19276bd905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272412521 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.272412521
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3294898043
Short name T658
Test name
Test status
Simulation time 570268178 ps
CPU time 22.16 seconds
Started Jul 07 07:05:18 PM PDT 24
Finished Jul 07 07:05:40 PM PDT 24
Peak memory 242376 kb
Host smart-3031dc47-bfc2-454c-ae05-3eff1a092f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294898043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3294898043
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.2911611834
Short name T871
Test name
Test status
Simulation time 114385868 ps
CPU time 4.06 seconds
Started Jul 07 07:08:49 PM PDT 24
Finished Jul 07 07:08:53 PM PDT 24
Peak memory 242108 kb
Host smart-74cbd520-692c-4527-8e8f-c07fbe9dffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911611834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2911611834
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.747925055
Short name T483
Test name
Test status
Simulation time 138503331 ps
CPU time 5.46 seconds
Started Jul 07 07:08:48 PM PDT 24
Finished Jul 07 07:08:54 PM PDT 24
Peak memory 242368 kb
Host smart-6cc04701-7f60-4673-a8a2-74a0195fb00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747925055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.747925055
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.1403483100
Short name T51
Test name
Test status
Simulation time 2199644227 ps
CPU time 7.41 seconds
Started Jul 07 07:08:51 PM PDT 24
Finished Jul 07 07:08:59 PM PDT 24
Peak memory 241960 kb
Host smart-caddda2b-a081-457c-8621-09505a281d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403483100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.1403483100
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2590697290
Short name T762
Test name
Test status
Simulation time 266296098 ps
CPU time 10.05 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:09:05 PM PDT 24
Peak memory 242032 kb
Host smart-8acd5e0a-1b07-4cc0-aa5d-d1ff64b3c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590697290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2590697290
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.2774164480
Short name T547
Test name
Test status
Simulation time 2230828208 ps
CPU time 5.38 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 241816 kb
Host smart-f1522279-bbb6-4d5c-9aa0-6b595f3e5746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774164480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2774164480
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.2819750844
Short name T509
Test name
Test status
Simulation time 392963819 ps
CPU time 5.27 seconds
Started Jul 07 07:08:53 PM PDT 24
Finished Jul 07 07:08:58 PM PDT 24
Peak memory 241696 kb
Host smart-befc0cc9-2341-4028-9a5e-ac7b547c2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819750844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2819750844
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3219173606
Short name T1126
Test name
Test status
Simulation time 119944499 ps
CPU time 3.29 seconds
Started Jul 07 07:09:02 PM PDT 24
Finished Jul 07 07:09:06 PM PDT 24
Peak memory 241908 kb
Host smart-b0dca9eb-7bb7-490b-afc5-706e1783ae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219173606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3219173606
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2118013148
Short name T909
Test name
Test status
Simulation time 461563348 ps
CPU time 6.21 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 241904 kb
Host smart-a5cf6991-c914-4034-ac40-b4a620b12b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118013148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2118013148
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.3941011948
Short name T528
Test name
Test status
Simulation time 217339110 ps
CPU time 5.34 seconds
Started Jul 07 07:08:55 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 242080 kb
Host smart-7143562a-60f0-471c-99b8-dfa39251e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941011948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3941011948
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.783650431
Short name T657
Test name
Test status
Simulation time 145799996 ps
CPU time 5.49 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 242292 kb
Host smart-bad4a17f-89d7-47a1-84b5-8595442168cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783650431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.783650431
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2337437138
Short name T74
Test name
Test status
Simulation time 434967992 ps
CPU time 3.6 seconds
Started Jul 07 07:08:52 PM PDT 24
Finished Jul 07 07:08:56 PM PDT 24
Peak memory 242020 kb
Host smart-0e04a234-70fa-4448-93d3-4d9255fb1cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337437138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2337437138
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.113290772
Short name T983
Test name
Test status
Simulation time 95302724 ps
CPU time 3.14 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 241828 kb
Host smart-67cb5cf9-b5c2-4489-a98c-7d4ddfc19ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113290772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.113290772
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.2437314498
Short name T161
Test name
Test status
Simulation time 609642914 ps
CPU time 4.75 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 241840 kb
Host smart-f760363e-9cb9-4425-8ff4-46152fb8e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437314498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2437314498
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.4271319502
Short name T578
Test name
Test status
Simulation time 351418879 ps
CPU time 8.5 seconds
Started Jul 07 07:08:51 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 241952 kb
Host smart-bdc7c05b-0dd5-4187-84e0-77e55b4dca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271319502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.4271319502
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.299202960
Short name T816
Test name
Test status
Simulation time 14118882645 ps
CPU time 44.47 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:42 PM PDT 24
Peak memory 242268 kb
Host smart-ed027b11-7b25-4f13-8d10-de2e983303db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299202960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.299202960
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.935916546
Short name T1008
Test name
Test status
Simulation time 1681981704 ps
CPU time 5.31 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 242060 kb
Host smart-c97769ee-aae2-4514-a897-1c53780a8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935916546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.935916546
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.945148273
Short name T1116
Test name
Test status
Simulation time 215931880 ps
CPU time 6.14 seconds
Started Jul 07 07:09:11 PM PDT 24
Finished Jul 07 07:09:18 PM PDT 24
Peak memory 241872 kb
Host smart-75a3f36d-680e-4629-9796-e6c04b213abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945148273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.945148273
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.4293700083
Short name T880
Test name
Test status
Simulation time 264777561 ps
CPU time 4.07 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 242060 kb
Host smart-3abd8d8b-4691-4c9b-a2be-a53fdc0e2a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293700083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4293700083
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2218837930
Short name T516
Test name
Test status
Simulation time 5019500316 ps
CPU time 21.65 seconds
Started Jul 07 07:08:55 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 242416 kb
Host smart-05fbf0df-4ceb-4104-b3a6-fdef0cfe7e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218837930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2218837930
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1091239335
Short name T297
Test name
Test status
Simulation time 107433530 ps
CPU time 1.83 seconds
Started Jul 07 07:05:23 PM PDT 24
Finished Jul 07 07:05:25 PM PDT 24
Peak memory 240748 kb
Host smart-eebfb5c5-0a6f-4a1d-a187-253a4c82f429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091239335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1091239335
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.3367831607
Short name T662
Test name
Test status
Simulation time 768537224 ps
CPU time 14.36 seconds
Started Jul 07 07:05:28 PM PDT 24
Finished Jul 07 07:05:43 PM PDT 24
Peak memory 242128 kb
Host smart-ed8b6551-f84c-4155-82ab-e15bd0180c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367831607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3367831607
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1452445196
Short name T1015
Test name
Test status
Simulation time 424936793 ps
CPU time 4.23 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:25 PM PDT 24
Peak memory 242212 kb
Host smart-94be58e0-8ea7-427d-bdfd-f5ec9134a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452445196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1452445196
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1475394574
Short name T1191
Test name
Test status
Simulation time 101826470 ps
CPU time 3.66 seconds
Started Jul 07 07:05:22 PM PDT 24
Finished Jul 07 07:05:25 PM PDT 24
Peak memory 241952 kb
Host smart-bc30f107-fa44-40f0-8e9b-45ec31308f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475394574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1475394574
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.959618733
Short name T525
Test name
Test status
Simulation time 528855426 ps
CPU time 4.53 seconds
Started Jul 07 07:05:28 PM PDT 24
Finished Jul 07 07:05:33 PM PDT 24
Peak memory 242224 kb
Host smart-fc266343-944a-4c69-8f2f-3be44bc02267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959618733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.959618733
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.669168471
Short name T1048
Test name
Test status
Simulation time 1705811898 ps
CPU time 4.74 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:26 PM PDT 24
Peak memory 248652 kb
Host smart-0860295b-569c-4710-af6f-58f5c44bfcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669168471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.669168471
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3569295678
Short name T928
Test name
Test status
Simulation time 298542279 ps
CPU time 6.05 seconds
Started Jul 07 07:05:23 PM PDT 24
Finished Jul 07 07:05:29 PM PDT 24
Peak memory 241872 kb
Host smart-fd76fb06-2ad9-4173-8894-5046411f58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569295678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3569295678
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.4169348605
Short name T1002
Test name
Test status
Simulation time 171695360 ps
CPU time 4.41 seconds
Started Jul 07 07:05:19 PM PDT 24
Finished Jul 07 07:05:23 PM PDT 24
Peak memory 248280 kb
Host smart-f62d9cca-c038-4bbf-b6ec-2dd26166a72e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169348605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.4169348605
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.95820458
Short name T362
Test name
Test status
Simulation time 1920464266 ps
CPU time 4.98 seconds
Started Jul 07 07:05:23 PM PDT 24
Finished Jul 07 07:05:28 PM PDT 24
Peak memory 248424 kb
Host smart-7beccf2a-73d0-4f35-8af5-9524393e099e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95820458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.95820458
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3115486668
Short name T1164
Test name
Test status
Simulation time 222761098 ps
CPU time 4.75 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:26 PM PDT 24
Peak memory 242156 kb
Host smart-a950ee88-7834-4704-9255-4f38f4f09fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115486668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3115486668
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2158402231
Short name T645
Test name
Test status
Simulation time 41682582088 ps
CPU time 89.8 seconds
Started Jul 07 07:05:24 PM PDT 24
Finished Jul 07 07:06:55 PM PDT 24
Peak memory 257068 kb
Host smart-d764c023-860c-47e5-94b5-cdf56eb2f94c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158402231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2158402231
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3910118998
Short name T225
Test name
Test status
Simulation time 390990086056 ps
CPU time 2336.01 seconds
Started Jul 07 07:05:24 PM PDT 24
Finished Jul 07 07:44:21 PM PDT 24
Peak memory 392144 kb
Host smart-6bcd9f59-3e14-4faa-8b73-ee9de0a246d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910118998 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.3910118998
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2784936714
Short name T17
Test name
Test status
Simulation time 2263034367 ps
CPU time 33.39 seconds
Started Jul 07 07:05:24 PM PDT 24
Finished Jul 07 07:05:57 PM PDT 24
Peak memory 242348 kb
Host smart-b21bd2e2-60f0-4115-8d0d-3ed9bb823855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784936714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2784936714
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1419172843
Short name T1135
Test name
Test status
Simulation time 822342548 ps
CPU time 12.4 seconds
Started Jul 07 07:08:51 PM PDT 24
Finished Jul 07 07:09:04 PM PDT 24
Peak memory 241956 kb
Host smart-6816bc62-b9bd-4c1d-a483-07ec259241cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419172843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1419172843
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2611368728
Short name T1138
Test name
Test status
Simulation time 268333281 ps
CPU time 8.38 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:06 PM PDT 24
Peak memory 241900 kb
Host smart-690b3779-1a2b-47f7-a988-976fa92c43a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611368728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2611368728
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.1584676499
Short name T1144
Test name
Test status
Simulation time 330392354 ps
CPU time 4.48 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:02 PM PDT 24
Peak memory 241972 kb
Host smart-a1f12ea2-8580-46d4-a424-79a9c768bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584676499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1584676499
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.766925791
Short name T768
Test name
Test status
Simulation time 2121355263 ps
CPU time 29.51 seconds
Started Jul 07 07:08:58 PM PDT 24
Finished Jul 07 07:09:28 PM PDT 24
Peak memory 241956 kb
Host smart-08b4eab6-6ad5-4c5b-b15d-b3e085be3d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766925791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.766925791
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1804065433
Short name T940
Test name
Test status
Simulation time 190866203 ps
CPU time 3.32 seconds
Started Jul 07 07:08:56 PM PDT 24
Finished Jul 07 07:08:59 PM PDT 24
Peak memory 242080 kb
Host smart-8458f5ec-83a5-40a7-9ac8-efc9d580481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804065433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1804065433
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1145888754
Short name T153
Test name
Test status
Simulation time 316058505 ps
CPU time 16.17 seconds
Started Jul 07 07:08:56 PM PDT 24
Finished Jul 07 07:09:13 PM PDT 24
Peak memory 241940 kb
Host smart-3b2c5067-fbf0-489b-8580-8bb62533bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145888754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1145888754
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.2942652488
Short name T82
Test name
Test status
Simulation time 297663146 ps
CPU time 3.36 seconds
Started Jul 07 07:08:56 PM PDT 24
Finished Jul 07 07:08:59 PM PDT 24
Peak memory 242148 kb
Host smart-7c7d7bbd-01c7-4fb9-81b6-36c11f077ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942652488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2942652488
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1763450207
Short name T502
Test name
Test status
Simulation time 324865163 ps
CPU time 4.48 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:08 PM PDT 24
Peak memory 241804 kb
Host smart-79c037ee-b8b7-49dc-a9b0-28d83b994378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763450207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1763450207
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1049597652
Short name T837
Test name
Test status
Simulation time 131014700 ps
CPU time 3.73 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:08:58 PM PDT 24
Peak memory 242344 kb
Host smart-c927d32d-b390-4664-8bba-d274ec4868b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049597652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1049597652
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.4086875202
Short name T932
Test name
Test status
Simulation time 89242329 ps
CPU time 3.22 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:01 PM PDT 24
Peak memory 241808 kb
Host smart-991ddac5-d49e-4b4b-8a5b-8d797f5a342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086875202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.4086875202
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.1888470251
Short name T205
Test name
Test status
Simulation time 1818134160 ps
CPU time 5.59 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:03 PM PDT 24
Peak memory 242040 kb
Host smart-0772aa8c-edb3-451f-a37c-de2f584dc831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888470251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1888470251
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3764142796
Short name T769
Test name
Test status
Simulation time 1604040048 ps
CPU time 4.08 seconds
Started Jul 07 07:09:02 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 242360 kb
Host smart-249f96fd-4dbe-49cd-a1c6-6a301ef49bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764142796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3764142796
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.4073286166
Short name T844
Test name
Test status
Simulation time 616929014 ps
CPU time 4.68 seconds
Started Jul 07 07:08:54 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 242424 kb
Host smart-7e6e4d1f-2590-4508-9684-ef5e7c43fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073286166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.4073286166
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3843763302
Short name T963
Test name
Test status
Simulation time 146098519 ps
CPU time 4.07 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:02 PM PDT 24
Peak memory 242000 kb
Host smart-37e0f960-0c76-43b8-ac04-0ff55fcd6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843763302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3843763302
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3634429044
Short name T164
Test name
Test status
Simulation time 8282520013 ps
CPU time 14.65 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:12 PM PDT 24
Peak memory 242416 kb
Host smart-85f42bb3-5a51-44a5-aec9-1a572b647050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634429044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3634429044
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.3113738688
Short name T706
Test name
Test status
Simulation time 115124131 ps
CPU time 3.9 seconds
Started Jul 07 07:08:55 PM PDT 24
Finished Jul 07 07:08:59 PM PDT 24
Peak memory 242184 kb
Host smart-4940c238-b205-4b8f-b092-86f96c6ce13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113738688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3113738688
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.82850704
Short name T1055
Test name
Test status
Simulation time 1734131981 ps
CPU time 4.63 seconds
Started Jul 07 07:08:58 PM PDT 24
Finished Jul 07 07:09:03 PM PDT 24
Peak memory 242220 kb
Host smart-ed5a491e-cbf2-4e41-909d-9ade51d7fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82850704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.82850704
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2920114970
Short name T633
Test name
Test status
Simulation time 199154014 ps
CPU time 2.13 seconds
Started Jul 07 07:05:30 PM PDT 24
Finished Jul 07 07:05:33 PM PDT 24
Peak memory 240160 kb
Host smart-dc03ed77-b34e-43d0-810d-74ca5d0966e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920114970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2920114970
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2486868763
Short name T893
Test name
Test status
Simulation time 1261834358 ps
CPU time 14.43 seconds
Started Jul 07 07:05:26 PM PDT 24
Finished Jul 07 07:05:41 PM PDT 24
Peak memory 242332 kb
Host smart-1d07c426-54f6-415a-af48-d43dfc3ad787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486868763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2486868763
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.858458723
Short name T923
Test name
Test status
Simulation time 1304029079 ps
CPU time 31.65 seconds
Started Jul 07 07:05:24 PM PDT 24
Finished Jul 07 07:05:56 PM PDT 24
Peak memory 243748 kb
Host smart-f5895d41-c7f5-4d6b-ac59-e39de73908dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858458723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.858458723
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.1881669621
Short name T820
Test name
Test status
Simulation time 430436673 ps
CPU time 8.99 seconds
Started Jul 07 07:05:26 PM PDT 24
Finished Jul 07 07:05:35 PM PDT 24
Peak memory 248788 kb
Host smart-65e9c9f1-5e8f-46e1-bf77-df9f64f90a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881669621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1881669621
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2045053182
Short name T435
Test name
Test status
Simulation time 186576616 ps
CPU time 3.77 seconds
Started Jul 07 07:05:25 PM PDT 24
Finished Jul 07 07:05:29 PM PDT 24
Peak memory 241856 kb
Host smart-eba0ad8e-412a-457a-8f8a-024f6e49f3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045053182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2045053182
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3704304345
Short name T1143
Test name
Test status
Simulation time 2439689881 ps
CPU time 6.38 seconds
Started Jul 07 07:05:25 PM PDT 24
Finished Jul 07 07:05:32 PM PDT 24
Peak memory 242360 kb
Host smart-69300d5f-92fa-432d-9e26-9ac40ce17cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704304345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3704304345
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.1528515024
Short name T381
Test name
Test status
Simulation time 1470247396 ps
CPU time 19.42 seconds
Started Jul 07 07:05:26 PM PDT 24
Finished Jul 07 07:05:46 PM PDT 24
Peak memory 242280 kb
Host smart-5587031f-6e40-4776-9184-c9bad1c5d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528515024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1528515024
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.1772820191
Short name T895
Test name
Test status
Simulation time 2335983964 ps
CPU time 6.75 seconds
Started Jul 07 07:05:24 PM PDT 24
Finished Jul 07 07:05:31 PM PDT 24
Peak memory 242496 kb
Host smart-c6f327be-f341-46bf-9ac7-49ca770cd5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772820191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1772820191
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2782698257
Short name T905
Test name
Test status
Simulation time 2091939230 ps
CPU time 8.3 seconds
Started Jul 07 07:05:27 PM PDT 24
Finished Jul 07 07:05:36 PM PDT 24
Peak memory 242248 kb
Host smart-1bd6e695-570c-4f98-ad69-8130cced6ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782698257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2782698257
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1656298416
Short name T365
Test name
Test status
Simulation time 261827401 ps
CPU time 5.95 seconds
Started Jul 07 07:05:25 PM PDT 24
Finished Jul 07 07:05:32 PM PDT 24
Peak memory 241956 kb
Host smart-0da7a5e5-d96d-42cf-bc1d-848ac754c1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656298416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1656298416
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.679473723
Short name T397
Test name
Test status
Simulation time 623024744 ps
CPU time 11.82 seconds
Started Jul 07 07:05:21 PM PDT 24
Finished Jul 07 07:05:33 PM PDT 24
Peak memory 242160 kb
Host smart-16b4c688-592e-40a5-8a78-31d6503b5c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679473723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.679473723
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3082607149
Short name T1110
Test name
Test status
Simulation time 10504885512 ps
CPU time 93.34 seconds
Started Jul 07 07:05:25 PM PDT 24
Finished Jul 07 07:06:58 PM PDT 24
Peak memory 248956 kb
Host smart-59737dfd-f1b4-4c38-bf5b-400f17f5ee9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082607149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3082607149
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3643292456
Short name T641
Test name
Test status
Simulation time 371155928 ps
CPU time 9.57 seconds
Started Jul 07 07:05:26 PM PDT 24
Finished Jul 07 07:05:36 PM PDT 24
Peak memory 242068 kb
Host smart-df71d0a7-3154-4480-9952-1fa8cc89c8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643292456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3643292456
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1063834486
Short name T829
Test name
Test status
Simulation time 2013812450 ps
CPU time 4.92 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:02 PM PDT 24
Peak memory 242172 kb
Host smart-a8b0c789-55cd-4a3e-8c27-b96ebb343e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063834486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1063834486
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.453510579
Short name T554
Test name
Test status
Simulation time 1168806908 ps
CPU time 30.9 seconds
Started Jul 07 07:08:56 PM PDT 24
Finished Jul 07 07:09:27 PM PDT 24
Peak memory 242220 kb
Host smart-a83daf84-1582-49f7-8e55-d6b522426445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453510579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.453510579
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.3455660019
Short name T971
Test name
Test status
Simulation time 241990917 ps
CPU time 3.65 seconds
Started Jul 07 07:08:57 PM PDT 24
Finished Jul 07 07:09:01 PM PDT 24
Peak memory 242168 kb
Host smart-57d68391-7283-4ce6-ba88-9412cfbeb1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455660019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3455660019
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.77508407
Short name T828
Test name
Test status
Simulation time 611301038 ps
CPU time 8.68 seconds
Started Jul 07 07:09:00 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 241900 kb
Host smart-51b4a05f-a977-477b-8f9b-47e74351afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77508407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.77508407
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2920909247
Short name T204
Test name
Test status
Simulation time 149021375 ps
CPU time 4.23 seconds
Started Jul 07 07:08:59 PM PDT 24
Finished Jul 07 07:09:04 PM PDT 24
Peak memory 242100 kb
Host smart-31650e78-aa76-4236-8196-9878a46d2a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920909247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2920909247
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.463392401
Short name T236
Test name
Test status
Simulation time 337281475 ps
CPU time 7.78 seconds
Started Jul 07 07:09:01 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 242008 kb
Host smart-7a5cb271-f2a3-4203-a309-86eeac25b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463392401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.463392401
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.3822781748
Short name T431
Test name
Test status
Simulation time 370565431 ps
CPU time 8.64 seconds
Started Jul 07 07:09:00 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 241796 kb
Host smart-4b8adf4d-9a66-475b-aa12-f1791c9fa408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822781748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3822781748
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.1746741740
Short name T116
Test name
Test status
Simulation time 181324195 ps
CPU time 4 seconds
Started Jul 07 07:09:00 PM PDT 24
Finished Jul 07 07:09:04 PM PDT 24
Peak memory 241916 kb
Host smart-39164d91-6cc3-4544-bf02-9b3b4419548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746741740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1746741740
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.1415306869
Short name T738
Test name
Test status
Simulation time 206160675 ps
CPU time 5.23 seconds
Started Jul 07 07:09:02 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 248536 kb
Host smart-9ea03ddb-195f-40bc-be27-2381079c33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415306869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1415306869
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.3888098733
Short name T432
Test name
Test status
Simulation time 435773935 ps
CPU time 5.44 seconds
Started Jul 07 07:09:00 PM PDT 24
Finished Jul 07 07:09:06 PM PDT 24
Peak memory 241812 kb
Host smart-49ce725c-cad0-45a0-af28-48c9477abeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888098733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3888098733
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3373545419
Short name T530
Test name
Test status
Simulation time 1410220978 ps
CPU time 5.15 seconds
Started Jul 07 07:09:05 PM PDT 24
Finished Jul 07 07:09:12 PM PDT 24
Peak memory 242000 kb
Host smart-e9374eeb-1609-40b6-9591-e0bd8ab8d085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373545419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3373545419
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.3874931845
Short name T145
Test name
Test status
Simulation time 2499012363 ps
CPU time 6.71 seconds
Started Jul 07 07:09:05 PM PDT 24
Finished Jul 07 07:09:13 PM PDT 24
Peak memory 242460 kb
Host smart-149ea03c-e497-4e10-a0a8-d940a437cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874931845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3874931845
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2247533770
Short name T929
Test name
Test status
Simulation time 247600937 ps
CPU time 4.27 seconds
Started Jul 07 07:09:02 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 242372 kb
Host smart-0c61ed04-3936-4203-8c5f-1c12f15e7eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247533770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2247533770
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3929567658
Short name T473
Test name
Test status
Simulation time 153083155 ps
CPU time 4.08 seconds
Started Jul 07 07:09:06 PM PDT 24
Finished Jul 07 07:09:11 PM PDT 24
Peak memory 242200 kb
Host smart-b84c294d-e2f1-4ed3-8df8-9722d251b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929567658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3929567658
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.2529478537
Short name T772
Test name
Test status
Simulation time 172724896 ps
CPU time 4.57 seconds
Started Jul 07 07:09:04 PM PDT 24
Finished Jul 07 07:09:09 PM PDT 24
Peak memory 241916 kb
Host smart-b060f613-3cc4-400b-acfe-7d8ba5d224e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529478537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2529478537
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.2899117557
Short name T57
Test name
Test status
Simulation time 278642255 ps
CPU time 4.09 seconds
Started Jul 07 07:09:05 PM PDT 24
Finished Jul 07 07:09:10 PM PDT 24
Peak memory 242076 kb
Host smart-8c7b7685-4683-452d-ae9c-0b542b485d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899117557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.2899117557
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2819185380
Short name T1001
Test name
Test status
Simulation time 2640647278 ps
CPU time 12.84 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 241964 kb
Host smart-94081d2c-ee49-4d0b-8b61-d3fe277ed7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819185380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2819185380
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1735307528
Short name T707
Test name
Test status
Simulation time 445603399 ps
CPU time 9.91 seconds
Started Jul 07 07:09:02 PM PDT 24
Finished Jul 07 07:09:13 PM PDT 24
Peak memory 241916 kb
Host smart-7e366f73-2ae6-473a-b32c-226965f65b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735307528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1735307528
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2146998953
Short name T937
Test name
Test status
Simulation time 251357616 ps
CPU time 2.27 seconds
Started Jul 07 07:04:25 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 240500 kb
Host smart-45710055-6ddc-4a35-aaad-a8b73f479967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146998953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2146998953
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.952885427
Short name T1087
Test name
Test status
Simulation time 747442204 ps
CPU time 16.89 seconds
Started Jul 07 07:04:18 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 242072 kb
Host smart-3cc5fa3b-17ef-4c39-8125-035a9cbb3696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952885427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.952885427
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1955483750
Short name T1026
Test name
Test status
Simulation time 786024845 ps
CPU time 27.56 seconds
Started Jul 07 07:04:22 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 242256 kb
Host smart-fd4bc686-b9b9-41b8-bdbc-06a65d0607fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955483750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1955483750
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.969400163
Short name T519
Test name
Test status
Simulation time 1831394519 ps
CPU time 18.97 seconds
Started Jul 07 07:04:20 PM PDT 24
Finished Jul 07 07:04:39 PM PDT 24
Peak memory 242352 kb
Host smart-0ad76b8a-a961-47c7-9146-a937eec585e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969400163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.969400163
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.3837454728
Short name T922
Test name
Test status
Simulation time 549020251 ps
CPU time 3.45 seconds
Started Jul 07 07:04:17 PM PDT 24
Finished Jul 07 07:04:20 PM PDT 24
Peak memory 242044 kb
Host smart-8e114b15-b091-4f13-b00f-d84f5743b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837454728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3837454728
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.2752982024
Short name T958
Test name
Test status
Simulation time 1069767113 ps
CPU time 23.25 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:04:42 PM PDT 24
Peak memory 248796 kb
Host smart-f5d243be-6206-4a41-a10d-5b39aeba0705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752982024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.2752982024
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1997134954
Short name T573
Test name
Test status
Simulation time 699169789 ps
CPU time 10.23 seconds
Started Jul 07 07:04:20 PM PDT 24
Finished Jul 07 07:04:31 PM PDT 24
Peak memory 248736 kb
Host smart-3682bdc9-9405-42bf-9c0a-1a05f2dbae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997134954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1997134954
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2022162090
Short name T1022
Test name
Test status
Simulation time 896295218 ps
CPU time 24.02 seconds
Started Jul 07 07:04:21 PM PDT 24
Finished Jul 07 07:04:46 PM PDT 24
Peak memory 241768 kb
Host smart-f1092553-c757-474e-9899-2cc642bc4cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022162090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2022162090
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2230457961
Short name T1065
Test name
Test status
Simulation time 700326859 ps
CPU time 16.98 seconds
Started Jul 07 07:04:24 PM PDT 24
Finished Jul 07 07:04:41 PM PDT 24
Peak memory 242120 kb
Host smart-0ae36c42-9088-4cb5-be05-1835a542da2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230457961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2230457961
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.2043332434
Short name T363
Test name
Test status
Simulation time 2390130190 ps
CPU time 7.46 seconds
Started Jul 07 07:04:21 PM PDT 24
Finished Jul 07 07:04:29 PM PDT 24
Peak memory 242168 kb
Host smart-8a1f5691-625e-44b5-8be0-ceda5f49b73f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043332434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2043332434
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1156716754
Short name T23
Test name
Test status
Simulation time 155343553066 ps
CPU time 201.19 seconds
Started Jul 07 07:04:24 PM PDT 24
Finished Jul 07 07:07:45 PM PDT 24
Peak memory 270312 kb
Host smart-fbcfdd67-87e8-4e62-9f21-ac4f77873f8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156716754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1156716754
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1073133282
Short name T1053
Test name
Test status
Simulation time 374035591 ps
CPU time 12.04 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:04:32 PM PDT 24
Peak memory 242076 kb
Host smart-637729cc-6937-4347-a3ac-45428b43c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073133282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1073133282
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.1543643068
Short name T336
Test name
Test status
Simulation time 33924224626 ps
CPU time 175.99 seconds
Started Jul 07 07:04:19 PM PDT 24
Finished Jul 07 07:07:15 PM PDT 24
Peak memory 265236 kb
Host smart-96a11e1a-df5a-4957-8299-7fb718338157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543643068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
1543643068
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3516523500
Short name T383
Test name
Test status
Simulation time 8628273676 ps
CPU time 68.9 seconds
Started Jul 07 07:04:20 PM PDT 24
Finished Jul 07 07:05:29 PM PDT 24
Peak memory 248840 kb
Host smart-fd904e50-edf2-47ff-996a-5582742935d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516523500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3516523500
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3115472058
Short name T241
Test name
Test status
Simulation time 135787239 ps
CPU time 1.69 seconds
Started Jul 07 07:05:38 PM PDT 24
Finished Jul 07 07:05:40 PM PDT 24
Peak memory 240144 kb
Host smart-39deff4e-1c6b-4215-89e5-5bd6a72dd64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115472058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3115472058
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.446507200
Short name T115
Test name
Test status
Simulation time 4963074392 ps
CPU time 18.07 seconds
Started Jul 07 07:05:27 PM PDT 24
Finished Jul 07 07:05:45 PM PDT 24
Peak memory 243140 kb
Host smart-dfe2502b-758d-4fa3-8d94-4be8e9078444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446507200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.446507200
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.4081490154
Short name T995
Test name
Test status
Simulation time 1013019190 ps
CPU time 11.5 seconds
Started Jul 07 07:05:31 PM PDT 24
Finished Jul 07 07:05:43 PM PDT 24
Peak memory 242184 kb
Host smart-5be266a0-f7a3-4603-9439-8776a2cab0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081490154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.4081490154
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3546055979
Short name T688
Test name
Test status
Simulation time 6295207538 ps
CPU time 46.4 seconds
Started Jul 07 07:05:28 PM PDT 24
Finished Jul 07 07:06:15 PM PDT 24
Peak memory 242472 kb
Host smart-6139b05d-cc06-4b84-980a-99243d24cf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546055979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3546055979
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2027663767
Short name T1079
Test name
Test status
Simulation time 244900966 ps
CPU time 3.75 seconds
Started Jul 07 07:05:30 PM PDT 24
Finished Jul 07 07:05:34 PM PDT 24
Peak memory 242028 kb
Host smart-029f7d48-3d1e-4237-b6db-9a8616fbf4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027663767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2027663767
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3422965123
Short name T453
Test name
Test status
Simulation time 851921626 ps
CPU time 11.43 seconds
Started Jul 07 07:05:30 PM PDT 24
Finished Jul 07 07:05:42 PM PDT 24
Peak memory 245940 kb
Host smart-ad0565b3-3105-47a0-aa6f-da8e6cc93e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422965123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3422965123
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.985465500
Short name T856
Test name
Test status
Simulation time 179184396 ps
CPU time 3.75 seconds
Started Jul 07 07:05:31 PM PDT 24
Finished Jul 07 07:05:35 PM PDT 24
Peak memory 242172 kb
Host smart-9b6a46c1-cfa9-4179-82de-da5efb25fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985465500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.985465500
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.3518043989
Short name T1113
Test name
Test status
Simulation time 493038994 ps
CPU time 13.48 seconds
Started Jul 07 07:05:30 PM PDT 24
Finished Jul 07 07:05:44 PM PDT 24
Peak memory 242176 kb
Host smart-d25ab623-4552-4bdf-97f4-178169caf941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518043989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.3518043989
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.400825828
Short name T385
Test name
Test status
Simulation time 409738656 ps
CPU time 13.86 seconds
Started Jul 07 07:05:36 PM PDT 24
Finished Jul 07 07:05:50 PM PDT 24
Peak memory 248720 kb
Host smart-6ab59a4b-4984-416f-9efa-f6c11d6d166b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400825828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.400825828
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3270583161
Short name T664
Test name
Test status
Simulation time 2071853588 ps
CPU time 6.8 seconds
Started Jul 07 07:05:31 PM PDT 24
Finished Jul 07 07:05:38 PM PDT 24
Peak memory 242180 kb
Host smart-b9539eec-309a-46b1-886f-e0e919ccb7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270583161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3270583161
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.3137582440
Short name T529
Test name
Test status
Simulation time 166986386 ps
CPU time 3.57 seconds
Started Jul 07 07:05:27 PM PDT 24
Finished Jul 07 07:05:31 PM PDT 24
Peak memory 242088 kb
Host smart-79baa26b-8613-4915-a263-2052c883d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137582440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3137582440
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1046982644
Short name T925
Test name
Test status
Simulation time 21793973143 ps
CPU time 262.12 seconds
Started Jul 07 07:05:32 PM PDT 24
Finished Jul 07 07:09:54 PM PDT 24
Peak memory 257192 kb
Host smart-b3630ea7-1939-47ee-bb53-381375f1355f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046982644 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1046982644
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.161349214
Short name T810
Test name
Test status
Simulation time 470668726 ps
CPU time 14.96 seconds
Started Jul 07 07:05:30 PM PDT 24
Finished Jul 07 07:05:46 PM PDT 24
Peak memory 242244 kb
Host smart-4981c009-e587-4909-9e04-dbdb9c6074d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161349214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.161349214
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3679446387
Short name T1093
Test name
Test status
Simulation time 395454362 ps
CPU time 3.98 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 242072 kb
Host smart-d3782c0f-ec62-438c-873a-64cd5701884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679446387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3679446387
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.2721946569
Short name T444
Test name
Test status
Simulation time 216949195 ps
CPU time 4.68 seconds
Started Jul 07 07:09:05 PM PDT 24
Finished Jul 07 07:09:11 PM PDT 24
Peak memory 241920 kb
Host smart-08ea0ee4-c967-4b97-a947-0e564a40f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721946569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2721946569
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.665681691
Short name T506
Test name
Test status
Simulation time 128381532 ps
CPU time 3.78 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:08 PM PDT 24
Peak memory 241908 kb
Host smart-256106a1-adb1-4900-97d1-f70b725b35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665681691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.665681691
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.754213233
Short name T196
Test name
Test status
Simulation time 121439331 ps
CPU time 4.72 seconds
Started Jul 07 07:09:05 PM PDT 24
Finished Jul 07 07:09:11 PM PDT 24
Peak memory 242324 kb
Host smart-6198bbf5-3eaf-49fb-8585-2c730b19feb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754213233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.754213233
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1697896490
Short name T53
Test name
Test status
Simulation time 759053303 ps
CPU time 5.52 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:10 PM PDT 24
Peak memory 241720 kb
Host smart-df1b9418-e94b-4a66-82d9-67b72f6cd8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697896490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1697896490
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.3913105307
Short name T521
Test name
Test status
Simulation time 95775298 ps
CPU time 3.64 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:08 PM PDT 24
Peak memory 242076 kb
Host smart-d0dd1f0e-3a8c-4ae9-8568-2746f3c5086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913105307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3913105307
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.3843979277
Short name T713
Test name
Test status
Simulation time 333305735 ps
CPU time 4.08 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 242072 kb
Host smart-a0805c63-36ab-4b77-aaa3-cae840cd9183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843979277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3843979277
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2933583282
Short name T784
Test name
Test status
Simulation time 487694572 ps
CPU time 3.94 seconds
Started Jul 07 07:09:03 PM PDT 24
Finished Jul 07 07:09:08 PM PDT 24
Peak memory 242040 kb
Host smart-4ac79210-8b5a-49c4-8e2a-c60534bf324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933583282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2933583282
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.684262719
Short name T35
Test name
Test status
Simulation time 170257126 ps
CPU time 4.17 seconds
Started Jul 07 07:09:01 PM PDT 24
Finished Jul 07 07:09:05 PM PDT 24
Peak memory 242144 kb
Host smart-1d7e6403-0265-4ef8-862b-24c2aac7f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684262719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.684262719
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3766445509
Short name T577
Test name
Test status
Simulation time 1976346784 ps
CPU time 4.74 seconds
Started Jul 07 07:09:02 PM PDT 24
Finished Jul 07 07:09:07 PM PDT 24
Peak memory 242172 kb
Host smart-e8438af9-35cc-4dba-bf12-d316f4d11a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766445509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3766445509
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.4275555195
Short name T438
Test name
Test status
Simulation time 122978605 ps
CPU time 2.01 seconds
Started Jul 07 07:05:36 PM PDT 24
Finished Jul 07 07:05:38 PM PDT 24
Peak memory 240076 kb
Host smart-c36086a5-21a9-4070-8eab-8e869ce722b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275555195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.4275555195
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3571129930
Short name T896
Test name
Test status
Simulation time 366198239 ps
CPU time 7.12 seconds
Started Jul 07 07:05:35 PM PDT 24
Finished Jul 07 07:05:42 PM PDT 24
Peak memory 242232 kb
Host smart-01bf5425-5b6e-40db-9de6-1debac160687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571129930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3571129930
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.4049890693
Short name T622
Test name
Test status
Simulation time 1919936610 ps
CPU time 17.15 seconds
Started Jul 07 07:05:36 PM PDT 24
Finished Jul 07 07:05:53 PM PDT 24
Peak memory 241952 kb
Host smart-168500eb-82ee-4a7d-bea0-5ab0467db471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049890693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.4049890693
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.2765936089
Short name T1169
Test name
Test status
Simulation time 589625563 ps
CPU time 13.3 seconds
Started Jul 07 07:05:32 PM PDT 24
Finished Jul 07 07:05:46 PM PDT 24
Peak memory 242256 kb
Host smart-acd401f4-6f91-4ec5-8678-8e3d19ab2cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765936089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2765936089
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.3674383909
Short name T1039
Test name
Test status
Simulation time 548585137 ps
CPU time 4.08 seconds
Started Jul 07 07:05:31 PM PDT 24
Finished Jul 07 07:05:36 PM PDT 24
Peak memory 242260 kb
Host smart-458219f9-1ee0-49ad-a16b-1f7d1d405b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674383909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3674383909
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.3368232258
Short name T684
Test name
Test status
Simulation time 1177114022 ps
CPU time 8.73 seconds
Started Jul 07 07:05:32 PM PDT 24
Finished Jul 07 07:05:41 PM PDT 24
Peak memory 242316 kb
Host smart-2dcd00d0-2f5f-4751-b30d-746dbe23e7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368232258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3368232258
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.3535588424
Short name T752
Test name
Test status
Simulation time 485445665 ps
CPU time 14.84 seconds
Started Jul 07 07:05:33 PM PDT 24
Finished Jul 07 07:05:48 PM PDT 24
Peak memory 241948 kb
Host smart-8ff55c0c-325e-479c-b6e4-5e38296c72a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535588424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3535588424
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2653363576
Short name T1163
Test name
Test status
Simulation time 2498368495 ps
CPU time 8.13 seconds
Started Jul 07 07:05:32 PM PDT 24
Finished Jul 07 07:05:41 PM PDT 24
Peak memory 242292 kb
Host smart-314a0924-bcc1-4c64-8d2c-c16c651dcf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653363576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2653363576
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.3261845543
Short name T107
Test name
Test status
Simulation time 307419715 ps
CPU time 6.36 seconds
Started Jul 07 07:05:31 PM PDT 24
Finished Jul 07 07:05:38 PM PDT 24
Peak memory 242000 kb
Host smart-f68d97d9-0c17-4248-81ad-8b1771bb7d70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261845543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3261845543
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.3009061550
Short name T942
Test name
Test status
Simulation time 2323202518 ps
CPU time 9.45 seconds
Started Jul 07 07:05:33 PM PDT 24
Finished Jul 07 07:05:43 PM PDT 24
Peak memory 242032 kb
Host smart-1beaf83c-4bc0-4b21-aad9-fa8361e571e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009061550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3009061550
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1275853661
Short name T1036
Test name
Test status
Simulation time 758806468 ps
CPU time 5.64 seconds
Started Jul 07 07:05:32 PM PDT 24
Finished Jul 07 07:05:38 PM PDT 24
Peak memory 242148 kb
Host smart-85837ec9-8983-4b1d-a531-2c2c77822bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275853661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1275853661
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.1027145992
Short name T1054
Test name
Test status
Simulation time 14426637232 ps
CPU time 132.08 seconds
Started Jul 07 07:05:37 PM PDT 24
Finished Jul 07 07:07:49 PM PDT 24
Peak memory 256988 kb
Host smart-871b3d32-d2bc-4f76-9f52-3658f240d6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027145992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.1027145992
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3972976870
Short name T1115
Test name
Test status
Simulation time 413092662780 ps
CPU time 810.85 seconds
Started Jul 07 07:05:39 PM PDT 24
Finished Jul 07 07:19:10 PM PDT 24
Peak memory 275928 kb
Host smart-0c721fec-4c82-4855-a9d9-e693919039b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972976870 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.3972976870
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.566926695
Short name T823
Test name
Test status
Simulation time 1257762015 ps
CPU time 13.19 seconds
Started Jul 07 07:05:36 PM PDT 24
Finished Jul 07 07:05:49 PM PDT 24
Peak memory 248808 kb
Host smart-0da1189e-c7f0-4fb0-949c-ded14cc23a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566926695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.566926695
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1865982324
Short name T1177
Test name
Test status
Simulation time 246376376 ps
CPU time 4.92 seconds
Started Jul 07 07:09:04 PM PDT 24
Finished Jul 07 07:09:10 PM PDT 24
Peak memory 242144 kb
Host smart-aefd624e-0af4-473f-ad76-f9a8b4021351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865982324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1865982324
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.608172954
Short name T558
Test name
Test status
Simulation time 2020010054 ps
CPU time 5.52 seconds
Started Jul 07 07:09:07 PM PDT 24
Finished Jul 07 07:09:13 PM PDT 24
Peak memory 242124 kb
Host smart-08d2e250-a526-487b-9268-712a76309604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608172954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.608172954
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1676658163
Short name T999
Test name
Test status
Simulation time 142009035 ps
CPU time 4.18 seconds
Started Jul 07 07:09:08 PM PDT 24
Finished Jul 07 07:09:13 PM PDT 24
Peak memory 241908 kb
Host smart-76738b1c-e6d7-4d53-b5f5-46abf5861c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676658163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1676658163
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.3354152508
Short name T179
Test name
Test status
Simulation time 297321763 ps
CPU time 4.12 seconds
Started Jul 07 07:09:06 PM PDT 24
Finished Jul 07 07:09:11 PM PDT 24
Peak memory 241904 kb
Host smart-b2d725a4-445c-414a-81f8-29ec3ae14ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354152508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3354152508
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3865990878
Short name T78
Test name
Test status
Simulation time 236244409 ps
CPU time 4.45 seconds
Started Jul 07 07:09:06 PM PDT 24
Finished Jul 07 07:09:12 PM PDT 24
Peak memory 242396 kb
Host smart-5ba97347-9858-4636-8c4f-670a263949b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865990878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3865990878
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3399168952
Short name T548
Test name
Test status
Simulation time 121631145 ps
CPU time 3.48 seconds
Started Jul 07 07:09:05 PM PDT 24
Finished Jul 07 07:09:10 PM PDT 24
Peak memory 241852 kb
Host smart-b2cde4bf-e3e2-4aa9-b788-6ab94170c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399168952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3399168952
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.1209037235
Short name T1154
Test name
Test status
Simulation time 475078315 ps
CPU time 3.84 seconds
Started Jul 07 07:09:07 PM PDT 24
Finished Jul 07 07:09:12 PM PDT 24
Peak memory 242052 kb
Host smart-335280e6-f8a4-439f-9031-de97870bb41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209037235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1209037235
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.3518965898
Short name T730
Test name
Test status
Simulation time 1907993575 ps
CPU time 4.89 seconds
Started Jul 07 07:09:09 PM PDT 24
Finished Jul 07 07:09:14 PM PDT 24
Peak memory 241900 kb
Host smart-1f9fef16-d036-4a95-b8af-208eb54e6d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518965898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.3518965898
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3835085253
Short name T239
Test name
Test status
Simulation time 116590803 ps
CPU time 1.69 seconds
Started Jul 07 07:05:41 PM PDT 24
Finished Jul 07 07:05:43 PM PDT 24
Peak memory 240092 kb
Host smart-6c2eef6d-74a9-4f08-8b90-74c949c60428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835085253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3835085253
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1755997037
Short name T617
Test name
Test status
Simulation time 2103957880 ps
CPU time 15.38 seconds
Started Jul 07 07:05:40 PM PDT 24
Finished Jul 07 07:05:56 PM PDT 24
Peak memory 241984 kb
Host smart-1a82ead6-db45-4a48-96a4-6815e4c2a107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755997037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1755997037
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2782010614
Short name T380
Test name
Test status
Simulation time 652653302 ps
CPU time 13.98 seconds
Started Jul 07 07:05:40 PM PDT 24
Finished Jul 07 07:05:54 PM PDT 24
Peak memory 242612 kb
Host smart-7892f97b-a18b-49b7-8972-cfaca8de3cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782010614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2782010614
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3368499896
Short name T73
Test name
Test status
Simulation time 485722276 ps
CPU time 4.49 seconds
Started Jul 07 07:05:37 PM PDT 24
Finished Jul 07 07:05:42 PM PDT 24
Peak memory 241912 kb
Host smart-03d89e51-83dc-4f80-b482-97f69fc95f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368499896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3368499896
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.2869775085
Short name T714
Test name
Test status
Simulation time 432550272 ps
CPU time 7.94 seconds
Started Jul 07 07:05:41 PM PDT 24
Finished Jul 07 07:05:49 PM PDT 24
Peak memory 242664 kb
Host smart-5b5e9678-8ced-4676-8d47-1a901323c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869775085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2869775085
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.2520833403
Short name T969
Test name
Test status
Simulation time 1044094133 ps
CPU time 16.97 seconds
Started Jul 07 07:05:45 PM PDT 24
Finished Jul 07 07:06:02 PM PDT 24
Peak memory 242128 kb
Host smart-2717709b-50b2-44c6-8b58-27f820b07c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520833403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.2520833403
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.258129780
Short name T748
Test name
Test status
Simulation time 892318233 ps
CPU time 30.8 seconds
Started Jul 07 07:05:38 PM PDT 24
Finished Jul 07 07:06:09 PM PDT 24
Peak memory 242240 kb
Host smart-b04facff-e3ef-4d75-9dd8-30ed13e2d739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258129780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.258129780
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.583843018
Short name T1069
Test name
Test status
Simulation time 2183797489 ps
CPU time 6.78 seconds
Started Jul 07 07:05:40 PM PDT 24
Finished Jul 07 07:05:47 PM PDT 24
Peak memory 242240 kb
Host smart-55c75d5e-67b9-4168-90a6-4592531b34d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583843018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.583843018
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.992820837
Short name T170
Test name
Test status
Simulation time 140600367 ps
CPU time 4.17 seconds
Started Jul 07 07:05:35 PM PDT 24
Finished Jul 07 07:05:40 PM PDT 24
Peak memory 241992 kb
Host smart-50a349f7-abd5-4da8-bd1d-3ba24b7a7232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992820837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.992820837
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.2341052528
Short name T1136
Test name
Test status
Simulation time 15382091361 ps
CPU time 166.08 seconds
Started Jul 07 07:05:45 PM PDT 24
Finished Jul 07 07:08:31 PM PDT 24
Peak memory 257068 kb
Host smart-658f2922-7002-4d99-a739-ad5159e2611b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341052528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.2341052528
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3534471422
Short name T843
Test name
Test status
Simulation time 92665237590 ps
CPU time 1111.51 seconds
Started Jul 07 07:05:41 PM PDT 24
Finished Jul 07 07:24:13 PM PDT 24
Peak memory 373120 kb
Host smart-f491c58e-979b-446e-b6aa-68b22f958acb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534471422 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.3534471422
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3392243607
Short name T302
Test name
Test status
Simulation time 1575087351 ps
CPU time 29.18 seconds
Started Jul 07 07:05:41 PM PDT 24
Finished Jul 07 07:06:10 PM PDT 24
Peak memory 242728 kb
Host smart-c4b9f45d-f2e0-4e63-be5d-bc75c97fa623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392243607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3392243607
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.469416486
Short name T787
Test name
Test status
Simulation time 2023757385 ps
CPU time 6.22 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:19 PM PDT 24
Peak memory 242340 kb
Host smart-412c3ce1-569c-47f6-a910-84d1d387fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469416486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.469416486
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3917813127
Short name T576
Test name
Test status
Simulation time 239832288 ps
CPU time 4.28 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 241904 kb
Host smart-26bdb10e-bed2-40f3-a48c-e52b283a0645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917813127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3917813127
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.4160377612
Short name T804
Test name
Test status
Simulation time 446174023 ps
CPU time 3.09 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242052 kb
Host smart-14914f53-1408-424f-b9cd-cda1c011858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160377612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.4160377612
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.215145755
Short name T1077
Test name
Test status
Simulation time 293627155 ps
CPU time 3.78 seconds
Started Jul 07 07:09:09 PM PDT 24
Finished Jul 07 07:09:14 PM PDT 24
Peak memory 241992 kb
Host smart-6ce92f22-21f9-45bf-a0cf-aa13e801a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215145755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.215145755
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3247726189
Short name T656
Test name
Test status
Simulation time 277371676 ps
CPU time 5.21 seconds
Started Jul 07 07:09:09 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242140 kb
Host smart-c70879b2-ca70-459c-b318-43c23d269f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247726189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3247726189
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.3214615075
Short name T1190
Test name
Test status
Simulation time 591677111 ps
CPU time 4.08 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 241904 kb
Host smart-33b91fe1-8722-4cb8-ae2d-7f351b215f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214615075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3214615075
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.1803415801
Short name T501
Test name
Test status
Simulation time 381381963 ps
CPU time 4.55 seconds
Started Jul 07 07:09:11 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 241876 kb
Host smart-c49dc250-6e79-45e1-b6dd-bc71265e46b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803415801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1803415801
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1972384057
Short name T464
Test name
Test status
Simulation time 208338557 ps
CPU time 4.76 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:15 PM PDT 24
Peak memory 241956 kb
Host smart-4b537765-3fab-4019-b4e3-d1839fa3ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972384057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1972384057
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.1677651522
Short name T520
Test name
Test status
Simulation time 536501156 ps
CPU time 4.54 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:15 PM PDT 24
Peak memory 242076 kb
Host smart-a54b9858-0a7e-4365-8481-fb36d02e8b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677651522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1677651522
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.4032395507
Short name T449
Test name
Test status
Simulation time 148190552 ps
CPU time 1.56 seconds
Started Jul 07 07:05:42 PM PDT 24
Finished Jul 07 07:05:44 PM PDT 24
Peak memory 240444 kb
Host smart-fb7be46b-37ca-4078-98cd-7a1e244495ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032395507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.4032395507
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.3437363369
Short name T943
Test name
Test status
Simulation time 877907454 ps
CPU time 10.37 seconds
Started Jul 07 07:05:44 PM PDT 24
Finished Jul 07 07:05:55 PM PDT 24
Peak memory 242116 kb
Host smart-0654a0b3-de2e-436a-afa4-1a04a176159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437363369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3437363369
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1548843620
Short name T1120
Test name
Test status
Simulation time 1048366124 ps
CPU time 25.51 seconds
Started Jul 07 07:05:45 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 242416 kb
Host smart-eb14fd61-c949-4691-be2d-35e73b05a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548843620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1548843620
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.4107775125
Short name T613
Test name
Test status
Simulation time 1184923664 ps
CPU time 26.45 seconds
Started Jul 07 07:05:43 PM PDT 24
Finished Jul 07 07:06:09 PM PDT 24
Peak memory 242320 kb
Host smart-2888cb78-5e57-456f-8cb8-cd9ae75a480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107775125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.4107775125
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2076084649
Short name T659
Test name
Test status
Simulation time 175573111 ps
CPU time 4.78 seconds
Started Jul 07 07:05:42 PM PDT 24
Finished Jul 07 07:05:47 PM PDT 24
Peak memory 242068 kb
Host smart-ff78b759-32be-40a1-a2d1-4002e1ba746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076084649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2076084649
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.463612821
Short name T740
Test name
Test status
Simulation time 486069349 ps
CPU time 10.6 seconds
Started Jul 07 07:05:43 PM PDT 24
Finished Jul 07 07:05:54 PM PDT 24
Peak memory 242076 kb
Host smart-f7473648-d892-42ec-912a-b05600f74194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463612821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.463612821
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.3063748745
Short name T482
Test name
Test status
Simulation time 848166271 ps
CPU time 16.84 seconds
Started Jul 07 07:05:46 PM PDT 24
Finished Jul 07 07:06:03 PM PDT 24
Peak memory 242516 kb
Host smart-9391c359-03a1-484f-8b50-b2ef7553f85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063748745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3063748745
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.176315778
Short name T1140
Test name
Test status
Simulation time 4181970863 ps
CPU time 16.1 seconds
Started Jul 07 07:05:43 PM PDT 24
Finished Jul 07 07:05:59 PM PDT 24
Peak memory 241944 kb
Host smart-96d2e10c-42ec-4a1c-9fed-8e4c780df8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176315778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.176315778
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2668677614
Short name T722
Test name
Test status
Simulation time 477169177 ps
CPU time 5.6 seconds
Started Jul 07 07:05:40 PM PDT 24
Finished Jul 07 07:05:46 PM PDT 24
Peak memory 242012 kb
Host smart-ea8c833b-89e5-4f94-82fe-a29f6b4ddaef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668677614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2668677614
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.225458997
Short name T366
Test name
Test status
Simulation time 159766310 ps
CPU time 5.51 seconds
Started Jul 07 07:05:43 PM PDT 24
Finished Jul 07 07:05:48 PM PDT 24
Peak memory 242360 kb
Host smart-21c45d0c-2e22-4ab0-b939-d269648295fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225458997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.225458997
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2595129197
Short name T716
Test name
Test status
Simulation time 494019543 ps
CPU time 5.58 seconds
Started Jul 07 07:05:39 PM PDT 24
Finished Jul 07 07:05:44 PM PDT 24
Peak memory 242248 kb
Host smart-6c8e6504-25f4-4c02-ba0f-125274c342c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595129197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2595129197
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.2949519687
Short name T330
Test name
Test status
Simulation time 158455365470 ps
CPU time 1640.46 seconds
Started Jul 07 07:05:44 PM PDT 24
Finished Jul 07 07:33:05 PM PDT 24
Peak memory 257136 kb
Host smart-fc376ef2-05e9-4b77-909d-361c08099d54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949519687 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.2949519687
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.1958315441
Short name T1161
Test name
Test status
Simulation time 4141682201 ps
CPU time 11.96 seconds
Started Jul 07 07:05:44 PM PDT 24
Finished Jul 07 07:05:56 PM PDT 24
Peak memory 242092 kb
Host smart-0af1ec96-e597-4085-a8bc-71a2bf3e6a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958315441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1958315441
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.287807545
Short name T867
Test name
Test status
Simulation time 2399105594 ps
CPU time 5.66 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 242072 kb
Host smart-e6918466-463f-4ad8-8eeb-50eeea81e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287807545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.287807545
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.1692878635
Short name T1098
Test name
Test status
Simulation time 423220502 ps
CPU time 3.78 seconds
Started Jul 07 07:09:09 PM PDT 24
Finished Jul 07 07:09:14 PM PDT 24
Peak memory 241824 kb
Host smart-9ba55fb7-4357-4b77-ba0b-0f2b05ee98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692878635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1692878635
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.3238486703
Short name T599
Test name
Test status
Simulation time 160804819 ps
CPU time 4.34 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:15 PM PDT 24
Peak memory 241920 kb
Host smart-34e021d6-c85c-41a1-aa82-34da9478859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238486703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3238486703
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.290599323
Short name T202
Test name
Test status
Simulation time 2060371024 ps
CPU time 6.35 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 242324 kb
Host smart-2ab3c62f-4a85-491f-8be8-901dfb7b0d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290599323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.290599323
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.599578865
Short name T406
Test name
Test status
Simulation time 163844433 ps
CPU time 4.87 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242164 kb
Host smart-c65bc63e-14ca-42f6-bfd0-b27b88ab2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599578865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.599578865
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.392020975
Short name T448
Test name
Test status
Simulation time 222778118 ps
CPU time 5.72 seconds
Started Jul 07 07:09:09 PM PDT 24
Finished Jul 07 07:09:15 PM PDT 24
Peak memory 242176 kb
Host smart-a0095fe4-cdaa-4b1e-8a70-64747d69990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392020975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.392020975
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.3292133994
Short name T152
Test name
Test status
Simulation time 159231429 ps
CPU time 4.49 seconds
Started Jul 07 07:09:13 PM PDT 24
Finished Jul 07 07:09:18 PM PDT 24
Peak memory 241992 kb
Host smart-ee1f53d7-55f2-4371-ad19-50c96ecd03d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292133994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3292133994
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2666471636
Short name T793
Test name
Test status
Simulation time 436897196 ps
CPU time 3.72 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242340 kb
Host smart-3c5dc9cb-e11a-4532-b0fe-ed8bff6b5015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666471636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2666471636
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.3686323188
Short name T1151
Test name
Test status
Simulation time 112209494 ps
CPU time 4.91 seconds
Started Jul 07 07:09:10 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 242116 kb
Host smart-61867269-bca9-47a3-8e87-ea79bc7f0a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686323188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3686323188
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2147750685
Short name T694
Test name
Test status
Simulation time 64119338 ps
CPU time 1.97 seconds
Started Jul 07 07:05:47 PM PDT 24
Finished Jul 07 07:05:49 PM PDT 24
Peak memory 240392 kb
Host smart-047969e0-8656-4fd9-a462-6bff5f606a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147750685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2147750685
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1783773110
Short name T933
Test name
Test status
Simulation time 12284899380 ps
CPU time 32.52 seconds
Started Jul 07 07:05:49 PM PDT 24
Finished Jul 07 07:06:22 PM PDT 24
Peak memory 243076 kb
Host smart-8f459101-33e4-4f52-951e-39e07df20fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783773110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1783773110
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.159725558
Short name T1090
Test name
Test status
Simulation time 466851933 ps
CPU time 20 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:06:08 PM PDT 24
Peak memory 241908 kb
Host smart-4c6bd394-0424-4b9c-8f67-5904b6162075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159725558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.159725558
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.3179775586
Short name T1078
Test name
Test status
Simulation time 772871060 ps
CPU time 16.92 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:06:06 PM PDT 24
Peak memory 242448 kb
Host smart-4cd869af-ab40-47ee-95fd-1fa984f0fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179775586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3179775586
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.544241590
Short name T595
Test name
Test status
Simulation time 199594051 ps
CPU time 5.02 seconds
Started Jul 07 07:05:47 PM PDT 24
Finished Jul 07 07:05:52 PM PDT 24
Peak memory 242052 kb
Host smart-bb5eba35-7a2a-45ae-9eb4-2ab06c40024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544241590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.544241590
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1369861953
Short name T1153
Test name
Test status
Simulation time 269443109 ps
CPU time 6.64 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:05:54 PM PDT 24
Peak memory 241988 kb
Host smart-2dbe3a09-c21f-407f-b536-d77b6fb07237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369861953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1369861953
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1972562333
Short name T1097
Test name
Test status
Simulation time 207763882 ps
CPU time 7.45 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:05:55 PM PDT 24
Peak memory 241896 kb
Host smart-64d45e63-49d3-4d42-a23a-5136de36c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972562333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1972562333
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1837154361
Short name T675
Test name
Test status
Simulation time 2436344684 ps
CPU time 27.31 seconds
Started Jul 07 07:05:46 PM PDT 24
Finished Jul 07 07:06:13 PM PDT 24
Peak memory 242064 kb
Host smart-c05c2c73-b62d-4eeb-8670-f27edd21a04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837154361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1837154361
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.438657001
Short name T1037
Test name
Test status
Simulation time 844494941 ps
CPU time 6.68 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:05:55 PM PDT 24
Peak memory 248732 kb
Host smart-25d339ab-145e-4dbb-b5a5-2f1fd6bacc84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438657001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.438657001
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.2471926000
Short name T579
Test name
Test status
Simulation time 574422816 ps
CPU time 7.44 seconds
Started Jul 07 07:05:44 PM PDT 24
Finished Jul 07 07:05:52 PM PDT 24
Peak memory 242140 kb
Host smart-38114e07-1ca2-47ed-b8d3-d00607d0383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471926000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2471926000
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.4207559878
Short name T335
Test name
Test status
Simulation time 24378916534 ps
CPU time 140.87 seconds
Started Jul 07 07:05:49 PM PDT 24
Finished Jul 07 07:08:10 PM PDT 24
Peak memory 265220 kb
Host smart-d86f1715-e7b7-4e31-88f3-bb0c69a8d9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207559878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.4207559878
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.1893235002
Short name T284
Test name
Test status
Simulation time 21490591004 ps
CPU time 485.93 seconds
Started Jul 07 07:05:49 PM PDT 24
Finished Jul 07 07:13:55 PM PDT 24
Peak memory 248940 kb
Host smart-2d631779-973b-44c7-adad-8535b8482109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893235002 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.1893235002
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.2524352564
Short name T811
Test name
Test status
Simulation time 625749385 ps
CPU time 12.45 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:06:00 PM PDT 24
Peak memory 242196 kb
Host smart-afa36d8e-39d4-44e4-9f05-112b1490eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524352564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2524352564
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.552693239
Short name T785
Test name
Test status
Simulation time 1828292384 ps
CPU time 6.33 seconds
Started Jul 07 07:09:20 PM PDT 24
Finished Jul 07 07:09:27 PM PDT 24
Peak memory 241924 kb
Host smart-2e2362e9-0011-4c49-8669-a521753afd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552693239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.552693239
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.4112192057
Short name T64
Test name
Test status
Simulation time 2260828167 ps
CPU time 6.51 seconds
Started Jul 07 07:09:15 PM PDT 24
Finished Jul 07 07:09:22 PM PDT 24
Peak memory 242132 kb
Host smart-5ec7d23e-d8d5-44a3-a8b0-09095a1abb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112192057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.4112192057
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.3160496724
Short name T681
Test name
Test status
Simulation time 349462986 ps
CPU time 4.84 seconds
Started Jul 07 07:09:14 PM PDT 24
Finished Jul 07 07:09:19 PM PDT 24
Peak memory 242264 kb
Host smart-9520ae32-9e17-4aa3-9155-f4e5d08c14fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160496724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3160496724
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.2532938865
Short name T935
Test name
Test status
Simulation time 219982470 ps
CPU time 3.7 seconds
Started Jul 07 07:09:14 PM PDT 24
Finished Jul 07 07:09:18 PM PDT 24
Peak memory 242140 kb
Host smart-d141b3b9-9a85-40a3-94bb-d221437edfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532938865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2532938865
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.4067450717
Short name T826
Test name
Test status
Simulation time 1580698054 ps
CPU time 4.59 seconds
Started Jul 07 07:09:15 PM PDT 24
Finished Jul 07 07:09:21 PM PDT 24
Peak memory 242252 kb
Host smart-6b6955dc-f474-452e-a6aa-c1fb5cff52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067450717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.4067450717
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1709098521
Short name T176
Test name
Test status
Simulation time 418193397 ps
CPU time 3.22 seconds
Started Jul 07 07:09:15 PM PDT 24
Finished Jul 07 07:09:19 PM PDT 24
Peak memory 242416 kb
Host smart-af151ae1-e90c-422a-bec2-ff1441a7ea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709098521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1709098521
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.619124948
Short name T1129
Test name
Test status
Simulation time 463951525 ps
CPU time 3.56 seconds
Started Jul 07 07:09:13 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 241900 kb
Host smart-fbae8ccf-b9d5-4505-a07f-f0132f88d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619124948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.619124948
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.907675765
Short name T695
Test name
Test status
Simulation time 571675987 ps
CPU time 5.1 seconds
Started Jul 07 07:09:13 PM PDT 24
Finished Jul 07 07:09:19 PM PDT 24
Peak memory 242128 kb
Host smart-e81a9dbd-2e67-4a0b-b345-3389439617d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907675765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.907675765
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.367539848
Short name T855
Test name
Test status
Simulation time 410714194 ps
CPU time 3.5 seconds
Started Jul 07 07:09:20 PM PDT 24
Finished Jul 07 07:09:24 PM PDT 24
Peak memory 242376 kb
Host smart-02a5964f-e894-4f20-bc55-c84809a0f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367539848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.367539848
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.646193447
Short name T628
Test name
Test status
Simulation time 672391783 ps
CPU time 5.03 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:18 PM PDT 24
Peak memory 241804 kb
Host smart-d183c6fc-6e5c-4c2e-bc97-ef05da249430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646193447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.646193447
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1527741180
Short name T454
Test name
Test status
Simulation time 87913379 ps
CPU time 1.92 seconds
Started Jul 07 07:05:55 PM PDT 24
Finished Jul 07 07:05:57 PM PDT 24
Peak memory 240176 kb
Host smart-d04dd545-f490-4eae-924f-99701ccec726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527741180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1527741180
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3983138981
Short name T789
Test name
Test status
Simulation time 572057769 ps
CPU time 7.81 seconds
Started Jul 07 07:05:51 PM PDT 24
Finished Jul 07 07:05:59 PM PDT 24
Peak memory 248772 kb
Host smart-e418b6a9-76b6-4a6d-9db7-4a7bd15331b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983138981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3983138981
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1978644726
Short name T705
Test name
Test status
Simulation time 2038580256 ps
CPU time 25.52 seconds
Started Jul 07 07:05:52 PM PDT 24
Finished Jul 07 07:06:18 PM PDT 24
Peak memory 242488 kb
Host smart-25521714-b73a-4839-8aa1-d808e7e16cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978644726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1978644726
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.882282113
Short name T739
Test name
Test status
Simulation time 2801891940 ps
CPU time 16.72 seconds
Started Jul 07 07:05:50 PM PDT 24
Finished Jul 07 07:06:07 PM PDT 24
Peak memory 242296 kb
Host smart-410d1e07-b290-4bd7-947a-4143762e2bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882282113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.882282113
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.2239318483
Short name T710
Test name
Test status
Simulation time 1629506324 ps
CPU time 5.03 seconds
Started Jul 07 07:05:51 PM PDT 24
Finished Jul 07 07:05:56 PM PDT 24
Peak memory 242092 kb
Host smart-0c87769e-881c-486f-820f-2d01fb351184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239318483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2239318483
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3295314040
Short name T661
Test name
Test status
Simulation time 1657348450 ps
CPU time 24.74 seconds
Started Jul 07 07:05:49 PM PDT 24
Finished Jul 07 07:06:14 PM PDT 24
Peak memory 248832 kb
Host smart-2c2b3eba-3b0b-465e-80ea-5d2e2d97ec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295314040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3295314040
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.450695201
Short name T1085
Test name
Test status
Simulation time 809576241 ps
CPU time 6.57 seconds
Started Jul 07 07:05:50 PM PDT 24
Finished Jul 07 07:05:56 PM PDT 24
Peak memory 248588 kb
Host smart-35ff8eb4-3f37-4e45-ba54-da2f6087885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450695201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.450695201
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2145097692
Short name T1125
Test name
Test status
Simulation time 547311571 ps
CPU time 15.1 seconds
Started Jul 07 07:05:51 PM PDT 24
Finished Jul 07 07:06:06 PM PDT 24
Peak memory 241976 kb
Host smart-7a8e9b52-5231-4dd9-b04b-b46b4639ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145097692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2145097692
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2386329031
Short name T100
Test name
Test status
Simulation time 1497749663 ps
CPU time 24.58 seconds
Started Jul 07 07:05:52 PM PDT 24
Finished Jul 07 07:06:17 PM PDT 24
Peak memory 241908 kb
Host smart-d0da6532-c842-40a9-b6bf-22362c47cd5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386329031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2386329031
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3309299389
Short name T1029
Test name
Test status
Simulation time 2227216117 ps
CPU time 7.73 seconds
Started Jul 07 07:05:52 PM PDT 24
Finished Jul 07 07:06:00 PM PDT 24
Peak memory 242048 kb
Host smart-21b92989-a11c-4d55-b165-a64973cfb8ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309299389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3309299389
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1595743467
Short name T741
Test name
Test status
Simulation time 420489657 ps
CPU time 12.43 seconds
Started Jul 07 07:05:51 PM PDT 24
Finished Jul 07 07:06:04 PM PDT 24
Peak memory 242032 kb
Host smart-0e3d8d1a-85d6-4967-9880-400a465276ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595743467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1595743467
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.801891484
Short name T1004
Test name
Test status
Simulation time 761458885 ps
CPU time 16.5 seconds
Started Jul 07 07:05:52 PM PDT 24
Finished Jul 07 07:06:09 PM PDT 24
Peak memory 242552 kb
Host smart-1d3ca9d1-1c6a-4ae8-8a70-2679f5c26508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801891484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.
801891484
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3507260842
Short name T1064
Test name
Test status
Simulation time 489062187 ps
CPU time 8.25 seconds
Started Jul 07 07:05:48 PM PDT 24
Finished Jul 07 07:05:57 PM PDT 24
Peak memory 242404 kb
Host smart-e96d3f0a-c5dc-4042-88c2-fafbd9f243ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507260842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3507260842
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.236143843
Short name T665
Test name
Test status
Simulation time 565403888 ps
CPU time 4.76 seconds
Started Jul 07 07:09:12 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 242128 kb
Host smart-fcecf15d-49a0-410c-be53-63867ff68587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236143843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.236143843
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2093700614
Short name T487
Test name
Test status
Simulation time 502260082 ps
CPU time 3.99 seconds
Started Jul 07 07:09:15 PM PDT 24
Finished Jul 07 07:09:20 PM PDT 24
Peak memory 242064 kb
Host smart-c4a3f4db-bb34-4936-b870-70bc82e42525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093700614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2093700614
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.2760411935
Short name T426
Test name
Test status
Simulation time 2449458812 ps
CPU time 6.46 seconds
Started Jul 07 07:09:17 PM PDT 24
Finished Jul 07 07:09:24 PM PDT 24
Peak memory 242136 kb
Host smart-3641c082-2565-4068-b4e3-b08a067a51af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760411935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2760411935
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.4005347743
Short name T840
Test name
Test status
Simulation time 390330032 ps
CPU time 4.78 seconds
Started Jul 07 07:09:15 PM PDT 24
Finished Jul 07 07:09:20 PM PDT 24
Peak memory 241956 kb
Host smart-c700d31c-1dea-405a-a5fb-d519bd971fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005347743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4005347743
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1739228826
Short name T1003
Test name
Test status
Simulation time 1771553529 ps
CPU time 5.56 seconds
Started Jul 07 07:09:16 PM PDT 24
Finished Jul 07 07:09:22 PM PDT 24
Peak memory 241956 kb
Host smart-6b895504-0999-41b6-a026-d387e6f47506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739228826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1739228826
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.3206161542
Short name T1013
Test name
Test status
Simulation time 364112605 ps
CPU time 4.57 seconds
Started Jul 07 07:09:17 PM PDT 24
Finished Jul 07 07:09:22 PM PDT 24
Peak memory 242168 kb
Host smart-32188c13-57cf-47dc-9467-a7e10e856f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206161542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3206161542
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2971893306
Short name T865
Test name
Test status
Simulation time 1762648386 ps
CPU time 4.16 seconds
Started Jul 07 07:09:16 PM PDT 24
Finished Jul 07 07:09:21 PM PDT 24
Peak memory 241912 kb
Host smart-bd235141-7944-4dcc-845c-c19cfdb70734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971893306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2971893306
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2317518169
Short name T472
Test name
Test status
Simulation time 2143958686 ps
CPU time 6.41 seconds
Started Jul 07 07:09:17 PM PDT 24
Finished Jul 07 07:09:24 PM PDT 24
Peak memory 242192 kb
Host smart-c00a138b-ee82-4a1e-b794-64d9515faab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317518169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2317518169
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3419548518
Short name T906
Test name
Test status
Simulation time 2120293923 ps
CPU time 5.69 seconds
Started Jul 07 07:09:16 PM PDT 24
Finished Jul 07 07:09:22 PM PDT 24
Peak memory 242280 kb
Host smart-d472c919-ea47-4b26-a1f4-fdbb538ff74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419548518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3419548518
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.1141649830
Short name T210
Test name
Test status
Simulation time 1876678443 ps
CPU time 4.92 seconds
Started Jul 07 07:09:15 PM PDT 24
Finished Jul 07 07:09:20 PM PDT 24
Peak memory 241888 kb
Host smart-52ef5080-ab65-443a-a78d-1f0b753e7775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141649830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1141649830
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3168582144
Short name T514
Test name
Test status
Simulation time 54960664 ps
CPU time 1.78 seconds
Started Jul 07 07:05:56 PM PDT 24
Finished Jul 07 07:05:58 PM PDT 24
Peak memory 240272 kb
Host smart-a8e3d133-35e3-4681-87d0-f95209930e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168582144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3168582144
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3461561954
Short name T75
Test name
Test status
Simulation time 1662268966 ps
CPU time 18.58 seconds
Started Jul 07 07:05:54 PM PDT 24
Finished Jul 07 07:06:13 PM PDT 24
Peak memory 242792 kb
Host smart-d6390b54-4031-4a6a-87c4-5e3a0441b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461561954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3461561954
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1810499372
Short name T463
Test name
Test status
Simulation time 1107596787 ps
CPU time 30 seconds
Started Jul 07 07:05:56 PM PDT 24
Finished Jul 07 07:06:27 PM PDT 24
Peak memory 244196 kb
Host smart-dc276cc4-58c6-4c9b-910c-f6840148af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810499372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1810499372
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.1733184556
Short name T991
Test name
Test status
Simulation time 742382802 ps
CPU time 14.06 seconds
Started Jul 07 07:05:54 PM PDT 24
Finished Jul 07 07:06:09 PM PDT 24
Peak memory 242260 kb
Host smart-360d8a40-aa6c-42d2-b3db-025d55140826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733184556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1733184556
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2915767967
Short name T460
Test name
Test status
Simulation time 482956944 ps
CPU time 4.34 seconds
Started Jul 07 07:05:55 PM PDT 24
Finished Jul 07 07:05:59 PM PDT 24
Peak memory 242060 kb
Host smart-57d070da-9796-49e6-ac1c-cbbc262810a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915767967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2915767967
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.2482356381
Short name T496
Test name
Test status
Simulation time 746857183 ps
CPU time 8.84 seconds
Started Jul 07 07:05:53 PM PDT 24
Finished Jul 07 07:06:03 PM PDT 24
Peak memory 242308 kb
Host smart-fb3396c1-2137-452c-933d-2756ba8efd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482356381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2482356381
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.4293190770
Short name T405
Test name
Test status
Simulation time 3533207139 ps
CPU time 10.62 seconds
Started Jul 07 07:05:54 PM PDT 24
Finished Jul 07 07:06:04 PM PDT 24
Peak memory 242000 kb
Host smart-12ccf4cd-bda6-4689-9d56-a5a2941a3397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293190770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.4293190770
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2979792233
Short name T593
Test name
Test status
Simulation time 3030370882 ps
CPU time 28.7 seconds
Started Jul 07 07:05:56 PM PDT 24
Finished Jul 07 07:06:25 PM PDT 24
Peak memory 241924 kb
Host smart-3ad3b79d-d07f-4742-a758-e9caa8cb5315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979792233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2979792233
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3607370108
Short name T984
Test name
Test status
Simulation time 1076569562 ps
CPU time 17.99 seconds
Started Jul 07 07:05:59 PM PDT 24
Finished Jul 07 07:06:17 PM PDT 24
Peak memory 248736 kb
Host smart-6509656f-46f1-4721-bf33-78d73cbe180f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607370108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3607370108
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2961297998
Short name T94
Test name
Test status
Simulation time 942531073 ps
CPU time 7.2 seconds
Started Jul 07 07:05:54 PM PDT 24
Finished Jul 07 07:06:01 PM PDT 24
Peak memory 241964 kb
Host smart-90cd4421-b156-4b61-8c9a-12747fb1dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961297998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2961297998
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.815940043
Short name T861
Test name
Test status
Simulation time 32138092849 ps
CPU time 195.89 seconds
Started Jul 07 07:05:59 PM PDT 24
Finished Jul 07 07:09:16 PM PDT 24
Peak memory 257024 kb
Host smart-868ea0f8-4620-4f68-af10-76dbab1291dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815940043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
815940043
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.4171101020
Short name T220
Test name
Test status
Simulation time 152188008738 ps
CPU time 1785.22 seconds
Started Jul 07 07:05:59 PM PDT 24
Finished Jul 07 07:35:45 PM PDT 24
Peak memory 354096 kb
Host smart-a57460e6-866f-4c6b-b980-d4cd8f8fcbbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171101020 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.4171101020
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3401334549
Short name T780
Test name
Test status
Simulation time 2220851106 ps
CPU time 12.17 seconds
Started Jul 07 07:05:57 PM PDT 24
Finished Jul 07 07:06:10 PM PDT 24
Peak memory 242316 kb
Host smart-349ec05c-6258-4272-82c7-fdc0a8894b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401334549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3401334549
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.1331969731
Short name T184
Test name
Test status
Simulation time 163089559 ps
CPU time 4.09 seconds
Started Jul 07 07:09:18 PM PDT 24
Finished Jul 07 07:09:22 PM PDT 24
Peak memory 242028 kb
Host smart-b0c4a8e9-ae6f-47ea-b6bb-3212eaae0b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331969731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1331969731
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1429150792
Short name T55
Test name
Test status
Simulation time 193875581 ps
CPU time 5.7 seconds
Started Jul 07 07:09:21 PM PDT 24
Finished Jul 07 07:09:27 PM PDT 24
Peak memory 241960 kb
Host smart-d0aadcb6-1dff-4441-9933-bf72316bb2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429150792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1429150792
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3098050341
Short name T891
Test name
Test status
Simulation time 710489984 ps
CPU time 5.89 seconds
Started Jul 07 07:09:18 PM PDT 24
Finished Jul 07 07:09:25 PM PDT 24
Peak memory 242392 kb
Host smart-ad68dc04-8418-480b-9c66-2ab7cbf73fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098050341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3098050341
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.918733538
Short name T173
Test name
Test status
Simulation time 228573466 ps
CPU time 4.03 seconds
Started Jul 07 07:09:18 PM PDT 24
Finished Jul 07 07:09:23 PM PDT 24
Peak memory 241968 kb
Host smart-273abf2f-8354-4a6b-adb0-863c2aff0443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918733538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.918733538
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.1876110683
Short name T493
Test name
Test status
Simulation time 644861248 ps
CPU time 4.04 seconds
Started Jul 07 07:09:17 PM PDT 24
Finished Jul 07 07:09:22 PM PDT 24
Peak memory 242016 kb
Host smart-3dd79342-364d-482c-b738-9c0a28e5097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876110683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1876110683
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.2864161648
Short name T203
Test name
Test status
Simulation time 528299119 ps
CPU time 4.96 seconds
Started Jul 07 07:09:18 PM PDT 24
Finished Jul 07 07:09:24 PM PDT 24
Peak memory 241988 kb
Host smart-850d7d35-9d8d-4c31-bf93-4b6df805f0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864161648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2864161648
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.3266882543
Short name T46
Test name
Test status
Simulation time 259066761 ps
CPU time 4.86 seconds
Started Jul 07 07:09:19 PM PDT 24
Finished Jul 07 07:09:25 PM PDT 24
Peak memory 242080 kb
Host smart-7c45cccb-2a26-407f-aa9a-63a8770025ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266882543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3266882543
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1600944654
Short name T250
Test name
Test status
Simulation time 99352269 ps
CPU time 4.24 seconds
Started Jul 07 07:09:22 PM PDT 24
Finished Jul 07 07:09:26 PM PDT 24
Peak memory 242088 kb
Host smart-075a4ecb-8b0d-4569-922c-7ee031e3e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600944654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1600944654
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1201529293
Short name T868
Test name
Test status
Simulation time 1880672068 ps
CPU time 4.22 seconds
Started Jul 07 07:09:19 PM PDT 24
Finished Jul 07 07:09:24 PM PDT 24
Peak memory 242464 kb
Host smart-2982ddb4-ad6e-4d03-8efd-98eaca2073b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201529293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1201529293
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.3826571965
Short name T699
Test name
Test status
Simulation time 109754008 ps
CPU time 4.24 seconds
Started Jul 07 07:09:22 PM PDT 24
Finished Jul 07 07:09:26 PM PDT 24
Peak memory 242020 kb
Host smart-d0ad68b7-49fd-460d-b0b3-aeaab6fa1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826571965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.3826571965
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.4101736765
Short name T775
Test name
Test status
Simulation time 56809387 ps
CPU time 1.8 seconds
Started Jul 07 07:05:59 PM PDT 24
Finished Jul 07 07:06:01 PM PDT 24
Peak memory 240212 kb
Host smart-dc072a0e-436c-475d-834d-7a20091b00da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101736765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.4101736765
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1995991997
Short name T494
Test name
Test status
Simulation time 4500338679 ps
CPU time 14.61 seconds
Started Jul 07 07:05:57 PM PDT 24
Finished Jul 07 07:06:12 PM PDT 24
Peak memory 243052 kb
Host smart-c33169f3-963e-44f5-ac19-c3c7f183552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995991997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1995991997
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1382615911
Short name T1122
Test name
Test status
Simulation time 1651213252 ps
CPU time 10.22 seconds
Started Jul 07 07:06:01 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 242240 kb
Host smart-b71aea90-8f6f-4501-b9f0-c0bf540024b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382615911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1382615911
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.2407884062
Short name T523
Test name
Test status
Simulation time 970794629 ps
CPU time 21.47 seconds
Started Jul 07 07:05:56 PM PDT 24
Finished Jul 07 07:06:18 PM PDT 24
Peak memory 242072 kb
Host smart-2f926639-6269-4b69-b600-92926afb09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407884062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2407884062
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.897382608
Short name T1011
Test name
Test status
Simulation time 518065011 ps
CPU time 4.95 seconds
Started Jul 07 07:05:59 PM PDT 24
Finished Jul 07 07:06:04 PM PDT 24
Peak memory 242056 kb
Host smart-3e4bc62a-b53b-43a5-a50c-f0ccf7ee81e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897382608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.897382608
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2917779514
Short name T931
Test name
Test status
Simulation time 462051334 ps
CPU time 16.72 seconds
Started Jul 07 07:05:57 PM PDT 24
Finished Jul 07 07:06:14 PM PDT 24
Peak memory 244028 kb
Host smart-03de7284-bc35-4f0a-955a-4bff9b862012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917779514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2917779514
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2959664331
Short name T764
Test name
Test status
Simulation time 2187351690 ps
CPU time 7.78 seconds
Started Jul 07 07:05:57 PM PDT 24
Finished Jul 07 07:06:05 PM PDT 24
Peak memory 242400 kb
Host smart-bb3762bc-fbd4-445d-9d50-abc18e08486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959664331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2959664331
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.111572331
Short name T687
Test name
Test status
Simulation time 566329147 ps
CPU time 9.25 seconds
Started Jul 07 07:05:59 PM PDT 24
Finished Jul 07 07:06:08 PM PDT 24
Peak memory 241864 kb
Host smart-00a96fe7-bca4-4174-8a31-f7e420f5b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111572331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.111572331
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2382914307
Short name T1189
Test name
Test status
Simulation time 173687336 ps
CPU time 6.04 seconds
Started Jul 07 07:05:56 PM PDT 24
Finished Jul 07 07:06:03 PM PDT 24
Peak memory 242368 kb
Host smart-9263ef4b-46a5-4ebe-bf34-5b4ca4c5e3a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382914307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2382914307
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.459626966
Short name T364
Test name
Test status
Simulation time 296869584 ps
CPU time 3.07 seconds
Started Jul 07 07:05:58 PM PDT 24
Finished Jul 07 07:06:02 PM PDT 24
Peak memory 241876 kb
Host smart-25c329c8-644c-4e9d-bcbe-95cdb80dbe2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459626966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.459626966
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.3193782621
Short name T691
Test name
Test status
Simulation time 4889906716 ps
CPU time 17.03 seconds
Started Jul 07 07:05:58 PM PDT 24
Finished Jul 07 07:06:15 PM PDT 24
Peak memory 242860 kb
Host smart-b95bc24b-9be3-47ca-bf05-e2700277c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193782621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3193782621
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2782348049
Short name T697
Test name
Test status
Simulation time 1770143622 ps
CPU time 59.23 seconds
Started Jul 07 07:06:03 PM PDT 24
Finished Jul 07 07:07:02 PM PDT 24
Peak memory 244792 kb
Host smart-518db4d2-0835-4c19-a172-d2a3705de929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782348049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2782348049
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.1016555211
Short name T292
Test name
Test status
Simulation time 284278148720 ps
CPU time 1313.18 seconds
Started Jul 07 07:06:02 PM PDT 24
Finished Jul 07 07:27:56 PM PDT 24
Peak memory 263380 kb
Host smart-6d86b40a-bcd0-4af7-8768-1e7b6f602747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016555211 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.1016555211
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.330097809
Short name T1034
Test name
Test status
Simulation time 1459694797 ps
CPU time 23.49 seconds
Started Jul 07 07:05:57 PM PDT 24
Finished Jul 07 07:06:21 PM PDT 24
Peak memory 242256 kb
Host smart-c6defc2d-1507-48b2-a05e-23106bd05116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330097809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.330097809
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.510730189
Short name T786
Test name
Test status
Simulation time 1906601413 ps
CPU time 5 seconds
Started Jul 07 07:09:19 PM PDT 24
Finished Jul 07 07:09:25 PM PDT 24
Peak memory 242160 kb
Host smart-f466c36b-9c57-4dd3-bc21-9e11871d9dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510730189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.510730189
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2050732377
Short name T139
Test name
Test status
Simulation time 389246790 ps
CPU time 4.67 seconds
Started Jul 07 07:09:24 PM PDT 24
Finished Jul 07 07:09:29 PM PDT 24
Peak memory 241808 kb
Host smart-27c1ef88-05da-4a62-b7b4-1839fe6ec400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050732377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2050732377
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.3004420620
Short name T517
Test name
Test status
Simulation time 270303926 ps
CPU time 4.06 seconds
Started Jul 07 07:09:24 PM PDT 24
Finished Jul 07 07:09:28 PM PDT 24
Peak memory 242368 kb
Host smart-27e82af4-170c-4aa1-bd6e-940b0bca64e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004420620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3004420620
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3443127274
Short name T423
Test name
Test status
Simulation time 165914526 ps
CPU time 3.31 seconds
Started Jul 07 07:09:28 PM PDT 24
Finished Jul 07 07:09:32 PM PDT 24
Peak memory 242160 kb
Host smart-df72a784-997e-47ea-adbb-e21a9823c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443127274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3443127274
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.4119085959
Short name T731
Test name
Test status
Simulation time 522781470 ps
CPU time 4.27 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 241928 kb
Host smart-6c7ab7d0-8e84-4ca3-baf7-d43f8212d952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119085959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.4119085959
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.2901297060
Short name T849
Test name
Test status
Simulation time 428337850 ps
CPU time 4.63 seconds
Started Jul 07 07:09:23 PM PDT 24
Finished Jul 07 07:09:28 PM PDT 24
Peak memory 241748 kb
Host smart-9b089966-349b-46d3-b6dd-a97899ba7589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901297060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2901297060
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.3010552892
Short name T47
Test name
Test status
Simulation time 300304678 ps
CPU time 4.37 seconds
Started Jul 07 07:09:27 PM PDT 24
Finished Jul 07 07:09:32 PM PDT 24
Peak memory 241816 kb
Host smart-7886f5fa-b6a7-4fbb-b268-3bc143d1c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010552892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3010552892
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.2594122556
Short name T585
Test name
Test status
Simulation time 1401453422 ps
CPU time 4.44 seconds
Started Jul 07 07:09:25 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 241968 kb
Host smart-d18a67b0-47e4-472d-8d5e-70b2685b634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594122556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2594122556
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.683063764
Short name T465
Test name
Test status
Simulation time 237315895 ps
CPU time 4.96 seconds
Started Jul 07 07:09:23 PM PDT 24
Finished Jul 07 07:09:28 PM PDT 24
Peak memory 242084 kb
Host smart-ff68e1e7-232f-4537-9d79-2b129ab61011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683063764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.683063764
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1837034466
Short name T433
Test name
Test status
Simulation time 66138553 ps
CPU time 1.85 seconds
Started Jul 07 07:06:12 PM PDT 24
Finished Jul 07 07:06:14 PM PDT 24
Peak memory 240156 kb
Host smart-d6cdf3fa-f97a-4be2-afb9-74f803991159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837034466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1837034466
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.1414990904
Short name T138
Test name
Test status
Simulation time 2156647170 ps
CPU time 23.98 seconds
Started Jul 07 07:06:01 PM PDT 24
Finished Jul 07 07:06:26 PM PDT 24
Peak memory 244348 kb
Host smart-bcba1f04-4f14-4009-9023-0cf47c8e9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414990904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1414990904
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2497377122
Short name T400
Test name
Test status
Simulation time 16249887457 ps
CPU time 54.73 seconds
Started Jul 07 07:06:01 PM PDT 24
Finished Jul 07 07:06:56 PM PDT 24
Peak memory 249260 kb
Host smart-1181b770-a05a-48aa-a580-d1eff6b3a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497377122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2497377122
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.135548879
Short name T551
Test name
Test status
Simulation time 1584103535 ps
CPU time 14.71 seconds
Started Jul 07 07:06:03 PM PDT 24
Finished Jul 07 07:06:18 PM PDT 24
Peak memory 242612 kb
Host smart-dd0bc291-b489-40d4-afbd-d3cc8370ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135548879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.135548879
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.121322547
Short name T818
Test name
Test status
Simulation time 1820033514 ps
CPU time 5.34 seconds
Started Jul 07 07:05:58 PM PDT 24
Finished Jul 07 07:06:04 PM PDT 24
Peak memory 242104 kb
Host smart-68438d58-0175-48c9-875e-ed7b89a8517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121322547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.121322547
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.37664719
Short name T692
Test name
Test status
Simulation time 13275796846 ps
CPU time 38.41 seconds
Started Jul 07 07:06:02 PM PDT 24
Finished Jul 07 07:06:41 PM PDT 24
Peak memory 246004 kb
Host smart-01e415b0-8702-433e-97fe-ced7934a987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37664719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.37664719
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3866174596
Short name T591
Test name
Test status
Simulation time 674374204 ps
CPU time 7.96 seconds
Started Jul 07 07:06:03 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 248796 kb
Host smart-b7f33960-bc56-4d4b-8dbc-09ce677f26b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866174596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3866174596
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1663623854
Short name T195
Test name
Test status
Simulation time 1860020713 ps
CPU time 16.54 seconds
Started Jul 07 07:06:02 PM PDT 24
Finished Jul 07 07:06:19 PM PDT 24
Peak memory 241964 kb
Host smart-422d3796-d658-48b4-b01d-e81892e10699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663623854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1663623854
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.745008543
Short name T1172
Test name
Test status
Simulation time 1394870657 ps
CPU time 19.67 seconds
Started Jul 07 07:06:01 PM PDT 24
Finished Jul 07 07:06:21 PM PDT 24
Peak memory 242252 kb
Host smart-6657bd30-029e-4d58-bad6-57188c81cf42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745008543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.745008543
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.642898900
Short name T960
Test name
Test status
Simulation time 418056096 ps
CPU time 9 seconds
Started Jul 07 07:06:02 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 242328 kb
Host smart-46fd9f9f-4b8b-4b4c-8645-b72ccfc5aedf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642898900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.642898900
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.3245125924
Short name T1086
Test name
Test status
Simulation time 1032868485 ps
CPU time 7.63 seconds
Started Jul 07 07:06:01 PM PDT 24
Finished Jul 07 07:06:08 PM PDT 24
Peak memory 242284 kb
Host smart-1660efcd-1c27-4331-9d1a-c07ee8fe1bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245125924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3245125924
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.1473089930
Short name T230
Test name
Test status
Simulation time 319070209750 ps
CPU time 585.85 seconds
Started Jul 07 07:06:05 PM PDT 24
Finished Jul 07 07:15:51 PM PDT 24
Peak memory 284508 kb
Host smart-ac016bf7-4a8c-4f0f-b8ac-1ef851099f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473089930 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.1473089930
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.1781813452
Short name T833
Test name
Test status
Simulation time 1171362021 ps
CPU time 16.46 seconds
Started Jul 07 07:06:06 PM PDT 24
Finished Jul 07 07:06:23 PM PDT 24
Peak memory 242308 kb
Host smart-e6821974-0f7d-47b4-a805-a0aabcbc7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781813452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1781813452
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3508466064
Short name T1167
Test name
Test status
Simulation time 230554464 ps
CPU time 4.49 seconds
Started Jul 07 07:09:22 PM PDT 24
Finished Jul 07 07:09:27 PM PDT 24
Peak memory 242072 kb
Host smart-a05feeed-5dfd-4be8-a867-37a4a1d18f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508466064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3508466064
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3988058788
Short name T216
Test name
Test status
Simulation time 189779587 ps
CPU time 4.07 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 241884 kb
Host smart-df8d38bc-4851-45c5-a910-a9dd047f5950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988058788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3988058788
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2052720209
Short name T985
Test name
Test status
Simulation time 202768038 ps
CPU time 4.02 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 242020 kb
Host smart-1be89a97-8767-436b-bcd5-8d77471fd9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052720209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2052720209
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.4221444624
Short name T555
Test name
Test status
Simulation time 152020661 ps
CPU time 3.78 seconds
Started Jul 07 07:09:25 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 242256 kb
Host smart-7ad57a0a-a079-4a81-98bc-6e6a22c37777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221444624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.4221444624
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3237139063
Short name T801
Test name
Test status
Simulation time 2701255492 ps
CPU time 6.58 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:33 PM PDT 24
Peak memory 242056 kb
Host smart-8d8d9913-b60d-4d92-953c-b360b9c5a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237139063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3237139063
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.929729341
Short name T858
Test name
Test status
Simulation time 2629963563 ps
CPU time 6.5 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:33 PM PDT 24
Peak memory 242252 kb
Host smart-2fbf8085-d247-4187-9f89-b96d8b903c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929729341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.929729341
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3481067772
Short name T797
Test name
Test status
Simulation time 2187786997 ps
CPU time 6.15 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:33 PM PDT 24
Peak memory 242200 kb
Host smart-5a844a92-b166-46e5-9bea-68552d319b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481067772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3481067772
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2935988586
Short name T649
Test name
Test status
Simulation time 164428945 ps
CPU time 3.56 seconds
Started Jul 07 07:09:27 PM PDT 24
Finished Jul 07 07:09:31 PM PDT 24
Peak memory 242176 kb
Host smart-d50db8be-704f-4b8d-8b73-a6c256be3320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935988586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2935988586
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3904573186
Short name T488
Test name
Test status
Simulation time 381851444 ps
CPU time 3.92 seconds
Started Jul 07 07:09:28 PM PDT 24
Finished Jul 07 07:09:32 PM PDT 24
Peak memory 242048 kb
Host smart-bdc11d9d-e486-404c-bab0-d682357b8bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904573186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3904573186
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1780221755
Short name T1062
Test name
Test status
Simulation time 155519975 ps
CPU time 3.73 seconds
Started Jul 07 07:09:27 PM PDT 24
Finished Jul 07 07:09:31 PM PDT 24
Peak memory 242124 kb
Host smart-5d616db3-b9df-490a-8597-917029d8e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780221755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1780221755
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.622337732
Short name T636
Test name
Test status
Simulation time 80224863 ps
CPU time 1.93 seconds
Started Jul 07 07:06:12 PM PDT 24
Finished Jul 07 07:06:14 PM PDT 24
Peak memory 240424 kb
Host smart-5a7699d4-bd35-4b11-aefb-e710e2587cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622337732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.622337732
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.3409632437
Short name T1091
Test name
Test status
Simulation time 2105630604 ps
CPU time 21.44 seconds
Started Jul 07 07:06:03 PM PDT 24
Finished Jul 07 07:06:25 PM PDT 24
Peak memory 248816 kb
Host smart-23c42ffb-6be1-4501-b2d6-ab0583929d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409632437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3409632437
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.2566113257
Short name T1194
Test name
Test status
Simulation time 407816305 ps
CPU time 25.75 seconds
Started Jul 07 07:06:08 PM PDT 24
Finished Jul 07 07:06:34 PM PDT 24
Peak memory 242160 kb
Host smart-73d368b4-20a2-4fd6-931d-943c14df6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566113257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2566113257
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3324935872
Short name T421
Test name
Test status
Simulation time 11360475253 ps
CPU time 25.77 seconds
Started Jul 07 07:06:03 PM PDT 24
Finished Jul 07 07:06:29 PM PDT 24
Peak memory 243996 kb
Host smart-fa14e98e-1c08-434e-8ab1-4eee216fd02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324935872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3324935872
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.733764640
Short name T975
Test name
Test status
Simulation time 606589336 ps
CPU time 4.81 seconds
Started Jul 07 07:06:02 PM PDT 24
Finished Jul 07 07:06:08 PM PDT 24
Peak memory 242324 kb
Host smart-a8ba02ef-ff4c-45e3-9d32-db9d25f76ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733764640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.733764640
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.2659764112
Short name T193
Test name
Test status
Simulation time 583540651 ps
CPU time 14.03 seconds
Started Jul 07 07:06:02 PM PDT 24
Finished Jul 07 07:06:17 PM PDT 24
Peak memory 243688 kb
Host smart-d946b9ad-a832-4613-937f-aa1a46ffe4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659764112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2659764112
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3102466477
Short name T950
Test name
Test status
Simulation time 898598685 ps
CPU time 24.99 seconds
Started Jul 07 07:06:08 PM PDT 24
Finished Jul 07 07:06:33 PM PDT 24
Peak memory 248704 kb
Host smart-4e0742e3-7fba-49e9-a8f7-8b37f247658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102466477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3102466477
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.1495341455
Short name T900
Test name
Test status
Simulation time 755861676 ps
CPU time 6.94 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:18 PM PDT 24
Peak memory 241892 kb
Host smart-f226fbf4-fcfc-41a9-b5e9-4520dc1a353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495341455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1495341455
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1555294017
Short name T158
Test name
Test status
Simulation time 729839272 ps
CPU time 14.11 seconds
Started Jul 07 07:06:04 PM PDT 24
Finished Jul 07 07:06:18 PM PDT 24
Peak memory 242080 kb
Host smart-ae781221-379f-412b-8a4a-0d59633d1326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555294017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1555294017
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.3401456928
Short name T1124
Test name
Test status
Simulation time 468705085 ps
CPU time 4.44 seconds
Started Jul 07 07:06:06 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 242252 kb
Host smart-a5ad3f75-ccc2-46b1-b6be-a0e6a47fe98d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401456928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3401456928
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.24994877
Short name T653
Test name
Test status
Simulation time 1979732665 ps
CPU time 6.18 seconds
Started Jul 07 07:06:04 PM PDT 24
Finished Jul 07 07:06:11 PM PDT 24
Peak memory 242116 kb
Host smart-92499c20-ad5d-495d-872d-d79ed33dd565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24994877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.24994877
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.3739777344
Short name T817
Test name
Test status
Simulation time 161074528902 ps
CPU time 258.12 seconds
Started Jul 07 07:06:07 PM PDT 24
Finished Jul 07 07:10:25 PM PDT 24
Peak memory 257028 kb
Host smart-3a4b717d-cce6-4e49-99b5-cf1292716158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739777344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.3739777344
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1730203075
Short name T280
Test name
Test status
Simulation time 143450232817 ps
CPU time 1293.77 seconds
Started Jul 07 07:06:07 PM PDT 24
Finished Jul 07 07:27:41 PM PDT 24
Peak memory 459472 kb
Host smart-7df16b72-874b-4fee-96bf-94d630de3bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730203075 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1730203075
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.2956784066
Short name T1052
Test name
Test status
Simulation time 4646686241 ps
CPU time 29.94 seconds
Started Jul 07 07:06:06 PM PDT 24
Finished Jul 07 07:06:36 PM PDT 24
Peak memory 242120 kb
Host smart-56623826-3d7e-4ec7-b8ae-b847c8827347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956784066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2956784066
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2311824126
Short name T36
Test name
Test status
Simulation time 369641529 ps
CPU time 5.47 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:32 PM PDT 24
Peak memory 241996 kb
Host smart-09d73d36-b214-4451-aa67-a82b75bf9ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311824126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2311824126
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.2908287477
Short name T1158
Test name
Test status
Simulation time 433348906 ps
CPU time 4.3 seconds
Started Jul 07 07:09:25 PM PDT 24
Finished Jul 07 07:09:29 PM PDT 24
Peak memory 242128 kb
Host smart-12ce3697-a12f-4177-b530-efa830b9b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908287477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2908287477
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.1845083111
Short name T68
Test name
Test status
Simulation time 577830703 ps
CPU time 4.76 seconds
Started Jul 07 07:09:27 PM PDT 24
Finished Jul 07 07:09:32 PM PDT 24
Peak memory 242172 kb
Host smart-30dbec93-58b5-42b5-b649-5871cb0ef135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845083111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1845083111
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1870107006
Short name T63
Test name
Test status
Simulation time 423241880 ps
CPU time 5.04 seconds
Started Jul 07 07:09:28 PM PDT 24
Finished Jul 07 07:09:33 PM PDT 24
Peak memory 242088 kb
Host smart-fc838f81-d09c-4b2f-a9a1-7eafaf4d1abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870107006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1870107006
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3365652904
Short name T119
Test name
Test status
Simulation time 100508034 ps
CPU time 3.95 seconds
Started Jul 07 07:09:27 PM PDT 24
Finished Jul 07 07:09:31 PM PDT 24
Peak memory 242396 kb
Host smart-6dc27d37-e3fd-436a-acc0-833a0d677c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365652904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3365652904
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.383547838
Short name T1100
Test name
Test status
Simulation time 187315311 ps
CPU time 3.66 seconds
Started Jul 07 07:09:26 PM PDT 24
Finished Jul 07 07:09:30 PM PDT 24
Peak memory 241892 kb
Host smart-410db5a6-c268-4a50-868f-b6a6bd996dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383547838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.383547838
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.4265260203
Short name T206
Test name
Test status
Simulation time 305930094 ps
CPU time 4.03 seconds
Started Jul 07 07:09:29 PM PDT 24
Finished Jul 07 07:09:33 PM PDT 24
Peak memory 242492 kb
Host smart-1b78f74e-5e80-4e4b-8909-a5ef01dd313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265260203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.4265260203
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1527579696
Short name T1156
Test name
Test status
Simulation time 496004987 ps
CPU time 4.33 seconds
Started Jul 07 07:09:32 PM PDT 24
Finished Jul 07 07:09:36 PM PDT 24
Peak memory 242396 kb
Host smart-6c92efa4-92da-4a04-9878-d2efac83c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527579696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1527579696
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.512533828
Short name T910
Test name
Test status
Simulation time 339873372 ps
CPU time 4.17 seconds
Started Jul 07 07:09:29 PM PDT 24
Finished Jul 07 07:09:33 PM PDT 24
Peak memory 242020 kb
Host smart-b06a29ae-a9a7-40e3-8c86-cbbce7bfb5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512533828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.512533828
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.1137600424
Short name T1142
Test name
Test status
Simulation time 200242944 ps
CPU time 1.91 seconds
Started Jul 07 07:04:26 PM PDT 24
Finished Jul 07 07:04:29 PM PDT 24
Peak memory 240176 kb
Host smart-e69d7a39-8bf7-40a9-ba60-cba242061cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137600424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1137600424
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.1893993948
Short name T386
Test name
Test status
Simulation time 436000246 ps
CPU time 14.95 seconds
Started Jul 07 07:04:25 PM PDT 24
Finished Jul 07 07:04:40 PM PDT 24
Peak memory 242080 kb
Host smart-4a5c98b5-8fb1-4565-829b-1971e436f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893993948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1893993948
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.597399174
Short name T949
Test name
Test status
Simulation time 16053462450 ps
CPU time 23.01 seconds
Started Jul 07 07:04:23 PM PDT 24
Finished Jul 07 07:04:46 PM PDT 24
Peak memory 248852 kb
Host smart-43de8a6a-dd66-4e62-9195-bfc99ac292e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597399174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.597399174
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1701512819
Short name T952
Test name
Test status
Simulation time 1633413110 ps
CPU time 23.49 seconds
Started Jul 07 07:04:26 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 241872 kb
Host smart-e440bc22-844e-44d5-b416-634a55ae12c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701512819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1701512819
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.2675650313
Short name T484
Test name
Test status
Simulation time 6308256267 ps
CPU time 34.45 seconds
Started Jul 07 07:04:23 PM PDT 24
Finished Jul 07 07:04:58 PM PDT 24
Peak memory 243016 kb
Host smart-76a96a23-4ead-41b1-9c53-2b44936bc1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675650313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2675650313
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.310275919
Short name T402
Test name
Test status
Simulation time 605668536 ps
CPU time 4.39 seconds
Started Jul 07 07:04:23 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 242360 kb
Host smart-1f35f1ce-93b9-4737-b402-b6f6fce92953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310275919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.310275919
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.2564516237
Short name T425
Test name
Test status
Simulation time 168388210 ps
CPU time 4.56 seconds
Started Jul 07 07:04:25 PM PDT 24
Finished Jul 07 07:04:29 PM PDT 24
Peak memory 242580 kb
Host smart-d765800c-749b-4316-8f3a-35f04fc9db85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564516237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2564516237
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3085342019
Short name T685
Test name
Test status
Simulation time 2424413041 ps
CPU time 32.42 seconds
Started Jul 07 07:04:22 PM PDT 24
Finished Jul 07 07:04:55 PM PDT 24
Peak memory 242068 kb
Host smart-daebb743-c59e-4629-a9c6-8026811b6645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085342019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3085342019
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.207180194
Short name T1188
Test name
Test status
Simulation time 3659310981 ps
CPU time 8.62 seconds
Started Jul 07 07:04:24 PM PDT 24
Finished Jul 07 07:04:33 PM PDT 24
Peak memory 241852 kb
Host smart-7fd7a088-361e-48ec-ad01-7b0a2d32fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207180194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.207180194
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2100221663
Short name T1025
Test name
Test status
Simulation time 1813269423 ps
CPU time 25.96 seconds
Started Jul 07 07:04:23 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 248728 kb
Host smart-fdebbb04-0606-4406-a01f-07d42545326f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100221663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2100221663
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3687904324
Short name T612
Test name
Test status
Simulation time 142094822 ps
CPU time 4.83 seconds
Started Jul 07 07:04:23 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 241968 kb
Host smart-783ea465-98ae-4696-b64c-65282ab104ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3687904324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3687904324
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2949552696
Short name T24
Test name
Test status
Simulation time 20629868236 ps
CPU time 186.8 seconds
Started Jul 07 07:04:27 PM PDT 24
Finished Jul 07 07:07:34 PM PDT 24
Peak memory 278488 kb
Host smart-0dcd70d1-79d0-4150-b4f5-c891b087073f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949552696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2949552696
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.3639073731
Short name T301
Test name
Test status
Simulation time 216569314 ps
CPU time 5.72 seconds
Started Jul 07 07:04:23 PM PDT 24
Finished Jul 07 07:04:29 PM PDT 24
Peak memory 241876 kb
Host smart-e1d32bf4-8e6d-4b25-9332-1b6a05a8a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639073731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3639073731
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.1315140927
Short name T803
Test name
Test status
Simulation time 10863010549 ps
CPU time 155.74 seconds
Started Jul 07 07:04:28 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 246684 kb
Host smart-c8c92822-e76b-42c5-9e5d-ec9f4f048900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315140927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
1315140927
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.850256079
Short name T298
Test name
Test status
Simulation time 460152654 ps
CPU time 6.45 seconds
Started Jul 07 07:04:26 PM PDT 24
Finished Jul 07 07:04:32 PM PDT 24
Peak memory 242144 kb
Host smart-fb332e12-e2a9-4e42-97f7-e67d8dcfc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850256079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.850256079
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2849244205
Short name T939
Test name
Test status
Simulation time 99251041 ps
CPU time 1.78 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:12 PM PDT 24
Peak memory 240360 kb
Host smart-cf0974f8-458a-4830-adc4-154ea36797a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849244205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2849244205
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.3691459321
Short name T1176
Test name
Test status
Simulation time 361703743 ps
CPU time 3.4 seconds
Started Jul 07 07:06:08 PM PDT 24
Finished Jul 07 07:06:12 PM PDT 24
Peak memory 248588 kb
Host smart-71f8d535-fafb-4861-840a-cda30235cbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691459321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3691459321
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.3464852834
Short name T954
Test name
Test status
Simulation time 8796439081 ps
CPU time 20.46 seconds
Started Jul 07 07:06:08 PM PDT 24
Finished Jul 07 07:06:28 PM PDT 24
Peak memory 242100 kb
Host smart-66c5d0d3-5475-44ff-a915-8c7a72005242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464852834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3464852834
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.1721860878
Short name T679
Test name
Test status
Simulation time 1306990811 ps
CPU time 16.39 seconds
Started Jul 07 07:06:09 PM PDT 24
Finished Jul 07 07:06:26 PM PDT 24
Peak memory 242544 kb
Host smart-331507c3-1f05-4068-88d6-13d64082e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721860878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1721860878
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.4188256749
Short name T990
Test name
Test status
Simulation time 1727323992 ps
CPU time 5.11 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:15 PM PDT 24
Peak memory 242056 kb
Host smart-cb2f5d19-e22b-4bee-a068-3fb0f22800ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188256749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.4188256749
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.3474639780
Short name T813
Test name
Test status
Simulation time 1744141298 ps
CPU time 19.27 seconds
Started Jul 07 07:06:13 PM PDT 24
Finished Jul 07 07:06:33 PM PDT 24
Peak memory 242564 kb
Host smart-82fecede-319c-4d01-9e6f-4361fba0c789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474639780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3474639780
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.2948537858
Short name T508
Test name
Test status
Simulation time 1714899957 ps
CPU time 18.89 seconds
Started Jul 07 07:06:08 PM PDT 24
Finished Jul 07 07:06:28 PM PDT 24
Peak memory 241964 kb
Host smart-32178bae-1716-4ae3-8fbb-7029d1c936a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948537858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2948537858
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3496113885
Short name T765
Test name
Test status
Simulation time 1300412480 ps
CPU time 10.49 seconds
Started Jul 07 07:06:06 PM PDT 24
Finished Jul 07 07:06:17 PM PDT 24
Peak memory 242148 kb
Host smart-29933f03-db89-4672-b246-1bd2f0743785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496113885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3496113885
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3277527883
Short name T727
Test name
Test status
Simulation time 2386579933 ps
CPU time 19.63 seconds
Started Jul 07 07:06:09 PM PDT 24
Finished Jul 07 07:06:29 PM PDT 24
Peak memory 242164 kb
Host smart-482befba-41ed-4e6e-8069-c6f3beb57683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277527883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3277527883
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.1554305931
Short name T490
Test name
Test status
Simulation time 130438472 ps
CPU time 4.51 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:15 PM PDT 24
Peak memory 242276 kb
Host smart-3ea11337-d34d-4f29-9eb5-d133b5ff9b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554305931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1554305931
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2538170306
Short name T631
Test name
Test status
Simulation time 500815650 ps
CPU time 5.21 seconds
Started Jul 07 07:06:09 PM PDT 24
Finished Jul 07 07:06:14 PM PDT 24
Peak memory 242016 kb
Host smart-234e1712-37b0-40ab-9508-10385250424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538170306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2538170306
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.3962103386
Short name T912
Test name
Test status
Simulation time 28868376070 ps
CPU time 185.5 seconds
Started Jul 07 07:06:12 PM PDT 24
Finished Jul 07 07:09:17 PM PDT 24
Peak memory 278000 kb
Host smart-2d3a34de-9689-47d8-9ba7-3969260c2430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962103386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.3962103386
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2108223153
Short name T966
Test name
Test status
Simulation time 1634571690886 ps
CPU time 4891.19 seconds
Started Jul 07 07:06:11 PM PDT 24
Finished Jul 07 08:27:43 PM PDT 24
Peak memory 740136 kb
Host smart-c1c9f89c-5c30-4663-8872-65c6621c0e48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108223153 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2108223153
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.547791985
Short name T401
Test name
Test status
Simulation time 642135122 ps
CPU time 14.2 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:24 PM PDT 24
Peak memory 242076 kb
Host smart-6170762d-c297-4912-8d66-a4faae91b696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547791985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.547791985
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1259006540
Short name T614
Test name
Test status
Simulation time 69353110 ps
CPU time 2.02 seconds
Started Jul 07 07:06:14 PM PDT 24
Finished Jul 07 07:06:17 PM PDT 24
Peak memory 240100 kb
Host smart-a9803158-6530-4f36-a8d8-200d498f1698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259006540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1259006540
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.2608690168
Short name T65
Test name
Test status
Simulation time 580797442 ps
CPU time 9.78 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:21 PM PDT 24
Peak memory 248832 kb
Host smart-87d5ae10-12af-4180-b17f-33f5365cafd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608690168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2608690168
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.4022337338
Short name T198
Test name
Test status
Simulation time 1619866296 ps
CPU time 23.65 seconds
Started Jul 07 07:06:14 PM PDT 24
Finished Jul 07 07:06:38 PM PDT 24
Peak memory 242048 kb
Host smart-91d782bc-f400-4416-a434-8af0a2f6bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022337338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.4022337338
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2123017917
Short name T853
Test name
Test status
Simulation time 703896767 ps
CPU time 28.26 seconds
Started Jul 07 07:06:11 PM PDT 24
Finished Jul 07 07:06:40 PM PDT 24
Peak memory 242668 kb
Host smart-4bf8c535-d563-4367-b7e1-7ac0b1db9025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123017917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2123017917
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.709014855
Short name T38
Test name
Test status
Simulation time 238457611 ps
CPU time 5.06 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:15 PM PDT 24
Peak memory 242284 kb
Host smart-916954ed-6ea9-421e-ab2e-c6b29cb91f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709014855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.709014855
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.1046923252
Short name T95
Test name
Test status
Simulation time 4305287122 ps
CPU time 29.6 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:40 PM PDT 24
Peak memory 249032 kb
Host smart-2b84c194-0d06-4704-86da-8e1856c788cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046923252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1046923252
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.4110116197
Short name T4
Test name
Test status
Simulation time 526113762 ps
CPU time 10.45 seconds
Started Jul 07 07:06:11 PM PDT 24
Finished Jul 07 07:06:22 PM PDT 24
Peak memory 242084 kb
Host smart-b86b827d-1798-40ca-99ec-91757d23c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110116197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.4110116197
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.943121831
Short name T724
Test name
Test status
Simulation time 227319531 ps
CPU time 3.6 seconds
Started Jul 07 07:06:10 PM PDT 24
Finished Jul 07 07:06:14 PM PDT 24
Peak memory 241904 kb
Host smart-9dd4ab3b-f286-4fa4-b3b2-154c4a9c8da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943121831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.943121831
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.25450831
Short name T128
Test name
Test status
Simulation time 656201022 ps
CPU time 19.68 seconds
Started Jul 07 07:06:11 PM PDT 24
Finished Jul 07 07:06:31 PM PDT 24
Peak memory 248728 kb
Host smart-0078809d-373a-41c9-af88-b96c1880fa64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25450831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.25450831
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1401089113
Short name T632
Test name
Test status
Simulation time 825483170 ps
CPU time 11.8 seconds
Started Jul 07 07:06:14 PM PDT 24
Finished Jul 07 07:06:26 PM PDT 24
Peak memory 242336 kb
Host smart-d837e435-46a6-481e-96bf-7d877f5fe65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401089113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1401089113
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2436111473
Short name T1149
Test name
Test status
Simulation time 299158095 ps
CPU time 9.55 seconds
Started Jul 07 07:06:14 PM PDT 24
Finished Jul 07 07:06:25 PM PDT 24
Peak memory 242008 kb
Host smart-2e4d2892-f780-455c-8113-75ab17f39eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436111473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2436111473
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.2376420359
Short name T603
Test name
Test status
Simulation time 5054321704 ps
CPU time 98.86 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:07:54 PM PDT 24
Peak memory 257020 kb
Host smart-a69fa9e3-0861-4ead-9901-1ad05f57c666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376420359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.2376420359
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.197008644
Short name T245
Test name
Test status
Simulation time 502041841 ps
CPU time 10.69 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:06:27 PM PDT 24
Peak memory 242068 kb
Host smart-8157444d-c996-4def-b387-2d9ee103b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197008644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.197008644
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2664892222
Short name T410
Test name
Test status
Simulation time 81515051 ps
CPU time 1.58 seconds
Started Jul 07 07:06:20 PM PDT 24
Finished Jul 07 07:06:22 PM PDT 24
Peak memory 240408 kb
Host smart-d55e9eb4-74cc-4db1-9155-9912c6d33c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664892222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2664892222
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.3665836381
Short name T7
Test name
Test status
Simulation time 807409198 ps
CPU time 22.06 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:06:37 PM PDT 24
Peak memory 242272 kb
Host smart-153856ee-0ecf-417f-b834-6a2198115170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665836381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3665836381
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.640794344
Short name T566
Test name
Test status
Simulation time 1813806129 ps
CPU time 22.82 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:06:40 PM PDT 24
Peak memory 242488 kb
Host smart-1b431d4e-7bc7-4263-b847-ebd4aee46364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640794344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.640794344
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.1055618546
Short name T1186
Test name
Test status
Simulation time 199955446 ps
CPU time 4.48 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:06:20 PM PDT 24
Peak memory 242032 kb
Host smart-e07a30e2-29de-4bba-b1cd-8bb876996fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055618546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1055618546
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.3614492287
Short name T1059
Test name
Test status
Simulation time 2114380779 ps
CPU time 25.91 seconds
Started Jul 07 07:06:14 PM PDT 24
Finished Jul 07 07:06:41 PM PDT 24
Peak memory 245136 kb
Host smart-f566a023-1858-48aa-a111-20106f16110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614492287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3614492287
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3092126017
Short name T625
Test name
Test status
Simulation time 400776020 ps
CPU time 16.8 seconds
Started Jul 07 07:06:17 PM PDT 24
Finished Jul 07 07:06:34 PM PDT 24
Peak memory 242284 kb
Host smart-89cb9df4-b1f4-40bc-965d-2b1c028f1173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092126017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3092126017
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.894388960
Short name T1147
Test name
Test status
Simulation time 230724340 ps
CPU time 11.41 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:06:27 PM PDT 24
Peak memory 247544 kb
Host smart-a4be2b8a-26a1-40ab-87ee-e76a747039e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894388960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.894388960
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1627002103
Short name T361
Test name
Test status
Simulation time 146663053 ps
CPU time 5.34 seconds
Started Jul 07 07:06:18 PM PDT 24
Finished Jul 07 07:06:24 PM PDT 24
Peak memory 242060 kb
Host smart-129ffda6-97b4-4b65-8748-e95d7c9419d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627002103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1627002103
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1953605208
Short name T157
Test name
Test status
Simulation time 107860166 ps
CPU time 2.64 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:06:18 PM PDT 24
Peak memory 242008 kb
Host smart-e978f7a7-287a-4dc3-b527-d0a7136bfdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953605208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1953605208
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.3855239322
Short name T219
Test name
Test status
Simulation time 18814251481 ps
CPU time 138.71 seconds
Started Jul 07 07:06:17 PM PDT 24
Finished Jul 07 07:08:36 PM PDT 24
Peak memory 248732 kb
Host smart-472e43da-2f6f-45fa-8b3c-6cad360602aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855239322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.3855239322
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.1367425679
Short name T323
Test name
Test status
Simulation time 1064524523633 ps
CPU time 2550.72 seconds
Started Jul 07 07:06:18 PM PDT 24
Finished Jul 07 07:48:50 PM PDT 24
Peak memory 318164 kb
Host smart-dafc10db-30dc-43e3-91a3-e8811e3fbfdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367425679 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.1367425679
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3237324578
Short name T427
Test name
Test status
Simulation time 288863046 ps
CPU time 4.66 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:06:20 PM PDT 24
Peak memory 242340 kb
Host smart-ef27758a-0085-45e9-adf8-158535f78ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237324578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3237324578
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3763145114
Short name T746
Test name
Test status
Simulation time 166955036 ps
CPU time 1.9 seconds
Started Jul 07 07:06:17 PM PDT 24
Finished Jul 07 07:06:19 PM PDT 24
Peak memory 240256 kb
Host smart-55d4cac5-eccb-4bdc-9713-ca462319157f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763145114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3763145114
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.4031369189
Short name T127
Test name
Test status
Simulation time 643382528 ps
CPU time 22.93 seconds
Started Jul 07 07:06:18 PM PDT 24
Finished Jul 07 07:06:42 PM PDT 24
Peak memory 248796 kb
Host smart-e7142950-abcd-4fb1-96b5-eb73d01b5d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031369189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.4031369189
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.268231290
Short name T898
Test name
Test status
Simulation time 4751719239 ps
CPU time 24.75 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:06:41 PM PDT 24
Peak memory 241880 kb
Host smart-709faa3e-bf6f-4252-9aec-194805663926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268231290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.268231290
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.4022317169
Short name T557
Test name
Test status
Simulation time 5961595373 ps
CPU time 12.53 seconds
Started Jul 07 07:06:17 PM PDT 24
Finished Jul 07 07:06:30 PM PDT 24
Peak memory 242604 kb
Host smart-50fdbf2d-d12f-45ef-a36a-ef44658fc2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022317169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.4022317169
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.3682371557
Short name T163
Test name
Test status
Simulation time 579931396 ps
CPU time 4.39 seconds
Started Jul 07 07:06:18 PM PDT 24
Finished Jul 07 07:06:23 PM PDT 24
Peak memory 242156 kb
Host smart-d565b9f2-0bba-4a51-8f06-b972694caee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682371557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3682371557
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.2039197699
Short name T717
Test name
Test status
Simulation time 11859906792 ps
CPU time 32.9 seconds
Started Jul 07 07:06:19 PM PDT 24
Finished Jul 07 07:06:52 PM PDT 24
Peak memory 246936 kb
Host smart-d1c21bfe-5b98-42e6-a04e-7fb560877a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039197699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2039197699
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3049712890
Short name T337
Test name
Test status
Simulation time 334501816 ps
CPU time 7.59 seconds
Started Jul 07 07:06:17 PM PDT 24
Finished Jul 07 07:06:25 PM PDT 24
Peak memory 242068 kb
Host smart-0ec992c1-f734-45a7-a7ed-d26cc8217a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049712890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3049712890
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3396678670
Short name T1035
Test name
Test status
Simulation time 320694827 ps
CPU time 7.21 seconds
Started Jul 07 07:06:19 PM PDT 24
Finished Jul 07 07:06:27 PM PDT 24
Peak memory 241764 kb
Host smart-99079e57-8853-448a-a7ec-671f3995713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396678670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3396678670
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.4177616622
Short name T1180
Test name
Test status
Simulation time 641434701 ps
CPU time 6.34 seconds
Started Jul 07 07:06:17 PM PDT 24
Finished Jul 07 07:06:24 PM PDT 24
Peak memory 248692 kb
Host smart-7a4ed184-f3a1-4bed-89dc-0f9002c91764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177616622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.4177616622
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.1068795042
Short name T398
Test name
Test status
Simulation time 146566694 ps
CPU time 5.02 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:06:22 PM PDT 24
Peak memory 242096 kb
Host smart-87f0898c-4c13-4276-94c7-44e3b4e82811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068795042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1068795042
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2735981912
Short name T1155
Test name
Test status
Simulation time 248738934 ps
CPU time 2.98 seconds
Started Jul 07 07:06:15 PM PDT 24
Finished Jul 07 07:06:19 PM PDT 24
Peak memory 241956 kb
Host smart-c0f797bd-486d-4d79-b901-7e281a15ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735981912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2735981912
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3146347980
Short name T1109
Test name
Test status
Simulation time 10042662604 ps
CPU time 145.89 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:08:42 PM PDT 24
Peak memory 249196 kb
Host smart-803ab438-c724-4e2d-bfa6-04fa46582988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146347980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3146347980
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3147022199
Short name T533
Test name
Test status
Simulation time 31284204389 ps
CPU time 810.85 seconds
Started Jul 07 07:06:22 PM PDT 24
Finished Jul 07 07:19:53 PM PDT 24
Peak memory 265732 kb
Host smart-69174d1d-e9b8-4855-bb6c-c35238c91562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147022199 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.3147022199
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.4006974018
Short name T1041
Test name
Test status
Simulation time 132201011 ps
CPU time 5.83 seconds
Started Jul 07 07:06:16 PM PDT 24
Finished Jul 07 07:06:22 PM PDT 24
Peak memory 242012 kb
Host smart-bda07262-0eb0-41e0-ab9a-429423adf700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006974018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.4006974018
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.2708870401
Short name T619
Test name
Test status
Simulation time 127260687 ps
CPU time 1.92 seconds
Started Jul 07 07:06:25 PM PDT 24
Finished Jul 07 07:06:28 PM PDT 24
Peak memory 240084 kb
Host smart-697a4fcf-9fec-4c05-b3c8-bcb3b0e706e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708870401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2708870401
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.2747680705
Short name T137
Test name
Test status
Simulation time 246051663 ps
CPU time 7.25 seconds
Started Jul 07 07:06:21 PM PDT 24
Finished Jul 07 07:06:28 PM PDT 24
Peak memory 242216 kb
Host smart-49d2e248-77c7-4fa4-84e6-264ff9416fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747680705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.2747680705
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3394674539
Short name T671
Test name
Test status
Simulation time 340279264 ps
CPU time 16.39 seconds
Started Jul 07 07:06:22 PM PDT 24
Finished Jul 07 07:06:38 PM PDT 24
Peak memory 241972 kb
Host smart-e35af137-4380-4b29-bba6-03fbfc256227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394674539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3394674539
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.2260879969
Short name T1165
Test name
Test status
Simulation time 2319055068 ps
CPU time 17.29 seconds
Started Jul 07 07:06:24 PM PDT 24
Finished Jul 07 07:06:41 PM PDT 24
Peak memory 242464 kb
Host smart-57e5fb42-2cd4-4819-b03f-c2fd9f1a1d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260879969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2260879969
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.1410866212
Short name T144
Test name
Test status
Simulation time 286073899 ps
CPU time 3.64 seconds
Started Jul 07 07:06:25 PM PDT 24
Finished Jul 07 07:06:29 PM PDT 24
Peak memory 241924 kb
Host smart-c02742e6-4f89-4d54-a666-3cbe85cdbb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410866212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1410866212
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.1985762005
Short name T723
Test name
Test status
Simulation time 2656476319 ps
CPU time 13.35 seconds
Started Jul 07 07:06:21 PM PDT 24
Finished Jul 07 07:06:34 PM PDT 24
Peak memory 242488 kb
Host smart-ba8bb160-502c-4acf-8e40-c67e53fd056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985762005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1985762005
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.397857317
Short name T802
Test name
Test status
Simulation time 1436966075 ps
CPU time 4.8 seconds
Started Jul 07 07:06:22 PM PDT 24
Finished Jul 07 07:06:27 PM PDT 24
Peak memory 242016 kb
Host smart-791e4f48-a9a3-45ad-87fa-1a96ba7c9494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397857317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.397857317
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.3286479888
Short name T580
Test name
Test status
Simulation time 1136381171 ps
CPU time 11.67 seconds
Started Jul 07 07:06:22 PM PDT 24
Finished Jul 07 07:06:33 PM PDT 24
Peak memory 242268 kb
Host smart-5f90afb4-42d2-4ea8-9771-d80f5ec07a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286479888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3286479888
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.4050756694
Short name T393
Test name
Test status
Simulation time 802372205 ps
CPU time 7.03 seconds
Started Jul 07 07:06:21 PM PDT 24
Finished Jul 07 07:06:28 PM PDT 24
Peak memory 242436 kb
Host smart-48fbe7f7-5caf-4d85-acd3-e57b1da4f81e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050756694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.4050756694
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1920805962
Short name T452
Test name
Test status
Simulation time 415707791 ps
CPU time 7.56 seconds
Started Jul 07 07:06:20 PM PDT 24
Finished Jul 07 07:06:28 PM PDT 24
Peak memory 242080 kb
Host smart-84b29a96-bdbc-4e65-9a29-bbc9fbc1170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920805962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1920805962
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.3968097540
Short name T783
Test name
Test status
Simulation time 15911136919 ps
CPU time 129.25 seconds
Started Jul 07 07:06:25 PM PDT 24
Finished Jul 07 07:08:35 PM PDT 24
Peak memory 248832 kb
Host smart-bacf1bfe-6edd-494a-b1db-78ab22e2a048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968097540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.3968097540
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1719032478
Short name T263
Test name
Test status
Simulation time 45172907508 ps
CPU time 1310.1 seconds
Started Jul 07 07:06:24 PM PDT 24
Finished Jul 07 07:28:15 PM PDT 24
Peak memory 436360 kb
Host smart-ddf95803-85ae-46c8-8b2f-ea842715ce10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719032478 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1719032478
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.2293816533
Short name T248
Test name
Test status
Simulation time 156267250 ps
CPU time 6.03 seconds
Started Jul 07 07:06:24 PM PDT 24
Finished Jul 07 07:06:30 PM PDT 24
Peak memory 248712 kb
Host smart-a5af781f-9f23-466e-bbf4-b61bcf6c6be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293816533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.2293816533
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.63436901
Short name T776
Test name
Test status
Simulation time 154125634 ps
CPU time 2.34 seconds
Started Jul 07 07:06:28 PM PDT 24
Finished Jul 07 07:06:31 PM PDT 24
Peak memory 240108 kb
Host smart-f826fafc-9b24-4376-926b-73df38a40d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63436901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.63436901
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1192413080
Short name T467
Test name
Test status
Simulation time 3160914279 ps
CPU time 23.19 seconds
Started Jul 07 07:06:27 PM PDT 24
Finished Jul 07 07:06:50 PM PDT 24
Peak memory 248836 kb
Host smart-87961304-195e-44aa-b18e-e345f28d0db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192413080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1192413080
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.310279917
Short name T711
Test name
Test status
Simulation time 1650624750 ps
CPU time 23.66 seconds
Started Jul 07 07:06:28 PM PDT 24
Finished Jul 07 07:06:52 PM PDT 24
Peak memory 241936 kb
Host smart-3b5e3a29-d58d-4f08-9697-5960623cf66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310279917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.310279917
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.2353706689
Short name T1018
Test name
Test status
Simulation time 956484047 ps
CPU time 33.33 seconds
Started Jul 07 07:06:30 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 242888 kb
Host smart-01cd574f-40cf-4010-81dc-e6cb2422585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353706689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2353706689
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1344683511
Short name T700
Test name
Test status
Simulation time 497721157 ps
CPU time 3.72 seconds
Started Jul 07 07:06:27 PM PDT 24
Finished Jul 07 07:06:31 PM PDT 24
Peak memory 242036 kb
Host smart-fe5b17a2-ea78-49af-b2a7-a0bc3ccabc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344683511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1344683511
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.915578289
Short name T1050
Test name
Test status
Simulation time 4987749802 ps
CPU time 37.69 seconds
Started Jul 07 07:06:29 PM PDT 24
Finished Jul 07 07:07:07 PM PDT 24
Peak memory 257056 kb
Host smart-10ff23bd-bcf9-44f2-8e09-9643dfd46c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915578289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.915578289
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.2604244734
Short name T863
Test name
Test status
Simulation time 3264972413 ps
CPU time 37.23 seconds
Started Jul 07 07:06:29 PM PDT 24
Finished Jul 07 07:07:07 PM PDT 24
Peak memory 243248 kb
Host smart-b8aafdb1-e6a0-4057-9633-2409cddcd3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604244734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.2604244734
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.2782915027
Short name T232
Test name
Test status
Simulation time 406553635 ps
CPU time 4.69 seconds
Started Jul 07 07:06:28 PM PDT 24
Finished Jul 07 07:06:33 PM PDT 24
Peak memory 241876 kb
Host smart-bf723ce4-8a40-4a0d-81c2-d7757b33d5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782915027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2782915027
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.593462451
Short name T260
Test name
Test status
Simulation time 1472005137 ps
CPU time 20.24 seconds
Started Jul 07 07:06:26 PM PDT 24
Finished Jul 07 07:06:46 PM PDT 24
Peak memory 242108 kb
Host smart-64e8e4e4-1e23-491b-8073-79e228cf0dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593462451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.593462451
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.1578235474
Short name T368
Test name
Test status
Simulation time 423373996 ps
CPU time 4.11 seconds
Started Jul 07 07:06:29 PM PDT 24
Finished Jul 07 07:06:33 PM PDT 24
Peak memory 242112 kb
Host smart-f8e5ca90-ee04-4527-adea-261ef00fb65f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578235474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1578235474
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.870110594
Short name T957
Test name
Test status
Simulation time 743094897 ps
CPU time 10.23 seconds
Started Jul 07 07:06:27 PM PDT 24
Finished Jul 07 07:06:38 PM PDT 24
Peak memory 242152 kb
Host smart-992f090d-89e5-41b7-a995-6036b85053b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870110594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.870110594
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.3415715499
Short name T779
Test name
Test status
Simulation time 39359531611 ps
CPU time 237.24 seconds
Started Jul 07 07:06:26 PM PDT 24
Finished Jul 07 07:10:23 PM PDT 24
Peak memory 281652 kb
Host smart-1e855b98-4498-41e3-b13d-a944b56397e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415715499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.3415715499
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1792558393
Short name T18
Test name
Test status
Simulation time 117648610246 ps
CPU time 1965.78 seconds
Started Jul 07 07:06:30 PM PDT 24
Finished Jul 07 07:39:16 PM PDT 24
Peak memory 577972 kb
Host smart-bab6443d-edc2-4181-934a-e235e26c1d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792558393 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.1792558393
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3001828702
Short name T188
Test name
Test status
Simulation time 5462598875 ps
CPU time 13.5 seconds
Started Jul 07 07:06:27 PM PDT 24
Finished Jul 07 07:06:41 PM PDT 24
Peak memory 248840 kb
Host smart-5648b03c-4748-4f46-b899-2e34d49e9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001828702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3001828702
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.684331731
Short name T961
Test name
Test status
Simulation time 52668105 ps
CPU time 1.77 seconds
Started Jul 07 07:06:36 PM PDT 24
Finished Jul 07 07:06:38 PM PDT 24
Peak memory 240300 kb
Host smart-529ed7a6-9638-4d10-a039-5a9d3ea6e294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684331731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.684331731
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1039172784
Short name T61
Test name
Test status
Simulation time 992888090 ps
CPU time 14.36 seconds
Started Jul 07 07:06:33 PM PDT 24
Finished Jul 07 07:06:48 PM PDT 24
Peak memory 242484 kb
Host smart-199f1a08-9f06-4643-b52a-d61f6c5b6130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039172784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1039172784
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.3627701108
Short name T413
Test name
Test status
Simulation time 1149549113 ps
CPU time 17.86 seconds
Started Jul 07 07:06:32 PM PDT 24
Finished Jul 07 07:06:50 PM PDT 24
Peak memory 241972 kb
Host smart-1f29c85a-3205-4090-a75c-5e43217db7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627701108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3627701108
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.353103466
Short name T767
Test name
Test status
Simulation time 1448829303 ps
CPU time 16.81 seconds
Started Jul 07 07:06:32 PM PDT 24
Finished Jul 07 07:06:49 PM PDT 24
Peak memory 248748 kb
Host smart-5e822f24-1f1d-4974-8bff-85b71c91b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353103466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.353103466
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3176068671
Short name T745
Test name
Test status
Simulation time 443892253 ps
CPU time 4.24 seconds
Started Jul 07 07:06:33 PM PDT 24
Finished Jul 07 07:06:37 PM PDT 24
Peak memory 241920 kb
Host smart-bccb5d40-bde0-42a3-a4de-59131e2516f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176068671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3176068671
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.3502987913
Short name T869
Test name
Test status
Simulation time 6122618618 ps
CPU time 37.58 seconds
Started Jul 07 07:06:32 PM PDT 24
Finished Jul 07 07:07:10 PM PDT 24
Peak memory 250816 kb
Host smart-c5005be9-5c14-490e-96a8-5051e80e8c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502987913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3502987913
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.2187107871
Short name T246
Test name
Test status
Simulation time 649452338 ps
CPU time 18.17 seconds
Started Jul 07 07:06:31 PM PDT 24
Finished Jul 07 07:06:50 PM PDT 24
Peak memory 248744 kb
Host smart-190c8456-8085-45f2-84d4-dff31d2b566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187107871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.2187107871
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1190245000
Short name T615
Test name
Test status
Simulation time 295919889 ps
CPU time 2.98 seconds
Started Jul 07 07:06:32 PM PDT 24
Finished Jul 07 07:06:36 PM PDT 24
Peak memory 242096 kb
Host smart-01dc46b4-0503-414d-9012-818f579effa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190245000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1190245000
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.1359568760
Short name T808
Test name
Test status
Simulation time 393971555 ps
CPU time 11.17 seconds
Started Jul 07 07:06:31 PM PDT 24
Finished Jul 07 07:06:42 PM PDT 24
Peak memory 242344 kb
Host smart-fc660b08-d388-4f6c-b202-82df9e464f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359568760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1359568760
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.968818448
Short name T581
Test name
Test status
Simulation time 518239511 ps
CPU time 10.06 seconds
Started Jul 07 07:06:35 PM PDT 24
Finished Jul 07 07:06:45 PM PDT 24
Peak memory 242428 kb
Host smart-981aa590-8d99-4474-94c1-a4930cc009ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968818448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.968818448
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.2901858206
Short name T1102
Test name
Test status
Simulation time 754907250 ps
CPU time 8.97 seconds
Started Jul 07 07:06:28 PM PDT 24
Finished Jul 07 07:06:37 PM PDT 24
Peak memory 248640 kb
Host smart-679d588a-abcc-487f-8667-5b1fed4237b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901858206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2901858206
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.4030048989
Short name T1010
Test name
Test status
Simulation time 4540665831 ps
CPU time 144.98 seconds
Started Jul 07 07:06:35 PM PDT 24
Finished Jul 07 07:09:00 PM PDT 24
Peak memory 248232 kb
Host smart-e597847d-87ff-44ce-91f8-cb281bac1604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030048989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.4030048989
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2919685885
Short name T331
Test name
Test status
Simulation time 287554255347 ps
CPU time 1755.18 seconds
Started Jul 07 07:06:35 PM PDT 24
Finished Jul 07 07:35:51 PM PDT 24
Peak memory 487696 kb
Host smart-9de9b0bf-f25f-4171-9f69-ea671e9a3584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919685885 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2919685885
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.4253799132
Short name T795
Test name
Test status
Simulation time 636777335 ps
CPU time 8.42 seconds
Started Jul 07 07:06:33 PM PDT 24
Finished Jul 07 07:06:42 PM PDT 24
Peak memory 242048 kb
Host smart-9b86df36-3293-43d7-89ff-c39486483a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253799132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.4253799132
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2814631133
Short name T1071
Test name
Test status
Simulation time 785503410 ps
CPU time 1.85 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:06:48 PM PDT 24
Peak memory 240640 kb
Host smart-06c8a06f-faac-4f52-87bd-2257c3c85817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814631133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2814631133
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.894786030
Short name T69
Test name
Test status
Simulation time 1271872282 ps
CPU time 17 seconds
Started Jul 07 07:06:37 PM PDT 24
Finished Jul 07 07:06:55 PM PDT 24
Peak memory 243016 kb
Host smart-f9690b57-9dfd-4d9a-95d9-35e72f8679d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894786030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.894786030
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.1795243639
Short name T1184
Test name
Test status
Simulation time 2907366213 ps
CPU time 13.09 seconds
Started Jul 07 07:06:40 PM PDT 24
Finished Jul 07 07:06:53 PM PDT 24
Peak memory 241744 kb
Host smart-c458120f-ea65-40c8-805a-e7f128ab710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795243639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1795243639
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.4265567769
Short name T510
Test name
Test status
Simulation time 1233216073 ps
CPU time 19.08 seconds
Started Jul 07 07:06:38 PM PDT 24
Finished Jul 07 07:06:57 PM PDT 24
Peak memory 242388 kb
Host smart-53ec6827-8206-48ff-9e1c-2871a3ace968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265567769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.4265567769
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.1168231552
Short name T126
Test name
Test status
Simulation time 232352288 ps
CPU time 3.66 seconds
Started Jul 07 07:06:33 PM PDT 24
Finished Jul 07 07:06:37 PM PDT 24
Peak memory 242012 kb
Host smart-399471fa-14d5-4343-8b75-050276b1c613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168231552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1168231552
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.4134627338
Short name T149
Test name
Test status
Simulation time 253755203 ps
CPU time 9.62 seconds
Started Jul 07 07:06:39 PM PDT 24
Finished Jul 07 07:06:49 PM PDT 24
Peak memory 242456 kb
Host smart-fc9f9763-cd42-4ce3-bc31-ffea4239f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134627338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.4134627338
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.3330886456
Short name T441
Test name
Test status
Simulation time 536058596 ps
CPU time 8.04 seconds
Started Jul 07 07:06:38 PM PDT 24
Finished Jul 07 07:06:47 PM PDT 24
Peak memory 242012 kb
Host smart-e35e4442-4af6-4e09-9628-ff5cd8b3e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330886456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3330886456
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.17280736
Short name T759
Test name
Test status
Simulation time 571098488 ps
CPU time 7.01 seconds
Started Jul 07 07:06:35 PM PDT 24
Finished Jul 07 07:06:42 PM PDT 24
Peak memory 241896 kb
Host smart-86ad273f-21b2-4ec9-849b-54b96d780b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17280736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.17280736
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2746110526
Short name T258
Test name
Test status
Simulation time 1284875874 ps
CPU time 18.06 seconds
Started Jul 07 07:06:40 PM PDT 24
Finished Jul 07 07:06:58 PM PDT 24
Peak memory 248708 kb
Host smart-5a43c9eb-8895-4dc8-bd9b-51f31730ffce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746110526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2746110526
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.1400702288
Short name T956
Test name
Test status
Simulation time 400195876 ps
CPU time 5 seconds
Started Jul 07 07:06:34 PM PDT 24
Finished Jul 07 07:06:40 PM PDT 24
Peak memory 242124 kb
Host smart-8f673760-ab87-4313-b3e7-0af465463fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400702288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1400702288
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3959847437
Short name T874
Test name
Test status
Simulation time 3600831374 ps
CPU time 75.25 seconds
Started Jul 07 07:06:40 PM PDT 24
Finished Jul 07 07:07:56 PM PDT 24
Peak memory 246244 kb
Host smart-297edb31-8be4-407c-8ac1-66e9d41cf079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959847437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3959847437
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.192637965
Short name T916
Test name
Test status
Simulation time 650315332 ps
CPU time 2.31 seconds
Started Jul 07 07:06:47 PM PDT 24
Finished Jul 07 07:06:50 PM PDT 24
Peak memory 240260 kb
Host smart-1546773f-b15e-4bbe-8634-d57759ebe9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192637965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.192637965
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.639804172
Short name T76
Test name
Test status
Simulation time 1252105113 ps
CPU time 6.23 seconds
Started Jul 07 07:06:42 PM PDT 24
Finished Jul 07 07:06:48 PM PDT 24
Peak memory 242336 kb
Host smart-29010ce6-e3f7-4671-8764-7e8747f9c136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639804172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.639804172
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.891113175
Short name T970
Test name
Test status
Simulation time 415374636 ps
CPU time 10.02 seconds
Started Jul 07 07:06:42 PM PDT 24
Finished Jul 07 07:06:52 PM PDT 24
Peak memory 241808 kb
Host smart-74bd4135-e626-40f8-8ea4-6e932c3defa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891113175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.891113175
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.755390191
Short name T1046
Test name
Test status
Simulation time 2761042682 ps
CPU time 19.63 seconds
Started Jul 07 07:06:42 PM PDT 24
Finished Jul 07 07:07:02 PM PDT 24
Peak memory 242472 kb
Host smart-7095339d-6989-468a-9e2f-71b764ccb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755390191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.755390191
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.829429877
Short name T412
Test name
Test status
Simulation time 2768238812 ps
CPU time 7.04 seconds
Started Jul 07 07:06:44 PM PDT 24
Finished Jul 07 07:06:51 PM PDT 24
Peak memory 242436 kb
Host smart-24b9f722-4677-45ea-993d-d1cb2aa7cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829429877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.829429877
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1078352000
Short name T469
Test name
Test status
Simulation time 1660157234 ps
CPU time 12 seconds
Started Jul 07 07:06:43 PM PDT 24
Finished Jul 07 07:06:55 PM PDT 24
Peak memory 241940 kb
Host smart-94c518ee-6f37-4143-9c05-1580049aa622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078352000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1078352000
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1877761025
Short name T378
Test name
Test status
Simulation time 1975840809 ps
CPU time 26.72 seconds
Started Jul 07 07:06:41 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 243280 kb
Host smart-27b95a81-b93d-45eb-9ab1-2b92bfce0430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877761025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1877761025
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3879202606
Short name T1123
Test name
Test status
Simulation time 310560503 ps
CPU time 8.54 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:06:53 PM PDT 24
Peak memory 241936 kb
Host smart-eb2ee5c9-b9d3-4f9e-911e-7117f93ee8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879202606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3879202606
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1439853678
Short name T504
Test name
Test status
Simulation time 530739955 ps
CPU time 16.37 seconds
Started Jul 07 07:06:41 PM PDT 24
Finished Jul 07 07:06:57 PM PDT 24
Peak memory 242236 kb
Host smart-fa840424-1091-4bb8-b20d-0b2bb74d6c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439853678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1439853678
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1423359793
Short name T108
Test name
Test status
Simulation time 647782221 ps
CPU time 10.55 seconds
Started Jul 07 07:06:42 PM PDT 24
Finished Jul 07 07:06:53 PM PDT 24
Peak memory 242044 kb
Host smart-ca6d401f-bd40-440c-a60d-039b9b6a9b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423359793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1423359793
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.3514579387
Short name T455
Test name
Test status
Simulation time 942966394 ps
CPU time 9.92 seconds
Started Jul 07 07:06:41 PM PDT 24
Finished Jul 07 07:06:51 PM PDT 24
Peak memory 242332 kb
Host smart-8c316d48-d04d-4912-ba31-f477407f6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514579387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3514579387
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.1091413640
Short name T836
Test name
Test status
Simulation time 20463506954 ps
CPU time 157.72 seconds
Started Jul 07 07:06:46 PM PDT 24
Finished Jul 07 07:09:24 PM PDT 24
Peak memory 258052 kb
Host smart-98e670e1-7cc3-4121-9d16-f40f3939809d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091413640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.1091413640
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.853655053
Short name T734
Test name
Test status
Simulation time 69199001396 ps
CPU time 981.55 seconds
Started Jul 07 07:06:44 PM PDT 24
Finished Jul 07 07:23:06 PM PDT 24
Peak memory 385116 kb
Host smart-56127f57-22cf-44b2-9af1-4c6f4df13888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853655053 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.853655053
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3641077973
Short name T592
Test name
Test status
Simulation time 261742461 ps
CPU time 7.99 seconds
Started Jul 07 07:06:42 PM PDT 24
Finished Jul 07 07:06:50 PM PDT 24
Peak memory 242328 kb
Host smart-d81f9873-ce91-46ef-b8db-fec50f599152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641077973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3641077973
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.4065434784
Short name T997
Test name
Test status
Simulation time 1527466535 ps
CPU time 2.4 seconds
Started Jul 07 07:06:49 PM PDT 24
Finished Jul 07 07:06:52 PM PDT 24
Peak memory 240496 kb
Host smart-1724d4d8-4641-4497-9126-0bc57b4e0ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065434784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.4065434784
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.964993358
Short name T114
Test name
Test status
Simulation time 11755525313 ps
CPU time 91.18 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:08:17 PM PDT 24
Peak memory 243584 kb
Host smart-38e5c4d6-2404-4d94-9af4-efb9b1821e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964993358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.964993358
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3419711789
Short name T732
Test name
Test status
Simulation time 278775164 ps
CPU time 14.9 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 242116 kb
Host smart-92ddbd77-9649-443d-ad4c-33a4da4d8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419711789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3419711789
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.2043798818
Short name T561
Test name
Test status
Simulation time 12987108726 ps
CPU time 26.42 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:07:12 PM PDT 24
Peak memory 242916 kb
Host smart-b6f12f80-fcd4-4707-91b6-a2bc9ce97caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043798818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2043798818
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.4102727793
Short name T37
Test name
Test status
Simulation time 97602274 ps
CPU time 3.87 seconds
Started Jul 07 07:06:47 PM PDT 24
Finished Jul 07 07:06:52 PM PDT 24
Peak memory 242196 kb
Host smart-5cd0d875-7d1f-49b4-9d83-3ab18fcef719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102727793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.4102727793
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.1441656641
Short name T683
Test name
Test status
Simulation time 3879901041 ps
CPU time 37 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:07:22 PM PDT 24
Peak memory 257032 kb
Host smart-7cc83162-4bbd-4d74-a053-51ab137315fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441656641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1441656641
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.261257627
Short name T1137
Test name
Test status
Simulation time 4197492834 ps
CPU time 48.35 seconds
Started Jul 07 07:06:46 PM PDT 24
Finished Jul 07 07:07:35 PM PDT 24
Peak memory 242628 kb
Host smart-4395cc4e-715e-4ab8-8a74-ee50fecc65d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261257627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.261257627
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3845021386
Short name T1182
Test name
Test status
Simulation time 526501746 ps
CPU time 8.15 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:06:54 PM PDT 24
Peak memory 242180 kb
Host smart-59bb906a-e96a-45ff-8604-e07633a121e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845021386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3845021386
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2234847298
Short name T1042
Test name
Test status
Simulation time 649802661 ps
CPU time 13.4 seconds
Started Jul 07 07:06:44 PM PDT 24
Finished Jul 07 07:06:58 PM PDT 24
Peak memory 242332 kb
Host smart-34342f5d-4752-4e6b-8ea2-9dbc519ec040
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234847298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2234847298
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3995380702
Short name T584
Test name
Test status
Simulation time 257350580 ps
CPU time 7.42 seconds
Started Jul 07 07:06:45 PM PDT 24
Finished Jul 07 07:06:53 PM PDT 24
Peak memory 242020 kb
Host smart-ec46455f-de36-438e-be45-cf4b18e3f1c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995380702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3995380702
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.295474656
Short name T93
Test name
Test status
Simulation time 4576988036 ps
CPU time 10.29 seconds
Started Jul 07 07:06:46 PM PDT 24
Finished Jul 07 07:06:56 PM PDT 24
Peak memory 242564 kb
Host smart-602724e2-4cba-46b8-b934-c03c33a98d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295474656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.295474656
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3312343960
Short name T1033
Test name
Test status
Simulation time 19118534717 ps
CPU time 200.5 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:10:09 PM PDT 24
Peak memory 250068 kb
Host smart-a359474c-26cc-400e-9a0f-77966f381739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312343960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3312343960
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.1749653865
Short name T283
Test name
Test status
Simulation time 155471291206 ps
CPU time 2346.2 seconds
Started Jul 07 07:06:50 PM PDT 24
Finished Jul 07 07:45:57 PM PDT 24
Peak memory 362376 kb
Host smart-332b588d-c746-474e-b1c2-2da8dbe9a44a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749653865 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.1749653865
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.3531384602
Short name T1130
Test name
Test status
Simulation time 316956815 ps
CPU time 14.17 seconds
Started Jul 07 07:06:51 PM PDT 24
Finished Jul 07 07:07:06 PM PDT 24
Peak memory 242304 kb
Host smart-2cc4cead-dc76-4c61-8437-992f26c44469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531384602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3531384602
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.495156042
Short name T564
Test name
Test status
Simulation time 236019370 ps
CPU time 3.03 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:37 PM PDT 24
Peak memory 240140 kb
Host smart-ad305551-d55b-4e6e-90c7-b5dd069f9cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495156042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.495156042
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.1243360379
Short name T1152
Test name
Test status
Simulation time 1370199897 ps
CPU time 27.05 seconds
Started Jul 07 07:04:26 PM PDT 24
Finished Jul 07 07:04:53 PM PDT 24
Peak memory 248816 kb
Host smart-04a28e1b-e51e-40ea-b35a-216e7ad16e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243360379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1243360379
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.903686386
Short name T43
Test name
Test status
Simulation time 1146006401 ps
CPU time 23.49 seconds
Started Jul 07 07:04:28 PM PDT 24
Finished Jul 07 07:04:52 PM PDT 24
Peak memory 242536 kb
Host smart-ed50e243-bfda-4194-b33b-8458f3d3b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903686386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.903686386
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.740609203
Short name T667
Test name
Test status
Simulation time 989310883 ps
CPU time 14.53 seconds
Started Jul 07 07:04:29 PM PDT 24
Finished Jul 07 07:04:44 PM PDT 24
Peak memory 242240 kb
Host smart-d4e3340d-2fa3-4a1b-801c-c707d97eaaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740609203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.740609203
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1824899224
Short name T974
Test name
Test status
Simulation time 1151088220 ps
CPU time 26.53 seconds
Started Jul 07 07:04:27 PM PDT 24
Finished Jul 07 07:04:54 PM PDT 24
Peak memory 242404 kb
Host smart-9ef8b5c6-32bc-4771-9be4-fae1fcf53284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824899224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1824899224
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3664859501
Short name T839
Test name
Test status
Simulation time 483192289 ps
CPU time 4.22 seconds
Started Jul 07 07:04:27 PM PDT 24
Finished Jul 07 07:04:31 PM PDT 24
Peak memory 242088 kb
Host smart-3d5c3c38-f59a-4883-a1df-56ced4502ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664859501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3664859501
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.852124424
Short name T238
Test name
Test status
Simulation time 837793034 ps
CPU time 7.18 seconds
Started Jul 07 07:04:29 PM PDT 24
Finished Jul 07 07:04:37 PM PDT 24
Peak memory 242532 kb
Host smart-326caec7-91ad-4337-bcd3-b8db12d321be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852124424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.852124424
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.527761900
Short name T881
Test name
Test status
Simulation time 573649689 ps
CPU time 20.91 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:55 PM PDT 24
Peak memory 242528 kb
Host smart-c002e38f-897d-4c52-a3a4-c1f2cafbabb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527761900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.527761900
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.3630273234
Short name T947
Test name
Test status
Simulation time 1396569374 ps
CPU time 3.89 seconds
Started Jul 07 07:04:31 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 241960 kb
Host smart-5f16a0a2-35dc-4aae-8ff0-21993fa6f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630273234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3630273234
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2544105443
Short name T831
Test name
Test status
Simulation time 866775927 ps
CPU time 8.12 seconds
Started Jul 07 07:04:27 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 242432 kb
Host smart-19941b39-e135-4b8c-8fc4-d6cda2c98e24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544105443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2544105443
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1944406158
Short name T848
Test name
Test status
Simulation time 278468022 ps
CPU time 6.35 seconds
Started Jul 07 07:04:29 PM PDT 24
Finished Jul 07 07:04:36 PM PDT 24
Peak memory 241948 kb
Host smart-5dfdfbdb-332c-4da8-8a31-267cdd934dcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944406158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1944406158
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3815334364
Short name T243
Test name
Test status
Simulation time 154670779576 ps
CPU time 266.99 seconds
Started Jul 07 07:04:29 PM PDT 24
Finished Jul 07 07:08:57 PM PDT 24
Peak memory 268040 kb
Host smart-d86020c4-0f11-490f-85d0-aebde9a9b61c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815334364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3815334364
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.2874871191
Short name T620
Test name
Test status
Simulation time 192161651 ps
CPU time 4.32 seconds
Started Jul 07 07:04:31 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 241956 kb
Host smart-097e77fd-8292-40b4-8bee-58b7735a3c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874871191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2874871191
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.3246492745
Short name T651
Test name
Test status
Simulation time 13880848487 ps
CPU time 97.33 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:06:15 PM PDT 24
Peak memory 257024 kb
Host smart-49477e2d-bf96-43cc-9a3f-b93cc0798940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246492745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
3246492745
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3018703475
Short name T872
Test name
Test status
Simulation time 334984687344 ps
CPU time 601.59 seconds
Started Jul 07 07:04:31 PM PDT 24
Finished Jul 07 07:14:33 PM PDT 24
Peak memory 265200 kb
Host smart-dc79e208-e107-4e3a-aabe-aeb0f0ef4f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018703475 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.3018703475
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.2616780207
Short name T290
Test name
Test status
Simulation time 1035605100 ps
CPU time 15.71 seconds
Started Jul 07 07:04:31 PM PDT 24
Finished Jul 07 07:04:47 PM PDT 24
Peak memory 242288 kb
Host smart-640bb40b-0912-4974-8d72-2e937ba7cc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616780207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2616780207
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.855781824
Short name T860
Test name
Test status
Simulation time 41801377 ps
CPU time 1.6 seconds
Started Jul 07 07:06:49 PM PDT 24
Finished Jul 07 07:06:51 PM PDT 24
Peak memory 240092 kb
Host smart-11559152-a7d9-49c3-b2ad-ac47f0ab8cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855781824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.855781824
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1125952687
Short name T48
Test name
Test status
Simulation time 1852070116 ps
CPU time 17.47 seconds
Started Jul 07 07:06:50 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 242484 kb
Host smart-481a5afe-29da-4e5e-9b38-1504371f8bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125952687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1125952687
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2886056984
Short name T604
Test name
Test status
Simulation time 538998191 ps
CPU time 18.01 seconds
Started Jul 07 07:06:50 PM PDT 24
Finished Jul 07 07:07:09 PM PDT 24
Peak memory 241828 kb
Host smart-9ce775a6-c9dd-43b3-b54b-86413524056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886056984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2886056984
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.401885597
Short name T693
Test name
Test status
Simulation time 588088702 ps
CPU time 13.16 seconds
Started Jul 07 07:06:50 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 242372 kb
Host smart-39858d73-3308-422e-8a08-269fda227c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401885597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.401885597
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.4102702623
Short name T755
Test name
Test status
Simulation time 296586033 ps
CPU time 5.73 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:06:55 PM PDT 24
Peak memory 242052 kb
Host smart-10c3e81d-3699-472b-8ce6-c3e4130dab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102702623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.4102702623
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3811373689
Short name T1099
Test name
Test status
Simulation time 87622953 ps
CPU time 3.47 seconds
Started Jul 07 07:06:51 PM PDT 24
Finished Jul 07 07:06:55 PM PDT 24
Peak memory 242308 kb
Host smart-ed2580da-787a-4ec1-bdef-9856e675abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811373689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3811373689
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.3860804142
Short name T104
Test name
Test status
Simulation time 1695603646 ps
CPU time 20.34 seconds
Started Jul 07 07:06:50 PM PDT 24
Finished Jul 07 07:07:11 PM PDT 24
Peak memory 248740 kb
Host smart-efd1f8e0-7c9d-4874-96ea-69c95e0c07cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860804142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3860804142
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.109747139
Short name T424
Test name
Test status
Simulation time 346025543 ps
CPU time 8.24 seconds
Started Jul 07 07:06:52 PM PDT 24
Finished Jul 07 07:07:01 PM PDT 24
Peak memory 242284 kb
Host smart-e5c77072-0d5f-4fe8-85b0-99024f106b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109747139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.109747139
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.2050162018
Short name T1119
Test name
Test status
Simulation time 3629108833 ps
CPU time 11.67 seconds
Started Jul 07 07:06:51 PM PDT 24
Finished Jul 07 07:07:03 PM PDT 24
Peak memory 242048 kb
Host smart-a191268d-118f-47a3-bffa-6d3194d0926f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050162018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2050162018
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.2645709579
Short name T1166
Test name
Test status
Simulation time 850204861 ps
CPU time 7.79 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:06:57 PM PDT 24
Peak memory 242264 kb
Host smart-a5b58e41-4b44-4949-ac4f-ccbda35543d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645709579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2645709579
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.425275491
Short name T574
Test name
Test status
Simulation time 2550590519 ps
CPU time 7.86 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:06:57 PM PDT 24
Peak memory 242472 kb
Host smart-b2513977-e884-4d4d-847f-ca8d71d55354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425275491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.425275491
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.4176861037
Short name T15
Test name
Test status
Simulation time 29806898975 ps
CPU time 364.45 seconds
Started Jul 07 07:06:49 PM PDT 24
Finished Jul 07 07:12:54 PM PDT 24
Peak memory 300136 kb
Host smart-6f38cba0-005a-4188-8616-9f663682b6bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176861037 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.4176861037
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.1956058440
Short name T1089
Test name
Test status
Simulation time 662149946 ps
CPU time 9.65 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:06:58 PM PDT 24
Peak memory 242496 kb
Host smart-b415028b-4dfa-4013-bbbe-9e83a53c6060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956058440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1956058440
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.4088046798
Short name T962
Test name
Test status
Simulation time 80965139 ps
CPU time 1.73 seconds
Started Jul 07 07:06:57 PM PDT 24
Finished Jul 07 07:06:59 PM PDT 24
Peak memory 240604 kb
Host smart-4c6fc432-33db-4111-8ca5-843704afa26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088046798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.4088046798
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.4180868451
Short name T686
Test name
Test status
Simulation time 671234470 ps
CPU time 16.07 seconds
Started Jul 07 07:06:54 PM PDT 24
Finished Jul 07 07:07:10 PM PDT 24
Peak memory 241980 kb
Host smart-a5842f65-bded-4310-9974-9000b23395f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180868451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.4180868451
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2912215464
Short name T268
Test name
Test status
Simulation time 1707804243 ps
CPU time 31.22 seconds
Started Jul 07 07:06:54 PM PDT 24
Finished Jul 07 07:07:26 PM PDT 24
Peak memory 242356 kb
Host smart-cd510201-bfac-414f-9af8-12e5120cb2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912215464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2912215464
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.773815468
Short name T499
Test name
Test status
Simulation time 487176337 ps
CPU time 4.68 seconds
Started Jul 07 07:06:54 PM PDT 24
Finished Jul 07 07:06:58 PM PDT 24
Peak memory 242404 kb
Host smart-0f4c23f5-783b-4a10-9f68-c09ae356198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773815468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.773815468
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2886393050
Short name T445
Test name
Test status
Simulation time 2393578153 ps
CPU time 20.53 seconds
Started Jul 07 07:06:51 PM PDT 24
Finished Jul 07 07:07:12 PM PDT 24
Peak memory 248684 kb
Host smart-5969dd2b-d546-4128-aa50-385f7c3c2262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886393050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2886393050
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.373206267
Short name T904
Test name
Test status
Simulation time 435260035 ps
CPU time 5.94 seconds
Started Jul 07 07:06:52 PM PDT 24
Finished Jul 07 07:06:59 PM PDT 24
Peak memory 242332 kb
Host smart-e3a8d5c8-5396-449e-8e19-9bbfdb6995ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373206267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.373206267
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2113665063
Short name T165
Test name
Test status
Simulation time 134579091 ps
CPU time 3.7 seconds
Started Jul 07 07:06:53 PM PDT 24
Finished Jul 07 07:06:57 PM PDT 24
Peak memory 241960 kb
Host smart-f2234f42-a05e-4d46-8973-cf96f8eda194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113665063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2113665063
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.861384489
Short name T373
Test name
Test status
Simulation time 583959438 ps
CPU time 18.87 seconds
Started Jul 07 07:06:55 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 242296 kb
Host smart-d05cfc30-59bb-497d-b8b2-71eef82feb9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861384489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.861384489
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.824589870
Short name T1005
Test name
Test status
Simulation time 289558393 ps
CPU time 3.75 seconds
Started Jul 07 07:06:52 PM PDT 24
Finished Jul 07 07:06:56 PM PDT 24
Peak memory 241896 kb
Host smart-7dfb928d-18f3-4357-916d-fc87c5c436b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824589870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.824589870
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.1050205969
Short name T742
Test name
Test status
Simulation time 896842630 ps
CPU time 6.98 seconds
Started Jul 07 07:06:48 PM PDT 24
Finished Jul 07 07:06:56 PM PDT 24
Peak memory 242660 kb
Host smart-0db3fa27-ed57-4289-86ed-d4ec7e1fe8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050205969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1050205969
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1195447173
Short name T1049
Test name
Test status
Simulation time 142328681068 ps
CPU time 1628.51 seconds
Started Jul 07 07:06:52 PM PDT 24
Finished Jul 07 07:34:01 PM PDT 24
Peak memory 349236 kb
Host smart-5dcfddf5-0882-4dfc-9021-935ab93c9e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195447173 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.1195447173
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.3589963084
Short name T451
Test name
Test status
Simulation time 8046843773 ps
CPU time 17.16 seconds
Started Jul 07 07:06:51 PM PDT 24
Finished Jul 07 07:07:09 PM PDT 24
Peak memory 248868 kb
Host smart-44292740-0f99-4e06-8796-090d5447d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589963084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3589963084
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1453366234
Short name T919
Test name
Test status
Simulation time 109980282 ps
CPU time 1.96 seconds
Started Jul 07 07:06:58 PM PDT 24
Finished Jul 07 07:07:00 PM PDT 24
Peak memory 240396 kb
Host smart-8f8a90f8-f301-4d6c-af51-55f5313cb62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453366234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1453366234
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.2243562043
Short name T877
Test name
Test status
Simulation time 4062380199 ps
CPU time 25.59 seconds
Started Jul 07 07:06:55 PM PDT 24
Finished Jul 07 07:07:21 PM PDT 24
Peak memory 245628 kb
Host smart-f52f2dc6-f5da-45c3-b4c9-b7f6600b42ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243562043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2243562043
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.244527427
Short name T951
Test name
Test status
Simulation time 323274786 ps
CPU time 19.83 seconds
Started Jul 07 07:06:57 PM PDT 24
Finished Jul 07 07:07:17 PM PDT 24
Peak memory 241932 kb
Host smart-ebb95aaa-4b80-4b2d-8be7-6512b1de34be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244527427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.244527427
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3109201076
Short name T475
Test name
Test status
Simulation time 2063986573 ps
CPU time 20.09 seconds
Started Jul 07 07:06:55 PM PDT 24
Finished Jul 07 07:07:15 PM PDT 24
Peak memory 242344 kb
Host smart-19574272-f93b-4508-8075-73e606d9b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109201076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3109201076
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.3172926302
Short name T630
Test name
Test status
Simulation time 493428080 ps
CPU time 4.98 seconds
Started Jul 07 07:06:57 PM PDT 24
Finished Jul 07 07:07:02 PM PDT 24
Peak memory 241988 kb
Host smart-bfdc0f5c-1d3e-43dc-a005-2b59e8e02315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172926302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3172926302
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1092481488
Short name T181
Test name
Test status
Simulation time 1415568570 ps
CPU time 17.1 seconds
Started Jul 07 07:06:57 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 244752 kb
Host smart-281cf4db-01f4-40fe-aecd-87c6c8d77f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092481488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1092481488
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.4096178527
Short name T543
Test name
Test status
Simulation time 202394379 ps
CPU time 7.02 seconds
Started Jul 07 07:06:58 PM PDT 24
Finished Jul 07 07:07:05 PM PDT 24
Peak memory 242376 kb
Host smart-62d5d32d-43bd-4bc4-b191-a52c560eeb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096178527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.4096178527
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1937866045
Short name T571
Test name
Test status
Simulation time 248683960 ps
CPU time 5.19 seconds
Started Jul 07 07:06:56 PM PDT 24
Finished Jul 07 07:07:01 PM PDT 24
Peak memory 241956 kb
Host smart-5bd5dc3a-5374-41cf-a0dd-73d629165934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937866045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1937866045
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3073543411
Short name T1088
Test name
Test status
Simulation time 502413804 ps
CPU time 4.82 seconds
Started Jul 07 07:06:56 PM PDT 24
Finished Jul 07 07:07:01 PM PDT 24
Peak memory 241928 kb
Host smart-f2998bb4-474b-47e3-a045-b07abb70b4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073543411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3073543411
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.468532236
Short name T169
Test name
Test status
Simulation time 3653279757 ps
CPU time 9.75 seconds
Started Jul 07 07:06:58 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 242184 kb
Host smart-f7add0c3-1895-4dd7-a3d8-b719a51a45e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468532236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.468532236
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.1502467550
Short name T98
Test name
Test status
Simulation time 773429986 ps
CPU time 8.76 seconds
Started Jul 07 07:06:56 PM PDT 24
Finished Jul 07 07:07:05 PM PDT 24
Peak memory 242068 kb
Host smart-ea9b6845-bbe2-4657-b949-f45d223cb67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502467550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1502467550
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2474645314
Short name T1043
Test name
Test status
Simulation time 785863714871 ps
CPU time 1141.85 seconds
Started Jul 07 07:06:57 PM PDT 24
Finished Jul 07 07:25:59 PM PDT 24
Peak memory 328064 kb
Host smart-17671e4a-1c45-4242-8b70-ffc3f8e01a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474645314 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2474645314
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3312478933
Short name T796
Test name
Test status
Simulation time 544688311 ps
CPU time 15.06 seconds
Started Jul 07 07:06:59 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 242636 kb
Host smart-fed2d022-7292-4ac7-94ac-d050af37b90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312478933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3312478933
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3897008482
Short name T568
Test name
Test status
Simulation time 62806059 ps
CPU time 2.01 seconds
Started Jul 07 07:07:04 PM PDT 24
Finished Jul 07 07:07:06 PM PDT 24
Peak memory 240244 kb
Host smart-dfc8253d-de2c-44b9-b966-b3ddfc63d03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897008482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3897008482
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.491843862
Short name T122
Test name
Test status
Simulation time 1646997803 ps
CPU time 32.4 seconds
Started Jul 07 07:07:00 PM PDT 24
Finished Jul 07 07:07:33 PM PDT 24
Peak memory 248720 kb
Host smart-2ab35168-1092-4d7a-965b-ee3eb6090ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491843862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.491843862
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.1354280857
Short name T864
Test name
Test status
Simulation time 2194791939 ps
CPU time 28.24 seconds
Started Jul 07 07:07:01 PM PDT 24
Finished Jul 07 07:07:29 PM PDT 24
Peak memory 244364 kb
Host smart-f27421a0-c04e-464d-ae19-8fe76a5a4320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354280857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1354280857
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.3629103441
Short name T639
Test name
Test status
Simulation time 2788889541 ps
CPU time 20.56 seconds
Started Jul 07 07:06:59 PM PDT 24
Finished Jul 07 07:07:20 PM PDT 24
Peak memory 241988 kb
Host smart-d61d5e4b-fd60-4762-b31b-ccee16304fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629103441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3629103441
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.3147010693
Short name T1134
Test name
Test status
Simulation time 240276386 ps
CPU time 4.29 seconds
Started Jul 07 07:06:59 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 242060 kb
Host smart-feca941a-f26f-4c4d-a0e4-f80ed5c39ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147010693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3147010693
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.4275867049
Short name T883
Test name
Test status
Simulation time 1461651520 ps
CPU time 33.36 seconds
Started Jul 07 07:07:02 PM PDT 24
Finished Jul 07 07:07:35 PM PDT 24
Peak memory 248792 kb
Host smart-92f14772-ec36-465e-a661-77c6462556d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275867049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.4275867049
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2556778367
Short name T678
Test name
Test status
Simulation time 175740531 ps
CPU time 6.57 seconds
Started Jul 07 07:06:59 PM PDT 24
Finished Jul 07 07:07:06 PM PDT 24
Peak memory 242072 kb
Host smart-4336af85-705b-440b-a435-881a8979ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556778367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2556778367
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3089229165
Short name T582
Test name
Test status
Simulation time 456611751 ps
CPU time 4.83 seconds
Started Jul 07 07:07:00 PM PDT 24
Finished Jul 07 07:07:05 PM PDT 24
Peak memory 248592 kb
Host smart-0b5fb13a-ab2e-4add-b948-6fe05533366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089229165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3089229165
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1615692327
Short name T359
Test name
Test status
Simulation time 452678006 ps
CPU time 5.25 seconds
Started Jul 07 07:07:01 PM PDT 24
Finished Jul 07 07:07:06 PM PDT 24
Peak memory 241872 kb
Host smart-56e7cc76-4b8e-459d-98bb-cf00e5f6ed53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615692327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1615692327
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.885097650
Short name T854
Test name
Test status
Simulation time 526809011 ps
CPU time 10.43 seconds
Started Jul 07 07:06:58 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 248764 kb
Host smart-1d4e1130-9f02-47ba-a422-04339f6d29c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885097650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.885097650
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.52944516
Short name T948
Test name
Test status
Simulation time 45360485694 ps
CPU time 262.78 seconds
Started Jul 07 07:06:59 PM PDT 24
Finished Jul 07 07:11:22 PM PDT 24
Peak memory 262020 kb
Host smart-c3559841-ba59-45f4-8c37-2b3a4328872b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52944516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.52944516
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.2768135492
Short name T1045
Test name
Test status
Simulation time 2293181225 ps
CPU time 33.9 seconds
Started Jul 07 07:07:00 PM PDT 24
Finished Jul 07 07:07:34 PM PDT 24
Peak memory 242160 kb
Host smart-7497ece7-1f1c-4aae-af16-9e8feea56797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768135492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2768135492
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.1111149675
Short name T468
Test name
Test status
Simulation time 372629082 ps
CPU time 4.02 seconds
Started Jul 07 07:07:05 PM PDT 24
Finished Jul 07 07:07:09 PM PDT 24
Peak memory 240532 kb
Host smart-4bb68ecf-bb8b-4044-86a7-305640a00808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111149675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1111149675
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.611148910
Short name T409
Test name
Test status
Simulation time 11802954407 ps
CPU time 19.59 seconds
Started Jul 07 07:07:03 PM PDT 24
Finished Jul 07 07:07:22 PM PDT 24
Peak memory 248844 kb
Host smart-2fc13cbf-f8ad-4d6d-82ed-a9a87e2c48bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611148910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.611148910
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1516242057
Short name T596
Test name
Test status
Simulation time 1417908295 ps
CPU time 22.86 seconds
Started Jul 07 07:07:07 PM PDT 24
Finished Jul 07 07:07:31 PM PDT 24
Peak memory 241896 kb
Host smart-cfe95a19-e709-43da-8fff-337bc8b11b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516242057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1516242057
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2572229202
Short name T436
Test name
Test status
Simulation time 932207955 ps
CPU time 7.27 seconds
Started Jul 07 07:07:00 PM PDT 24
Finished Jul 07 07:07:07 PM PDT 24
Peak memory 242300 kb
Host smart-96782e01-1068-4a04-9179-4a7782868c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572229202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2572229202
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.2351076572
Short name T846
Test name
Test status
Simulation time 135371727 ps
CPU time 4.19 seconds
Started Jul 07 07:07:00 PM PDT 24
Finished Jul 07 07:07:04 PM PDT 24
Peak memory 242380 kb
Host smart-cbbc9c84-16cf-4690-8a81-44323a661e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351076572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2351076572
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.415818239
Short name T608
Test name
Test status
Simulation time 426029058 ps
CPU time 11.07 seconds
Started Jul 07 07:07:04 PM PDT 24
Finished Jul 07 07:07:15 PM PDT 24
Peak memory 242184 kb
Host smart-d48e4fb4-df59-4f64-a92d-807f9aff12ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415818239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.415818239
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.3776289229
Short name T41
Test name
Test status
Simulation time 950298526 ps
CPU time 24.3 seconds
Started Jul 07 07:07:02 PM PDT 24
Finished Jul 07 07:07:27 PM PDT 24
Peak memory 241936 kb
Host smart-78d99140-3598-487d-9f78-662165cb7954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776289229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3776289229
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2762261617
Short name T597
Test name
Test status
Simulation time 230015839 ps
CPU time 6.73 seconds
Started Jul 07 07:07:02 PM PDT 24
Finished Jul 07 07:07:09 PM PDT 24
Peak memory 242044 kb
Host smart-8117eeba-464c-4894-9138-d9d45d70ed04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762261617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2762261617
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.852414906
Short name T1076
Test name
Test status
Simulation time 139054266 ps
CPU time 6.2 seconds
Started Jul 07 07:07:05 PM PDT 24
Finished Jul 07 07:07:11 PM PDT 24
Peak memory 248784 kb
Host smart-47209ab1-5e0a-4b2d-a0fc-aeac87a996ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852414906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.852414906
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1142560030
Short name T668
Test name
Test status
Simulation time 604998814 ps
CPU time 7.5 seconds
Started Jul 07 07:07:04 PM PDT 24
Finished Jul 07 07:07:12 PM PDT 24
Peak memory 242284 kb
Host smart-a08509b7-5d2f-4e65-b1f5-1ca36c7b9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142560030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1142560030
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.1216128412
Short name T374
Test name
Test status
Simulation time 4132925225 ps
CPU time 59.85 seconds
Started Jul 07 07:07:03 PM PDT 24
Finished Jul 07 07:08:03 PM PDT 24
Peak memory 248080 kb
Host smart-6028ad67-557a-4795-b700-8485e2db7efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216128412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.1216128412
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1515472093
Short name T447
Test name
Test status
Simulation time 116410041 ps
CPU time 1.89 seconds
Started Jul 07 07:07:12 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 240496 kb
Host smart-72508a50-75b7-44bf-81fe-98a5ab6e9d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515472093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1515472093
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2552136965
Short name T887
Test name
Test status
Simulation time 5946490823 ps
CPU time 12.74 seconds
Started Jul 07 07:07:06 PM PDT 24
Finished Jul 07 07:07:19 PM PDT 24
Peak memory 242052 kb
Host smart-ab9163f7-9174-4a91-9b30-c65f87e9dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552136965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2552136965
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.2299536269
Short name T166
Test name
Test status
Simulation time 941247302 ps
CPU time 5.98 seconds
Started Jul 07 07:07:08 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 242416 kb
Host smart-908b4ce1-4cfa-4f86-affa-3d389176bbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299536269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2299536269
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1711071863
Short name T809
Test name
Test status
Simulation time 273479383 ps
CPU time 3.15 seconds
Started Jul 07 07:07:05 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 242356 kb
Host smart-0adcf7e4-ac04-4c4d-a5a9-48107d85e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711071863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1711071863
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.4281227775
Short name T736
Test name
Test status
Simulation time 5177378351 ps
CPU time 12.58 seconds
Started Jul 07 07:07:08 PM PDT 24
Finished Jul 07 07:07:21 PM PDT 24
Peak memory 242576 kb
Host smart-39ae5c17-e19d-410c-8c83-6f4af83ead7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281227775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.4281227775
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.2707901480
Short name T715
Test name
Test status
Simulation time 3498422089 ps
CPU time 30.15 seconds
Started Jul 07 07:07:09 PM PDT 24
Finished Jul 07 07:07:40 PM PDT 24
Peak memory 242420 kb
Host smart-fa4bc631-a233-45dc-987a-bedc76067478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707901480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2707901480
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.739229815
Short name T918
Test name
Test status
Simulation time 453457160 ps
CPU time 8.14 seconds
Started Jul 07 07:07:06 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 241776 kb
Host smart-55bb602b-5a66-4bdd-a168-563342a8a8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739229815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.739229815
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.614037514
Short name T500
Test name
Test status
Simulation time 2735165829 ps
CPU time 5.69 seconds
Started Jul 07 07:07:02 PM PDT 24
Finished Jul 07 07:07:08 PM PDT 24
Peak memory 248700 kb
Host smart-ff4b2d2e-c211-42c7-b19d-c3972ebd1806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614037514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.614037514
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.375893492
Short name T415
Test name
Test status
Simulation time 371236942 ps
CPU time 8.54 seconds
Started Jul 07 07:07:05 PM PDT 24
Finished Jul 07 07:07:14 PM PDT 24
Peak memory 241964 kb
Host smart-282c3f1c-c3a1-4851-a6b1-3c47a75e346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375893492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.375893492
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2555530354
Short name T1157
Test name
Test status
Simulation time 548588085 ps
CPU time 10.23 seconds
Started Jul 07 07:07:11 PM PDT 24
Finished Jul 07 07:07:22 PM PDT 24
Peak memory 241472 kb
Host smart-aa769a40-76d2-4590-9ce0-2b72beb2af62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555530354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2555530354
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.3212895981
Short name T676
Test name
Test status
Simulation time 474159620293 ps
CPU time 1240.16 seconds
Started Jul 07 07:07:08 PM PDT 24
Finished Jul 07 07:27:49 PM PDT 24
Peak memory 303296 kb
Host smart-58136b28-13aa-4529-8346-a4eebc8d4a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212895981 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.3212895981
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.2318217786
Short name T287
Test name
Test status
Simulation time 680298266 ps
CPU time 19.53 seconds
Started Jul 07 07:07:08 PM PDT 24
Finished Jul 07 07:07:28 PM PDT 24
Peak memory 242032 kb
Host smart-1a0d8d8b-d39c-4c98-953d-32e383e751c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318217786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2318217786
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.3037108046
Short name T814
Test name
Test status
Simulation time 747606024 ps
CPU time 2.29 seconds
Started Jul 07 07:07:14 PM PDT 24
Finished Jul 07 07:07:17 PM PDT 24
Peak memory 240276 kb
Host smart-d5a4c664-bd40-486c-b706-ad2064088f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037108046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3037108046
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.228692104
Short name T136
Test name
Test status
Simulation time 10251163312 ps
CPU time 22.93 seconds
Started Jul 07 07:07:13 PM PDT 24
Finished Jul 07 07:07:36 PM PDT 24
Peak memory 242288 kb
Host smart-b4642f20-d01a-4906-b814-6eac6ab4193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228692104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.228692104
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3568546310
Short name T1095
Test name
Test status
Simulation time 17262280047 ps
CPU time 43.73 seconds
Started Jul 07 07:07:12 PM PDT 24
Finished Jul 07 07:07:56 PM PDT 24
Peak memory 247876 kb
Host smart-5ebb4a4e-99a9-4cfb-a8be-29b87e198e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568546310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3568546310
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.541180779
Short name T1183
Test name
Test status
Simulation time 1608862201 ps
CPU time 34.4 seconds
Started Jul 07 07:07:10 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 242400 kb
Host smart-40c188d6-3ab2-4f65-a987-47330f9a2dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541180779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.541180779
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2517622113
Short name T1083
Test name
Test status
Simulation time 1603449739 ps
CPU time 3.97 seconds
Started Jul 07 07:07:12 PM PDT 24
Finished Jul 07 07:07:16 PM PDT 24
Peak memory 242144 kb
Host smart-733ba590-7dc6-4460-b10a-155009c07082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517622113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2517622113
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3616443555
Short name T6
Test name
Test status
Simulation time 2083575104 ps
CPU time 14.85 seconds
Started Jul 07 07:07:13 PM PDT 24
Finished Jul 07 07:07:28 PM PDT 24
Peak memory 248816 kb
Host smart-242b371b-1f97-44be-87b5-bf4cc9c0f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616443555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3616443555
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.2985323521
Short name T1070
Test name
Test status
Simulation time 1117460247 ps
CPU time 21.47 seconds
Started Jul 07 07:07:11 PM PDT 24
Finished Jul 07 07:07:32 PM PDT 24
Peak memory 242412 kb
Host smart-6767f1a6-bc8a-4403-b070-878e6686cc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985323521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2985323521
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.3259339424
Short name T777
Test name
Test status
Simulation time 175831810 ps
CPU time 6.23 seconds
Started Jul 07 07:07:13 PM PDT 24
Finished Jul 07 07:07:20 PM PDT 24
Peak memory 242204 kb
Host smart-2463c6b6-6980-46ec-a66a-145ce68d91ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259339424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3259339424
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.4280527932
Short name T1171
Test name
Test status
Simulation time 1469909590 ps
CPU time 19.86 seconds
Started Jul 07 07:07:11 PM PDT 24
Finished Jul 07 07:07:32 PM PDT 24
Peak memory 248664 kb
Host smart-5c4a1655-e630-4d6f-948b-f851b6a1942e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280527932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.4280527932
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2228468670
Short name T5
Test name
Test status
Simulation time 207862019 ps
CPU time 3.28 seconds
Started Jul 07 07:07:11 PM PDT 24
Finished Jul 07 07:07:15 PM PDT 24
Peak memory 242444 kb
Host smart-290ee356-fdb1-4769-b44b-5c3d73903570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2228468670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2228468670
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3409156573
Short name T634
Test name
Test status
Simulation time 2436211294 ps
CPU time 6.67 seconds
Started Jul 07 07:07:11 PM PDT 24
Finished Jul 07 07:07:18 PM PDT 24
Peak memory 241996 kb
Host smart-27b93e83-ea13-4f97-8bd5-070122ce6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409156573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3409156573
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.689051965
Short name T704
Test name
Test status
Simulation time 44263723600 ps
CPU time 119.99 seconds
Started Jul 07 07:07:14 PM PDT 24
Finished Jul 07 07:09:15 PM PDT 24
Peak memory 261348 kb
Host smart-a1ff0a34-c6c2-46bf-ac4f-32e7b98f3932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689051965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
689051965
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.1467409153
Short name T1121
Test name
Test status
Simulation time 430677201798 ps
CPU time 1207.24 seconds
Started Jul 07 07:07:16 PM PDT 24
Finished Jul 07 07:27:24 PM PDT 24
Peak memory 338020 kb
Host smart-7de83116-e857-42ef-ad7f-27c9e2b58cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467409153 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.1467409153
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.3982966080
Short name T411
Test name
Test status
Simulation time 1113635245 ps
CPU time 7.09 seconds
Started Jul 07 07:07:15 PM PDT 24
Finished Jul 07 07:07:22 PM PDT 24
Peak memory 242420 kb
Host smart-7acdb6b0-2545-4a76-81cb-6a11324ea923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982966080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3982966080
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2835442544
Short name T538
Test name
Test status
Simulation time 111222555 ps
CPU time 2.03 seconds
Started Jul 07 07:07:21 PM PDT 24
Finished Jul 07 07:07:24 PM PDT 24
Peak memory 240056 kb
Host smart-3d29fd93-8c33-40b5-9bfd-f57c7eb50d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835442544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2835442544
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.1489955168
Short name T118
Test name
Test status
Simulation time 1812963551 ps
CPU time 31.14 seconds
Started Jul 07 07:07:14 PM PDT 24
Finished Jul 07 07:07:45 PM PDT 24
Peak memory 242236 kb
Host smart-093ae9de-aa1f-43d9-894e-99f4d48e8729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489955168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1489955168
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.1000510521
Short name T343
Test name
Test status
Simulation time 1243038529 ps
CPU time 17.62 seconds
Started Jul 07 07:07:20 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 242160 kb
Host smart-ded6aede-659a-4d14-9588-8c550ea86bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000510521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1000510521
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.4023140672
Short name T850
Test name
Test status
Simulation time 1403645014 ps
CPU time 27 seconds
Started Jul 07 07:07:13 PM PDT 24
Finished Jul 07 07:07:41 PM PDT 24
Peak memory 242264 kb
Host smart-cbf31c26-0d3f-4af8-a9f6-eda1950a7ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023140672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.4023140672
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.2230683538
Short name T478
Test name
Test status
Simulation time 2534856949 ps
CPU time 6.57 seconds
Started Jul 07 07:07:16 PM PDT 24
Finished Jul 07 07:07:23 PM PDT 24
Peak memory 241964 kb
Host smart-3d9e4249-c7d5-44f4-b99f-2a950f76ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230683538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2230683538
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.1385508993
Short name T623
Test name
Test status
Simulation time 3551506512 ps
CPU time 25.19 seconds
Started Jul 07 07:07:14 PM PDT 24
Finished Jul 07 07:07:40 PM PDT 24
Peak memory 248884 kb
Host smart-28c884fa-27b1-4e9b-95fa-8b26ce47c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385508993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1385508993
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.134755585
Short name T1080
Test name
Test status
Simulation time 184403714 ps
CPU time 4.91 seconds
Started Jul 07 07:07:14 PM PDT 24
Finished Jul 07 07:07:19 PM PDT 24
Peak memory 242400 kb
Host smart-56c2d14d-2348-4422-820b-9f337aebb157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134755585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.134755585
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2776880641
Short name T461
Test name
Test status
Simulation time 498189795 ps
CPU time 5.3 seconds
Started Jul 07 07:07:16 PM PDT 24
Finished Jul 07 07:07:21 PM PDT 24
Peak memory 241708 kb
Host smart-fdcfcf95-e694-4b0a-a351-178fc7d28500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776880641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2776880641
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.477448724
Short name T416
Test name
Test status
Simulation time 394058209 ps
CPU time 6.64 seconds
Started Jul 07 07:07:14 PM PDT 24
Finished Jul 07 07:07:21 PM PDT 24
Peak memory 241848 kb
Host smart-802644f0-bd4d-450c-af52-d90ac336fe4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477448724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.477448724
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.3739415503
Short name T602
Test name
Test status
Simulation time 262817684 ps
CPU time 4.9 seconds
Started Jul 07 07:07:18 PM PDT 24
Finished Jul 07 07:07:23 PM PDT 24
Peak memory 242032 kb
Host smart-f3ee400c-17af-411c-8398-b5c7c502172e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739415503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3739415503
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3267003299
Short name T749
Test name
Test status
Simulation time 689559831 ps
CPU time 9.66 seconds
Started Jul 07 07:07:17 PM PDT 24
Finished Jul 07 07:07:27 PM PDT 24
Peak memory 242072 kb
Host smart-69d70e8d-1e99-4525-86aa-a62518aa785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267003299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3267003299
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.4288203728
Short name T790
Test name
Test status
Simulation time 15625121002 ps
CPU time 51.3 seconds
Started Jul 07 07:07:23 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 244240 kb
Host smart-4bbba2f2-81b4-477a-a933-3396c2345868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288203728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.4288203728
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1880075796
Short name T834
Test name
Test status
Simulation time 206343707713 ps
CPU time 673.26 seconds
Started Jul 07 07:07:21 PM PDT 24
Finished Jul 07 07:18:35 PM PDT 24
Peak memory 306580 kb
Host smart-616870cc-4d53-4cbb-963b-c562805db5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880075796 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.1880075796
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.4259516215
Short name T640
Test name
Test status
Simulation time 3481513231 ps
CPU time 55.48 seconds
Started Jul 07 07:07:19 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 248868 kb
Host smart-e7e55393-fbb4-4bda-b083-94896a7a2a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259516215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4259516215
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.1757999717
Short name T627
Test name
Test status
Simulation time 201477222 ps
CPU time 1.88 seconds
Started Jul 07 07:07:28 PM PDT 24
Finished Jul 07 07:07:30 PM PDT 24
Peak memory 240404 kb
Host smart-9dfe8476-2c09-4e9d-8724-f52846d5b148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757999717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1757999717
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.3352378229
Short name T58
Test name
Test status
Simulation time 1006085771 ps
CPU time 9.98 seconds
Started Jul 07 07:07:21 PM PDT 24
Finished Jul 07 07:07:32 PM PDT 24
Peak memory 248828 kb
Host smart-3ae317aa-e34d-4830-8cf9-b88d4870c192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352378229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3352378229
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.972547211
Short name T408
Test name
Test status
Simulation time 13910494567 ps
CPU time 35.55 seconds
Started Jul 07 07:07:23 PM PDT 24
Finished Jul 07 07:07:59 PM PDT 24
Peak memory 244912 kb
Host smart-9e0b7c62-db5e-4758-a4d4-f1de652380e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972547211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.972547211
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.2917836341
Short name T1127
Test name
Test status
Simulation time 145083354 ps
CPU time 4.18 seconds
Started Jul 07 07:07:22 PM PDT 24
Finished Jul 07 07:07:27 PM PDT 24
Peak memory 242352 kb
Host smart-af6a8ded-978d-47d5-aa8a-2dc072ea2960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917836341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2917836341
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.3280414081
Short name T45
Test name
Test status
Simulation time 673862722 ps
CPU time 5.66 seconds
Started Jul 07 07:07:22 PM PDT 24
Finished Jul 07 07:07:28 PM PDT 24
Peak memory 242040 kb
Host smart-4774c67f-a999-4b62-b168-a4a21cc0e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280414081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3280414081
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.469197895
Short name T563
Test name
Test status
Simulation time 11472256211 ps
CPU time 28.36 seconds
Started Jul 07 07:07:22 PM PDT 24
Finished Jul 07 07:07:51 PM PDT 24
Peak memory 247300 kb
Host smart-4ff91ec1-b691-4db4-8c3f-a7b52aed4f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469197895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.469197895
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.1606880672
Short name T155
Test name
Test status
Simulation time 345146259 ps
CPU time 7.33 seconds
Started Jul 07 07:07:22 PM PDT 24
Finished Jul 07 07:07:29 PM PDT 24
Peak memory 242608 kb
Host smart-59a67102-3167-48ac-bf50-cef87941162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606880672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1606880672
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3562987380
Short name T341
Test name
Test status
Simulation time 2091386329 ps
CPU time 15.58 seconds
Started Jul 07 07:07:20 PM PDT 24
Finished Jul 07 07:07:36 PM PDT 24
Peak memory 242212 kb
Host smart-fc6623b1-62c5-4b56-bdfc-095f3d79232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562987380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3562987380
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1103074487
Short name T1114
Test name
Test status
Simulation time 414140567 ps
CPU time 11.65 seconds
Started Jul 07 07:07:23 PM PDT 24
Finished Jul 07 07:07:35 PM PDT 24
Peak memory 242008 kb
Host smart-0ca35a02-2f9d-469d-a01e-c6337bab027c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103074487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1103074487
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1962330919
Short name T474
Test name
Test status
Simulation time 487965370 ps
CPU time 5.55 seconds
Started Jul 07 07:07:22 PM PDT 24
Finished Jul 07 07:07:28 PM PDT 24
Peak memory 241900 kb
Host smart-e70263b8-e462-4bd4-b815-a527a857b349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962330919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1962330919
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.476433978
Short name T908
Test name
Test status
Simulation time 271636366 ps
CPU time 6.31 seconds
Started Jul 07 07:07:22 PM PDT 24
Finished Jul 07 07:07:29 PM PDT 24
Peak memory 248744 kb
Host smart-ce5a2a54-ff00-4592-8539-52ddbc063750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476433978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.476433978
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3758553344
Short name T994
Test name
Test status
Simulation time 227198621495 ps
CPU time 1752.2 seconds
Started Jul 07 07:07:27 PM PDT 24
Finished Jul 07 07:36:40 PM PDT 24
Peak memory 319552 kb
Host smart-f6b3035a-980c-434b-b41d-db2b6437c634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758553344 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3758553344
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.320286029
Short name T914
Test name
Test status
Simulation time 766730773 ps
CPU time 11.12 seconds
Started Jul 07 07:07:27 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 242172 kb
Host smart-d77aaa5f-3759-4c66-8449-a3c37252489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320286029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.320286029
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.2903312718
Short name T559
Test name
Test status
Simulation time 275724982 ps
CPU time 2.34 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:33 PM PDT 24
Peak memory 240128 kb
Host smart-57441572-6cb6-4145-93ce-63573482c782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903312718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2903312718
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1320700106
Short name T1146
Test name
Test status
Simulation time 1462399605 ps
CPU time 31.35 seconds
Started Jul 07 07:07:26 PM PDT 24
Finished Jul 07 07:07:58 PM PDT 24
Peak memory 242316 kb
Host smart-e257e36d-e063-4a44-928b-4886e4a000bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320700106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1320700106
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.3114998899
Short name T439
Test name
Test status
Simulation time 247619764 ps
CPU time 12.74 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:43 PM PDT 24
Peak memory 241952 kb
Host smart-b4b82b1a-e17f-4550-aacb-7663904f04dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114998899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3114998899
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.2887640349
Short name T372
Test name
Test status
Simulation time 1282512034 ps
CPU time 14.58 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:45 PM PDT 24
Peak memory 242188 kb
Host smart-156343b0-4087-4690-a3ff-dfbda64e4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887640349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2887640349
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3940376821
Short name T847
Test name
Test status
Simulation time 166221875 ps
CPU time 4.86 seconds
Started Jul 07 07:07:24 PM PDT 24
Finished Jul 07 07:07:30 PM PDT 24
Peak memory 242012 kb
Host smart-6d5d4a40-c07a-4cf7-95fe-0004fd67e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940376821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3940376821
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3753644139
Short name T986
Test name
Test status
Simulation time 698748176 ps
CPU time 8.54 seconds
Started Jul 07 07:07:28 PM PDT 24
Finished Jul 07 07:07:37 PM PDT 24
Peak memory 242324 kb
Host smart-1d0a4c3a-5d2d-47c2-8da3-eafee8bcbbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753644139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3753644139
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3088857741
Short name T747
Test name
Test status
Simulation time 538302436 ps
CPU time 7.37 seconds
Started Jul 07 07:07:27 PM PDT 24
Finished Jul 07 07:07:35 PM PDT 24
Peak memory 241964 kb
Host smart-29ed04d9-3d3a-47b9-9c91-4d7aeb32ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088857741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3088857741
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.520692714
Short name T154
Test name
Test status
Simulation time 12664777872 ps
CPU time 35.39 seconds
Started Jul 07 07:07:25 PM PDT 24
Finished Jul 07 07:08:01 PM PDT 24
Peak memory 242160 kb
Host smart-bdfe669c-badd-4f18-b63b-35deeb239905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520692714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.520692714
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2963013415
Short name T830
Test name
Test status
Simulation time 452896351 ps
CPU time 11.06 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:41 PM PDT 24
Peak memory 241976 kb
Host smart-2dc99ac2-06b6-4950-9bb2-2a8d8ad8872a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963013415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2963013415
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2034693015
Short name T396
Test name
Test status
Simulation time 226874472 ps
CPU time 3.26 seconds
Started Jul 07 07:07:27 PM PDT 24
Finished Jul 07 07:07:31 PM PDT 24
Peak memory 242252 kb
Host smart-52e1ac14-880c-4933-b6d3-5b0bc958869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034693015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2034693015
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.1548771955
Short name T186
Test name
Test status
Simulation time 163704775944 ps
CPU time 228.78 seconds
Started Jul 07 07:07:28 PM PDT 24
Finished Jul 07 07:11:17 PM PDT 24
Peak memory 289788 kb
Host smart-3c54b31b-8a92-47a2-9b7b-25349eb573ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548771955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.1548771955
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.766861699
Short name T1107
Test name
Test status
Simulation time 85174387888 ps
CPU time 654.78 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:18:25 PM PDT 24
Peak memory 257168 kb
Host smart-d874d8a0-be3d-497b-876f-ea5820acfc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766861699 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.766861699
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3656434168
Short name T698
Test name
Test status
Simulation time 915187041 ps
CPU time 16.13 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:46 PM PDT 24
Peak memory 242248 kb
Host smart-535c0f01-f011-4f2f-91fd-bf3e90257fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656434168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3656434168
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2413907931
Short name T240
Test name
Test status
Simulation time 40827746 ps
CPU time 1.61 seconds
Started Jul 07 07:04:33 PM PDT 24
Finished Jul 07 07:04:35 PM PDT 24
Peak memory 240112 kb
Host smart-78596430-f699-48ee-9f33-14166cfefa91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413907931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2413907931
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.3219889299
Short name T926
Test name
Test status
Simulation time 2157818352 ps
CPU time 25.37 seconds
Started Jul 07 07:04:29 PM PDT 24
Finished Jul 07 07:04:54 PM PDT 24
Peak memory 242316 kb
Host smart-af94d906-1f26-4c54-a7db-fe5f0cec5552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219889299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3219889299
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3063913192
Short name T477
Test name
Test status
Simulation time 1149495774 ps
CPU time 27.81 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:05:02 PM PDT 24
Peak memory 242056 kb
Host smart-004db3f7-5de0-4d74-b8ff-ba326fee6683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063913192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3063913192
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3016249091
Short name T495
Test name
Test status
Simulation time 1248246899 ps
CPU time 11.03 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:04:48 PM PDT 24
Peak memory 242300 kb
Host smart-c745460b-c451-4844-8d00-62cccb82c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016249091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3016249091
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3941342167
Short name T513
Test name
Test status
Simulation time 169171417 ps
CPU time 4.25 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:38 PM PDT 24
Peak memory 242056 kb
Host smart-5fb6eac5-a248-498b-8f36-0faead284379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941342167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3941342167
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.4248291337
Short name T505
Test name
Test status
Simulation time 724961799 ps
CPU time 7.15 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:04:47 PM PDT 24
Peak memory 242448 kb
Host smart-f81d24a4-f834-46a5-a12c-3aa1572fd4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248291337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.4248291337
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.2795292698
Short name T392
Test name
Test status
Simulation time 419938747 ps
CPU time 11.17 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 242188 kb
Host smart-95ed2bfc-9af8-45be-bc83-66038a3c87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795292698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.2795292698
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.778093713
Short name T326
Test name
Test status
Simulation time 407583556 ps
CPU time 4.57 seconds
Started Jul 07 07:04:36 PM PDT 24
Finished Jul 07 07:04:41 PM PDT 24
Peak memory 241916 kb
Host smart-ea081e70-bc64-4d48-bd63-440f8567c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778093713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.778093713
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2534659842
Short name T845
Test name
Test status
Simulation time 321363454 ps
CPU time 4.47 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:39 PM PDT 24
Peak memory 248440 kb
Host smart-7fe7d706-7638-42b3-931c-7124a58bb0da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534659842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2534659842
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.2149169456
Short name T709
Test name
Test status
Simulation time 122469204 ps
CPU time 3.8 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:38 PM PDT 24
Peak memory 242084 kb
Host smart-271b2a9c-92e3-4fef-a82e-268eccb9e6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149169456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2149169456
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3384263017
Short name T1092
Test name
Test status
Simulation time 460408393 ps
CPU time 6.86 seconds
Started Jul 07 07:04:36 PM PDT 24
Finished Jul 07 07:04:44 PM PDT 24
Peak memory 242200 kb
Host smart-61430329-4364-4196-9185-c8a18dceecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384263017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3384263017
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1403607165
Short name T333
Test name
Test status
Simulation time 121962275820 ps
CPU time 916.31 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:19:51 PM PDT 24
Peak memory 388844 kb
Host smart-ee467fc2-7c40-4b4d-93ac-9da72dc3f746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403607165 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1403607165
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3652220430
Short name T934
Test name
Test status
Simulation time 932424267 ps
CPU time 20.29 seconds
Started Jul 07 07:04:33 PM PDT 24
Finished Jul 07 07:04:54 PM PDT 24
Peak memory 242412 kb
Host smart-6d5d7bc2-383d-4e32-a9a1-93d27a3eafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652220430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3652220430
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.2819490177
Short name T1056
Test name
Test status
Simulation time 94784884 ps
CPU time 3.4 seconds
Started Jul 07 07:07:29 PM PDT 24
Finished Jul 07 07:07:33 PM PDT 24
Peak memory 241928 kb
Host smart-0c24af6b-8b90-4076-b4f0-89dbe401e92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819490177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2819490177
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1981029581
Short name T1006
Test name
Test status
Simulation time 133773329 ps
CPU time 4.57 seconds
Started Jul 07 07:07:31 PM PDT 24
Finished Jul 07 07:07:36 PM PDT 24
Peak memory 242228 kb
Host smart-d1f111de-2b7c-4880-967d-55fece76ccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981029581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1981029581
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1205252282
Short name T19
Test name
Test status
Simulation time 480615045605 ps
CPU time 1472.56 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:32:03 PM PDT 24
Peak memory 289068 kb
Host smart-c323ae3f-c65f-41a2-8988-98947bf68f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205252282 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.1205252282
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.3734169144
Short name T282
Test name
Test status
Simulation time 260761800 ps
CPU time 6.79 seconds
Started Jul 07 07:07:32 PM PDT 24
Finished Jul 07 07:07:39 PM PDT 24
Peak memory 241668 kb
Host smart-67864dc2-f09b-4302-8445-a69c27203561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734169144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3734169144
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.2579195598
Short name T382
Test name
Test status
Simulation time 29340605472 ps
CPU time 774.23 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:20:25 PM PDT 24
Peak memory 275048 kb
Host smart-19936726-5cba-4258-82fb-9b46d678a89e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579195598 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.2579195598
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3179482955
Short name T1139
Test name
Test status
Simulation time 373940370 ps
CPU time 3.93 seconds
Started Jul 07 07:07:32 PM PDT 24
Finished Jul 07 07:07:36 PM PDT 24
Peak memory 242064 kb
Host smart-577241b9-5299-4333-9984-b74d2e3c1a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179482955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3179482955
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3318194674
Short name T827
Test name
Test status
Simulation time 428313374 ps
CPU time 7 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:37 PM PDT 24
Peak memory 241884 kb
Host smart-58c7121e-7223-4098-a607-34bded0f94a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318194674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3318194674
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.882021559
Short name T387
Test name
Test status
Simulation time 400107613740 ps
CPU time 1441.39 seconds
Started Jul 07 07:07:29 PM PDT 24
Finished Jul 07 07:31:31 PM PDT 24
Peak memory 345416 kb
Host smart-d14dc560-e5c6-45df-a59d-04da249bd62c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882021559 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.882021559
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.1829784264
Short name T52
Test name
Test status
Simulation time 365397505 ps
CPU time 3.24 seconds
Started Jul 07 07:07:31 PM PDT 24
Finished Jul 07 07:07:34 PM PDT 24
Peak memory 242196 kb
Host smart-08f3d5b8-727d-42ce-bb97-2779c363b3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829784264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1829784264
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3546329642
Short name T946
Test name
Test status
Simulation time 264586095 ps
CPU time 6.22 seconds
Started Jul 07 07:07:30 PM PDT 24
Finished Jul 07 07:07:37 PM PDT 24
Peak memory 242124 kb
Host smart-ef08855b-b8db-4b29-9600-8ac079470451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546329642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3546329642
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.4209174
Short name T638
Test name
Test status
Simulation time 45043164913 ps
CPU time 1210.77 seconds
Started Jul 07 07:07:28 PM PDT 24
Finished Jul 07 07:27:40 PM PDT 24
Peak memory 262184 kb
Host smart-68f2babd-5601-4247-b6e1-72489fd4d1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209174 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.4209174
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.343782868
Short name T600
Test name
Test status
Simulation time 160700892 ps
CPU time 4.35 seconds
Started Jul 07 07:07:34 PM PDT 24
Finished Jul 07 07:07:39 PM PDT 24
Peak memory 241992 kb
Host smart-b500bed7-493d-48e6-84d3-1904e3b97b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343782868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.343782868
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1977386503
Short name T598
Test name
Test status
Simulation time 2262126209 ps
CPU time 5.75 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:39 PM PDT 24
Peak memory 242276 kb
Host smart-c686c1c4-1edc-4b0f-9fa0-91264a619053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977386503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1977386503
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.40258213
Short name T191
Test name
Test status
Simulation time 742054121 ps
CPU time 11.49 seconds
Started Jul 07 07:07:31 PM PDT 24
Finished Jul 07 07:07:43 PM PDT 24
Peak memory 241828 kb
Host smart-5be0694e-ac85-489a-a71c-b6547489460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40258213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.40258213
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.617620790
Short name T285
Test name
Test status
Simulation time 90063826517 ps
CPU time 1366.79 seconds
Started Jul 07 07:07:32 PM PDT 24
Finished Jul 07 07:30:20 PM PDT 24
Peak memory 273372 kb
Host smart-2336bb67-afb1-4f2e-b222-33fa6d1950ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617620790 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.617620790
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.2092679373
Short name T489
Test name
Test status
Simulation time 274520773 ps
CPU time 4.36 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 242132 kb
Host smart-4f06b0dc-2576-4b60-9eb4-9c51a87900d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092679373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2092679373
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.429386216
Short name T231
Test name
Test status
Simulation time 846679913 ps
CPU time 13.07 seconds
Started Jul 07 07:07:36 PM PDT 24
Finished Jul 07 07:07:49 PM PDT 24
Peak memory 242220 kb
Host smart-7fe21e68-6fc8-40cf-be64-55d88b42b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429386216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.429386216
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.322248113
Short name T394
Test name
Test status
Simulation time 48713372830 ps
CPU time 558.65 seconds
Started Jul 07 07:07:32 PM PDT 24
Finished Jul 07 07:16:52 PM PDT 24
Peak memory 297088 kb
Host smart-71711b0a-8c5e-4f74-b7f1-6bc8316d7e43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322248113 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.322248113
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1606610396
Short name T907
Test name
Test status
Simulation time 112191596 ps
CPU time 3.32 seconds
Started Jul 07 07:07:34 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 242092 kb
Host smart-508b2373-8d3a-4c35-a786-9b94b7c1a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606610396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1606610396
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2725605401
Short name T113
Test name
Test status
Simulation time 507451188 ps
CPU time 14.02 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:47 PM PDT 24
Peak memory 242196 kb
Host smart-265a020a-76ea-4272-9e3e-4e13cd4156f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725605401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2725605401
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.1305871559
Short name T329
Test name
Test status
Simulation time 26080353756 ps
CPU time 575.39 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:17:09 PM PDT 24
Peak memory 272760 kb
Host smart-d74fdc77-0b7c-425c-9ca3-6bead88181ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305871559 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.1305871559
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1400843053
Short name T1000
Test name
Test status
Simulation time 610982260 ps
CPU time 4.68 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 242352 kb
Host smart-2b1492f2-f3e6-42c3-8b5b-dbefac4808a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400843053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1400843053
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.27704335
Short name T228
Test name
Test status
Simulation time 532419028 ps
CPU time 8.15 seconds
Started Jul 07 07:07:36 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 241904 kb
Host smart-57b0cf95-1c52-46e8-b375-844fbc91b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27704335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.27704335
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3222587524
Short name T222
Test name
Test status
Simulation time 396845053635 ps
CPU time 3132.2 seconds
Started Jul 07 07:07:36 PM PDT 24
Finished Jul 07 07:59:49 PM PDT 24
Peak memory 345952 kb
Host smart-c0b119ef-8dd8-4f8e-aa78-7b4a84936918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222587524 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.3222587524
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3989691034
Short name T212
Test name
Test status
Simulation time 296628127 ps
CPU time 4.43 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 241944 kb
Host smart-9e543d33-cfdf-43f8-addd-ad5a2c48660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989691034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3989691034
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.14374203
Short name T10
Test name
Test status
Simulation time 281501496 ps
CPU time 7.27 seconds
Started Jul 07 07:07:33 PM PDT 24
Finished Jul 07 07:07:40 PM PDT 24
Peak memory 242156 kb
Host smart-00de62aa-72c3-46a7-993c-fad9449b9eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14374203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.14374203
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.2346276467
Short name T655
Test name
Test status
Simulation time 54807909 ps
CPU time 1.68 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:04:41 PM PDT 24
Peak memory 240096 kb
Host smart-696aa910-24e9-4e78-b859-203d3f8053b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346276467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2346276467
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.401012950
Short name T532
Test name
Test status
Simulation time 4548830543 ps
CPU time 37.55 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:05:15 PM PDT 24
Peak memory 242604 kb
Host smart-29faeefc-0dfb-4f0e-9447-b381c7755d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401012950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.401012950
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.208097590
Short name T812
Test name
Test status
Simulation time 317336282 ps
CPU time 3.81 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:04:42 PM PDT 24
Peak memory 248776 kb
Host smart-6c120216-b263-4300-9c77-73f2715ef13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208097590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.208097590
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.2414259429
Short name T654
Test name
Test status
Simulation time 4723360508 ps
CPU time 43.33 seconds
Started Jul 07 07:04:35 PM PDT 24
Finished Jul 07 07:05:18 PM PDT 24
Peak memory 250548 kb
Host smart-a0be4c77-cad0-4c5f-88c4-5992ea7383a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414259429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2414259429
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.1564042085
Short name T160
Test name
Test status
Simulation time 420683134 ps
CPU time 9.42 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:44 PM PDT 24
Peak memory 242104 kb
Host smart-6378f5ee-9553-4509-8abf-fa1e476684f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564042085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1564042085
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1559191378
Short name T815
Test name
Test status
Simulation time 180275373 ps
CPU time 4.14 seconds
Started Jul 07 07:04:33 PM PDT 24
Finished Jul 07 07:04:37 PM PDT 24
Peak memory 242460 kb
Host smart-b8449a0f-dd62-4d21-82c8-98a33d0ec6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559191378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1559191378
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1514402088
Short name T964
Test name
Test status
Simulation time 927063849 ps
CPU time 20.82 seconds
Started Jul 07 07:04:36 PM PDT 24
Finished Jul 07 07:04:57 PM PDT 24
Peak memory 242072 kb
Host smart-cf26816e-9995-49f2-996c-a7dc069ccb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514402088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1514402088
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1205091043
Short name T788
Test name
Test status
Simulation time 150936923 ps
CPU time 4.61 seconds
Started Jul 07 07:04:36 PM PDT 24
Finished Jul 07 07:04:41 PM PDT 24
Peak memory 241816 kb
Host smart-dbd6ce1b-99bd-44ed-880f-1218c5e05b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205091043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1205091043
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3003600243
Short name T150
Test name
Test status
Simulation time 283326053 ps
CPU time 5.75 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:40 PM PDT 24
Peak memory 242220 kb
Host smart-801f58e5-7828-4302-bf83-2a95e43f586f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003600243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3003600243
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.803530197
Short name T1096
Test name
Test status
Simulation time 2433648531 ps
CPU time 6.09 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:04:44 PM PDT 24
Peak memory 249060 kb
Host smart-4ff0f2ba-a62d-46d9-ba84-d3cbdb01953f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803530197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.803530197
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.1848893797
Short name T541
Test name
Test status
Simulation time 553883713 ps
CPU time 10.8 seconds
Started Jul 07 07:04:34 PM PDT 24
Finished Jul 07 07:04:45 PM PDT 24
Peak memory 241992 kb
Host smart-9f1d7794-9ab9-43e0-8473-78e98f2d480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848893797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.1848893797
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.2201716817
Short name T884
Test name
Test status
Simulation time 438785240934 ps
CPU time 884.61 seconds
Started Jul 07 07:04:36 PM PDT 24
Finished Jul 07 07:19:21 PM PDT 24
Peak memory 313908 kb
Host smart-e1e57a6a-19dd-45ac-8abf-3c8712e4300b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201716817 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.2201716817
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.530881734
Short name T442
Test name
Test status
Simulation time 1525938351 ps
CPU time 17.47 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:04:55 PM PDT 24
Peak memory 242624 kb
Host smart-836358e1-0209-41d4-b8ce-238d8bdf0542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530881734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.530881734
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1205341332
Short name T760
Test name
Test status
Simulation time 392910699 ps
CPU time 2.99 seconds
Started Jul 07 07:07:34 PM PDT 24
Finished Jul 07 07:07:38 PM PDT 24
Peak memory 242252 kb
Host smart-b16225f7-5d99-4a01-b9d9-08bdfed3e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205341332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1205341332
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.2600575461
Short name T404
Test name
Test status
Simulation time 829560732 ps
CPU time 11.95 seconds
Started Jul 07 07:07:35 PM PDT 24
Finished Jul 07 07:07:47 PM PDT 24
Peak memory 241896 kb
Host smart-46602328-3919-4f50-b52d-9eccbc604c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600575461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2600575461
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2229717915
Short name T725
Test name
Test status
Simulation time 240920145531 ps
CPU time 803.58 seconds
Started Jul 07 07:07:37 PM PDT 24
Finished Jul 07 07:21:01 PM PDT 24
Peak memory 305800 kb
Host smart-5544f43e-e52f-4202-bcee-6dfc7d220da0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229717915 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.2229717915
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2073098217
Short name T247
Test name
Test status
Simulation time 143544276 ps
CPU time 4.33 seconds
Started Jul 07 07:07:38 PM PDT 24
Finished Jul 07 07:07:43 PM PDT 24
Peak memory 241928 kb
Host smart-97d8ed1f-e0e2-4d5d-ad99-474d5f73df07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073098217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2073098217
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.567885479
Short name T674
Test name
Test status
Simulation time 431642683 ps
CPU time 5.43 seconds
Started Jul 07 07:07:38 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 241876 kb
Host smart-546699df-a6de-4a47-a782-92a0bab31e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567885479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.567885479
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.579667050
Short name T244
Test name
Test status
Simulation time 317981293182 ps
CPU time 2048.57 seconds
Started Jul 07 07:07:38 PM PDT 24
Finished Jul 07 07:41:47 PM PDT 24
Peak memory 449548 kb
Host smart-938d6884-8211-4593-b7c1-f5b7ff54fb98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579667050 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.579667050
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1556562353
Short name T1067
Test name
Test status
Simulation time 231337458 ps
CPU time 4.46 seconds
Started Jul 07 07:07:37 PM PDT 24
Finished Jul 07 07:07:42 PM PDT 24
Peak memory 242344 kb
Host smart-d768fbee-81ad-467e-bd87-56dc82e2b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556562353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1556562353
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.2798363260
Short name T1185
Test name
Test status
Simulation time 433027726 ps
CPU time 6.6 seconds
Started Jul 07 07:07:36 PM PDT 24
Finished Jul 07 07:07:43 PM PDT 24
Peak memory 241956 kb
Host smart-21201621-ace1-4e3c-b9db-14fb30c349cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798363260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2798363260
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2981577597
Short name T982
Test name
Test status
Simulation time 38170239096 ps
CPU time 1016.8 seconds
Started Jul 07 07:07:34 PM PDT 24
Finished Jul 07 07:24:31 PM PDT 24
Peak memory 257184 kb
Host smart-3f63be18-79f5-4aed-932a-ca385680104a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981577597 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2981577597
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2562104308
Short name T626
Test name
Test status
Simulation time 138956113 ps
CPU time 4.05 seconds
Started Jul 07 07:07:35 PM PDT 24
Finished Jul 07 07:07:40 PM PDT 24
Peak memory 242168 kb
Host smart-9225a095-2c1c-4d65-b617-5a7613b17903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562104308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2562104308
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3055940550
Short name T587
Test name
Test status
Simulation time 426900610 ps
CPU time 5.61 seconds
Started Jul 07 07:07:38 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 241812 kb
Host smart-4a04a5c2-9e84-4cf2-a58d-1e36861470c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055940550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3055940550
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.4270397701
Short name T875
Test name
Test status
Simulation time 241274703475 ps
CPU time 725.79 seconds
Started Jul 07 07:07:41 PM PDT 24
Finished Jul 07 07:19:47 PM PDT 24
Peak memory 333200 kb
Host smart-d6530aa5-25f1-4a3a-ba0c-031e0d307857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270397701 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.4270397701
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.2981653679
Short name T185
Test name
Test status
Simulation time 1849695187 ps
CPU time 4.73 seconds
Started Jul 07 07:07:42 PM PDT 24
Finished Jul 07 07:07:48 PM PDT 24
Peak memory 242064 kb
Host smart-18654059-c09e-41c8-8831-16fb5132a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981653679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2981653679
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2146363
Short name T70
Test name
Test status
Simulation time 204750883 ps
CPU time 9.75 seconds
Started Jul 07 07:07:40 PM PDT 24
Finished Jul 07 07:07:50 PM PDT 24
Peak memory 241824 kb
Host smart-d39f7e66-5e31-418e-aa7f-8a52b406322e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2146363
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.4055435480
Short name T1047
Test name
Test status
Simulation time 65473790020 ps
CPU time 1638.89 seconds
Started Jul 07 07:07:38 PM PDT 24
Finished Jul 07 07:34:57 PM PDT 24
Peak memory 281668 kb
Host smart-fad5d707-0a58-4c69-a6ae-a39b31d75d58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055435480 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.4055435480
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2023745870
Short name T143
Test name
Test status
Simulation time 209858915 ps
CPU time 3.9 seconds
Started Jul 07 07:07:40 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 242184 kb
Host smart-856e2927-e310-4336-ae6e-b98d9030ac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023745870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2023745870
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.2250300585
Short name T729
Test name
Test status
Simulation time 4494593826 ps
CPU time 23.35 seconds
Started Jul 07 07:07:39 PM PDT 24
Finished Jul 07 07:08:03 PM PDT 24
Peak memory 242420 kb
Host smart-0cc51014-8a99-4cae-9de1-8703a007e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250300585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2250300585
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2719619635
Short name T774
Test name
Test status
Simulation time 13681104851 ps
CPU time 385.16 seconds
Started Jul 07 07:07:42 PM PDT 24
Finished Jul 07 07:14:08 PM PDT 24
Peak memory 248900 kb
Host smart-3b9a6edf-4d99-43db-8a66-898bf25f504e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719619635 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.2719619635
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2363123784
Short name T434
Test name
Test status
Simulation time 177657459 ps
CPU time 3.52 seconds
Started Jul 07 07:07:40 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 242080 kb
Host smart-e7bdd4b3-069d-4005-9855-a3faee386b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363123784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2363123784
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3127053727
Short name T921
Test name
Test status
Simulation time 381422087 ps
CPU time 3.51 seconds
Started Jul 07 07:07:38 PM PDT 24
Finished Jul 07 07:07:42 PM PDT 24
Peak memory 241876 kb
Host smart-a18ec389-998c-4a29-bf22-437c18a55ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127053727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3127053727
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.4163388794
Short name T677
Test name
Test status
Simulation time 488452133 ps
CPU time 4.32 seconds
Started Jul 07 07:07:41 PM PDT 24
Finished Jul 07 07:07:46 PM PDT 24
Peak memory 242156 kb
Host smart-4c63b804-805a-4e2e-bec0-8e4d33c66d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163388794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.4163388794
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.3900644108
Short name T224
Test name
Test status
Simulation time 983421144 ps
CPU time 6.51 seconds
Started Jul 07 07:07:40 PM PDT 24
Finished Jul 07 07:07:47 PM PDT 24
Peak memory 242360 kb
Host smart-3f9a58d9-708c-442f-952d-ecd5010d1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900644108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3900644108
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2692461974
Short name T980
Test name
Test status
Simulation time 219153973855 ps
CPU time 2708.35 seconds
Started Jul 07 07:07:42 PM PDT 24
Finished Jul 07 07:52:52 PM PDT 24
Peak memory 602104 kb
Host smart-631ecc12-5ab0-4c60-b2cd-dfccd5a31db2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692461974 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.2692461974
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.418488217
Short name T1179
Test name
Test status
Simulation time 103725090 ps
CPU time 3.46 seconds
Started Jul 07 07:07:40 PM PDT 24
Finished Jul 07 07:07:44 PM PDT 24
Peak memory 241924 kb
Host smart-8bf08b74-a026-47ea-b5d6-79f86373503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418488217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.418488217
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.638771956
Short name T340
Test name
Test status
Simulation time 253078290 ps
CPU time 6.81 seconds
Started Jul 07 07:07:42 PM PDT 24
Finished Jul 07 07:07:49 PM PDT 24
Peak memory 242380 kb
Host smart-d5263f5c-a78e-4803-8aac-7af499bc4e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638771956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.638771956
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3330119340
Short name T1032
Test name
Test status
Simulation time 186744026 ps
CPU time 3.75 seconds
Started Jul 07 07:07:43 PM PDT 24
Finished Jul 07 07:07:47 PM PDT 24
Peak memory 242084 kb
Host smart-3c7b634e-ac24-4b51-842a-788893955ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330119340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3330119340
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.67608389
Short name T901
Test name
Test status
Simulation time 2557098787 ps
CPU time 9.36 seconds
Started Jul 07 07:07:43 PM PDT 24
Finished Jul 07 07:07:53 PM PDT 24
Peak memory 241808 kb
Host smart-a93483d1-94b6-4379-bbf0-ca1f7e805eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67608389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.67608389
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.2226028190
Short name T689
Test name
Test status
Simulation time 295447216 ps
CPU time 2.09 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:04:45 PM PDT 24
Peak memory 240416 kb
Host smart-8a8adb36-3293-4037-8cb9-5f00dbb2d9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226028190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2226028190
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.2977360743
Short name T973
Test name
Test status
Simulation time 2397874916 ps
CPU time 31.86 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:05:10 PM PDT 24
Peak memory 242148 kb
Host smart-8c657dc2-b587-4267-b2df-ec019346659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977360743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2977360743
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.4204810230
Short name T456
Test name
Test status
Simulation time 1069207163 ps
CPU time 37.72 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:05:18 PM PDT 24
Peak memory 241704 kb
Host smart-382a3d1a-0f4a-4b4f-88d0-edf170da21e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204810230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.4204810230
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.402330321
Short name T1141
Test name
Test status
Simulation time 1350088689 ps
CPU time 16.42 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:04:54 PM PDT 24
Peak memory 242232 kb
Host smart-714f8d14-086a-4fd2-b655-ab9c43822660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402330321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.402330321
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3081072322
Short name T938
Test name
Test status
Simulation time 132162532 ps
CPU time 4.31 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:04:43 PM PDT 24
Peak memory 242332 kb
Host smart-addaa309-6a90-4d6f-a93a-a841145f7dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081072322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3081072322
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2985990301
Short name T182
Test name
Test status
Simulation time 4491507110 ps
CPU time 28.36 seconds
Started Jul 07 07:04:37 PM PDT 24
Finished Jul 07 07:05:06 PM PDT 24
Peak memory 246872 kb
Host smart-d055aebc-d64d-494c-818c-8fca273808d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985990301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2985990301
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.4115965989
Short name T545
Test name
Test status
Simulation time 1199898001 ps
CPU time 35.19 seconds
Started Jul 07 07:04:41 PM PDT 24
Finished Jul 07 07:05:16 PM PDT 24
Peak memory 242752 kb
Host smart-3d857ed6-0c96-4465-b9ed-d51dd6b1a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115965989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.4115965989
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.129043016
Short name T418
Test name
Test status
Simulation time 163728453 ps
CPU time 8.11 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:04:47 PM PDT 24
Peak memory 242116 kb
Host smart-6b978949-227b-48ea-a94f-679759aa7d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129043016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.129043016
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.215975801
Short name T1084
Test name
Test status
Simulation time 1290286946 ps
CPU time 28.84 seconds
Started Jul 07 07:04:36 PM PDT 24
Finished Jul 07 07:05:05 PM PDT 24
Peak memory 242112 kb
Host smart-2657666f-a1c9-4800-b7f4-0eb60c0141f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=215975801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.215975801
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2486725395
Short name T358
Test name
Test status
Simulation time 5951283104 ps
CPU time 20.77 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:05:04 PM PDT 24
Peak memory 242932 kb
Host smart-d2d606a3-4436-4bb3-88d3-5ee9fcf341cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486725395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2486725395
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1260073310
Short name T334
Test name
Test status
Simulation time 625739990 ps
CPU time 5.02 seconds
Started Jul 07 07:04:38 PM PDT 24
Finished Jul 07 07:04:43 PM PDT 24
Peak memory 242040 kb
Host smart-3266553e-185b-4a6a-bd7a-b47bd01fee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260073310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1260073310
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.1914584837
Short name T327
Test name
Test status
Simulation time 12846965883 ps
CPU time 261.46 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:09:03 PM PDT 24
Peak memory 250144 kb
Host smart-89d9ee5f-f3a8-4a50-927e-ceb38b9c471d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914584837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
1914584837
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3050288001
Short name T281
Test name
Test status
Simulation time 113849032779 ps
CPU time 1864.77 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:35:47 PM PDT 24
Peak memory 279000 kb
Host smart-3fc5df87-7058-499e-8f06-e7352982d653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050288001 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3050288001
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2990397113
Short name T515
Test name
Test status
Simulation time 1150830153 ps
CPU time 14.36 seconds
Started Jul 07 07:04:41 PM PDT 24
Finished Jul 07 07:04:56 PM PDT 24
Peak memory 242032 kb
Host smart-a50c89f2-2d69-44e6-af8c-3a01eda5d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990397113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2990397113
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.66876861
Short name T770
Test name
Test status
Simulation time 239030264 ps
CPU time 4.24 seconds
Started Jul 07 07:07:43 PM PDT 24
Finished Jul 07 07:07:48 PM PDT 24
Peak memory 241864 kb
Host smart-466d5a6d-94c1-4903-8f3f-f617b85fd96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66876861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.66876861
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2994597555
Short name T233
Test name
Test status
Simulation time 1302250104 ps
CPU time 19.65 seconds
Started Jul 07 07:07:43 PM PDT 24
Finished Jul 07 07:08:03 PM PDT 24
Peak memory 241868 kb
Host smart-a232adb9-f2a6-43c1-9e61-5472ff9859d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994597555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2994597555
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.2742009239
Short name T180
Test name
Test status
Simulation time 244407930 ps
CPU time 3.89 seconds
Started Jul 07 07:07:45 PM PDT 24
Finished Jul 07 07:07:50 PM PDT 24
Peak memory 242148 kb
Host smart-c3b4def0-fbe2-4b50-b728-4ced6451adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742009239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.2742009239
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2136895619
Short name T791
Test name
Test status
Simulation time 519975248 ps
CPU time 16.11 seconds
Started Jul 07 07:07:42 PM PDT 24
Finished Jul 07 07:07:58 PM PDT 24
Peak memory 242304 kb
Host smart-85c31588-ed03-48c4-8ffd-1310e80c3e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136895619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2136895619
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.1585694016
Short name T177
Test name
Test status
Simulation time 2125121736 ps
CPU time 4.86 seconds
Started Jul 07 07:07:45 PM PDT 24
Finished Jul 07 07:07:50 PM PDT 24
Peak memory 242112 kb
Host smart-e24a67be-849a-4d51-b853-5cd9cb2fb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585694016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.1585694016
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.2218696235
Short name T511
Test name
Test status
Simulation time 175078305 ps
CPU time 6.42 seconds
Started Jul 07 07:07:44 PM PDT 24
Finished Jul 07 07:07:50 PM PDT 24
Peak memory 241836 kb
Host smart-7131da98-daad-474b-bdc3-0c2372dad0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218696235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2218696235
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3479068526
Short name T1133
Test name
Test status
Simulation time 428725771 ps
CPU time 4.59 seconds
Started Jul 07 07:07:43 PM PDT 24
Finished Jul 07 07:07:48 PM PDT 24
Peak memory 241860 kb
Host smart-40217b8a-85b2-43e8-841a-9d4f9cd0c15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479068526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3479068526
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3173282477
Short name T842
Test name
Test status
Simulation time 256272528 ps
CPU time 5.18 seconds
Started Jul 07 07:07:45 PM PDT 24
Finished Jul 07 07:07:51 PM PDT 24
Peak memory 241908 kb
Host smart-8ff298b4-8128-4b5b-ba31-ef289dd2205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173282477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3173282477
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2103751737
Short name T322
Test name
Test status
Simulation time 78725372358 ps
CPU time 1469.65 seconds
Started Jul 07 07:07:46 PM PDT 24
Finished Jul 07 07:32:16 PM PDT 24
Peak memory 288600 kb
Host smart-998c1466-dffb-469d-a5bb-cdff0da2a641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103751737 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.2103751737
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.162833366
Short name T583
Test name
Test status
Simulation time 147069168 ps
CPU time 3.69 seconds
Started Jul 07 07:07:49 PM PDT 24
Finished Jul 07 07:07:53 PM PDT 24
Peak memory 241804 kb
Host smart-cc00baf8-effd-4eba-86c8-2a4f33748ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162833366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.162833366
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.189956048
Short name T1075
Test name
Test status
Simulation time 871952729 ps
CPU time 11.25 seconds
Started Jul 07 07:07:46 PM PDT 24
Finished Jul 07 07:07:58 PM PDT 24
Peak memory 241904 kb
Host smart-ea9fd9b6-0a49-4ebd-8aff-10b5e0e3c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189956048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.189956048
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2258397253
Short name T643
Test name
Test status
Simulation time 50637598405 ps
CPU time 404.4 seconds
Started Jul 07 07:07:47 PM PDT 24
Finished Jul 07 07:14:31 PM PDT 24
Peak memory 261928 kb
Host smart-a142f1b7-514c-4dca-bf6d-221f05542f25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258397253 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2258397253
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3876283768
Short name T147
Test name
Test status
Simulation time 137489714 ps
CPU time 5.55 seconds
Started Jul 07 07:07:46 PM PDT 24
Finished Jul 07 07:07:51 PM PDT 24
Peak memory 241952 kb
Host smart-650824d1-251c-482f-9d42-52d802620a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876283768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3876283768
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2858530347
Short name T771
Test name
Test status
Simulation time 1582145003 ps
CPU time 24.29 seconds
Started Jul 07 07:07:47 PM PDT 24
Finished Jul 07 07:08:11 PM PDT 24
Peak memory 241788 kb
Host smart-2fa5fb29-918f-48b6-af15-24b630d3156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858530347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2858530347
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.971178817
Short name T16
Test name
Test status
Simulation time 20792216254 ps
CPU time 500.49 seconds
Started Jul 07 07:07:47 PM PDT 24
Finished Jul 07 07:16:08 PM PDT 24
Peak memory 294148 kb
Host smart-2a124123-5343-4b14-a28a-44451b567c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971178817 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.971178817
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.1167627397
Short name T663
Test name
Test status
Simulation time 184865406 ps
CPU time 3.13 seconds
Started Jul 07 07:07:45 PM PDT 24
Finished Jul 07 07:07:49 PM PDT 24
Peak memory 242080 kb
Host smart-66cd954e-8dcd-4b82-8ae0-a924db8eb63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167627397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1167627397
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.112166837
Short name T498
Test name
Test status
Simulation time 9401139339 ps
CPU time 19.95 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:08:11 PM PDT 24
Peak memory 241932 kb
Host smart-9e5a6f6a-0674-47c8-814a-b56a8260a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112166837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.112166837
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2354182605
Short name T259
Test name
Test status
Simulation time 1590845879502 ps
CPU time 3921.97 seconds
Started Jul 07 07:07:46 PM PDT 24
Finished Jul 07 08:13:09 PM PDT 24
Peak memory 466288 kb
Host smart-8ea879cb-e8c5-4c11-9bb7-c92f8a0e1863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354182605 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2354182605
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.3599594048
Short name T414
Test name
Test status
Simulation time 111206329 ps
CPU time 4.39 seconds
Started Jul 07 07:07:45 PM PDT 24
Finished Jul 07 07:07:49 PM PDT 24
Peak memory 241840 kb
Host smart-6adbe55e-b13b-4c66-9226-9f61ce9519e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599594048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3599594048
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.711547687
Short name T286
Test name
Test status
Simulation time 172109913692 ps
CPU time 2544.09 seconds
Started Jul 07 07:07:47 PM PDT 24
Finished Jul 07 07:50:11 PM PDT 24
Peak memory 342488 kb
Host smart-c75d0bd8-ebcb-4365-9d5c-2ef8f836ea11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711547687 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.711547687
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.3429948439
Short name T174
Test name
Test status
Simulation time 1852879663 ps
CPU time 5.14 seconds
Started Jul 07 07:07:46 PM PDT 24
Finished Jul 07 07:07:52 PM PDT 24
Peak memory 242260 kb
Host smart-a221ab65-59b2-4933-b330-6d160010839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429948439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3429948439
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1627798312
Short name T255
Test name
Test status
Simulation time 5425570751 ps
CPU time 13.36 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:08:05 PM PDT 24
Peak memory 241884 kb
Host smart-d129e6f3-1223-4e76-b232-856a6612949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627798312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1627798312
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3971409938
Short name T835
Test name
Test status
Simulation time 139730373895 ps
CPU time 262.35 seconds
Started Jul 07 07:07:50 PM PDT 24
Finished Jul 07 07:12:13 PM PDT 24
Peak memory 267304 kb
Host smart-df911383-de06-48b4-85e6-f464c80c936d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971409938 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3971409938
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.488325706
Short name T156
Test name
Test status
Simulation time 150518473 ps
CPU time 3.34 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:07:55 PM PDT 24
Peak memory 241936 kb
Host smart-6453507b-612a-4bac-bea0-22a9378d72dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488325706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.488325706
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.790666467
Short name T998
Test name
Test status
Simulation time 308232423 ps
CPU time 4.15 seconds
Started Jul 07 07:07:50 PM PDT 24
Finished Jul 07 07:07:55 PM PDT 24
Peak memory 241944 kb
Host smart-caa54026-f5b8-4d36-9e0c-b1e59d6c13e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790666467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.790666467
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.2429130597
Short name T798
Test name
Test status
Simulation time 54396485 ps
CPU time 1.77 seconds
Started Jul 07 07:04:41 PM PDT 24
Finished Jul 07 07:04:43 PM PDT 24
Peak memory 240164 kb
Host smart-b910fd52-0f64-4269-b1ac-d45f901efa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429130597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.2429130597
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.4034104760
Short name T586
Test name
Test status
Simulation time 1711886795 ps
CPU time 17.16 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:05:00 PM PDT 24
Peak memory 248756 kb
Host smart-32f3991f-f608-4aaa-952a-8905d7334c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034104760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.4034104760
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.1161226870
Short name T33
Test name
Test status
Simulation time 5518362958 ps
CPU time 34.13 seconds
Started Jul 07 07:04:41 PM PDT 24
Finished Jul 07 07:05:15 PM PDT 24
Peak memory 248888 kb
Host smart-83573897-a84a-4bdf-9266-910e11c5e316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161226870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1161226870
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1492535198
Short name T1023
Test name
Test status
Simulation time 10545173654 ps
CPU time 25.06 seconds
Started Jul 07 07:04:40 PM PDT 24
Finished Jul 07 07:05:05 PM PDT 24
Peak memory 242220 kb
Host smart-ca19f20c-638d-4a07-b5a7-ce8ac2df31ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492535198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1492535198
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1744744671
Short name T889
Test name
Test status
Simulation time 5358770109 ps
CPU time 8.61 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:04:52 PM PDT 24
Peak memory 242664 kb
Host smart-a9288347-db29-4fff-8990-d8fbe5a9dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744744671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1744744671
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2777701431
Short name T824
Test name
Test status
Simulation time 218012788 ps
CPU time 4.43 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:04:46 PM PDT 24
Peak memory 242080 kb
Host smart-494c3a0d-f569-41bc-9997-f618c11d543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777701431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2777701431
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1363495877
Short name T1020
Test name
Test status
Simulation time 223255019 ps
CPU time 6.36 seconds
Started Jul 07 07:04:40 PM PDT 24
Finished Jul 07 07:04:47 PM PDT 24
Peak memory 248688 kb
Host smart-c255ace2-6a40-417d-b514-469373cf352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363495877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1363495877
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.3934300192
Short name T605
Test name
Test status
Simulation time 1383696218 ps
CPU time 11.31 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:04:55 PM PDT 24
Peak memory 242364 kb
Host smart-3235252e-ce3d-4826-a701-a96d6392c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934300192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3934300192
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.847546868
Short name T1178
Test name
Test status
Simulation time 291146751 ps
CPU time 7.1 seconds
Started Jul 07 07:04:40 PM PDT 24
Finished Jul 07 07:04:48 PM PDT 24
Peak memory 241708 kb
Host smart-425de7a5-4090-4f50-b94b-b2cfcd12ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847546868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.847546868
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2810452276
Short name T911
Test name
Test status
Simulation time 1964409234 ps
CPU time 31.46 seconds
Started Jul 07 07:04:39 PM PDT 24
Finished Jul 07 07:05:11 PM PDT 24
Peak memory 241968 kb
Host smart-8870af64-106b-4c61-8e4e-41e8075412ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810452276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2810452276
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.809130686
Short name T805
Test name
Test status
Simulation time 362434091 ps
CPU time 5.99 seconds
Started Jul 07 07:04:40 PM PDT 24
Finished Jul 07 07:04:47 PM PDT 24
Peak memory 241824 kb
Host smart-7468ff5d-f08d-4d19-92ce-d4b10a17df16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809130686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.809130686
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.858235154
Short name T1057
Test name
Test status
Simulation time 745669999 ps
CPU time 5.44 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:04:49 PM PDT 24
Peak memory 241960 kb
Host smart-409824e9-2908-44a1-94c3-a922b8dbc242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858235154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.858235154
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.358024714
Short name T556
Test name
Test status
Simulation time 14608791467 ps
CPU time 37.93 seconds
Started Jul 07 07:04:40 PM PDT 24
Finished Jul 07 07:05:18 PM PDT 24
Peak memory 245496 kb
Host smart-badf8235-b08e-45be-be30-4cf657f02c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358024714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.358024714
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3641865751
Short name T289
Test name
Test status
Simulation time 1371659506406 ps
CPU time 2034.11 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:38:37 PM PDT 24
Peak memory 299112 kb
Host smart-9c85d4ed-ce7f-4a2f-b2b1-ca45536aca21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641865751 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3641865751
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.2229430604
Short name T886
Test name
Test status
Simulation time 522212133 ps
CPU time 18.3 seconds
Started Jul 07 07:04:41 PM PDT 24
Finished Jul 07 07:05:00 PM PDT 24
Peak memory 242752 kb
Host smart-4124e2e0-be12-4bf8-aea4-4b62dc799a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229430604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2229430604
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1379835137
Short name T1175
Test name
Test status
Simulation time 336351363 ps
CPU time 3.51 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:07:55 PM PDT 24
Peak memory 241948 kb
Host smart-a878b10b-8d7f-4b0e-81ff-b3e2153a2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379835137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1379835137
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3496345701
Short name T873
Test name
Test status
Simulation time 475470363 ps
CPU time 6.56 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:07:57 PM PDT 24
Peak memory 241904 kb
Host smart-586e02c8-e449-49f6-a7a7-b2638a5860ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496345701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3496345701
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3301581473
Short name T690
Test name
Test status
Simulation time 197812075800 ps
CPU time 1492.02 seconds
Started Jul 07 07:07:49 PM PDT 24
Finished Jul 07 07:32:42 PM PDT 24
Peak memory 302744 kb
Host smart-79211af3-0fba-49a1-b966-6f960681e6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301581473 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.3301581473
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.776524036
Short name T992
Test name
Test status
Simulation time 141958255 ps
CPU time 4.28 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:07:56 PM PDT 24
Peak memory 241912 kb
Host smart-dce23f6e-1bf7-43e2-8008-d65f6f88c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776524036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.776524036
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3282278588
Short name T885
Test name
Test status
Simulation time 351574450 ps
CPU time 4.89 seconds
Started Jul 07 07:07:51 PM PDT 24
Finished Jul 07 07:07:56 PM PDT 24
Peak memory 241760 kb
Host smart-1438c340-a895-4839-809b-d2f570ad9df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282278588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3282278588
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1523464617
Short name T288
Test name
Test status
Simulation time 224016233273 ps
CPU time 735.62 seconds
Started Jul 07 07:07:52 PM PDT 24
Finished Jul 07 07:20:08 PM PDT 24
Peak memory 277820 kb
Host smart-a140cef2-bcff-4474-aaaa-4ebe3c756afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523464617 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1523464617
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.3307712316
Short name T540
Test name
Test status
Simulation time 146830531 ps
CPU time 4.21 seconds
Started Jul 07 07:07:55 PM PDT 24
Finished Jul 07 07:07:59 PM PDT 24
Peak memory 242164 kb
Host smart-8e0f1a39-fd25-402e-9ff8-c05a43ce1099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307712316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3307712316
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.4164338723
Short name T650
Test name
Test status
Simulation time 257809157 ps
CPU time 7.92 seconds
Started Jul 07 07:07:55 PM PDT 24
Finished Jul 07 07:08:03 PM PDT 24
Peak memory 241868 kb
Host smart-0258aefb-592d-497a-b966-0ba5ee7b4dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164338723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.4164338723
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3726687269
Short name T735
Test name
Test status
Simulation time 346370236049 ps
CPU time 736.79 seconds
Started Jul 07 07:07:54 PM PDT 24
Finished Jul 07 07:20:11 PM PDT 24
Peak memory 323688 kb
Host smart-a5cbfd81-41ee-4cf1-b719-4bff1c8765e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726687269 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3726687269
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3872812775
Short name T751
Test name
Test status
Simulation time 2002921260 ps
CPU time 5.61 seconds
Started Jul 07 07:07:52 PM PDT 24
Finished Jul 07 07:07:58 PM PDT 24
Peak memory 242400 kb
Host smart-3c9a3b7e-8ab0-4a0a-8ca0-a7e0bab58824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872812775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3872812775
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3721437238
Short name T621
Test name
Test status
Simulation time 7414881037 ps
CPU time 22.65 seconds
Started Jul 07 07:07:54 PM PDT 24
Finished Jul 07 07:08:16 PM PDT 24
Peak memory 242288 kb
Host smart-9ae610a2-ca71-453e-af1a-220807b8237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721437238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3721437238
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.797425860
Short name T135
Test name
Test status
Simulation time 333140100 ps
CPU time 4.59 seconds
Started Jul 07 07:07:55 PM PDT 24
Finished Jul 07 07:08:00 PM PDT 24
Peak memory 241912 kb
Host smart-0273f830-8568-4445-9b97-5ead0135290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797425860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.797425860
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3318070080
Short name T226
Test name
Test status
Simulation time 479346274 ps
CPU time 4.93 seconds
Started Jul 07 07:07:54 PM PDT 24
Finished Jul 07 07:07:59 PM PDT 24
Peak memory 242304 kb
Host smart-5f4873b6-404e-4e5e-be32-d7f966b7c438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318070080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3318070080
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1562644793
Short name T133
Test name
Test status
Simulation time 384208836775 ps
CPU time 3617.79 seconds
Started Jul 07 07:07:54 PM PDT 24
Finished Jul 07 08:08:13 PM PDT 24
Peak memory 546016 kb
Host smart-c536787a-c5ae-46d7-b017-a13a7e2f519d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562644793 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.1562644793
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.568611264
Short name T1044
Test name
Test status
Simulation time 263166432 ps
CPU time 3.8 seconds
Started Jul 07 07:07:55 PM PDT 24
Finished Jul 07 07:07:59 PM PDT 24
Peak memory 242068 kb
Host smart-2174927b-6d6b-4c60-a14a-96f1665e5da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568611264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.568611264
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.2470923335
Short name T1160
Test name
Test status
Simulation time 84551598 ps
CPU time 2.97 seconds
Started Jul 07 07:07:54 PM PDT 24
Finished Jul 07 07:07:57 PM PDT 24
Peak memory 241796 kb
Host smart-7a443ba6-9718-4cf9-8633-e6bd1a35864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470923335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2470923335
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4129346069
Short name T332
Test name
Test status
Simulation time 61948884435 ps
CPU time 1040.31 seconds
Started Jul 07 07:07:57 PM PDT 24
Finished Jul 07 07:25:17 PM PDT 24
Peak memory 282812 kb
Host smart-65749d88-1c04-42f3-8f74-2faeab436939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129346069 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.4129346069
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2896703983
Short name T539
Test name
Test status
Simulation time 493342076 ps
CPU time 5.9 seconds
Started Jul 07 07:07:57 PM PDT 24
Finished Jul 07 07:08:03 PM PDT 24
Peak memory 242084 kb
Host smart-1c1dc2db-da85-4b23-9dc3-6a88b689aed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896703983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2896703983
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2635888116
Short name T129
Test name
Test status
Simulation time 569242814 ps
CPU time 16.51 seconds
Started Jul 07 07:07:59 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 241956 kb
Host smart-2898fca5-a11d-433b-b4da-e06ff4661916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635888116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2635888116
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3901871422
Short name T72
Test name
Test status
Simulation time 171963151 ps
CPU time 3.28 seconds
Started Jul 07 07:07:57 PM PDT 24
Finished Jul 07 07:08:01 PM PDT 24
Peak memory 242380 kb
Host smart-5fcab0b3-e393-47b7-ace1-53173a64aa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901871422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3901871422
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.2276790371
Short name T1073
Test name
Test status
Simulation time 3103353889 ps
CPU time 20.14 seconds
Started Jul 07 07:07:59 PM PDT 24
Finished Jul 07 07:08:19 PM PDT 24
Peak memory 248624 kb
Host smart-bebcb556-ea68-46c3-8eab-9349db749acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276790371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2276790371
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2916363307
Short name T838
Test name
Test status
Simulation time 304577776081 ps
CPU time 2725.82 seconds
Started Jul 07 07:07:57 PM PDT 24
Finished Jul 07 07:53:24 PM PDT 24
Peak memory 338776 kb
Host smart-fee2aca9-8c26-4095-80d6-5fb946510e10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916363307 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.2916363307
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.2409734092
Short name T171
Test name
Test status
Simulation time 322744934 ps
CPU time 5.01 seconds
Started Jul 07 07:07:57 PM PDT 24
Finished Jul 07 07:08:03 PM PDT 24
Peak memory 242248 kb
Host smart-c5fad368-a405-42ca-9d65-495c90ccab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409734092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2409734092
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3119914260
Short name T192
Test name
Test status
Simulation time 4758150637 ps
CPU time 13.04 seconds
Started Jul 07 07:07:56 PM PDT 24
Finished Jul 07 07:08:09 PM PDT 24
Peak memory 242412 kb
Host smart-cbe65f82-e612-4ac8-a83a-bd86cbf9af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119914260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3119914260
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3354997025
Short name T67
Test name
Test status
Simulation time 76692576083 ps
CPU time 1633.02 seconds
Started Jul 07 07:08:01 PM PDT 24
Finished Jul 07 07:35:15 PM PDT 24
Peak memory 315336 kb
Host smart-de3bc7a8-2289-4598-8cbe-de8f75051cbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354997025 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3354997025
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3623890822
Short name T719
Test name
Test status
Simulation time 230685752 ps
CPU time 4.47 seconds
Started Jul 07 07:08:01 PM PDT 24
Finished Jul 07 07:08:05 PM PDT 24
Peak memory 241932 kb
Host smart-b024f7a4-759b-4f77-945b-3000ea10f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623890822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3623890822
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.2913069759
Short name T988
Test name
Test status
Simulation time 635432135 ps
CPU time 17.69 seconds
Started Jul 07 07:08:02 PM PDT 24
Finished Jul 07 07:08:20 PM PDT 24
Peak memory 241784 kb
Host smart-9185f025-9033-42e0-b0e1-bd7b60e17a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913069759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2913069759
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3866715090
Short name T342
Test name
Test status
Simulation time 133148849310 ps
CPU time 1053.24 seconds
Started Jul 07 07:08:03 PM PDT 24
Finished Jul 07 07:25:36 PM PDT 24
Peak memory 298088 kb
Host smart-d72d8690-864f-454e-953d-1bd98f4c3429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866715090 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3866715090
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3393892420
Short name T1131
Test name
Test status
Simulation time 204765884 ps
CPU time 1.74 seconds
Started Jul 07 07:04:45 PM PDT 24
Finished Jul 07 07:04:47 PM PDT 24
Peak memory 240384 kb
Host smart-f76166e6-cb63-472b-bef3-fac495767ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393892420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3393892420
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.3759169571
Short name T101
Test name
Test status
Simulation time 2594880189 ps
CPU time 16.33 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:05:00 PM PDT 24
Peak memory 243124 kb
Host smart-92fa624a-2be5-481e-9d58-0217a3bd9a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759169571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3759169571
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.1444567966
Short name T249
Test name
Test status
Simulation time 179920406 ps
CPU time 4.17 seconds
Started Jul 07 07:04:44 PM PDT 24
Finished Jul 07 07:04:48 PM PDT 24
Peak memory 242152 kb
Host smart-7c649309-f8cb-4258-9387-a3f13892fa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444567966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1444567966
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.956868862
Short name T800
Test name
Test status
Simulation time 1606706569 ps
CPU time 36.73 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:05:19 PM PDT 24
Peak memory 242164 kb
Host smart-515c98b3-d74e-4331-9218-6707d177125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956868862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.956868862
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2198098394
Short name T590
Test name
Test status
Simulation time 19559487869 ps
CPU time 28.93 seconds
Started Jul 07 07:04:40 PM PDT 24
Finished Jul 07 07:05:10 PM PDT 24
Peak memory 242952 kb
Host smart-075a714c-0e36-4a53-974d-c5ca3e7f095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198098394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2198098394
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.509703937
Short name T708
Test name
Test status
Simulation time 1904276918 ps
CPU time 8.04 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:04:50 PM PDT 24
Peak memory 242088 kb
Host smart-c607d1ad-6163-4ea5-b919-5f758ca229e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509703937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.509703937
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.3948803187
Short name T944
Test name
Test status
Simulation time 8349236108 ps
CPU time 33.91 seconds
Started Jul 07 07:04:45 PM PDT 24
Finished Jul 07 07:05:19 PM PDT 24
Peak memory 243252 kb
Host smart-8a1144e7-e4ac-4308-9da2-2ff4fefadb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948803187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3948803187
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1284668760
Short name T878
Test name
Test status
Simulation time 204781288 ps
CPU time 3.2 seconds
Started Jul 07 07:04:42 PM PDT 24
Finished Jul 07 07:04:46 PM PDT 24
Peak memory 242328 kb
Host smart-8364905f-1695-4f04-ae99-9246d3533af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284668760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1284668760
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2689288841
Short name T159
Test name
Test status
Simulation time 1113795639 ps
CPU time 20.79 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:05:05 PM PDT 24
Peak memory 248740 kb
Host smart-ef8e496c-5e49-411a-af19-ed64c6a4bf3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2689288841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2689288841
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.4076372981
Short name T480
Test name
Test status
Simulation time 4119121418 ps
CPU time 13.24 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:04:57 PM PDT 24
Peak memory 242140 kb
Host smart-7ad9cf9a-9888-44f5-8e72-296bc7fb814a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076372981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.4076372981
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.847533425
Short name T1031
Test name
Test status
Simulation time 5981047297 ps
CPU time 134.31 seconds
Started Jul 07 07:04:44 PM PDT 24
Finished Jul 07 07:06:59 PM PDT 24
Peak memory 247352 kb
Host smart-62cc80c9-be79-46e3-8bd0-137131cfa0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847533425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.847533425
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.4064195670
Short name T544
Test name
Test status
Simulation time 530587214 ps
CPU time 11.68 seconds
Started Jul 07 07:04:43 PM PDT 24
Finished Jul 07 07:04:56 PM PDT 24
Peak memory 248772 kb
Host smart-91bb1bd2-8a5e-4dac-b567-1d94c0af36e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064195670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.4064195670
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.1670074887
Short name T553
Test name
Test status
Simulation time 185265922 ps
CPU time 3.24 seconds
Started Jul 07 07:08:03 PM PDT 24
Finished Jul 07 07:08:06 PM PDT 24
Peak memory 242320 kb
Host smart-af923f1e-36e7-4636-a6f1-02e3f5075cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670074887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1670074887
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3948343845
Short name T882
Test name
Test status
Simulation time 211697729 ps
CPU time 5.44 seconds
Started Jul 07 07:08:01 PM PDT 24
Finished Jul 07 07:08:07 PM PDT 24
Peak memory 241808 kb
Host smart-4adbddfb-653c-4ba9-91cf-740f4db30002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948343845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3948343845
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3242352543
Short name T572
Test name
Test status
Simulation time 101551235 ps
CPU time 3.78 seconds
Started Jul 07 07:08:01 PM PDT 24
Finished Jul 07 07:08:05 PM PDT 24
Peak memory 242152 kb
Host smart-34246648-58cc-46fc-bf1c-de893be218d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242352543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3242352543
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3566596347
Short name T256
Test name
Test status
Simulation time 543768316 ps
CPU time 6.24 seconds
Started Jul 07 07:08:00 PM PDT 24
Finished Jul 07 07:08:06 PM PDT 24
Peak memory 242068 kb
Host smart-c8205954-7dae-43b9-8420-b7f334c0fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566596347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3566596347
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.787242638
Short name T328
Test name
Test status
Simulation time 37973587955 ps
CPU time 894.62 seconds
Started Jul 07 07:08:02 PM PDT 24
Finished Jul 07 07:22:57 PM PDT 24
Peak memory 257080 kb
Host smart-de685c70-710f-42c0-8208-a253bf719dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787242638 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.787242638
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.3662211986
Short name T1081
Test name
Test status
Simulation time 490023777 ps
CPU time 4.13 seconds
Started Jul 07 07:08:06 PM PDT 24
Finished Jul 07 07:08:10 PM PDT 24
Peak memory 242052 kb
Host smart-560aed71-caf3-4084-b8a2-45832daad093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662211986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3662211986
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1430271224
Short name T870
Test name
Test status
Simulation time 2013008740 ps
CPU time 7.31 seconds
Started Jul 07 07:08:07 PM PDT 24
Finished Jul 07 07:08:14 PM PDT 24
Peak memory 241884 kb
Host smart-b75aa85e-636a-47db-8236-e9db272764b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430271224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1430271224
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3479343957
Short name T841
Test name
Test status
Simulation time 536809014 ps
CPU time 3.98 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 242072 kb
Host smart-2c084218-bef9-4cdb-a8ed-a2d6f0aa6bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479343957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3479343957
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2494148112
Short name T763
Test name
Test status
Simulation time 552760420 ps
CPU time 4.55 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:08:16 PM PDT 24
Peak memory 241772 kb
Host smart-49df0641-c511-47a0-be07-52f65331c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494148112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2494148112
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1534620380
Short name T955
Test name
Test status
Simulation time 559373865201 ps
CPU time 1675.57 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:36:07 PM PDT 24
Peak memory 250312 kb
Host smart-9cabe86e-dcdd-4e36-a210-55f7ed409b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534620380 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1534620380
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.978004530
Short name T913
Test name
Test status
Simulation time 411570028 ps
CPU time 4.24 seconds
Started Jul 07 07:08:06 PM PDT 24
Finished Jul 07 07:08:10 PM PDT 24
Peak memory 242128 kb
Host smart-45c594db-549c-4f0f-8f91-346af3474d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978004530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.978004530
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.82790306
Short name T266
Test name
Test status
Simulation time 1473061822 ps
CPU time 19.47 seconds
Started Jul 07 07:08:03 PM PDT 24
Finished Jul 07 07:08:23 PM PDT 24
Peak memory 241752 kb
Host smart-f1289bff-6a94-40e7-9c85-ad07ac1663ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82790306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.82790306
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.4111742774
Short name T1145
Test name
Test status
Simulation time 413124659 ps
CPU time 4.65 seconds
Started Jul 07 07:08:06 PM PDT 24
Finished Jul 07 07:08:11 PM PDT 24
Peak memory 241948 kb
Host smart-6802906b-096b-4627-ae7a-0d2958ed9ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111742774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4111742774
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.442536950
Short name T852
Test name
Test status
Simulation time 546437030 ps
CPU time 4.25 seconds
Started Jul 07 07:08:05 PM PDT 24
Finished Jul 07 07:08:09 PM PDT 24
Peak memory 241964 kb
Host smart-dd3597ea-05ab-4f7d-ab81-e8112c1bab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442536950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.442536950
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1987458946
Short name T648
Test name
Test status
Simulation time 483840201736 ps
CPU time 1636.56 seconds
Started Jul 07 07:08:07 PM PDT 24
Finished Jul 07 07:35:24 PM PDT 24
Peak memory 447636 kb
Host smart-4b237e61-c781-487f-8606-ad405c6b58cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987458946 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1987458946
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.3329792589
Short name T459
Test name
Test status
Simulation time 370417468 ps
CPU time 4.19 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:08:16 PM PDT 24
Peak memory 242032 kb
Host smart-105178e5-3c17-46f9-b9b7-0ab41d7fe975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329792589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3329792589
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3842048119
Short name T106
Test name
Test status
Simulation time 1004424404 ps
CPU time 15.94 seconds
Started Jul 07 07:08:12 PM PDT 24
Finished Jul 07 07:08:28 PM PDT 24
Peak memory 242012 kb
Host smart-24d3e155-477d-479c-ad43-0c60c8b3dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842048119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3842048119
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1102166221
Short name T1063
Test name
Test status
Simulation time 51647210246 ps
CPU time 852.12 seconds
Started Jul 07 07:08:10 PM PDT 24
Finished Jul 07 07:22:22 PM PDT 24
Peak memory 431028 kb
Host smart-24a1e868-ebb2-49f0-9d9d-6430093441a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102166221 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.1102166221
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.1932513096
Short name T607
Test name
Test status
Simulation time 179660043 ps
CPU time 3.46 seconds
Started Jul 07 07:08:12 PM PDT 24
Finished Jul 07 07:08:15 PM PDT 24
Peak memory 241896 kb
Host smart-0292d552-08d5-4686-9352-a3f406305a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932513096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1932513096
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.3514128409
Short name T339
Test name
Test status
Simulation time 459512769 ps
CPU time 3.94 seconds
Started Jul 07 07:08:10 PM PDT 24
Finished Jul 07 07:08:14 PM PDT 24
Peak memory 242284 kb
Host smart-5f9f3c6f-89a1-4c44-bb41-922342bbc573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514128409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3514128409
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1085996254
Short name T291
Test name
Test status
Simulation time 14999057967 ps
CPU time 387.91 seconds
Started Jul 07 07:08:10 PM PDT 24
Finished Jul 07 07:14:38 PM PDT 24
Peak memory 298652 kb
Host smart-c7d6446f-c50c-4ccb-8bb0-782e486fe556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085996254 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.1085996254
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.1771869221
Short name T497
Test name
Test status
Simulation time 435172184 ps
CPU time 4.25 seconds
Started Jul 07 07:08:12 PM PDT 24
Finished Jul 07 07:08:16 PM PDT 24
Peak memory 242088 kb
Host smart-0094205a-d46f-45b9-b03e-4662ae09915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771869221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1771869221
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3411478086
Short name T1105
Test name
Test status
Simulation time 1775925649 ps
CPU time 28.34 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:08:40 PM PDT 24
Peak memory 242372 kb
Host smart-b917fa5e-c4db-4da4-a222-e51255006999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411478086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3411478086
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2700161443
Short name T1012
Test name
Test status
Simulation time 320308137 ps
CPU time 4.84 seconds
Started Jul 07 07:08:13 PM PDT 24
Finished Jul 07 07:08:18 PM PDT 24
Peak memory 241968 kb
Host smart-46ce70bc-63e6-48f1-91d2-733b677530d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700161443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2700161443
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3601017656
Short name T518
Test name
Test status
Simulation time 634679376 ps
CPU time 16.96 seconds
Started Jul 07 07:08:11 PM PDT 24
Finished Jul 07 07:08:28 PM PDT 24
Peak memory 241964 kb
Host smart-44e2a870-c296-4432-91c3-3b152459d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601017656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3601017656
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1213081572
Short name T22
Test name
Test status
Simulation time 189690517773 ps
CPU time 2752.8 seconds
Started Jul 07 07:08:12 PM PDT 24
Finished Jul 07 07:54:05 PM PDT 24
Peak memory 633148 kb
Host smart-0aba4d1c-3a77-40af-8d50-f8380144123f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213081572 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1213081572
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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