Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
lc_esc_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_esc_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_esc_during_lc_otp_prog_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_esc_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 350 1 T6 2 T5 2 T174 2
auto[1] 32 1 T13 2 T263 1 T239 2



Summary for Variable lc_esc_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329 1 T6 2 T5 2 T174 2
auto[1] 53 1 T131 1 T265 1 T133 1



Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 339 1 T6 2 T5 2 T174 2
auto[1] 43 1 T407 1 T131 1 T142 1



Summary for Variable lc_esc_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331 1 T6 1 T5 2 T174 1
auto[1] 51 1 T6 1 T174 1 T219 1



Summary for Variable lc_esc_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29 1 T239 1 T408 1 T81 1
auto[1] 353 1 T6 2 T5 2 T174 2



Summary for Variable lc_esc_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 352 1 T6 2 T5 2 T174 2
auto[1] 30 1 T245 1 T136 2 T237 2



Summary for Variable lc_esc_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 351 1 T6 2 T5 2 T174 2
auto[1] 31 1 T245 1 T136 2 T237 2

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