Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_0_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_0_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_0_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_0_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12741 1 T3 4 T4 35 T5 24
auto[1] 953 1 T4 11 T65 13 T107 2



Summary for Variable sram_0_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12674 1 T3 4 T4 36 T5 24
auto[1] 1020 1 T4 10 T65 13 T100 1



Summary for Variable sram_0_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_0_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13668 1 T3 4 T4 46 T5 24
lc_esc_on 26 1 T245 1 T137 1 T132 1



Summary for Variable sram_0_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12687 1 T3 4 T4 40 T5 24
auto[1] 1007 1 T4 6 T65 12 T100 2



Summary for Variable sram_0_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2127 1 T4 6 T31 2 T65 12
auto[1] 11567 1 T3 4 T4 40 T5 24



Summary for Variable sram_0_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11632 1 T3 4 T4 46 T5 12
auto[1] 2062 1 T5 12 T11 2 T16 3

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