Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
dai_access_cmd 3 0 3 100.00 100 1 1 0
lc_creator_seed_sw_rw_en 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_access_secret2 6 0 6 100.00 100 1 1 0


Summary for Variable dai_access_cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for dai_access_cmd

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
dai_digest 2326 1 T2 1 T4 4 T5 6
dai_wr 4134 1 T1 3 T4 4 T5 5
dai_rd 6996 1 T1 2 T4 9 T5 8



Summary for Variable lc_creator_seed_sw_rw_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6057 1 T4 2 T5 6 T16 3
auto[1] 7399 1 T1 5 T2 1 T4 15



Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for dai_access_secret2

Bins
lc_creator_seed_sw_rw_endai_access_cmdCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] dai_digest 1272 1 T4 1 T5 2 T16 1
auto[0] dai_wr 1503 1 T5 1 T38 1 T152 2
auto[0] dai_rd 3282 1 T4 1 T5 3 T16 2
auto[1] dai_digest 1054 1 T2 1 T4 3 T5 4
auto[1] dai_wr 2631 1 T1 3 T4 4 T5 4
auto[1] dai_rd 3714 1 T1 2 T4 8 T5 5

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