Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	42155	1			T1	168		T3	106		T6	30
access_err	61669	1			T1	6		T4	80		T5	27
write_blank_err	394	1			T7	1		T8	2		T14	3
ecc_uncorr_err	64647	1			T11	177		T7	402		T8	573
ecc_corr_err	1323	1			T11	1		T76	29		T8	1
no_err	90581	1			T1	51		T2	62		T6	3

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	704	1			T7	8		T8	3		T14	26
secret2	21374	1			T1	7		T2	1		T4	19
secret1	29225	1			T1	2		T6	2		T4	22
secret0	33814	1			T1	171		T2	4		T4	8
hw_cfg1	36408	1			T1	5		T2	3		T4	15
hw_cfg0	26382	1			T1	4		T2	9		T4	7
rot_creator_auth_state	20425	1			T1	10		T2	7		T9	398
rot_creator_auth_codesign	20964	1			T1	8		T2	9		T4	9
owner_sw_cfg	20561	1			T1	1		T2	9		T6	31
creator_sw_cfg	19999	1			T1	9		T2	12		T4	15
vendor_test	30913	1			T1	8		T2	8		T3	106

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2430	1			T152	244		T131	24		T136	302
fsm_err	secret1	2763	1			T342	23		T343	373		T344	72
fsm_err	secret0	5332	1			T1	168		T147	23		T245	71
fsm_err	hw_cfg1	1960	1			T174	149		T131	100		T345	108
fsm_err	hw_cfg0	3793	1			T143	8		T346	3		T347	143
fsm_err	rot_creator_auth_state	2804	1			T9	398		T348	414		T238	44
fsm_err	rot_creator_auth_codesign	2584	1			T8	259		T237	206		T172	7
fsm_err	owner_sw_cfg	3353	1			T6	30		T219	380		T157	2
fsm_err	creator_sw_cfg	3978	1			T13	109		T225	162		T349	346
fsm_err	vendor_test	13158	1			T3	106		T76	216		T83	280
access_err	life_cycle	704	1			T7	8		T8	3		T14	26
access_err	secret2	10826	1			T4	14		T5	9		T16	11
access_err	secret1	5740	1			T4	15		T5	2		T38	1
access_err	secret0	4770	1			T4	8		T5	1		T16	22
access_err	hw_cfg1	1287	1			T4	5		T11	2		T16	1
access_err	hw_cfg0	2198	1			T4	2		T16	3		T65	22
access_err	rot_creator_auth_state	5948	1			T1	2		T4	1		T5	1
access_err	rot_creator_auth_codesign	8071	1			T1	2		T4	2		T5	6
access_err	owner_sw_cfg	7113	1			T4	17		T5	1		T16	8
access_err	creator_sw_cfg	7352	1			T1	2		T4	6		T5	5
access_err	vendor_test	7660	1			T4	10		T5	2		T11	4
write_blank_err	secret2	8	1			T144	1		T350	1		T351	1
write_blank_err	secret1	27	1			T228	1		T225	1		T226	1
write_blank_err	secret0	39	1			T160	2		T161	1		T194	1
write_blank_err	hw_cfg1	74	1			T7	1		T8	1		T158	1
write_blank_err	hw_cfg0	24	1			T8	1		T14	1		T161	1
write_blank_err	rot_creator_auth_state	113	1			T14	2		T160	4		T161	1
write_blank_err	rot_creator_auth_codesign	56	1			T158	1		T137	1		T226	4
write_blank_err	owner_sw_cfg	22	1			T160	1		T161	2		T352	1
write_blank_err	creator_sw_cfg	11	1			T161	1		T353	1		T354	1
write_blank_err	vendor_test	20	1			T137	1		T352	1		T355	1
ecc_uncorr_err	secret2	2901	1			T144	236		T356	67		T357	29
ecc_uncorr_err	secret1	11346	1			T157	9		T159	36		T228	164
ecc_uncorr_err	secret0	15068	1			T159	41		T161	64		T194	558
ecc_uncorr_err	hw_cfg1	22011	1			T7	402		T8	573		T157	8
ecc_uncorr_err	hw_cfg0	7964	1			T11	54		T14	579		T358	211
ecc_uncorr_err	rot_creator_auth_state	3106	1			T160	279		T359	28		T212	130
ecc_uncorr_err	rot_creator_auth_codesign	1270	1			T158	663		T356	102		T360	47
ecc_uncorr_err	owner_sw_cfg	576	1			T11	63		T359	32		T212	65
ecc_uncorr_err	creator_sw_cfg	405	1			T11	60		T157	5		T176	5
ecc_corr_err	secret2	85	1			T76	7		T157	1		T83	2
ecc_corr_err	secret1	141	1			T76	9		T54	18		T39	1
ecc_corr_err	secret0	118	1			T76	3		T83	2		T62	2
ecc_corr_err	hw_cfg1	275	1			T76	1		T83	4		T62	2
ecc_corr_err	hw_cfg0	230	1			T76	5		T8	1		T157	2
ecc_corr_err	rot_creator_auth_state	113	1			T76	4		T157	2		T83	1
ecc_corr_err	rot_creator_auth_codesign	121	1			T83	4		T62	8		T54	5
ecc_corr_err	owner_sw_cfg	119	1			T83	6		T62	1		T159	1
ecc_corr_err	creator_sw_cfg	121	1			T11	1		T62	2		T54	2
no_err	secret2	5124	1			T1	7		T2	1		T4	5
no_err	secret1	9208	1			T1	2		T6	2		T4	7
no_err	secret0	8487	1			T1	3		T2	4		T5	3
no_err	hw_cfg1	10801	1			T1	5		T2	3		T4	10
no_err	hw_cfg0	12173	1			T1	4		T2	9		T4	5
no_err	rot_creator_auth_state	8341	1			T1	8		T2	7		T4	15
no_err	rot_creator_auth_codesign	8862	1			T1	6		T2	9		T4	7
no_err	owner_sw_cfg	9378	1			T1	1		T2	9		T6	1
no_err	creator_sw_cfg	8132	1			T1	7		T2	12		T4	9
no_err	vendor_test	10075	1			T1	8		T2	8		T4	13

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded