| | | | | | |
tb.dut.core_tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 467393296 | 49532771 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 467392391 | 6636791 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 467393296 | 5503664 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 467393296 | 9004838 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 467392391 | 6943067 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 467393296 | 62318162 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 467393296 | 51949158 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 467393296 | 62318162 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 467393296 | 51949158 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 467393296 | 51949158 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 467393296 | 51949158 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 467392391 | 4808040 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 467392391 | 4947115 | 0 | 0 |
|
tb.dut.core_tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 1318 | 1318 | 0 | 0 |
|
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.AccessKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.DigestKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.EccErrorState_A
| 0 | 0 | 464535028 | 5377 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.ErrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.FsmStateKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitDoneKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A
| 0 | 0 | 464535028 | 103396698 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A
| 0 | 0 | 464535028 | 103396698 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A
| 0 | 0 | 464535028 | 198501243 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulGntKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A
| 0 | 0 | 464535028 | 7878 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A
| 0 | 0 | 464535028 | 2419104 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A
| 0 | 0 | 464535028 | 27867801 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.AccessKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.CnstyChkAckKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DigestKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DigestOffsetMustBeRepresentable_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ErrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitDoneKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitReadLocksPartition_A
| 0 | 0 | 464535028 | 110519188 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitWriteLocksPartition_A
| 0 | 0 | 464535028 | 110519188 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.IntegChkAckKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OffsetMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpAddrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpErrorState_A
| 0 | 0 | 464535028 | 10 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpPartBufSize_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpSizeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpWdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ReadLockPropagation_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblDataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblModeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblMtxReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblSelKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblValidKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.SizeMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.WriteLockPropagation_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs.AssertConnected_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.AccessKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.DigestKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.EccErrorState_A
| 0 | 0 | 464535028 | 9156 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.ErrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.FsmStateKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitDoneKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A
| 0 | 0 | 464535028 | 103578622 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A
| 0 | 0 | 464535028 | 103578622 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpErrorState_A
| 0 | 0 | 464535028 | 73 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A
| 0 | 0 | 464535028 | 203920815 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulGntKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A
| 0 | 0 | 464535028 | 8308 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A
| 0 | 0 | 464535028 | 2508397 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A
| 0 | 0 | 464535028 | 29869548 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.AccessKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.DigestKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.EccErrorState_A
| 0 | 0 | 464535028 | 6518 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.ErrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.FsmStateKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.InitDoneKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A
| 0 | 0 | 464535028 | 103759363 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A
| 0 | 0 | 464535028 | 103759363 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpErrorState_A
| 0 | 0 | 464535028 | 56 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A
| 0 | 0 | 464535028 | 198556090 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulGntKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A
| 0 | 0 | 464535028 | 8682 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A
| 0 | 0 | 464535028 | 1418321 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A
| 0 | 0 | 464535028 | 17738157 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.AccessKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.DigestKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.EccErrorState_A
| 0 | 0 | 464535028 | 9579 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.ErrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.FsmStateKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.InitDoneKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A
| 0 | 0 | 464535028 | 103939182 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A
| 0 | 0 | 464535028 | 103939182 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpErrorState_A
| 0 | 0 | 464535028 | 30 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A
| 0 | 0 | 464535028 | 203145629 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulGntKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A
| 0 | 0 | 464535028 | 8424 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A
| 0 | 0 | 464535028 | 2526113 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A
| 0 | 0 | 464535028 | 28929043 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A
| 0 | 0 | 464535028 | 50 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.AccessKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.DigestKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.ErrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.FsmStateKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.InitDoneKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A
| 0 | 0 | 464535028 | 104118339 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A
| 0 | 0 | 464535028 | 104118339 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpErrorState_A
| 0 | 0 | 464535028 | 33 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpReqKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A
| 0 | 0 | 464535028 | 196537497 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A
| 0 | 0 | 1143 | 1143 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulGntKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A
| 0 | 0 | 464535028 | 8137 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A
| 0 | 0 | 464535028 | 1156502 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A
| 0 | 0 | 464535028 | 13447281 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A
| 0 | 0 | 464535028 | 463675205 | 0 | 0 |
|