Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv


Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
sram_1_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_1_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_1_req_during_sram_0_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_1_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12661 1 T1 14 T2 2 T4 4
auto[1] 673 1 T96 1 T92 14 T19 14


Summary for Variable sram_1_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12689 1 T1 14 T2 2 T4 4
auto[1] 645 1 T175 1 T92 26 T19 18


Summary for Variable sram_1_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_1_req_during_lc_esc

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
lc_esc_off 13302 1 T1 14 T2 2 T4 4
lc_esc_on 32 1 T168 1 T95 1 T307 1


Summary for Variable sram_1_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otbn_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12763 1 T1 14 T2 2 T4 4
auto[1] 571 1 T92 8 T19 10 T100 6


Summary for Variable sram_1_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otp_idle

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2086 1 T2 1 T12 4 T96 4
auto[1] 11248 1 T1 14 T2 1 T4 4


Summary for Variable sram_1_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 13213 1 T1 14 T2 2 T4 4
auto[1] 121 1 T95 1 T195 1 T17 1