Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
dai_access_cmd 3 0 3 100.00 100 1 1 0
lc_creator_seed_sw_rw_en 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_access_secret2 6 0 6 100.00 100 1 1 0


Summary for Variable dai_access_cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for dai_access_cmd

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
dai_digest 2305 1 T1 5 T4 1 T10 1
dai_wr 4179 1 T1 6 T2 3 T9 3
dai_rd 7305 1 T1 20 T2 1 T4 2



Summary for Variable lc_creator_seed_sw_rw_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6199 1 T1 12 T5 5 T11 2
auto[1] 7590 1 T1 19 T2 4 T4 3



Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for dai_access_secret2

Bins
lc_creator_seed_sw_rw_endai_access_cmdCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] dai_digest 1261 1 T1 2 T5 1 T11 1
auto[0] dai_wr 1527 1 T1 3 T5 2 T11 1
auto[0] dai_rd 3411 1 T1 7 T5 2 T12 1
auto[1] dai_digest 1044 1 T1 3 T4 1 T10 1
auto[1] dai_wr 2652 1 T1 3 T2 3 T9 3
auto[1] dai_rd 3894 1 T1 13 T2 1 T4 2

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