SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 54443 | 1 | T2 | 102 | T5 | 59 | T11 | 30 | ||||
access_err | 64007 | 1 | T1 | 255 | T2 | 6 | T4 | 4 | ||||
write_blank_err | 465 | 1 | T6 | 1 | T8 | 1 | T14 | 10 | ||||
ecc_uncorr_err | 74658 | 1 | T6 | 53 | T8 | 268 | T14 | 569 | ||||
ecc_corr_err | 1349 | 1 | T5 | 29 | T11 | 6 | T107 | 3 | ||||
no_err | 92827 | 1 | T1 | 235 | T2 | 36 | T4 | 42 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 838 | 1 | T8 | 4 | T14 | 21 | T15 | 15 | ||||
secret2 | 28596 | 1 | T1 | 46 | T2 | 8 | T4 | 3 | ||||
secret1 | 30250 | 1 | T1 | 49 | T2 | 2 | T4 | 8 | ||||
secret0 | 34271 | 1 | T1 | 42 | T2 | 3 | T4 | 10 | ||||
hw_cfg1 | 41871 | 1 | T1 | 35 | T2 | 4 | T4 | 5 | ||||
hw_cfg0 | 26775 | 1 | T1 | 39 | T2 | 2 | T4 | 4 | ||||
rot_creator_auth_state | 23200 | 1 | T1 | 41 | T2 | 2 | T4 | 4 | ||||
rot_creator_auth_codesign | 22186 | 1 | T1 | 55 | T2 | 4 | T4 | 2 | ||||
owner_sw_cfg | 24120 | 1 | T1 | 55 | T2 | 7 | T4 | 3 | ||||
creator_sw_cfg | 22373 | 1 | T1 | 57 | T2 | 5 | T4 | 3 | ||||
vendor_test | 33269 | 1 | T1 | 71 | T2 | 107 | T4 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 5914 | 1 | T217 | 51 | T17 | 98 | T304 | 411 | ||||
fsm_err | secret1 | 5569 | 1 | T90 | 8 | T259 | 284 | T196 | 508 | ||||
fsm_err | secret0 | 4572 | 1 | T195 | 588 | T206 | 179 | T199 | 245 | ||||
fsm_err | hw_cfg1 | 2029 | 1 | T103 | 470 | T305 | 13 | T306 | 223 | ||||
fsm_err | hw_cfg0 | 3741 | 1 | T63 | 30 | T139 | 33 | T67 | 118 | ||||
fsm_err | rot_creator_auth_state | 3489 | 1 | T139 | 28 | T230 | 45 | T307 | 359 | ||||
fsm_err | rot_creator_auth_codesign | 3591 | 1 | T308 | 96 | T194 | 188 | T140 | 66 | ||||
fsm_err | owner_sw_cfg | 5775 | 1 | T105 | 98 | T139 | 34 | T17 | 366 | ||||
fsm_err | creator_sw_cfg | 4502 | 1 | T91 | 330 | T142 | 326 | T139 | 63 | ||||
fsm_err | vendor_test | 15261 | 1 | T2 | 102 | T5 | 59 | T11 | 30 | ||||
access_err | life_cycle | 838 | 1 | T8 | 4 | T14 | 21 | T15 | 15 | ||||
access_err | secret2 | 11238 | 1 | T1 | 39 | T5 | 9 | T11 | 5 | ||||
access_err | secret1 | 6244 | 1 | T1 | 39 | T5 | 5 | T11 | 4 | ||||
access_err | secret0 | 4912 | 1 | T1 | 22 | T4 | 1 | T5 | 3 | ||||
access_err | hw_cfg1 | 1356 | 1 | T1 | 4 | T4 | 2 | T28 | 2 | ||||
access_err | hw_cfg0 | 2302 | 1 | T1 | 10 | T5 | 1 | T11 | 1 | ||||
access_err | rot_creator_auth_state | 6079 | 1 | T1 | 14 | T9 | 5 | T5 | 1 | ||||
access_err | rot_creator_auth_codesign | 8207 | 1 | T1 | 32 | T2 | 2 | T4 | 1 | ||||
access_err | owner_sw_cfg | 7160 | 1 | T1 | 18 | T2 | 1 | T12 | 1 | ||||
access_err | creator_sw_cfg | 8108 | 1 | T1 | 44 | T2 | 1 | T9 | 2 | ||||
access_err | vendor_test | 7563 | 1 | T1 | 33 | T2 | 2 | T9 | 5 | ||||
write_blank_err | secret2 | 16 | 1 | T14 | 2 | T15 | 1 | T220 | 1 | ||||
write_blank_err | secret1 | 22 | 1 | T309 | 1 | T310 | 1 | T311 | 1 | ||||
write_blank_err | secret0 | 40 | 1 | T8 | 1 | T194 | 1 | T312 | 1 | ||||
write_blank_err | hw_cfg1 | 86 | 1 | T6 | 1 | T14 | 1 | T194 | 1 | ||||
write_blank_err | hw_cfg0 | 22 | 1 | T313 | 1 | T124 | 1 | T310 | 1 | ||||
write_blank_err | rot_creator_auth_state | 172 | 1 | T14 | 4 | T194 | 5 | T18 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 49 | 1 | T14 | 3 | T314 | 1 | T232 | 1 | ||||
write_blank_err | owner_sw_cfg | 18 | 1 | T125 | 1 | T234 | 1 | T315 | 1 | ||||
write_blank_err | creator_sw_cfg | 8 | 1 | T295 | 1 | T315 | 1 | T316 | 1 | ||||
write_blank_err | vendor_test | 32 | 1 | T194 | 4 | T317 | 1 | T309 | 1 | ||||
ecc_uncorr_err | secret2 | 5932 | 1 | T14 | 412 | T15 | 532 | T220 | 273 | ||||
ecc_uncorr_err | secret1 | 9053 | 1 | T309 | 572 | T318 | 58 | T310 | 617 | ||||
ecc_uncorr_err | secret0 | 15887 | 1 | T8 | 268 | T194 | 491 | T140 | 61 | ||||
ecc_uncorr_err | hw_cfg1 | 27298 | 1 | T6 | 53 | T14 | 157 | T139 | 29 | ||||
ecc_uncorr_err | hw_cfg0 | 7920 | 1 | T139 | 62 | T313 | 649 | T124 | 411 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4706 | 1 | T140 | 73 | T239 | 495 | T141 | 60 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 971 | 1 | T139 | 36 | T319 | 61 | T320 | 46 | ||||
ecc_uncorr_err | owner_sw_cfg | 1653 | 1 | T139 | 38 | T140 | 65 | T141 | 61 | ||||
ecc_uncorr_err | creator_sw_cfg | 1238 | 1 | T295 | 41 | T186 | 28 | T320 | 122 | ||||
ecc_corr_err | secret2 | 116 | 1 | T5 | 2 | T52 | 5 | T71 | 4 | ||||
ecc_corr_err | secret1 | 106 | 1 | T5 | 2 | T52 | 4 | T75 | 4 | ||||
ecc_corr_err | secret0 | 156 | 1 | T52 | 3 | T71 | 5 | T43 | 3 | ||||
ecc_corr_err | hw_cfg1 | 252 | 1 | T5 | 2 | T11 | 3 | T107 | 2 | ||||
ecc_corr_err | hw_cfg0 | 249 | 1 | T5 | 11 | T11 | 1 | T52 | 11 | ||||
ecc_corr_err | rot_creator_auth_state | 116 | 1 | T5 | 3 | T11 | 2 | T52 | 1 | ||||
ecc_corr_err | rot_creator_auth_codesign | 115 | 1 | T5 | 1 | T52 | 7 | T71 | 8 | ||||
ecc_corr_err | owner_sw_cfg | 95 | 1 | T5 | 7 | T52 | 1 | T71 | 5 | ||||
ecc_corr_err | creator_sw_cfg | 144 | 1 | T5 | 1 | T107 | 1 | T52 | 1 | ||||
no_err | secret2 | 5380 | 1 | T1 | 7 | T2 | 8 | T4 | 3 | ||||
no_err | secret1 | 9256 | 1 | T1 | 10 | T2 | 2 | T4 | 8 | ||||
no_err | secret0 | 8704 | 1 | T1 | 20 | T2 | 3 | T4 | 9 | ||||
no_err | hw_cfg1 | 10850 | 1 | T1 | 31 | T2 | 4 | T4 | 3 | ||||
no_err | hw_cfg0 | 12541 | 1 | T1 | 29 | T2 | 2 | T4 | 4 | ||||
no_err | rot_creator_auth_state | 8638 | 1 | T1 | 27 | T2 | 2 | T4 | 4 | ||||
no_err | rot_creator_auth_codesign | 9253 | 1 | T1 | 23 | T2 | 2 | T4 | 1 | ||||
no_err | owner_sw_cfg | 9419 | 1 | T1 | 37 | T2 | 6 | T4 | 3 | ||||
no_err | creator_sw_cfg | 8373 | 1 | T1 | 13 | T2 | 4 | T4 | 3 | ||||
no_err | vendor_test | 10413 | 1 | T1 | 38 | T2 | 3 | T4 | 4 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |