Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_index 2 0 2 100.00 100 1 1 0
secret1_lock 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
flash_req_lock_cross 4 0 4 100.00 100 1 1 0


Summary for Variable flash_index

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_index

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
flash_addr_key 5898 1 T1 7 T4 2 T5 5
flash_data_key 5858 1 T1 7 T4 2 T5 5



Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6797 1 T1 4 T4 4 T5 4
auto[1] 4959 1 T1 10 T5 6 T11 10



Summary for Cross flash_req_lock_cross

Samples crossed: flash_index secret1_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for flash_req_lock_cross

Bins
flash_indexsecret1_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
flash_addr_key auto[0] 3392 1 T1 2 T4 2 T5 2
flash_addr_key auto[1] 2506 1 T1 5 T5 3 T11 5
flash_data_key auto[0] 3405 1 T1 2 T4 2 T5 2
flash_data_key auto[1] 2453 1 T1 5 T5 3 T11 5

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