Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49977	1			T5	129		T134	14		T175	448
access_err	57508	1			T4	34		T5	103		T31	3
write_blank_err	516	1			T7	4		T8	1		T15	4
ecc_uncorr_err	65900	1			T2	149		T7	668		T8	421
ecc_corr_err	1247	1			T2	4		T5	33		T15	1
no_err	87669	1			T2	15		T4	37		T5	80

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	877	1			T8	5		T15	10		T16	7
secret2	23818	1			T2	2		T4	7		T5	39
secret1	29092	1			T2	37		T4	6		T5	18
secret0	36358	1			T2	1		T4	12		T5	19
hw_cfg1	35628	1			T2	39		T4	5		T5	7
hw_cfg0	23664	1			T2	44		T4	3		T5	25
rot_creator_auth_state	21287	1			T4	6		T5	18		T12	2
rot_creator_auth_codesign	22181	1			T2	1		T4	8		T5	23
owner_sw_cfg	20839	1			T2	3		T4	4		T5	27
creator_sw_cfg	19069	1			T2	34		T4	15		T5	15
vendor_test	30004	1			T2	7		T4	5		T5	154

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5597	1			T117	349		T214	12		T332	499
fsm_err	secret1	4525	1			T14	14		T19	65		T20	28
fsm_err	secret0	3610	1			T228	132		T144	9		T266	247
fsm_err	hw_cfg1	2350	1			T145	60		T21	355		T226	49
fsm_err	hw_cfg0	4822	1			T134	14		T19	97		T331	43
fsm_err	rot_creator_auth_state	3944	1			T175	448		T105	29		T19	171
fsm_err	rot_creator_auth_codesign	4378	1			T333	507		T117	101		T334	192
fsm_err	owner_sw_cfg	4715	1			T105	24		T108	159		T91	293
fsm_err	creator_sw_cfg	2636	1			T174	123		T335	21		T325	109
fsm_err	vendor_test	13400	1			T5	129		T75	223		T32	111
access_err	life_cycle	877	1			T8	5		T15	10		T16	7
access_err	secret2	10439	1			T4	2		T5	32		T31	3
access_err	secret1	5285	1			T4	2		T5	6		T17	12
access_err	secret0	4148	1			T4	12		T5	12		T17	5
access_err	hw_cfg1	1108	1			T4	2		T5	2		T17	1
access_err	hw_cfg0	1973	1			T4	1		T5	5		T17	6
access_err	rot_creator_auth_state	5621	1			T5	4		T17	3		T6	19
access_err	rot_creator_auth_codesign	7287	1			T4	5		T5	6		T6	43
access_err	owner_sw_cfg	6593	1			T4	2		T5	13		T17	1
access_err	creator_sw_cfg	7057	1			T4	5		T5	14		T17	3
access_err	vendor_test	7120	1			T4	3		T5	9		T6	31
write_blank_err	secret2	6	1			T135	1		T336	1		T133	1
write_blank_err	secret1	20	1			T15	1		T337	1		T338	1
write_blank_err	secret0	55	1			T7	1		T21	1		T224	1
write_blank_err	hw_cfg1	89	1			T7	1		T8	1		T15	1
write_blank_err	hw_cfg0	17	1			T14	1		T231	1		T157	1
write_blank_err	rot_creator_auth_state	155	1			T7	1		T15	1		T21	10
write_blank_err	rot_creator_auth_codesign	68	1			T15	1		T16	4		T339	1
write_blank_err	owner_sw_cfg	37	1			T211	2		T220	4		T340	1
write_blank_err	creator_sw_cfg	26	1			T327	3		T336	1		T23	2
write_blank_err	vendor_test	43	1			T7	1		T232	5		T220	1
ecc_uncorr_err	secret2	2541	1			T135	443		T203	63		T143	75
ecc_uncorr_err	secret1	10003	1			T2	35		T15	555		T105	23
ecc_uncorr_err	secret0	20057	1			T7	463		T105	58		T21	691
ecc_uncorr_err	hw_cfg1	21529	1			T2	38		T7	205		T8	421
ecc_uncorr_err	hw_cfg0	5078	1			T2	43		T105	26		T14	131
ecc_uncorr_err	rot_creator_auth_state	3369	1			T187	3		T203	51		T172	69
ecc_uncorr_err	rot_creator_auth_codesign	1558	1			T105	32		T187	16		T203	50
ecc_uncorr_err	owner_sw_cfg	590	1			T187	11		T143	69		T341	45
ecc_uncorr_err	creator_sw_cfg	1175	1			T2	33		T105	20		T143	64
ecc_corr_err	secret2	60	1			T2	1		T5	1		T32	2
ecc_corr_err	secret1	87	1			T2	1		T5	1		T32	4
ecc_corr_err	secret0	114	1			T5	1		T81	5		T64	1
ecc_corr_err	hw_cfg1	257	1			T2	1		T5	3		T15	1
ecc_corr_err	hw_cfg0	216	1			T5	10		T32	14		T81	5
ecc_corr_err	rot_creator_auth_state	141	1			T5	5		T32	2		T81	1
ecc_corr_err	rot_creator_auth_codesign	143	1			T5	4		T32	2		T81	1
ecc_corr_err	owner_sw_cfg	110	1			T2	1		T5	8		T105	1
ecc_corr_err	creator_sw_cfg	119	1			T32	1		T81	1		T64	2
no_err	secret2	5175	1			T2	1		T4	5		T5	6
no_err	secret1	9172	1			T2	1		T4	4		T5	11
no_err	secret0	8374	1			T2	1		T5	6		T12	1
no_err	hw_cfg1	10295	1			T4	3		T5	2		T12	6
no_err	hw_cfg0	11558	1			T2	1		T4	2		T5	10
no_err	rot_creator_auth_state	8057	1			T4	6		T5	9		T12	2
no_err	rot_creator_auth_codesign	8747	1			T2	1		T4	3		T5	13
no_err	owner_sw_cfg	8794	1			T2	2		T4	2		T5	6
no_err	creator_sw_cfg	8056	1			T2	1		T4	10		T5	1
no_err	vendor_test	9441	1			T2	7		T4	2		T5	16

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded