Unified Coverage Report :: Cond split page

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 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T14
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T26,T27
1	0	Covered	T269,T270,T271

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T25,T26,T27
0	1	0	Covered	T269,T270,T271
1	0	0	Covered	T25,T26,T27

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T269,T270,T271
0	1	0	Covered	T6,T7,T14
1	0	0	Covered	T6,T7,T14

 LINE       1118
 EXPRESSION (direct_access_cmd_we & direct_access_regwen_qs)
             ----------1---------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T111
1	1	Covered	T1,T2,T3

 LINE       1171
 EXPRESSION (direct_access_address_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T111
1	1	Covered	T1,T2,T3

 LINE       1203
 EXPRESSION (direct_access_wdata_0_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T111
1	1	Covered	T1,T2,T3

 LINE       1235
 EXPRESSION (direct_access_wdata_1_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T111
1	1	Covered	T1,T2,T3

 LINE       1331
 EXPRESSION (check_trigger_we & check_trigger_regwen_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T134
1	1	Covered	T2,T4,T5

 LINE       1396
 EXPRESSION (check_timeout_we & check_regwen_qs)
             --------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T31,T17
1	1	Covered	T2,T4,T5

 LINE       1427
 EXPRESSION (integrity_check_period_we & check_regwen_qs)
             ------------1------------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T272,T273,T274
1	1	Covered	T15,T126,T135

 LINE       1458
 EXPRESSION (consistency_check_period_we & check_regwen_qs)
             -------------1-------------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T272,T273,T274
1	1	Covered	T15,T20,T126

 LINE       1489
 EXPRESSION (vendor_test_read_lock_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T7
1	1	Covered	T4,T5,T17

 LINE       1520
 EXPRESSION (creator_sw_cfg_read_lock_we & direct_access_regwen_qs)
             -------------1-------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T7
1	1	Covered	T4,T5,T17

 LINE       1551
 EXPRESSION (owner_sw_cfg_read_lock_we & direct_access_regwen_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T111
1	1	Covered	T4,T5,T17

 LINE       1582
 EXPRESSION (rot_creator_auth_codesign_read_lock_we & direct_access_regwen_qs)
             -------------------1------------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T113
1	1	Covered	T4,T5,T17

 LINE       1614
 EXPRESSION (rot_creator_auth_state_read_lock_we & direct_access_regwen_qs)
             -----------------1-----------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T111
1	1	Covered	T4,T5,T17

 LINE       1987
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1988
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1989
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T28

 LINE       1990
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T5,T28

 LINE       1991
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1992
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1993
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1994
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_2_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T4

 LINE       1995
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_3_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       1996
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_4_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1997
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_5_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1998
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_6_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T4

 LINE       1999
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_7_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2000
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_8_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       2001
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_9_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       2002
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_10_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2003
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_11_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2004
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_12_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T4

 LINE       2005
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2006
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2007
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2008
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2009
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2010
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2011
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2012
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2013
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2014
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2015
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2016
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T110

 LINE       2017
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T110

 LINE       2018
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2019
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2020
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2021
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK_OFFSET)
            -----------------------------------------1-----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2022
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK_OFFSET)
            ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2023
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2024
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2025
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2026
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2027
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2028
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2029
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_OFFSET)
            -----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2030
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_OFFSET)
            -----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2031
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_OFFSET)
            ---------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2032
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1_OFFSET)
            ---------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2033
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2034
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2035
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG1_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2036
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG1_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2037
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2038
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2039
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2040
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2041
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       2042
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T4

 LINE       2045
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2045
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2049
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T14

 LINE       2049
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
56 (addr_hit[55] & ((\|(4'...	Covered	T2,T9,T4
55 (addr_hit[54] & ((\|(4'...	Covered	T1,T2,T4
54 (addr_hit[53] & ((\|(4'...	Covered	T1,T2,T4
53 (addr_hit[52] & ((\|(4'...	Covered	T1,T2,T4
52 (addr_hit[51] & ((\|(4'...	Covered	T2,T4,T5
51 (addr_hit[50] & ((\|(4'...	Covered	T1,T2,T4
50 (addr_hit[49] & ((\|(4'...	Covered	T2,T4,T5
49 (addr_hit[48] & ((\|(4'...	Covered	T2,T4,T5
48 (addr_hit[47] & ((\|(4'...	Covered	T2,T4,T5
47 (addr_hit[46] & ((\|(4'...	Covered	T2,T4,T5
46 (addr_hit[45] & ((\|(4'...	Covered	T2,T4,T5
45 (addr_hit[44] & ((\|(4'...	Covered	T2,T4,T5
44 (addr_hit[43] & ((\|(4'...	Covered	T1,T2,T4
43 (addr_hit[42] & ((\|(4'...	Covered	T1,T2,T4
42 (addr_hit[41] & ((\|(4'...	Covered	T2,T4,T5
41 (addr_hit[40] & ((\|(4'...	Covered	T2,T4,T5
40 (addr_hit[39] & ((\|(4'...	Covered	T2,T4,T5
39 (addr_hit[38] & ((\|(4'...	Covered	T2,T4,T5
38 (addr_hit[37] & ((\|(4'...	Covered	T2,T4,T5
37 (addr_hit[36] & ((\|(4'...	Covered	T1,T4,T5
36 (addr_hit[35] & ((\|(4'...	Covered	T1,T5,T28
35 (addr_hit[34] & ((\|(4'...	Covered	T5,T110,T17
34 (addr_hit[33] & ((\|(4'...	Covered	T5,T11,T28
33 (addr_hit[32] & ((\|(4'...	Covered	T5,T11,T6
32 (addr_hit[31] & ((\|(4'...	Covered	T1,T5,T110
31 (addr_hit[30] & ((\|(4'...	Covered	T1,T5,T110
30 (addr_hit[29] & ((\|(4'...	Covered	T5,T11,T110
29 (addr_hit[28] & ((\|(4'...	Covered	T5,T28,T110
28 (addr_hit[27] & ((\|(4'...	Covered	T5,T28,T17
27 (addr_hit[26] & ((\|(4'...	Covered	T5,T17,T6
26 (addr_hit[25] & ((\|(4'...	Covered	T5,T110,T17
25 (addr_hit[24] & ((\|(4'...	Covered	T1,T2,T3
24 (addr_hit[23] & ((\|(4'...	Covered	T1,T2,T3
23 (addr_hit[22] & ((\|(4'...	Covered	T1,T5,T11
22 (addr_hit[21] & ((\|(4'...	Covered	T5,T110,T17
21 (addr_hit[20] & ((\|(4'...	Covered	T5,T110,T17
20 (addr_hit[19] & ((\|(4'...	Covered	T1,T5,T17
19 (addr_hit[18] & ((\|(4'...	Covered	T2,T3,T4
18 (addr_hit[17] & ((\|(4'...	Covered	T2,T4,T5
17 (addr_hit[16] & ((\|(4'...	Covered	T2,T4,T5
16 (addr_hit[15] & ((\|(4'...	Covered	T2,T4,T5
15 (addr_hit[14] & ((\|(4'...	Covered	T1,T2,T4
14 (addr_hit[13] & ((\|(4'...	Covered	T2,T4,T5
13 (addr_hit[12] & ((\|(4'...	Covered	T2,T4,T5
12 (addr_hit[11] & ((\|(4'...	Covered	T2,T4,T5
11 (addr_hit[10] & ((\|(4'...	Covered	T2,T4,T5
10 (addr_hit[9] & ((\|(4'b...	Covered	T1,T2,T4
9 (addr_hit[8] & ((\|(4'b...	Covered	T2,T4,T5
8 (addr_hit[7] & ((\|(4'b...	Covered	T2,T4,T5
7 (addr_hit[6] & ((\|(4'b...	Covered	T2,T4,T5
6 (addr_hit[5] & ((\|(4'b...	Covered	T2,T4,T5
5 (addr_hit[4] & ((\|(4'b...	Covered	T1,T2,T3
4 (addr_hit[3] & ((\|(4'b...	Covered	T5,T28,T110
3 (addr_hit[2] & ((\|(4'b...	Covered	T5,T11,T28
2 (addr_hit[1] & ((\|(4'b...	Covered	T5,T17,T6
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3

 LINE       2049
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2049
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T17,T6

 LINE       2049
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T110,T17
1	1	Covered	T5,T11,T28

 LINE       2049
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T5,T110
1	1	Covered	T5,T28,T110

 LINE       2049
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2049
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T4
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T17

 LINE       2049
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T110,T17

 LINE       2049
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T110,T17

 LINE       2049
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T11

 LINE       2049
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2049
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2049
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T110,T17

 LINE       2049
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T17,T6

 LINE       2049
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T28,T17

 LINE       2049
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T28,T110

 LINE       2049
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T110,T17
1	1	Covered	T5,T11,T110

 LINE       2049
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T110
1	1	Covered	T1,T5,T110

 LINE       2049
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T110

 LINE       2049
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T11,T6

 LINE       2049
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T11,T28

 LINE       2049
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T110,T17

 LINE       2049
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T28

 LINE       2049
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2049
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       2049
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T9,T4

 LINE       2109
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T7,T14
1	1	1	Covered	T1,T2,T3

 LINE       2114
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T7,T14
1	1	1	Covered	T1,T2,T3

 LINE       2119
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T11,T28
1	1	0	Covered	T6,T7,T14
1	1	1	Covered	T17,T20,T21