Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.05 93.81 96.67 96.08 91.89 97.24 96.34 93.35


Total test records in report: 1328
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1262 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1775378259 Jul 11 06:32:35 PM PDT 24 Jul 11 06:32:41 PM PDT 24 130925999 ps
T1263 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2964475087 Jul 11 06:33:44 PM PDT 24 Jul 11 06:33:48 PM PDT 24 285889159 ps
T1264 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2621402545 Jul 11 06:32:59 PM PDT 24 Jul 11 06:33:02 PM PDT 24 71336696 ps
T1265 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.842186614 Jul 11 06:34:07 PM PDT 24 Jul 11 06:34:13 PM PDT 24 389778415 ps
T306 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2685727657 Jul 11 06:34:07 PM PDT 24 Jul 11 06:34:10 PM PDT 24 149446409 ps
T1266 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2637422683 Jul 11 06:33:41 PM PDT 24 Jul 11 06:33:51 PM PDT 24 3081625646 ps
T1267 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2876348247 Jul 11 06:34:09 PM PDT 24 Jul 11 06:34:12 PM PDT 24 84855515 ps
T1268 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.245627422 Jul 11 06:33:54 PM PDT 24 Jul 11 06:34:15 PM PDT 24 4906338366 ps
T1269 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2978277426 Jul 11 06:33:56 PM PDT 24 Jul 11 06:33:59 PM PDT 24 58017638 ps
T1270 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1601363995 Jul 11 06:33:22 PM PDT 24 Jul 11 06:33:25 PM PDT 24 48045222 ps
T348 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3817988635 Jul 11 06:33:19 PM PDT 24 Jul 11 06:33:44 PM PDT 24 4599538502 ps
T1271 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.538112463 Jul 11 06:34:07 PM PDT 24 Jul 11 06:34:14 PM PDT 24 1521122849 ps
T1272 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.698769350 Jul 11 06:34:04 PM PDT 24 Jul 11 06:34:18 PM PDT 24 2352731141 ps
T303 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1040406336 Jul 11 06:33:18 PM PDT 24 Jul 11 06:33:22 PM PDT 24 98927020 ps
T307 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.792142892 Jul 11 06:33:07 PM PDT 24 Jul 11 06:33:11 PM PDT 24 362619982 ps
T1273 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2439249685 Jul 11 06:34:18 PM PDT 24 Jul 11 06:34:20 PM PDT 24 42404474 ps
T1274 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2329510706 Jul 11 06:33:31 PM PDT 24 Jul 11 06:33:34 PM PDT 24 39839653 ps
T1275 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.477167376 Jul 11 06:33:42 PM PDT 24 Jul 11 06:33:49 PM PDT 24 1207961224 ps
T1276 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1022674031 Jul 11 06:32:58 PM PDT 24 Jul 11 06:33:02 PM PDT 24 214465352 ps
T1277 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.667234147 Jul 11 06:33:26 PM PDT 24 Jul 11 06:33:29 PM PDT 24 144996645 ps
T1278 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1470701046 Jul 11 06:34:03 PM PDT 24 Jul 11 06:34:07 PM PDT 24 200710487 ps
T1279 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3131605985 Jul 11 06:34:23 PM PDT 24 Jul 11 06:34:25 PM PDT 24 97051652 ps
T308 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.4277870593 Jul 11 06:33:19 PM PDT 24 Jul 11 06:33:22 PM PDT 24 40217686 ps
T1280 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1643730217 Jul 11 06:33:10 PM PDT 24 Jul 11 06:33:15 PM PDT 24 37750706 ps
T1281 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2909432701 Jul 11 06:34:19 PM PDT 24 Jul 11 06:34:21 PM PDT 24 69802006 ps
T1282 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1565801476 Jul 11 06:33:27 PM PDT 24 Jul 11 06:33:38 PM PDT 24 2440062133 ps
T1283 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1509100663 Jul 11 06:32:41 PM PDT 24 Jul 11 06:32:43 PM PDT 24 130404259 ps
T1284 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.465083103 Jul 11 06:33:53 PM PDT 24 Jul 11 06:33:56 PM PDT 24 54744048 ps
T1285 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3686803198 Jul 11 06:33:16 PM PDT 24 Jul 11 06:33:19 PM PDT 24 39997326 ps
T1286 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1294339961 Jul 11 06:33:36 PM PDT 24 Jul 11 06:33:40 PM PDT 24 1063017428 ps
T1287 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2760844974 Jul 11 06:34:18 PM PDT 24 Jul 11 06:34:21 PM PDT 24 42109628 ps
T1288 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.259308198 Jul 11 06:34:07 PM PDT 24 Jul 11 06:34:10 PM PDT 24 49043197 ps
T1289 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.705967289 Jul 11 06:33:49 PM PDT 24 Jul 11 06:33:53 PM PDT 24 107868664 ps
T1290 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3325708052 Jul 11 06:33:10 PM PDT 24 Jul 11 06:33:26 PM PDT 24 6267212524 ps
T1291 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2198250921 Jul 11 06:33:02 PM PDT 24 Jul 11 06:33:04 PM PDT 24 136308518 ps
T1292 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3976709061 Jul 11 06:33:57 PM PDT 24 Jul 11 06:33:59 PM PDT 24 74326808 ps
T1293 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1395245382 Jul 11 06:33:22 PM PDT 24 Jul 11 06:33:25 PM PDT 24 551126287 ps
T1294 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2058434185 Jul 11 06:34:02 PM PDT 24 Jul 11 06:34:07 PM PDT 24 201573159 ps
T1295 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1361522392 Jul 11 06:32:47 PM PDT 24 Jul 11 06:32:51 PM PDT 24 670544960 ps
T309 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2890919566 Jul 11 06:33:59 PM PDT 24 Jul 11 06:34:01 PM PDT 24 37675450 ps
T1296 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2815563453 Jul 11 06:33:39 PM PDT 24 Jul 11 06:33:51 PM PDT 24 2465721010 ps
T1297 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.473390346 Jul 11 06:33:42 PM PDT 24 Jul 11 06:33:46 PM PDT 24 49935745 ps
T1298 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1918977973 Jul 11 06:32:41 PM PDT 24 Jul 11 06:32:44 PM PDT 24 145646083 ps
T1299 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3537481236 Jul 11 06:33:43 PM PDT 24 Jul 11 06:33:49 PM PDT 24 446457736 ps
T1300 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1348204733 Jul 11 06:34:03 PM PDT 24 Jul 11 06:34:06 PM PDT 24 79239340 ps
T1301 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1412068928 Jul 11 06:32:45 PM PDT 24 Jul 11 06:32:51 PM PDT 24 136132502 ps
T1302 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.696879769 Jul 11 06:34:14 PM PDT 24 Jul 11 06:34:16 PM PDT 24 38305385 ps
T1303 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3246758436 Jul 11 06:33:58 PM PDT 24 Jul 11 06:34:03 PM PDT 24 210393143 ps
T1304 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2462892935 Jul 11 06:33:58 PM PDT 24 Jul 11 06:34:01 PM PDT 24 69675572 ps
T310 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.760239957 Jul 11 06:33:31 PM PDT 24 Jul 11 06:33:33 PM PDT 24 554808640 ps
T311 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2463883321 Jul 11 06:33:18 PM PDT 24 Jul 11 06:33:29 PM PDT 24 1592114720 ps
T1305 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1809771572 Jul 11 06:34:04 PM PDT 24 Jul 11 06:34:09 PM PDT 24 97992683 ps
T1306 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.247968422 Jul 11 06:33:39 PM PDT 24 Jul 11 06:33:44 PM PDT 24 121058400 ps
T1307 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1752541049 Jul 11 06:33:41 PM PDT 24 Jul 11 06:33:44 PM PDT 24 90040981 ps
T1308 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2283742205 Jul 11 06:33:09 PM PDT 24 Jul 11 06:33:13 PM PDT 24 247950449 ps
T1309 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.4083717565 Jul 11 06:33:27 PM PDT 24 Jul 11 06:33:32 PM PDT 24 194949279 ps
T1310 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1239658388 Jul 11 06:33:57 PM PDT 24 Jul 11 06:34:00 PM PDT 24 123203642 ps
T1311 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.954901376 Jul 11 06:33:07 PM PDT 24 Jul 11 06:33:15 PM PDT 24 723024555 ps
T349 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1775811515 Jul 11 06:33:09 PM PDT 24 Jul 11 06:33:33 PM PDT 24 1814433289 ps
T1312 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2690585498 Jul 11 06:32:56 PM PDT 24 Jul 11 06:33:00 PM PDT 24 146397165 ps
T1313 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1822200318 Jul 11 06:33:58 PM PDT 24 Jul 11 06:34:01 PM PDT 24 85910360 ps
T1314 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2672476610 Jul 11 06:33:14 PM PDT 24 Jul 11 06:33:20 PM PDT 24 309940652 ps
T275 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1193150126 Jul 11 06:34:07 PM PDT 24 Jul 11 06:34:26 PM PDT 24 1351805319 ps
T1315 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.4282671197 Jul 11 06:34:14 PM PDT 24 Jul 11 06:34:17 PM PDT 24 57554280 ps
T1316 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3251599037 Jul 11 06:33:23 PM PDT 24 Jul 11 06:34:07 PM PDT 24 19811052523 ps
T1317 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3711625831 Jul 11 06:34:00 PM PDT 24 Jul 11 06:34:07 PM PDT 24 152490779 ps
T1318 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1456218742 Jul 11 06:33:41 PM PDT 24 Jul 11 06:33:46 PM PDT 24 1084132275 ps
T1319 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2916112532 Jul 11 06:34:08 PM PDT 24 Jul 11 06:34:11 PM PDT 24 73257396 ps
T312 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3588553925 Jul 11 06:33:41 PM PDT 24 Jul 11 06:33:44 PM PDT 24 129570300 ps
T1320 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1274556686 Jul 11 06:34:24 PM PDT 24 Jul 11 06:34:27 PM PDT 24 147684810 ps
T1321 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1001119718 Jul 11 06:33:27 PM PDT 24 Jul 11 06:33:30 PM PDT 24 85977612 ps
T1322 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2000071128 Jul 11 06:33:59 PM PDT 24 Jul 11 06:34:02 PM PDT 24 155372145 ps
T1323 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3381917603 Jul 11 06:33:51 PM PDT 24 Jul 11 06:33:55 PM PDT 24 79926192 ps
T1324 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.958245037 Jul 11 06:33:38 PM PDT 24 Jul 11 06:33:40 PM PDT 24 43682123 ps
T1325 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.710244805 Jul 11 06:33:19 PM PDT 24 Jul 11 06:33:21 PM PDT 24 136010808 ps
T1326 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.366016332 Jul 11 06:34:01 PM PDT 24 Jul 11 06:34:04 PM PDT 24 266473952 ps
T1327 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3784499787 Jul 11 06:33:59 PM PDT 24 Jul 11 06:34:34 PM PDT 24 6279528642 ps
T1328 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2040987263 Jul 11 06:33:27 PM PDT 24 Jul 11 06:33:30 PM PDT 24 146457044 ps

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1814014322
Short name T5
Test name
Test status
Simulation time 3342488656 ps
CPU time 24.44 seconds
Started Jul 11 06:55:22 PM PDT 24
Finished Jul 11 06:55:48 PM PDT 24
Peak memory 242144 kb
Host smart-35cba5d2-b318-4ead-b150-7e790ea60e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814014322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1814014322
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3554747257
Short name T15
Test name
Test status
Simulation time 9097222287 ps
CPU time 151.29 seconds
Started Jul 11 06:56:12 PM PDT 24
Finished Jul 11 06:58:45 PM PDT 24
Peak memory 248808 kb
Host smart-f8f9aa98-91c4-44fa-82a9-4a7e2fc03fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554747257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3554747257
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3382791001
Short name T14
Test name
Test status
Simulation time 430784436865 ps
CPU time 3380.83 seconds
Started Jul 11 06:59:32 PM PDT 24
Finished Jul 11 07:55:54 PM PDT 24
Peak memory 387028 kb
Host smart-24e4c2c1-d3d9-4059-bd35-618e82f64bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382791001 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3382791001
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.2513310161
Short name T126
Test name
Test status
Simulation time 34365641494 ps
CPU time 172.65 seconds
Started Jul 11 06:57:26 PM PDT 24
Finished Jul 11 07:00:20 PM PDT 24
Peak memory 250304 kb
Host smart-f924bb43-3e95-4f72-8eb8-b84e70320a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513310161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.2513310161
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.751084148
Short name T28
Test name
Test status
Simulation time 152849600 ps
CPU time 4.59 seconds
Started Jul 11 07:01:21 PM PDT 24
Finished Jul 11 07:01:27 PM PDT 24
Peak memory 242148 kb
Host smart-b71d4705-8342-4c96-93d1-02299a1cb09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751084148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.751084148
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3572894790
Short name T26
Test name
Test status
Simulation time 15123174359 ps
CPU time 210.6 seconds
Started Jul 11 06:53:06 PM PDT 24
Finished Jul 11 06:56:37 PM PDT 24
Peak memory 266116 kb
Host smart-2c110d72-3815-4f84-823b-2780c90e9459
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572894790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3572894790
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.124435809
Short name T137
Test name
Test status
Simulation time 497312591 ps
CPU time 4.05 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242404 kb
Host smart-325db9e0-e29d-4f45-b4e2-4f938ebad845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124435809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.124435809
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3039405741
Short name T117
Test name
Test status
Simulation time 3721822092 ps
CPU time 82.08 seconds
Started Jul 11 06:58:07 PM PDT 24
Finished Jul 11 06:59:30 PM PDT 24
Peak memory 248768 kb
Host smart-08416d90-62c2-4d35-bb65-70e9ef188edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039405741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3039405741
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.1980341800
Short name T21
Test name
Test status
Simulation time 89333116209 ps
CPU time 1482.19 seconds
Started Jul 11 06:59:28 PM PDT 24
Finished Jul 11 07:24:11 PM PDT 24
Peak memory 293768 kb
Host smart-ed2955a4-e23a-42ce-a3c4-c04caf256321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980341800 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.1980341800
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.254453073
Short name T64
Test name
Test status
Simulation time 6425070207 ps
CPU time 40.91 seconds
Started Jul 11 06:57:00 PM PDT 24
Finished Jul 11 06:57:42 PM PDT 24
Peak memory 248196 kb
Host smart-9c3e1fd5-c00c-48bf-9870-11e142fc3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254453073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.254453073
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.854395614
Short name T371
Test name
Test status
Simulation time 11291424803 ps
CPU time 124.52 seconds
Started Jul 11 06:57:43 PM PDT 24
Finished Jul 11 06:59:50 PM PDT 24
Peak memory 246576 kb
Host smart-54ce916d-f77c-4a71-bd88-d02f1c409554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854395614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
854395614
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.1410038462
Short name T110
Test name
Test status
Simulation time 227723462 ps
CPU time 4.23 seconds
Started Jul 11 07:00:10 PM PDT 24
Finished Jul 11 07:00:15 PM PDT 24
Peak memory 242088 kb
Host smart-4dad533d-5edf-48d3-b94d-3d241594565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410038462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1410038462
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3463769661
Short name T271
Test name
Test status
Simulation time 2339062009 ps
CPU time 19.03 seconds
Started Jul 11 06:34:02 PM PDT 24
Finished Jul 11 06:34:22 PM PDT 24
Peak memory 239400 kb
Host smart-7fd18882-9a23-45ee-bd77-9116ca2874fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463769661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3463769661
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3017766911
Short name T119
Test name
Test status
Simulation time 127712481411 ps
CPU time 2274.76 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 07:36:58 PM PDT 24
Peak memory 369376 kb
Host smart-86d16b34-5ae3-4c3b-a566-eaa5d38c8960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017766911 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.3017766911
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3858474655
Short name T47
Test name
Test status
Simulation time 2792192345 ps
CPU time 7.15 seconds
Started Jul 11 07:01:55 PM PDT 24
Finished Jul 11 07:02:03 PM PDT 24
Peak memory 242232 kb
Host smart-76e5e82f-548b-4d1c-b092-64d516f0c976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858474655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3858474655
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.1078945841
Short name T390
Test name
Test status
Simulation time 25551578842 ps
CPU time 190.99 seconds
Started Jul 11 06:57:48 PM PDT 24
Finished Jul 11 07:01:01 PM PDT 24
Peak memory 248776 kb
Host smart-2607efe5-5439-46c0-aacf-ce6e58d941c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078945841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.1078945841
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.1933794174
Short name T67
Test name
Test status
Simulation time 2198220083 ps
CPU time 6.03 seconds
Started Jul 11 07:00:56 PM PDT 24
Finished Jul 11 07:01:03 PM PDT 24
Peak memory 242392 kb
Host smart-af6bd45c-0f3d-455a-a07e-2eef228dd292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933794174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1933794174
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3201929519
Short name T37
Test name
Test status
Simulation time 214822887 ps
CPU time 5.35 seconds
Started Jul 11 07:00:33 PM PDT 24
Finished Jul 11 07:00:39 PM PDT 24
Peak memory 242076 kb
Host smart-73b8e4e0-c98c-43c5-ae4c-093649d08e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201929519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3201929519
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.2703173265
Short name T184
Test name
Test status
Simulation time 2130420041 ps
CPU time 25.86 seconds
Started Jul 11 06:56:28 PM PDT 24
Finished Jul 11 06:56:55 PM PDT 24
Peak memory 242296 kb
Host smart-d77f8ccc-253b-48a4-b353-cb5bbc11bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703173265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2703173265
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3647760638
Short name T33
Test name
Test status
Simulation time 819843138 ps
CPU time 15.83 seconds
Started Jul 11 06:57:53 PM PDT 24
Finished Jul 11 06:58:11 PM PDT 24
Peak memory 244116 kb
Host smart-2482102a-cfb7-4733-a7b3-117528b98984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647760638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3647760638
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.1909973001
Short name T40
Test name
Test status
Simulation time 179274608 ps
CPU time 3.99 seconds
Started Jul 11 06:54:11 PM PDT 24
Finished Jul 11 06:54:16 PM PDT 24
Peak memory 242156 kb
Host smart-195cce6e-7c09-4c96-8d7c-4f976c10d704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909973001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1909973001
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.316041900
Short name T252
Test name
Test status
Simulation time 31649561773 ps
CPU time 300 seconds
Started Jul 11 06:54:47 PM PDT 24
Finished Jul 11 06:59:47 PM PDT 24
Peak memory 297700 kb
Host smart-3be877f9-61f1-48e3-b606-36f67312e21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316041900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.
316041900
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3679756089
Short name T18
Test name
Test status
Simulation time 72234922 ps
CPU time 1.81 seconds
Started Jul 11 06:58:23 PM PDT 24
Finished Jul 11 06:58:26 PM PDT 24
Peak memory 240424 kb
Host smart-f9f4d2d8-5cb8-40ea-ac1a-c2c3583e4715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679756089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3679756089
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.353340519
Short name T144
Test name
Test status
Simulation time 11206127195 ps
CPU time 23.37 seconds
Started Jul 11 06:53:43 PM PDT 24
Finished Jul 11 06:54:07 PM PDT 24
Peak memory 243136 kb
Host smart-86eafc19-beef-43c5-8d91-09d33ac0b771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353340519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.353340519
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1488208840
Short name T51
Test name
Test status
Simulation time 2272762521 ps
CPU time 7.54 seconds
Started Jul 11 07:00:53 PM PDT 24
Finished Jul 11 07:01:02 PM PDT 24
Peak memory 241972 kb
Host smart-7fd9d3c7-d77d-4d93-b04d-b2b9906d7d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488208840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1488208840
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.2917675721
Short name T388
Test name
Test status
Simulation time 301025311677 ps
CPU time 2587.46 seconds
Started Jul 11 06:57:30 PM PDT 24
Finished Jul 11 07:40:39 PM PDT 24
Peak memory 458920 kb
Host smart-06f05b2e-ef82-43cc-968b-1242211c5a5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917675721 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.2917675721
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.759447067
Short name T76
Test name
Test status
Simulation time 145020637 ps
CPU time 3.97 seconds
Started Jul 11 06:59:36 PM PDT 24
Finished Jul 11 06:59:40 PM PDT 24
Peak memory 241840 kb
Host smart-77517041-beeb-46fc-9ab8-29c356cb0a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759447067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.759447067
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1446622755
Short name T182
Test name
Test status
Simulation time 5305044681 ps
CPU time 10.18 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:01:02 PM PDT 24
Peak memory 242024 kb
Host smart-f86de2ec-9eca-4eb4-b4ab-a91cff0ce7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446622755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1446622755
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.2724948436
Short name T140
Test name
Test status
Simulation time 133203435 ps
CPU time 3.63 seconds
Started Jul 11 07:01:28 PM PDT 24
Finished Jul 11 07:01:34 PM PDT 24
Peak memory 241928 kb
Host smart-87f2185e-bae3-43f9-b3ad-41a197044fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724948436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2724948436
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1013993088
Short name T58
Test name
Test status
Simulation time 151623203 ps
CPU time 5.76 seconds
Started Jul 11 07:01:07 PM PDT 24
Finished Jul 11 07:01:14 PM PDT 24
Peak memory 242160 kb
Host smart-b6da1a28-ae52-4d46-a700-485850af7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013993088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1013993088
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2043912705
Short name T22
Test name
Test status
Simulation time 82595606079 ps
CPU time 1196.67 seconds
Started Jul 11 06:59:38 PM PDT 24
Finished Jul 11 07:19:35 PM PDT 24
Peak memory 263016 kb
Host smart-fee433b1-5cc4-4f4a-8e11-21ff340bd2df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043912705 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.2043912705
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3739643473
Short name T145
Test name
Test status
Simulation time 286174433 ps
CPU time 5.95 seconds
Started Jul 11 07:00:33 PM PDT 24
Finished Jul 11 07:00:39 PM PDT 24
Peak memory 242368 kb
Host smart-8906e768-1f0f-46f1-a42d-4c0b1aac5c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739643473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3739643473
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3362684494
Short name T161
Test name
Test status
Simulation time 225857608 ps
CPU time 4.05 seconds
Started Jul 11 07:01:04 PM PDT 24
Finished Jul 11 07:01:10 PM PDT 24
Peak memory 241928 kb
Host smart-77e00f42-fe1b-4576-90b5-9bab13d08ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362684494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3362684494
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1759996832
Short name T44
Test name
Test status
Simulation time 196408061 ps
CPU time 5.12 seconds
Started Jul 11 06:58:31 PM PDT 24
Finished Jul 11 06:58:37 PM PDT 24
Peak memory 242084 kb
Host smart-66f2ccec-541c-4196-984c-d576f9ca4bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759996832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1759996832
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.2967790073
Short name T83
Test name
Test status
Simulation time 167734287 ps
CPU time 4.01 seconds
Started Jul 11 07:00:28 PM PDT 24
Finished Jul 11 07:00:33 PM PDT 24
Peak memory 242088 kb
Host smart-4c6f4895-245c-43fa-af37-671f8dfe73a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967790073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.2967790073
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3607658667
Short name T90
Test name
Test status
Simulation time 2253492551 ps
CPU time 7.14 seconds
Started Jul 11 07:01:32 PM PDT 24
Finished Jul 11 07:01:40 PM PDT 24
Peak memory 242100 kb
Host smart-3be0fcc8-8f55-4cbf-a4ba-c1d8ed13c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607658667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3607658667
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.3086034696
Short name T389
Test name
Test status
Simulation time 147370799388 ps
CPU time 326.84 seconds
Started Jul 11 06:54:11 PM PDT 24
Finished Jul 11 06:59:39 PM PDT 24
Peak memory 284352 kb
Host smart-4c005fad-394d-4e4c-bb2a-94333aa01b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086034696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
3086034696
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.484925006
Short name T154
Test name
Test status
Simulation time 17542650270 ps
CPU time 145.69 seconds
Started Jul 11 06:57:07 PM PDT 24
Finished Jul 11 06:59:33 PM PDT 24
Peak memory 251280 kb
Host smart-7a9a033f-7904-421f-bdec-0e5896c87217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484925006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.
484925006
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3563739495
Short name T111
Test name
Test status
Simulation time 556220921 ps
CPU time 9.5 seconds
Started Jul 11 06:52:06 PM PDT 24
Finished Jul 11 06:52:17 PM PDT 24
Peak memory 242112 kb
Host smart-ada3c3f0-5c63-4c59-ac34-f7684e6b35d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563739495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3563739495
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.3529046705
Short name T71
Test name
Test status
Simulation time 310879604 ps
CPU time 4.17 seconds
Started Jul 11 06:59:57 PM PDT 24
Finished Jul 11 07:00:02 PM PDT 24
Peak memory 242164 kb
Host smart-b5fc1870-219d-4858-8f1b-c2af50065c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529046705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3529046705
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.4259302930
Short name T99
Test name
Test status
Simulation time 12046742241 ps
CPU time 39.78 seconds
Started Jul 11 06:58:59 PM PDT 24
Finished Jul 11 06:59:40 PM PDT 24
Peak memory 242092 kb
Host smart-13a8c1a9-d433-495a-b78f-6d1e8afa8bf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259302930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.4259302930
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2696119431
Short name T118
Test name
Test status
Simulation time 111332291 ps
CPU time 3.82 seconds
Started Jul 11 07:01:30 PM PDT 24
Finished Jul 11 07:01:35 PM PDT 24
Peak memory 241804 kb
Host smart-dc8337b8-b393-4732-b438-5fad78af1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696119431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2696119431
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.352054904
Short name T214
Test name
Test status
Simulation time 70561359120 ps
CPU time 629.46 seconds
Started Jul 11 06:59:04 PM PDT 24
Finished Jul 11 07:09:34 PM PDT 24
Peak memory 323728 kb
Host smart-235d12a7-64df-4fa4-961c-9aabb4f51fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352054904 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.352054904
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.3981038936
Short name T62
Test name
Test status
Simulation time 1506336198 ps
CPU time 24.03 seconds
Started Jul 11 06:53:17 PM PDT 24
Finished Jul 11 06:53:42 PM PDT 24
Peak memory 242364 kb
Host smart-21620717-7de1-4cbe-86f2-3b2bb494e1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981038936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3981038936
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2974156204
Short name T204
Test name
Test status
Simulation time 1874413753 ps
CPU time 4.1 seconds
Started Jul 11 07:01:33 PM PDT 24
Finished Jul 11 07:01:38 PM PDT 24
Peak memory 242408 kb
Host smart-76356754-ef9f-4a6d-b22e-6d1e0d2fc54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974156204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2974156204
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.4196671906
Short name T384
Test name
Test status
Simulation time 6183076342 ps
CPU time 82.93 seconds
Started Jul 11 06:55:27 PM PDT 24
Finished Jul 11 06:56:51 PM PDT 24
Peak memory 244848 kb
Host smart-34d3420c-002b-4bd5-8975-5542036e6cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196671906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.4196671906
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.844376807
Short name T304
Test name
Test status
Simulation time 128518330 ps
CPU time 1.77 seconds
Started Jul 11 06:33:45 PM PDT 24
Finished Jul 11 06:33:48 PM PDT 24
Peak memory 241724 kb
Host smart-de48b6b5-7986-491a-b160-76c62efa481a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844376807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.844376807
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3980874696
Short name T350
Test name
Test status
Simulation time 1388186550 ps
CPU time 19.11 seconds
Started Jul 11 06:33:44 PM PDT 24
Finished Jul 11 06:34:05 PM PDT 24
Peak memory 244364 kb
Host smart-fbb1851d-6454-4e55-b9e6-68ef28c4b7e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980874696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3980874696
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.431207907
Short name T39
Test name
Test status
Simulation time 784112786 ps
CPU time 4.88 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:56 PM PDT 24
Peak memory 242044 kb
Host smart-e615a8b7-6e8d-4f98-bec9-eaa163bb8e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431207907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.431207907
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2417045703
Short name T75
Test name
Test status
Simulation time 589112330 ps
CPU time 13.36 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 06:59:17 PM PDT 24
Peak memory 242112 kb
Host smart-f5b193a4-6a1b-48d2-99d9-063a5d5b0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417045703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2417045703
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2377724073
Short name T42
Test name
Test status
Simulation time 1653344960 ps
CPU time 17.16 seconds
Started Jul 11 06:54:52 PM PDT 24
Finished Jul 11 06:55:10 PM PDT 24
Peak memory 242504 kb
Host smart-8fa7fd31-dd5d-43d2-b88f-ca08fa467b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377724073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2377724073
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1580785805
Short name T50
Test name
Test status
Simulation time 688378649 ps
CPU time 13.41 seconds
Started Jul 11 06:58:03 PM PDT 24
Finished Jul 11 06:58:17 PM PDT 24
Peak memory 242608 kb
Host smart-bd3ef4d2-7f17-4e01-9e4a-636da2f3334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580785805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1580785805
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.358817960
Short name T299
Test name
Test status
Simulation time 398030462 ps
CPU time 10.48 seconds
Started Jul 11 06:58:43 PM PDT 24
Finished Jul 11 06:58:54 PM PDT 24
Peak memory 242016 kb
Host smart-b6cc76c7-56a5-4a91-a93d-cf052c2daba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358817960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.358817960
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3809390631
Short name T128
Test name
Test status
Simulation time 506079529 ps
CPU time 7.08 seconds
Started Jul 11 07:00:04 PM PDT 24
Finished Jul 11 07:00:12 PM PDT 24
Peak memory 241832 kb
Host smart-a2c5f872-8b5e-4fc1-95d9-a73fe7946a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809390631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3809390631
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.282264752
Short name T216
Test name
Test status
Simulation time 482002144 ps
CPU time 11.95 seconds
Started Jul 11 07:00:52 PM PDT 24
Finished Jul 11 07:01:05 PM PDT 24
Peak memory 241948 kb
Host smart-7c7f95ab-42bd-4d20-9be4-90d51a3d7148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282264752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.282264752
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.3303608704
Short name T179
Test name
Test status
Simulation time 428724075 ps
CPU time 6.92 seconds
Started Jul 11 07:00:54 PM PDT 24
Finished Jul 11 07:01:01 PM PDT 24
Peak memory 242364 kb
Host smart-03659fa0-2ef6-4aee-81ec-020aa898f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303608704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.3303608704
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3197337185
Short name T215
Test name
Test status
Simulation time 702557148 ps
CPU time 5.45 seconds
Started Jul 11 07:01:01 PM PDT 24
Finished Jul 11 07:01:07 PM PDT 24
Peak memory 242120 kb
Host smart-c3756b05-cc63-48e0-8648-41116d285adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197337185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3197337185
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2239966460
Short name T112
Test name
Test status
Simulation time 1806809303 ps
CPU time 19.24 seconds
Started Jul 11 06:56:07 PM PDT 24
Finished Jul 11 06:56:27 PM PDT 24
Peak memory 243264 kb
Host smart-88f86cda-7e0f-4786-9c46-b2bae0f99ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239966460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2239966460
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2603754537
Short name T221
Test name
Test status
Simulation time 1273236702 ps
CPU time 19.69 seconds
Started Jul 11 06:59:20 PM PDT 24
Finished Jul 11 06:59:42 PM PDT 24
Peak memory 241824 kb
Host smart-86946c9b-8051-45f4-b82a-461e85ccf8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603754537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2603754537
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1193150126
Short name T275
Test name
Test status
Simulation time 1351805319 ps
CPU time 17.74 seconds
Started Jul 11 06:34:07 PM PDT 24
Finished Jul 11 06:34:26 PM PDT 24
Peak memory 244288 kb
Host smart-1f8b92d4-53cd-4e7b-b463-e2ffe2a2f625
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193150126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1193150126
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.1901230078
Short name T397
Test name
Test status
Simulation time 1356886907 ps
CPU time 36.76 seconds
Started Jul 11 06:56:02 PM PDT 24
Finished Jul 11 06:56:39 PM PDT 24
Peak memory 242704 kb
Host smart-873974fc-6242-4c5a-93e7-fa7cf72db332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901230078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1901230078
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.3874963772
Short name T400
Test name
Test status
Simulation time 1190460148 ps
CPU time 26.06 seconds
Started Jul 11 06:51:53 PM PDT 24
Finished Jul 11 06:52:19 PM PDT 24
Peak memory 242364 kb
Host smart-8d3871d5-d1e0-4646-af71-216d9b9f1bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874963772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3874963772
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.2961332184
Short name T135
Test name
Test status
Simulation time 231678700203 ps
CPU time 3721.05 seconds
Started Jul 11 06:53:05 PM PDT 24
Finished Jul 11 07:55:08 PM PDT 24
Peak memory 646516 kb
Host smart-bc0b0041-b978-494e-b637-1e51f30e6817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961332184 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.2961332184
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.745899095
Short name T106
Test name
Test status
Simulation time 3612381011 ps
CPU time 11.14 seconds
Started Jul 11 06:55:50 PM PDT 24
Finished Jul 11 06:56:02 PM PDT 24
Peak memory 242032 kb
Host smart-86d4003a-b5f7-44fc-b641-47d185eea1d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745899095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.745899095
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3733623827
Short name T392
Test name
Test status
Simulation time 3955087917 ps
CPU time 130.14 seconds
Started Jul 11 06:54:33 PM PDT 24
Finished Jul 11 06:56:44 PM PDT 24
Peak memory 257092 kb
Host smart-e3127e30-4632-4639-9860-1bdf96c5c575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733623827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3733623827
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.1698881332
Short name T362
Test name
Test status
Simulation time 4367969525 ps
CPU time 18.97 seconds
Started Jul 11 06:57:45 PM PDT 24
Finished Jul 11 06:58:06 PM PDT 24
Peak memory 242068 kb
Host smart-66806206-a959-48b3-a117-38bcb50200fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698881332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1698881332
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.4116207514
Short name T243
Test name
Test status
Simulation time 70800183369 ps
CPU time 898.85 seconds
Started Jul 11 06:58:01 PM PDT 24
Finished Jul 11 07:13:01 PM PDT 24
Peak memory 267340 kb
Host smart-8b0656c2-2a68-45ac-a8b3-adc1e5f1a120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116207514 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.4116207514
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2147040881
Short name T211
Test name
Test status
Simulation time 2750871989 ps
CPU time 43.8 seconds
Started Jul 11 06:57:51 PM PDT 24
Finished Jul 11 06:58:35 PM PDT 24
Peak memory 249328 kb
Host smart-0ebcb7ab-a152-46cd-81ee-c59dc3b67526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147040881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2147040881
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.378343175
Short name T356
Test name
Test status
Simulation time 726306457 ps
CPU time 12.18 seconds
Started Jul 11 06:54:19 PM PDT 24
Finished Jul 11 06:54:32 PM PDT 24
Peak memory 242064 kb
Host smart-d89d73f5-4c9b-487b-b7d6-f965a1b845f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378343175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.378343175
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2089497339
Short name T133
Test name
Test status
Simulation time 260475162475 ps
CPU time 2904.57 seconds
Started Jul 11 06:56:20 PM PDT 24
Finished Jul 11 07:44:46 PM PDT 24
Peak memory 720144 kb
Host smart-1b111407-0d2c-410e-8f8a-1a1973278df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089497339 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2089497339
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.456085730
Short name T830
Test name
Test status
Simulation time 2731482461 ps
CPU time 5.97 seconds
Started Jul 11 07:00:13 PM PDT 24
Finished Jul 11 07:00:20 PM PDT 24
Peak memory 242240 kb
Host smart-fdb30f42-aa51-438d-879c-58ff7612903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456085730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.456085730
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.4000224173
Short name T148
Test name
Test status
Simulation time 244499992 ps
CPU time 3.96 seconds
Started Jul 11 07:00:46 PM PDT 24
Finished Jul 11 07:00:51 PM PDT 24
Peak memory 242180 kb
Host smart-79207bbf-3298-4d50-8f68-5d98c8eb0593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000224173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.4000224173
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.3555298063
Short name T370
Test name
Test status
Simulation time 6107168171 ps
CPU time 42.26 seconds
Started Jul 11 06:58:36 PM PDT 24
Finished Jul 11 06:59:19 PM PDT 24
Peak memory 242104 kb
Host smart-1bad0e49-58c9-4611-b6ce-aafdeab7935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555298063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3555298063
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.3884288907
Short name T1039
Test name
Test status
Simulation time 1554314129 ps
CPU time 30.11 seconds
Started Jul 11 06:52:24 PM PDT 24
Finished Jul 11 06:52:55 PM PDT 24
Peak memory 242008 kb
Host smart-c8208283-4812-4f72-98e0-1ba6c3ef0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884288907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3884288907
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.937714267
Short name T272
Test name
Test status
Simulation time 438378041 ps
CPU time 6.34 seconds
Started Jul 11 06:32:44 PM PDT 24
Finished Jul 11 06:32:52 PM PDT 24
Peak memory 239200 kb
Host smart-1383e39b-7685-4ccc-bf8e-06a41df5f34d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937714267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.937714267
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.901213688
Short name T316
Test name
Test status
Simulation time 532632632 ps
CPU time 1.82 seconds
Started Jul 11 06:32:58 PM PDT 24
Finished Jul 11 06:33:01 PM PDT 24
Peak memory 241468 kb
Host smart-a14e87f2-f378-4ee9-8a02-d2d979156824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901213688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.901213688
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1487718269
Short name T255
Test name
Test status
Simulation time 514825671272 ps
CPU time 1340.05 seconds
Started Jul 11 06:53:33 PM PDT 24
Finished Jul 11 07:15:54 PM PDT 24
Peak memory 330428 kb
Host smart-bca6aca8-8513-45f7-83be-e13b67ab9083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487718269 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1487718269
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1724214622
Short name T230
Test name
Test status
Simulation time 53754739 ps
CPU time 1.65 seconds
Started Jul 11 06:51:40 PM PDT 24
Finished Jul 11 06:51:43 PM PDT 24
Peak memory 240240 kb
Host smart-127d25b9-8cb6-47aa-94a8-115d22f18a62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1724214622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1724214622
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3790803610
Short name T1009
Test name
Test status
Simulation time 463687327 ps
CPU time 3.68 seconds
Started Jul 11 07:00:52 PM PDT 24
Finished Jul 11 07:00:57 PM PDT 24
Peak memory 241944 kb
Host smart-c4fde4de-8b91-4df6-8642-ae6401238201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790803610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3790803610
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.3831125083
Short name T234
Test name
Test status
Simulation time 84507986936 ps
CPU time 594.34 seconds
Started Jul 11 06:56:55 PM PDT 24
Finished Jul 11 07:06:51 PM PDT 24
Peak memory 311616 kb
Host smart-02862c68-8786-49d8-882b-b2c8aa4a6a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831125083 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.3831125083
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.4091111594
Short name T270
Test name
Test status
Simulation time 2386489345 ps
CPU time 22.4 seconds
Started Jul 11 06:33:02 PM PDT 24
Finished Jul 11 06:33:25 PM PDT 24
Peak memory 245688 kb
Host smart-e3f025df-94a0-4439-8b5f-b63514a73ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091111594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.4091111594
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.717097663
Short name T257
Test name
Test status
Simulation time 901316238 ps
CPU time 20.93 seconds
Started Jul 11 06:54:37 PM PDT 24
Finished Jul 11 06:54:59 PM PDT 24
Peak memory 242028 kb
Host smart-c9d35be1-e3d0-43c7-a503-9ca1edb42275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717097663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.717097663
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.766728777
Short name T256
Test name
Test status
Simulation time 283682873 ps
CPU time 4.09 seconds
Started Jul 11 07:01:54 PM PDT 24
Finished Jul 11 07:01:59 PM PDT 24
Peak memory 241964 kb
Host smart-df53cee4-578f-4e2a-ba4e-b0d0b7d48504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766728777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.766728777
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3544867417
Short name T61
Test name
Test status
Simulation time 7334220260 ps
CPU time 19.59 seconds
Started Jul 11 06:54:28 PM PDT 24
Finished Jul 11 06:54:48 PM PDT 24
Peak memory 243284 kb
Host smart-68c693e9-8ac8-49d4-ae60-3b7ee621f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544867417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3544867417
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.1780187971
Short name T96
Test name
Test status
Simulation time 420116286 ps
CPU time 14.45 seconds
Started Jul 11 06:58:24 PM PDT 24
Finished Jul 11 06:58:39 PM PDT 24
Peak memory 248732 kb
Host smart-29ef40d4-84c4-4099-b0ca-33a29e429aec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780187971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1780187971
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.372177678
Short name T86
Test name
Test status
Simulation time 102814044 ps
CPU time 3.43 seconds
Started Jul 11 07:00:52 PM PDT 24
Finished Jul 11 07:00:57 PM PDT 24
Peak memory 242296 kb
Host smart-b6c15c30-e940-4f28-855e-90f689021a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372177678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.372177678
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.2992199876
Short name T85
Test name
Test status
Simulation time 472234292 ps
CPU time 4.14 seconds
Started Jul 11 06:59:14 PM PDT 24
Finished Jul 11 06:59:19 PM PDT 24
Peak memory 242140 kb
Host smart-1986f6e8-3197-455d-95d9-f1eb2798c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992199876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2992199876
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2798247992
Short name T103
Test name
Test status
Simulation time 7720018862 ps
CPU time 37.53 seconds
Started Jul 11 06:57:37 PM PDT 24
Finished Jul 11 06:58:16 PM PDT 24
Peak memory 243284 kb
Host smart-7e98857a-b9fd-495a-9130-be348de169f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798247992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2798247992
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.1432280558
Short name T1161
Test name
Test status
Simulation time 625337466 ps
CPU time 5.21 seconds
Started Jul 11 06:59:11 PM PDT 24
Finished Jul 11 06:59:18 PM PDT 24
Peak memory 241932 kb
Host smart-9d336cea-6110-49f4-929e-83717bb3f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432280558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1432280558
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.2597499227
Short name T502
Test name
Test status
Simulation time 575098828 ps
CPU time 17.37 seconds
Started Jul 11 06:52:07 PM PDT 24
Finished Jul 11 06:52:26 PM PDT 24
Peak memory 241788 kb
Host smart-6bb90a5d-55e1-4372-862e-bd3a72920a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597499227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2597499227
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1412068928
Short name T1301
Test name
Test status
Simulation time 136132502 ps
CPU time 3.22 seconds
Started Jul 11 06:32:45 PM PDT 24
Finished Jul 11 06:32:51 PM PDT 24
Peak memory 230948 kb
Host smart-5f50378b-9ce2-484b-98cd-7d86995f7b3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412068928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1412068928
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2873863081
Short name T297
Test name
Test status
Simulation time 258308680 ps
CPU time 1.86 seconds
Started Jul 11 06:32:41 PM PDT 24
Finished Jul 11 06:32:44 PM PDT 24
Peak memory 239184 kb
Host smart-23e436c9-1297-41a3-b84a-d50032c9b292
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873863081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2873863081
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2881555010
Short name T1207
Test name
Test status
Simulation time 77229856 ps
CPU time 2.19 seconds
Started Jul 11 06:32:46 PM PDT 24
Finished Jul 11 06:32:50 PM PDT 24
Peak memory 245068 kb
Host smart-5b393e48-07c1-4831-88c5-b3ed66668636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881555010 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2881555010
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1495021167
Short name T1246
Test name
Test status
Simulation time 45155549 ps
CPU time 1.58 seconds
Started Jul 11 06:32:40 PM PDT 24
Finished Jul 11 06:32:43 PM PDT 24
Peak memory 240884 kb
Host smart-5cfa83d1-ab82-4d18-b954-82a512889e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495021167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1495021167
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1918977973
Short name T1298
Test name
Test status
Simulation time 145646083 ps
CPU time 1.55 seconds
Started Jul 11 06:32:41 PM PDT 24
Finished Jul 11 06:32:44 PM PDT 24
Peak memory 230596 kb
Host smart-d0cf10ba-7da6-4ecc-8e9c-0829e4284180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918977973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1918977973
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1509100663
Short name T1283
Test name
Test status
Simulation time 130404259 ps
CPU time 1.35 seconds
Started Jul 11 06:32:41 PM PDT 24
Finished Jul 11 06:32:43 PM PDT 24
Peak memory 229812 kb
Host smart-3a800028-7c48-47ef-9126-20b73468dcd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509100663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1509100663
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2462970039
Short name T1226
Test name
Test status
Simulation time 38889667 ps
CPU time 1.36 seconds
Started Jul 11 06:32:41 PM PDT 24
Finished Jul 11 06:32:43 PM PDT 24
Peak memory 230776 kb
Host smart-d9bf1ac6-16aa-44b7-a70b-aafc820cc85c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462970039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.2462970039
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1361522392
Short name T1295
Test name
Test status
Simulation time 670544960 ps
CPU time 2.28 seconds
Started Jul 11 06:32:47 PM PDT 24
Finished Jul 11 06:32:51 PM PDT 24
Peak memory 242228 kb
Host smart-1099c2fa-f561-4874-9228-8718d6da5f79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361522392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1361522392
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1775378259
Short name T1262
Test name
Test status
Simulation time 130925999 ps
CPU time 4.17 seconds
Started Jul 11 06:32:35 PM PDT 24
Finished Jul 11 06:32:41 PM PDT 24
Peak memory 247280 kb
Host smart-f2fb814d-4fed-4f60-9e28-ad6c472a7624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775378259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1775378259
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1217757480
Short name T351
Test name
Test status
Simulation time 2548567752 ps
CPU time 14.08 seconds
Started Jul 11 06:32:40 PM PDT 24
Finished Jul 11 06:32:55 PM PDT 24
Peak memory 244360 kb
Host smart-83314158-6215-4879-b500-88c64c42141e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217757480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.1217757480
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2048129641
Short name T273
Test name
Test status
Simulation time 198082450 ps
CPU time 6.7 seconds
Started Jul 11 06:32:58 PM PDT 24
Finished Jul 11 06:33:07 PM PDT 24
Peak memory 239144 kb
Host smart-95b13090-6800-41d6-8ec3-ceaf9ce4d09f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048129641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.2048129641
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2778660472
Short name T322
Test name
Test status
Simulation time 123151963 ps
CPU time 6.36 seconds
Started Jul 11 06:32:59 PM PDT 24
Finished Jul 11 06:33:06 PM PDT 24
Peak memory 239236 kb
Host smart-35b9668e-0bfb-43fb-9d96-9d456d869571
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778660472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.2778660472
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1079688222
Short name T1242
Test name
Test status
Simulation time 185409556 ps
CPU time 2.12 seconds
Started Jul 11 06:32:58 PM PDT 24
Finished Jul 11 06:33:02 PM PDT 24
Peak memory 240728 kb
Host smart-a3d1239c-2c61-4780-99d6-cbd7ca054ff8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079688222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1079688222
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2621402545
Short name T1264
Test name
Test status
Simulation time 71336696 ps
CPU time 2.16 seconds
Started Jul 11 06:32:59 PM PDT 24
Finished Jul 11 06:33:02 PM PDT 24
Peak memory 245988 kb
Host smart-9dfbd401-a3b6-40e2-b816-2d38fbe0098f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621402545 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2621402545
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1481108523
Short name T1213
Test name
Test status
Simulation time 154605559 ps
CPU time 1.75 seconds
Started Jul 11 06:32:46 PM PDT 24
Finished Jul 11 06:32:50 PM PDT 24
Peak memory 231028 kb
Host smart-a2f046a2-9b6e-436c-9dc5-2edbea0f4d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481108523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1481108523
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2690585498
Short name T1312
Test name
Test status
Simulation time 146397165 ps
CPU time 1.4 seconds
Started Jul 11 06:32:56 PM PDT 24
Finished Jul 11 06:33:00 PM PDT 24
Peak memory 230188 kb
Host smart-cb54d74d-f296-41d3-a88a-0146683e7090
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690585498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2690585498
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2778018649
Short name T1222
Test name
Test status
Simulation time 68661314 ps
CPU time 1.32 seconds
Started Jul 11 06:32:46 PM PDT 24
Finished Jul 11 06:32:49 PM PDT 24
Peak memory 230204 kb
Host smart-6c835c23-0f64-41b9-b1e3-2683ebf09486
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778018649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2778018649
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1022674031
Short name T1276
Test name
Test status
Simulation time 214465352 ps
CPU time 2.68 seconds
Started Jul 11 06:32:58 PM PDT 24
Finished Jul 11 06:33:02 PM PDT 24
Peak memory 242356 kb
Host smart-37357034-c895-4c6c-b4e0-34e5f8738adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022674031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.1022674031
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2044338788
Short name T1230
Test name
Test status
Simulation time 276276065 ps
CPU time 5.04 seconds
Started Jul 11 06:32:45 PM PDT 24
Finished Jul 11 06:32:52 PM PDT 24
Peak memory 246616 kb
Host smart-be6e9268-ed05-4584-9cf2-9dc559065b56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044338788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2044338788
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1156929354
Short name T346
Test name
Test status
Simulation time 648379220 ps
CPU time 10.58 seconds
Started Jul 11 06:32:45 PM PDT 24
Finished Jul 11 06:32:58 PM PDT 24
Peak memory 243796 kb
Host smart-cbaed64a-3255-42eb-aa2a-f7b158062ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156929354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1156929354
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2557071920
Short name T1204
Test name
Test status
Simulation time 282061352 ps
CPU time 2.16 seconds
Started Jul 11 06:33:47 PM PDT 24
Finished Jul 11 06:33:51 PM PDT 24
Peak memory 244872 kb
Host smart-62579417-6842-4de5-99f1-571ee9c4ba31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557071920 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2557071920
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.748706859
Short name T302
Test name
Test status
Simulation time 48767188 ps
CPU time 1.72 seconds
Started Jul 11 06:33:40 PM PDT 24
Finished Jul 11 06:33:42 PM PDT 24
Peak memory 241248 kb
Host smart-763f4423-6535-4735-9974-353d6e222358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748706859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.748706859
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1752541049
Short name T1307
Test name
Test status
Simulation time 90040981 ps
CPU time 1.43 seconds
Started Jul 11 06:33:41 PM PDT 24
Finished Jul 11 06:33:44 PM PDT 24
Peak memory 231084 kb
Host smart-4e50131a-c734-41d9-bd6c-e20c9af56a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752541049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1752541049
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2964475087
Short name T1263
Test name
Test status
Simulation time 285889159 ps
CPU time 2.29 seconds
Started Jul 11 06:33:44 PM PDT 24
Finished Jul 11 06:33:48 PM PDT 24
Peak memory 239192 kb
Host smart-d4c0d66f-6bea-408f-a15d-496be5373cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964475087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2964475087
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.477167376
Short name T1275
Test name
Test status
Simulation time 1207961224 ps
CPU time 5.96 seconds
Started Jul 11 06:33:42 PM PDT 24
Finished Jul 11 06:33:49 PM PDT 24
Peak memory 246952 kb
Host smart-5c9bac5d-be40-4aec-8fe2-0e6b5903202b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477167376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.477167376
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2815563453
Short name T1296
Test name
Test status
Simulation time 2465721010 ps
CPU time 11.38 seconds
Started Jul 11 06:33:39 PM PDT 24
Finished Jul 11 06:33:51 PM PDT 24
Peak memory 244204 kb
Host smart-0ac9e03d-a4db-488e-aa3f-314c017ff9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815563453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.2815563453
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.594201625
Short name T1254
Test name
Test status
Simulation time 262388777 ps
CPU time 2.34 seconds
Started Jul 11 06:33:50 PM PDT 24
Finished Jul 11 06:33:53 PM PDT 24
Peak memory 244164 kb
Host smart-e0b27936-5d7d-468d-8ced-1d3574417eef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594201625 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.594201625
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1527700186
Short name T1214
Test name
Test status
Simulation time 38409145 ps
CPU time 1.38 seconds
Started Jul 11 06:33:43 PM PDT 24
Finished Jul 11 06:33:46 PM PDT 24
Peak memory 230580 kb
Host smart-45a66873-216b-4713-84ad-68c5e0786b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527700186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1527700186
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.705967289
Short name T1289
Test name
Test status
Simulation time 107868664 ps
CPU time 3.1 seconds
Started Jul 11 06:33:49 PM PDT 24
Finished Jul 11 06:33:53 PM PDT 24
Peak memory 239304 kb
Host smart-1d7e6ba6-b214-4b1a-8505-783a6a9e4eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705967289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_c
trl_same_csr_outstanding.705967289
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3537481236
Short name T1299
Test name
Test status
Simulation time 446457736 ps
CPU time 4.85 seconds
Started Jul 11 06:33:43 PM PDT 24
Finished Jul 11 06:33:49 PM PDT 24
Peak memory 246328 kb
Host smart-161e1669-8c12-4c7f-a9fe-de04b3221a13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537481236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3537481236
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1165381437
Short name T1215
Test name
Test status
Simulation time 208612410 ps
CPU time 3.15 seconds
Started Jul 11 06:33:53 PM PDT 24
Finished Jul 11 06:33:57 PM PDT 24
Peak memory 247360 kb
Host smart-872fcc5d-9081-498c-93ff-c4e4aaa64f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165381437 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1165381437
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3976709061
Short name T1292
Test name
Test status
Simulation time 74326808 ps
CPU time 1.53 seconds
Started Jul 11 06:33:57 PM PDT 24
Finished Jul 11 06:33:59 PM PDT 24
Peak memory 239236 kb
Host smart-0e91243d-77ac-4705-be39-0ac3ef815eba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976709061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3976709061
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.229595907
Short name T1233
Test name
Test status
Simulation time 43635944 ps
CPU time 1.5 seconds
Started Jul 11 06:33:50 PM PDT 24
Finished Jul 11 06:33:53 PM PDT 24
Peak memory 231116 kb
Host smart-235bb17d-b4c6-4239-8a92-9d22f6afa9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229595907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.229595907
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1822200318
Short name T1313
Test name
Test status
Simulation time 85910360 ps
CPU time 1.93 seconds
Started Jul 11 06:33:58 PM PDT 24
Finished Jul 11 06:34:01 PM PDT 24
Peak memory 239208 kb
Host smart-98694471-d02b-4c8a-afaf-05583fa89027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822200318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1822200318
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3381917603
Short name T1323
Test name
Test status
Simulation time 79926192 ps
CPU time 3.45 seconds
Started Jul 11 06:33:51 PM PDT 24
Finished Jul 11 06:33:55 PM PDT 24
Peak memory 246120 kb
Host smart-d4b203af-fd54-4e92-95a3-dbfab24f98b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381917603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3381917603
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.17546682
Short name T352
Test name
Test status
Simulation time 2500872293 ps
CPU time 19.92 seconds
Started Jul 11 06:33:49 PM PDT 24
Finished Jul 11 06:34:10 PM PDT 24
Peak memory 244812 kb
Host smart-e9be9de3-6b1f-457d-a2e2-54f84e78e4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_int
g_err.17546682
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.454120300
Short name T1221
Test name
Test status
Simulation time 206668698 ps
CPU time 2.81 seconds
Started Jul 11 06:34:04 PM PDT 24
Finished Jul 11 06:34:08 PM PDT 24
Peak memory 247092 kb
Host smart-18fa09de-f3f0-4294-9b99-23c5d15e4de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454120300 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.454120300
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.465083103
Short name T1284
Test name
Test status
Simulation time 54744048 ps
CPU time 1.57 seconds
Started Jul 11 06:33:53 PM PDT 24
Finished Jul 11 06:33:56 PM PDT 24
Peak memory 240912 kb
Host smart-4b1c2d1f-8f1d-4cff-b557-3898bdf56c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465083103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.465083103
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2641709835
Short name T1234
Test name
Test status
Simulation time 516891804 ps
CPU time 1.68 seconds
Started Jul 11 06:33:56 PM PDT 24
Finished Jul 11 06:33:58 PM PDT 24
Peak memory 231056 kb
Host smart-e9988ae5-89db-40f3-8c11-3b301e8f0357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641709835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2641709835
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1741808293
Short name T1241
Test name
Test status
Simulation time 256106300 ps
CPU time 2.4 seconds
Started Jul 11 06:33:59 PM PDT 24
Finished Jul 11 06:34:03 PM PDT 24
Peak memory 239448 kb
Host smart-1a70a891-0096-4452-8cbc-99af1a0496ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741808293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1741808293
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2978277426
Short name T1269
Test name
Test status
Simulation time 58017638 ps
CPU time 3.04 seconds
Started Jul 11 06:33:56 PM PDT 24
Finished Jul 11 06:33:59 PM PDT 24
Peak memory 246488 kb
Host smart-f39bac9b-f898-4996-9812-21c44e29ad1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978277426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2978277426
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.245627422
Short name T1268
Test name
Test status
Simulation time 4906338366 ps
CPU time 19.8 seconds
Started Jul 11 06:33:54 PM PDT 24
Finished Jul 11 06:34:15 PM PDT 24
Peak memory 239412 kb
Host smart-a5c5f841-3128-4d87-a8a6-52a205fcf2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245627422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.245627422
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.366016332
Short name T1326
Test name
Test status
Simulation time 266473952 ps
CPU time 2.56 seconds
Started Jul 11 06:34:01 PM PDT 24
Finished Jul 11 06:34:04 PM PDT 24
Peak memory 247432 kb
Host smart-2bac0232-1d11-41b6-8aa3-21f4e6513b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366016332 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.366016332
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2890919566
Short name T309
Test name
Test status
Simulation time 37675450 ps
CPU time 1.65 seconds
Started Jul 11 06:33:59 PM PDT 24
Finished Jul 11 06:34:01 PM PDT 24
Peak memory 241268 kb
Host smart-c2d9b70e-c396-4109-a1ca-d59faebcb0ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890919566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2890919566
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2582303622
Short name T1202
Test name
Test status
Simulation time 40939317 ps
CPU time 1.56 seconds
Started Jul 11 06:34:05 PM PDT 24
Finished Jul 11 06:34:09 PM PDT 24
Peak memory 230432 kb
Host smart-13b61d87-b12d-473d-8ec4-4290b1693eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582303622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2582303622
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3750920069
Short name T315
Test name
Test status
Simulation time 44029707 ps
CPU time 1.95 seconds
Started Jul 11 06:34:02 PM PDT 24
Finished Jul 11 06:34:05 PM PDT 24
Peak memory 242348 kb
Host smart-b8d24721-a9a1-4f78-ac38-6b5877e4e8b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750920069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.3750920069
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3711625831
Short name T1317
Test name
Test status
Simulation time 152490779 ps
CPU time 6.36 seconds
Started Jul 11 06:34:00 PM PDT 24
Finished Jul 11 06:34:07 PM PDT 24
Peak memory 246596 kb
Host smart-96e0715f-da15-430a-ac11-663928c83a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711625831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3711625831
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3784499787
Short name T1327
Test name
Test status
Simulation time 6279528642 ps
CPU time 34.31 seconds
Started Jul 11 06:33:59 PM PDT 24
Finished Jul 11 06:34:34 PM PDT 24
Peak memory 246080 kb
Host smart-c52cdca7-92f8-4f1d-b7dd-c5f2c2d12cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784499787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3784499787
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1239658388
Short name T1310
Test name
Test status
Simulation time 123203642 ps
CPU time 2.05 seconds
Started Jul 11 06:33:57 PM PDT 24
Finished Jul 11 06:34:00 PM PDT 24
Peak memory 245720 kb
Host smart-678bd4c6-3306-44d9-9611-3c0982e441f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239658388 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1239658388
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2000071128
Short name T1322
Test name
Test status
Simulation time 155372145 ps
CPU time 1.71 seconds
Started Jul 11 06:33:59 PM PDT 24
Finished Jul 11 06:34:02 PM PDT 24
Peak memory 241148 kb
Host smart-b1418d7d-d9ff-4886-850d-2fc94014f615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000071128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2000071128
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2462892935
Short name T1304
Test name
Test status
Simulation time 69675572 ps
CPU time 1.3 seconds
Started Jul 11 06:33:58 PM PDT 24
Finished Jul 11 06:34:01 PM PDT 24
Peak memory 230360 kb
Host smart-95318bbc-6368-4f0b-9015-0867b378f60c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462892935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2462892935
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3246758436
Short name T1303
Test name
Test status
Simulation time 210393143 ps
CPU time 3.72 seconds
Started Jul 11 06:33:58 PM PDT 24
Finished Jul 11 06:34:03 PM PDT 24
Peak memory 239180 kb
Host smart-f6069563-8df4-45a7-a9af-3dbdf86ddbde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246758436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.3246758436
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1809771572
Short name T1305
Test name
Test status
Simulation time 97992683 ps
CPU time 4.19 seconds
Started Jul 11 06:34:04 PM PDT 24
Finished Jul 11 06:34:09 PM PDT 24
Peak memory 239296 kb
Host smart-b6c301a7-720e-466f-851b-a0fbbba9851f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809771572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1809771572
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.304368777
Short name T347
Test name
Test status
Simulation time 4759157916 ps
CPU time 24.91 seconds
Started Jul 11 06:33:57 PM PDT 24
Finished Jul 11 06:34:23 PM PDT 24
Peak memory 245160 kb
Host smart-113ea0e2-e138-41f6-b640-2d147f0e510d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304368777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.304368777
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2058434185
Short name T1294
Test name
Test status
Simulation time 201573159 ps
CPU time 3.12 seconds
Started Jul 11 06:34:02 PM PDT 24
Finished Jul 11 06:34:07 PM PDT 24
Peak memory 247368 kb
Host smart-9d735cf2-b25f-41bc-badd-2cd5bd718b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058434185 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2058434185
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3534554488
Short name T296
Test name
Test status
Simulation time 71404732 ps
CPU time 1.53 seconds
Started Jul 11 06:34:03 PM PDT 24
Finished Jul 11 06:34:05 PM PDT 24
Peak memory 239312 kb
Host smart-07641bff-c4d6-47a3-9516-9b31c3f507c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534554488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3534554488
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.325875618
Short name T1227
Test name
Test status
Simulation time 38638535 ps
CPU time 1.39 seconds
Started Jul 11 06:34:02 PM PDT 24
Finished Jul 11 06:34:05 PM PDT 24
Peak memory 230324 kb
Host smart-82dfdaa5-aefc-499d-a16f-89893ebef057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325875618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.325875618
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3396423652
Short name T276
Test name
Test status
Simulation time 438038064 ps
CPU time 3.65 seconds
Started Jul 11 06:34:02 PM PDT 24
Finished Jul 11 06:34:06 PM PDT 24
Peak memory 239212 kb
Host smart-42fa983e-f529-4c15-b88c-5e1a6c40f6cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396423652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.3396423652
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3739783829
Short name T1216
Test name
Test status
Simulation time 174991142 ps
CPU time 3.83 seconds
Started Jul 11 06:33:59 PM PDT 24
Finished Jul 11 06:34:04 PM PDT 24
Peak memory 246372 kb
Host smart-f85518b0-de58-42f6-a1db-5097c8d159a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739783829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3739783829
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.698769350
Short name T1272
Test name
Test status
Simulation time 2352731141 ps
CPU time 12.11 seconds
Started Jul 11 06:34:04 PM PDT 24
Finished Jul 11 06:34:18 PM PDT 24
Peak memory 244092 kb
Host smart-6469b24f-fe7a-463b-80ce-7aca45c9178b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698769350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_in
tg_err.698769350
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.525716431
Short name T1219
Test name
Test status
Simulation time 72401213 ps
CPU time 2.85 seconds
Started Jul 11 06:34:03 PM PDT 24
Finished Jul 11 06:34:08 PM PDT 24
Peak memory 247432 kb
Host smart-a45d2fbb-221f-4130-8987-af0bab74988f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525716431 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.525716431
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3968645959
Short name T305
Test name
Test status
Simulation time 82192602 ps
CPU time 1.63 seconds
Started Jul 11 06:34:03 PM PDT 24
Finished Jul 11 06:34:06 PM PDT 24
Peak memory 239228 kb
Host smart-509484ef-dca8-4db0-9f10-e52bf4ac1e94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968645959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3968645959
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1348204733
Short name T1300
Test name
Test status
Simulation time 79239340 ps
CPU time 1.49 seconds
Started Jul 11 06:34:03 PM PDT 24
Finished Jul 11 06:34:06 PM PDT 24
Peak memory 231120 kb
Host smart-5b808932-4013-44d9-bbab-60f8a04fb632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348204733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1348204733
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3399180282
Short name T1261
Test name
Test status
Simulation time 678961398 ps
CPU time 3.04 seconds
Started Jul 11 06:34:04 PM PDT 24
Finished Jul 11 06:34:08 PM PDT 24
Peak memory 239204 kb
Host smart-0a910c42-af67-4944-9116-0194b458c156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399180282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.3399180282
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1470701046
Short name T1278
Test name
Test status
Simulation time 200710487 ps
CPU time 3.14 seconds
Started Jul 11 06:34:03 PM PDT 24
Finished Jul 11 06:34:07 PM PDT 24
Peak memory 246436 kb
Host smart-a4eb740d-3e4c-4c44-b57e-a3c28c481c90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470701046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1470701046
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.538112463
Short name T1271
Test name
Test status
Simulation time 1521122849 ps
CPU time 4.9 seconds
Started Jul 11 06:34:07 PM PDT 24
Finished Jul 11 06:34:14 PM PDT 24
Peak memory 247436 kb
Host smart-f57a935b-f94e-43db-be14-a5a7518c9314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538112463 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.538112463
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2685727657
Short name T306
Test name
Test status
Simulation time 149446409 ps
CPU time 1.76 seconds
Started Jul 11 06:34:07 PM PDT 24
Finished Jul 11 06:34:10 PM PDT 24
Peak memory 239408 kb
Host smart-7593efce-3895-4771-8d46-360be0223702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685727657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.2685727657
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1493987885
Short name T1200
Test name
Test status
Simulation time 145340058 ps
CPU time 1.49 seconds
Started Jul 11 06:34:05 PM PDT 24
Finished Jul 11 06:34:09 PM PDT 24
Peak memory 230620 kb
Host smart-2724e0b0-0e31-41e0-842b-9df58ff1c51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493987885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1493987885
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.651558509
Short name T313
Test name
Test status
Simulation time 67998048 ps
CPU time 2.08 seconds
Started Jul 11 06:34:05 PM PDT 24
Finished Jul 11 06:34:09 PM PDT 24
Peak memory 239128 kb
Host smart-73254886-b6ac-48e2-9595-583fca7ff811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651558509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c
trl_same_csr_outstanding.651558509
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.842186614
Short name T1265
Test name
Test status
Simulation time 389778415 ps
CPU time 4.49 seconds
Started Jul 11 06:34:07 PM PDT 24
Finished Jul 11 06:34:13 PM PDT 24
Peak memory 246232 kb
Host smart-f0b68595-acb3-405d-a482-102d8bd7fe3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842186614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.842186614
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1122503073
Short name T365
Test name
Test status
Simulation time 69444744 ps
CPU time 1.93 seconds
Started Jul 11 06:34:10 PM PDT 24
Finished Jul 11 06:34:14 PM PDT 24
Peak memory 244104 kb
Host smart-9be58264-a181-4bbb-a992-a8bd3cf51c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122503073 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1122503073
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.259308198
Short name T1288
Test name
Test status
Simulation time 49043197 ps
CPU time 1.75 seconds
Started Jul 11 06:34:07 PM PDT 24
Finished Jul 11 06:34:10 PM PDT 24
Peak memory 239256 kb
Host smart-7d2ae63f-fc05-438b-a2a6-907dcac669dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259308198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.259308198
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.887621536
Short name T1238
Test name
Test status
Simulation time 585032329 ps
CPU time 1.57 seconds
Started Jul 11 06:34:11 PM PDT 24
Finished Jul 11 06:34:13 PM PDT 24
Peak memory 230580 kb
Host smart-ad134d83-054e-4b05-a0e0-19e11a00e007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887621536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.887621536
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1942038326
Short name T1258
Test name
Test status
Simulation time 205106542 ps
CPU time 2.72 seconds
Started Jul 11 06:34:11 PM PDT 24
Finished Jul 11 06:34:15 PM PDT 24
Peak memory 242180 kb
Host smart-e8bb33dd-c179-4c5c-b742-09a9906631ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942038326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1942038326
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2627143498
Short name T1199
Test name
Test status
Simulation time 335870011 ps
CPU time 6.43 seconds
Started Jul 11 06:34:11 PM PDT 24
Finished Jul 11 06:34:19 PM PDT 24
Peak memory 246288 kb
Host smart-4cabed43-5f23-4f46-997d-2960d12528a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627143498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2627143498
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2835659937
Short name T269
Test name
Test status
Simulation time 2977617174 ps
CPU time 10.08 seconds
Started Jul 11 06:34:06 PM PDT 24
Finished Jul 11 06:34:18 PM PDT 24
Peak memory 239404 kb
Host smart-93492883-941b-4c33-bcb0-0721fabde32d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835659937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2835659937
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.954901376
Short name T1311
Test name
Test status
Simulation time 723024555 ps
CPU time 7.27 seconds
Started Jul 11 06:33:07 PM PDT 24
Finished Jul 11 06:33:15 PM PDT 24
Peak memory 239200 kb
Host smart-adbe1e83-268e-4543-956c-8f0670dba56f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954901376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.954901376
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3325708052
Short name T1290
Test name
Test status
Simulation time 6267212524 ps
CPU time 13.28 seconds
Started Jul 11 06:33:10 PM PDT 24
Finished Jul 11 06:33:26 PM PDT 24
Peak memory 239180 kb
Host smart-c55d5e51-6b75-4e4d-976c-7a343e9ae7c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325708052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3325708052
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.792142892
Short name T307
Test name
Test status
Simulation time 362619982 ps
CPU time 2.66 seconds
Started Jul 11 06:33:07 PM PDT 24
Finished Jul 11 06:33:11 PM PDT 24
Peak memory 241372 kb
Host smart-20c205fd-914e-4135-a817-51eec31e3c1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792142892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.792142892
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3953923344
Short name T1247
Test name
Test status
Simulation time 293980925 ps
CPU time 2.55 seconds
Started Jul 11 06:33:10 PM PDT 24
Finished Jul 11 06:33:15 PM PDT 24
Peak memory 245364 kb
Host smart-2ec8dda3-4572-4a47-a760-5c4edc27b5d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953923344 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3953923344
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1741622181
Short name T319
Test name
Test status
Simulation time 153866283 ps
CPU time 1.87 seconds
Started Jul 11 06:33:08 PM PDT 24
Finished Jul 11 06:33:11 PM PDT 24
Peak memory 241400 kb
Host smart-58ad4985-5597-4655-b879-86f54463e876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741622181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1741622181
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3397654864
Short name T1243
Test name
Test status
Simulation time 42902961 ps
CPU time 1.46 seconds
Started Jul 11 06:33:02 PM PDT 24
Finished Jul 11 06:33:04 PM PDT 24
Peak memory 231072 kb
Host smart-980ab6bd-4e60-4a3e-b1d8-dfd961265307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397654864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3397654864
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2198250921
Short name T1291
Test name
Test status
Simulation time 136308518 ps
CPU time 1.42 seconds
Started Jul 11 06:33:02 PM PDT 24
Finished Jul 11 06:33:04 PM PDT 24
Peak memory 230212 kb
Host smart-fcf3b7a4-7afe-46b4-a2b8-00e9d78ca699
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198250921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.2198250921
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3433522447
Short name T1198
Test name
Test status
Simulation time 73244391 ps
CPU time 1.38 seconds
Started Jul 11 06:33:02 PM PDT 24
Finished Jul 11 06:33:04 PM PDT 24
Peak memory 230788 kb
Host smart-022c4a98-8877-4670-9376-4bcf886c26aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433522447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3433522447
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2283742205
Short name T1308
Test name
Test status
Simulation time 247950449 ps
CPU time 2.22 seconds
Started Jul 11 06:33:09 PM PDT 24
Finished Jul 11 06:33:13 PM PDT 24
Peak memory 239288 kb
Host smart-bdca5093-7571-4948-822b-443a3ad969f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283742205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.2283742205
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3101868287
Short name T1231
Test name
Test status
Simulation time 1055774548 ps
CPU time 5.64 seconds
Started Jul 11 06:33:00 PM PDT 24
Finished Jul 11 06:33:07 PM PDT 24
Peak memory 246428 kb
Host smart-2752c002-c1ec-4ad6-b41e-1c62d0cf72e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101868287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3101868287
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.799226556
Short name T1218
Test name
Test status
Simulation time 73250413 ps
CPU time 1.38 seconds
Started Jul 11 06:34:12 PM PDT 24
Finished Jul 11 06:34:14 PM PDT 24
Peak memory 231036 kb
Host smart-24061a12-e538-43ef-8c0b-8f890ab27ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799226556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.799226556
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2876348247
Short name T1267
Test name
Test status
Simulation time 84855515 ps
CPU time 1.43 seconds
Started Jul 11 06:34:09 PM PDT 24
Finished Jul 11 06:34:12 PM PDT 24
Peak memory 230600 kb
Host smart-7b01720f-6594-4176-b5b6-eeaf81e3ff19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876348247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2876348247
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.4053831457
Short name T1245
Test name
Test status
Simulation time 41517624 ps
CPU time 1.44 seconds
Started Jul 11 06:34:09 PM PDT 24
Finished Jul 11 06:34:13 PM PDT 24
Peak memory 230652 kb
Host smart-f6253d5c-492e-4776-9559-fbbe8b15be42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053831457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.4053831457
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2070373315
Short name T1223
Test name
Test status
Simulation time 132527363 ps
CPU time 1.39 seconds
Started Jul 11 06:34:09 PM PDT 24
Finished Jul 11 06:34:12 PM PDT 24
Peak memory 230624 kb
Host smart-0cafbfde-4f05-466a-9aaa-c1732c7c6270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070373315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2070373315
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2916112532
Short name T1319
Test name
Test status
Simulation time 73257396 ps
CPU time 1.41 seconds
Started Jul 11 06:34:08 PM PDT 24
Finished Jul 11 06:34:11 PM PDT 24
Peak memory 230264 kb
Host smart-e487340c-81d6-46b4-b7b9-a474940838b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916112532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2916112532
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3306147502
Short name T1260
Test name
Test status
Simulation time 136571683 ps
CPU time 1.44 seconds
Started Jul 11 06:34:11 PM PDT 24
Finished Jul 11 06:34:13 PM PDT 24
Peak memory 230372 kb
Host smart-ae8bcbbd-a29c-41df-98f2-faf222836101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306147502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3306147502
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.126428201
Short name T1201
Test name
Test status
Simulation time 557792801 ps
CPU time 1.45 seconds
Started Jul 11 06:34:10 PM PDT 24
Finished Jul 11 06:34:13 PM PDT 24
Peak memory 230268 kb
Host smart-afcd7d86-8457-4d89-bcd0-1128182343f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126428201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.126428201
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1274556686
Short name T1320
Test name
Test status
Simulation time 147684810 ps
CPU time 1.48 seconds
Started Jul 11 06:34:24 PM PDT 24
Finished Jul 11 06:34:27 PM PDT 24
Peak memory 230288 kb
Host smart-17f7c8b3-e36c-4851-9752-fee39f5de53d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274556686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1274556686
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3436392594
Short name T1206
Test name
Test status
Simulation time 543128270 ps
CPU time 1.92 seconds
Started Jul 11 06:34:12 PM PDT 24
Finished Jul 11 06:34:15 PM PDT 24
Peak memory 230276 kb
Host smart-40a877b1-61fc-4fa5-9920-de5f80a3d6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436392594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3436392594
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2809799938
Short name T1244
Test name
Test status
Simulation time 41006949 ps
CPU time 1.53 seconds
Started Jul 11 06:34:14 PM PDT 24
Finished Jul 11 06:34:17 PM PDT 24
Peak memory 230424 kb
Host smart-6c5a692b-e86d-4cb8-bea1-80f848fc3a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809799938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2809799938
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2411791741
Short name T366
Test name
Test status
Simulation time 1831022099 ps
CPU time 5.32 seconds
Started Jul 11 06:33:15 PM PDT 24
Finished Jul 11 06:33:23 PM PDT 24
Peak memory 239196 kb
Host smart-d500f0d4-74e8-4109-a9c6-84ab08b279b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411791741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2411791741
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2672476610
Short name T1314
Test name
Test status
Simulation time 309940652 ps
CPU time 4.45 seconds
Started Jul 11 06:33:14 PM PDT 24
Finished Jul 11 06:33:20 PM PDT 24
Peak memory 239260 kb
Host smart-c9c5755f-3a33-43f0-87ca-3e412048fad8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672476610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.2672476610
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.855375831
Short name T1208
Test name
Test status
Simulation time 190988390 ps
CPU time 2.5 seconds
Started Jul 11 06:33:15 PM PDT 24
Finished Jul 11 06:33:20 PM PDT 24
Peak memory 241568 kb
Host smart-50fb29db-6e0d-483a-8321-9bb8c2dd11e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855375831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.855375831
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2050546985
Short name T1253
Test name
Test status
Simulation time 252604120 ps
CPU time 2.05 seconds
Started Jul 11 06:33:20 PM PDT 24
Finished Jul 11 06:33:23 PM PDT 24
Peak memory 244536 kb
Host smart-a2bc3f78-c914-49aa-b9e8-127e24f159e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050546985 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.2050546985
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2022957493
Short name T1255
Test name
Test status
Simulation time 141514766 ps
CPU time 1.51 seconds
Started Jul 11 06:33:17 PM PDT 24
Finished Jul 11 06:33:20 PM PDT 24
Peak memory 241448 kb
Host smart-2bc47d05-faa0-462c-bf9d-69149f4bb85f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022957493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2022957493
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1248179063
Short name T1250
Test name
Test status
Simulation time 152743861 ps
CPU time 1.35 seconds
Started Jul 11 06:33:10 PM PDT 24
Finished Jul 11 06:33:15 PM PDT 24
Peak memory 230256 kb
Host smart-64e505dc-133d-4102-b5d4-d9759a549a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248179063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1248179063
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3686803198
Short name T1285
Test name
Test status
Simulation time 39997326 ps
CPU time 1.41 seconds
Started Jul 11 06:33:16 PM PDT 24
Finished Jul 11 06:33:19 PM PDT 24
Peak memory 229880 kb
Host smart-4d71271f-8184-41cf-89f7-5dc2e9b31e7f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686803198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.3686803198
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1643730217
Short name T1280
Test name
Test status
Simulation time 37750706 ps
CPU time 1.39 seconds
Started Jul 11 06:33:10 PM PDT 24
Finished Jul 11 06:33:15 PM PDT 24
Peak memory 230076 kb
Host smart-2d3a139f-d4c3-409e-ba79-b969a8771232
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643730217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.1643730217
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3877824151
Short name T1240
Test name
Test status
Simulation time 106949877 ps
CPU time 2.01 seconds
Started Jul 11 06:33:14 PM PDT 24
Finished Jul 11 06:33:19 PM PDT 24
Peak memory 242224 kb
Host smart-e1f67694-c250-4939-80b9-0f0c79571bca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877824151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.3877824151
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2445056908
Short name T1237
Test name
Test status
Simulation time 82280507 ps
CPU time 4.92 seconds
Started Jul 11 06:33:10 PM PDT 24
Finished Jul 11 06:33:18 PM PDT 24
Peak memory 246492 kb
Host smart-eedd16fe-f3c0-45dd-ab62-27cdef4118d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445056908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2445056908
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1775811515
Short name T349
Test name
Test status
Simulation time 1814433289 ps
CPU time 22.74 seconds
Started Jul 11 06:33:09 PM PDT 24
Finished Jul 11 06:33:33 PM PDT 24
Peak memory 244488 kb
Host smart-2dcebe8d-5a94-47d4-92ed-f2f78c3b219e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775811515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.1775811515
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.696879769
Short name T1302
Test name
Test status
Simulation time 38305385 ps
CPU time 1.37 seconds
Started Jul 11 06:34:14 PM PDT 24
Finished Jul 11 06:34:16 PM PDT 24
Peak memory 230564 kb
Host smart-2137a0f7-2cfc-40d9-b059-5c890b35ee0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696879769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.696879769
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.4282671197
Short name T1315
Test name
Test status
Simulation time 57554280 ps
CPU time 1.49 seconds
Started Jul 11 06:34:14 PM PDT 24
Finished Jul 11 06:34:17 PM PDT 24
Peak memory 231116 kb
Host smart-f9ee28b2-8045-4096-92db-5fec3d2a6c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282671197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.4282671197
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1203623971
Short name T1220
Test name
Test status
Simulation time 71369558 ps
CPU time 1.4 seconds
Started Jul 11 06:34:15 PM PDT 24
Finished Jul 11 06:34:17 PM PDT 24
Peak memory 230984 kb
Host smart-a9e4eceb-dca6-49d1-bd89-bee39460cd8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203623971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1203623971
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1164612830
Short name T1224
Test name
Test status
Simulation time 74071799 ps
CPU time 1.52 seconds
Started Jul 11 06:34:13 PM PDT 24
Finished Jul 11 06:34:16 PM PDT 24
Peak memory 230384 kb
Host smart-934228a6-85f3-439c-9ca1-69f7bf8f1a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164612830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1164612830
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.1191251835
Short name T1205
Test name
Test status
Simulation time 42364690 ps
CPU time 1.39 seconds
Started Jul 11 06:34:20 PM PDT 24
Finished Jul 11 06:34:22 PM PDT 24
Peak memory 230432 kb
Host smart-084e2d0b-440b-4493-abdb-793dee6858d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191251835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.1191251835
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1386961156
Short name T1197
Test name
Test status
Simulation time 618375103 ps
CPU time 2.31 seconds
Started Jul 11 06:34:19 PM PDT 24
Finished Jul 11 06:34:22 PM PDT 24
Peak memory 230576 kb
Host smart-683e4a7b-729d-4ec2-9004-74503adc3aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386961156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1386961156
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2760844974
Short name T1287
Test name
Test status
Simulation time 42109628 ps
CPU time 1.48 seconds
Started Jul 11 06:34:18 PM PDT 24
Finished Jul 11 06:34:21 PM PDT 24
Peak memory 230324 kb
Host smart-d3e6d263-41d6-45fb-95a8-6466354d4811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760844974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2760844974
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.4040990079
Short name T1210
Test name
Test status
Simulation time 39326753 ps
CPU time 1.44 seconds
Started Jul 11 06:34:18 PM PDT 24
Finished Jul 11 06:34:21 PM PDT 24
Peak memory 230332 kb
Host smart-32717104-0c39-4348-b2b2-7f718728481d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040990079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.4040990079
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2909432701
Short name T1281
Test name
Test status
Simulation time 69802006 ps
CPU time 1.4 seconds
Started Jul 11 06:34:19 PM PDT 24
Finished Jul 11 06:34:21 PM PDT 24
Peak memory 230308 kb
Host smart-2fec0067-162b-4858-a26f-d51e2e75054e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909432701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2909432701
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3407054031
Short name T1235
Test name
Test status
Simulation time 556053128 ps
CPU time 1.52 seconds
Started Jul 11 06:34:18 PM PDT 24
Finished Jul 11 06:34:21 PM PDT 24
Peak memory 231080 kb
Host smart-98fc1d69-ab76-4765-92b4-e77944070e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407054031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3407054031
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3825636044
Short name T301
Test name
Test status
Simulation time 229637787 ps
CPU time 4.09 seconds
Started Jul 11 06:33:22 PM PDT 24
Finished Jul 11 06:33:27 PM PDT 24
Peak memory 239328 kb
Host smart-f3a23d58-5ced-4fb5-901d-2174e3da3468
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825636044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.3825636044
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2463883321
Short name T311
Test name
Test status
Simulation time 1592114720 ps
CPU time 9.68 seconds
Started Jul 11 06:33:18 PM PDT 24
Finished Jul 11 06:33:29 PM PDT 24
Peak memory 239256 kb
Host smart-bc134417-c9ae-408e-bff1-a66d98478618
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463883321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2463883321
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1040406336
Short name T303
Test name
Test status
Simulation time 98927020 ps
CPU time 2.27 seconds
Started Jul 11 06:33:18 PM PDT 24
Finished Jul 11 06:33:22 PM PDT 24
Peak memory 241188 kb
Host smart-d752f930-1535-47e8-9d58-b50ea68ec538
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040406336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.1040406336
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3155678043
Short name T367
Test name
Test status
Simulation time 100444738 ps
CPU time 2.65 seconds
Started Jul 11 06:33:19 PM PDT 24
Finished Jul 11 06:33:22 PM PDT 24
Peak memory 247500 kb
Host smart-cba2c9b9-d8ce-429b-adf9-e880c249010f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155678043 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3155678043
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.4277870593
Short name T308
Test name
Test status
Simulation time 40217686 ps
CPU time 1.56 seconds
Started Jul 11 06:33:19 PM PDT 24
Finished Jul 11 06:33:22 PM PDT 24
Peak memory 240916 kb
Host smart-5664e467-ff24-4479-a6f3-31f8ce4fa126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277870593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.4277870593
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.710244805
Short name T1325
Test name
Test status
Simulation time 136010808 ps
CPU time 1.41 seconds
Started Jul 11 06:33:19 PM PDT 24
Finished Jul 11 06:33:21 PM PDT 24
Peak memory 230336 kb
Host smart-363de6ef-d364-436e-9d42-3fdac2322f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710244805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.710244805
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1395245382
Short name T1293
Test name
Test status
Simulation time 551126287 ps
CPU time 1.76 seconds
Started Jul 11 06:33:22 PM PDT 24
Finished Jul 11 06:33:25 PM PDT 24
Peak memory 230012 kb
Host smart-daca34a9-ad12-4065-b27a-b9a6699a788a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395245382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1395245382
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2983613939
Short name T1256
Test name
Test status
Simulation time 37962087 ps
CPU time 1.32 seconds
Started Jul 11 06:33:20 PM PDT 24
Finished Jul 11 06:33:22 PM PDT 24
Peak memory 229952 kb
Host smart-efee17cc-3d36-4239-aaf5-b49d2af7ef03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983613939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2983613939
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1462878452
Short name T318
Test name
Test status
Simulation time 164578567 ps
CPU time 2.74 seconds
Started Jul 11 06:33:22 PM PDT 24
Finished Jul 11 06:33:26 PM PDT 24
Peak memory 239320 kb
Host smart-9616a409-5551-4092-94a5-8b3a119dde6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462878452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.1462878452
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1280495775
Short name T1252
Test name
Test status
Simulation time 860259142 ps
CPU time 4.3 seconds
Started Jul 11 06:33:18 PM PDT 24
Finished Jul 11 06:33:24 PM PDT 24
Peak memory 246152 kb
Host smart-35b6304d-51c4-4041-ab08-69938ae38577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280495775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1280495775
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3817988635
Short name T348
Test name
Test status
Simulation time 4599538502 ps
CPU time 23.92 seconds
Started Jul 11 06:33:19 PM PDT 24
Finished Jul 11 06:33:44 PM PDT 24
Peak memory 245064 kb
Host smart-02f05468-08dd-414a-815a-5e18e7936a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817988635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3817988635
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.471605639
Short name T1248
Test name
Test status
Simulation time 65317938 ps
CPU time 1.37 seconds
Started Jul 11 06:34:19 PM PDT 24
Finished Jul 11 06:34:21 PM PDT 24
Peak memory 230472 kb
Host smart-ab110d48-2068-46cb-9598-7bd1a8e384e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471605639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.471605639
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2132617872
Short name T1229
Test name
Test status
Simulation time 71366233 ps
CPU time 1.45 seconds
Started Jul 11 06:34:19 PM PDT 24
Finished Jul 11 06:34:22 PM PDT 24
Peak memory 231064 kb
Host smart-c5a8813d-47f6-4699-a37d-d5a1eca8668d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132617872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2132617872
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2087978464
Short name T1249
Test name
Test status
Simulation time 71776296 ps
CPU time 1.47 seconds
Started Jul 11 06:34:19 PM PDT 24
Finished Jul 11 06:34:22 PM PDT 24
Peak memory 230596 kb
Host smart-4ea0ab73-f8c6-4405-901b-ad9a35f68833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087978464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2087978464
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2439249685
Short name T1273
Test name
Test status
Simulation time 42404474 ps
CPU time 1.33 seconds
Started Jul 11 06:34:18 PM PDT 24
Finished Jul 11 06:34:20 PM PDT 24
Peak memory 230296 kb
Host smart-e9834aa9-3b5b-4ad2-8563-ef32d28f3f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439249685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2439249685
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3131605985
Short name T1279
Test name
Test status
Simulation time 97051652 ps
CPU time 1.4 seconds
Started Jul 11 06:34:23 PM PDT 24
Finished Jul 11 06:34:25 PM PDT 24
Peak memory 230660 kb
Host smart-5082ecfa-6332-43cf-864f-f67cfbc3c298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131605985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3131605985
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.598750844
Short name T1228
Test name
Test status
Simulation time 513006529 ps
CPU time 2.04 seconds
Started Jul 11 06:34:23 PM PDT 24
Finished Jul 11 06:34:26 PM PDT 24
Peak memory 230568 kb
Host smart-764e756a-2ab6-4c2b-acf4-379d003a1e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598750844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.598750844
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1512674489
Short name T1217
Test name
Test status
Simulation time 636709972 ps
CPU time 2.06 seconds
Started Jul 11 06:34:22 PM PDT 24
Finished Jul 11 06:34:25 PM PDT 24
Peak memory 230420 kb
Host smart-00f88a3d-1e4c-491b-b862-7aca04a74671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512674489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1512674489
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.2813577527
Short name T1203
Test name
Test status
Simulation time 140993914 ps
CPU time 1.32 seconds
Started Jul 11 06:34:23 PM PDT 24
Finished Jul 11 06:34:25 PM PDT 24
Peak memory 231080 kb
Host smart-97cca14a-0f7e-49fa-8363-1f5734e150cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813577527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.2813577527
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3725707397
Short name T1211
Test name
Test status
Simulation time 97985713 ps
CPU time 1.42 seconds
Started Jul 11 06:34:23 PM PDT 24
Finished Jul 11 06:34:25 PM PDT 24
Peak memory 230324 kb
Host smart-144dc0b2-c5ed-47d1-8425-313089ba4673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725707397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3725707397
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.754971310
Short name T1232
Test name
Test status
Simulation time 146846101 ps
CPU time 1.45 seconds
Started Jul 11 06:34:25 PM PDT 24
Finished Jul 11 06:34:27 PM PDT 24
Peak memory 230984 kb
Host smart-ba640fdb-cffb-4d0e-99fa-55cfc998f47d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754971310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.754971310
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2588173299
Short name T1257
Test name
Test status
Simulation time 420255169 ps
CPU time 2.79 seconds
Started Jul 11 06:33:28 PM PDT 24
Finished Jul 11 06:33:32 PM PDT 24
Peak memory 247300 kb
Host smart-3f94cbeb-fca8-4a0a-99a4-d4ec46cd01a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588173299 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2588173299
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1601363995
Short name T1270
Test name
Test status
Simulation time 48045222 ps
CPU time 1.55 seconds
Started Jul 11 06:33:22 PM PDT 24
Finished Jul 11 06:33:25 PM PDT 24
Peak memory 240908 kb
Host smart-ce6f1e7f-104a-4c7d-b5b5-98f650b67d7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601363995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1601363995
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.155355889
Short name T1239
Test name
Test status
Simulation time 51577304 ps
CPU time 1.48 seconds
Started Jul 11 06:33:24 PM PDT 24
Finished Jul 11 06:33:26 PM PDT 24
Peak memory 231048 kb
Host smart-816d8d00-f6ed-4499-a91c-1713954d178a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155355889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.155355889
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1545166984
Short name T274
Test name
Test status
Simulation time 156268328 ps
CPU time 3.79 seconds
Started Jul 11 06:33:30 PM PDT 24
Finished Jul 11 06:33:35 PM PDT 24
Peak memory 242376 kb
Host smart-499e1f85-08cd-4fa8-9c5a-03d2b01cb062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545166984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1545166984
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.4043735472
Short name T1236
Test name
Test status
Simulation time 177072413 ps
CPU time 6.47 seconds
Started Jul 11 06:33:25 PM PDT 24
Finished Jul 11 06:33:32 PM PDT 24
Peak memory 247224 kb
Host smart-562f0f3e-4e1f-48f7-bb49-aa27cf428f24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043735472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.4043735472
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3251599037
Short name T1316
Test name
Test status
Simulation time 19811052523 ps
CPU time 42.54 seconds
Started Jul 11 06:33:23 PM PDT 24
Finished Jul 11 06:34:07 PM PDT 24
Peak memory 244964 kb
Host smart-bd0387f4-b0e9-4f30-bb2f-2ad31e10ff8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251599037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3251599037
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2040987263
Short name T1328
Test name
Test status
Simulation time 146457044 ps
CPU time 1.98 seconds
Started Jul 11 06:33:27 PM PDT 24
Finished Jul 11 06:33:30 PM PDT 24
Peak memory 239340 kb
Host smart-0521906b-231f-4208-b41c-ed5e7d1a8e48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040987263 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2040987263
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.667234147
Short name T1277
Test name
Test status
Simulation time 144996645 ps
CPU time 1.57 seconds
Started Jul 11 06:33:26 PM PDT 24
Finished Jul 11 06:33:29 PM PDT 24
Peak memory 240952 kb
Host smart-fcb95b9c-f0e4-4cde-b743-d1f4860dc48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667234147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.667234147
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1001119718
Short name T1321
Test name
Test status
Simulation time 85977612 ps
CPU time 1.37 seconds
Started Jul 11 06:33:27 PM PDT 24
Finished Jul 11 06:33:30 PM PDT 24
Peak memory 230296 kb
Host smart-dbaace68-7269-4b35-9fea-392be89c7b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001119718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1001119718
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.316635504
Short name T314
Test name
Test status
Simulation time 261888903 ps
CPU time 2.42 seconds
Started Jul 11 06:33:27 PM PDT 24
Finished Jul 11 06:33:31 PM PDT 24
Peak memory 239232 kb
Host smart-a10c0761-ce95-44c8-b179-da5c0f0ef3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316635504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct
rl_same_csr_outstanding.316635504
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.4083717565
Short name T1309
Test name
Test status
Simulation time 194949279 ps
CPU time 3.6 seconds
Started Jul 11 06:33:27 PM PDT 24
Finished Jul 11 06:33:32 PM PDT 24
Peak memory 246300 kb
Host smart-82e99d20-d67a-4b51-947e-7acf844ff9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083717565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.4083717565
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2280447036
Short name T343
Test name
Test status
Simulation time 2656104358 ps
CPU time 11.12 seconds
Started Jul 11 06:33:28 PM PDT 24
Finished Jul 11 06:33:40 PM PDT 24
Peak memory 244332 kb
Host smart-7b031d06-76cd-4138-8575-599765e889b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280447036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2280447036
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1294339961
Short name T1286
Test name
Test status
Simulation time 1063017428 ps
CPU time 3.12 seconds
Started Jul 11 06:33:36 PM PDT 24
Finished Jul 11 06:33:40 PM PDT 24
Peak memory 247492 kb
Host smart-4f66cc42-135d-42d5-b866-756ed6a1f6cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294339961 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1294339961
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.760239957
Short name T310
Test name
Test status
Simulation time 554808640 ps
CPU time 1.73 seconds
Started Jul 11 06:33:31 PM PDT 24
Finished Jul 11 06:33:33 PM PDT 24
Peak memory 241732 kb
Host smart-4d37994a-2f32-4f68-9358-f342ee1d6791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760239957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.760239957
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2329510706
Short name T1274
Test name
Test status
Simulation time 39839653 ps
CPU time 1.39 seconds
Started Jul 11 06:33:31 PM PDT 24
Finished Jul 11 06:33:34 PM PDT 24
Peak memory 230204 kb
Host smart-9ed7e563-6641-44ac-ae66-ab834fd4a6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329510706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2329510706
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.970283412
Short name T317
Test name
Test status
Simulation time 93217498 ps
CPU time 2.96 seconds
Started Jul 11 06:33:32 PM PDT 24
Finished Jul 11 06:33:36 PM PDT 24
Peak memory 239244 kb
Host smart-5790c6a8-aa5c-4ee7-a8f6-aa8ed305f16c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970283412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.970283412
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.890036676
Short name T1212
Test name
Test status
Simulation time 1135539901 ps
CPU time 2.91 seconds
Started Jul 11 06:33:29 PM PDT 24
Finished Jul 11 06:33:34 PM PDT 24
Peak memory 245168 kb
Host smart-8e50502a-038c-4eef-890e-7e58bb1521cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890036676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.890036676
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1565801476
Short name T1282
Test name
Test status
Simulation time 2440062133 ps
CPU time 9.52 seconds
Started Jul 11 06:33:27 PM PDT 24
Finished Jul 11 06:33:38 PM PDT 24
Peak memory 244356 kb
Host smart-7ba59a82-7550-46d1-8789-d5f35bd9bfa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565801476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1565801476
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1370149400
Short name T1209
Test name
Test status
Simulation time 404087891 ps
CPU time 3.21 seconds
Started Jul 11 06:33:42 PM PDT 24
Finished Jul 11 06:33:46 PM PDT 24
Peak memory 247160 kb
Host smart-8bcdc81f-7a72-4511-a0f7-2b715e4d4102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370149400 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.1370149400
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.958245037
Short name T1324
Test name
Test status
Simulation time 43682123 ps
CPU time 1.48 seconds
Started Jul 11 06:33:38 PM PDT 24
Finished Jul 11 06:33:40 PM PDT 24
Peak memory 240960 kb
Host smart-5c9ad26b-a0ba-4ac3-a420-72f8e38a2bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958245037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.958245037
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.4016771446
Short name T1259
Test name
Test status
Simulation time 515538269 ps
CPU time 1.34 seconds
Started Jul 11 06:33:37 PM PDT 24
Finished Jul 11 06:33:39 PM PDT 24
Peak memory 230560 kb
Host smart-cfa38f36-dc58-4535-b9ae-f22d823e963c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016771446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.4016771446
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3286188316
Short name T1251
Test name
Test status
Simulation time 76294932 ps
CPU time 2.41 seconds
Started Jul 11 06:33:40 PM PDT 24
Finished Jul 11 06:33:44 PM PDT 24
Peak memory 239208 kb
Host smart-5bcd017b-9c49-4ac7-9ba1-2dfebb6fac3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286188316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.3286188316
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.247968422
Short name T1306
Test name
Test status
Simulation time 121058400 ps
CPU time 4.48 seconds
Started Jul 11 06:33:39 PM PDT 24
Finished Jul 11 06:33:44 PM PDT 24
Peak memory 246212 kb
Host smart-61fa8fde-602c-4dab-9a31-7c60f9cb96ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247968422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.247968422
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.495489698
Short name T345
Test name
Test status
Simulation time 1390433702 ps
CPU time 9.94 seconds
Started Jul 11 06:33:38 PM PDT 24
Finished Jul 11 06:33:49 PM PDT 24
Peak memory 239232 kb
Host smart-3e94fca1-b67f-4493-8c7f-c746ff6b9bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495489698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_int
g_err.495489698
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1456218742
Short name T1318
Test name
Test status
Simulation time 1084132275 ps
CPU time 3.12 seconds
Started Jul 11 06:33:41 PM PDT 24
Finished Jul 11 06:33:46 PM PDT 24
Peak memory 247432 kb
Host smart-e4b514f2-a74d-4b20-83a5-c7c70baff406
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456218742 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1456218742
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3588553925
Short name T312
Test name
Test status
Simulation time 129570300 ps
CPU time 1.49 seconds
Started Jul 11 06:33:41 PM PDT 24
Finished Jul 11 06:33:44 PM PDT 24
Peak memory 239268 kb
Host smart-3dc79994-aa4f-4b56-aafe-31b57bbea3e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588553925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3588553925
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.723145132
Short name T1225
Test name
Test status
Simulation time 41819784 ps
CPU time 1.46 seconds
Started Jul 11 06:33:42 PM PDT 24
Finished Jul 11 06:33:45 PM PDT 24
Peak memory 231016 kb
Host smart-b5b34b63-35d9-43a6-96d2-7637d4099554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723145132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.723145132
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.473390346
Short name T1297
Test name
Test status
Simulation time 49935745 ps
CPU time 1.99 seconds
Started Jul 11 06:33:42 PM PDT 24
Finished Jul 11 06:33:46 PM PDT 24
Peak memory 239428 kb
Host smart-a94fe26e-17f9-41ed-ad20-b30c81ceeee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473390346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.473390346
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2637422683
Short name T1266
Test name
Test status
Simulation time 3081625646 ps
CPU time 7.89 seconds
Started Jul 11 06:33:41 PM PDT 24
Finished Jul 11 06:33:51 PM PDT 24
Peak memory 247096 kb
Host smart-9d1f5ddd-ae27-426d-8cc6-871206e745e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637422683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2637422683
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1530329713
Short name T344
Test name
Test status
Simulation time 2209964073 ps
CPU time 10.72 seconds
Started Jul 11 06:33:41 PM PDT 24
Finished Jul 11 06:33:53 PM PDT 24
Peak memory 244124 kb
Host smart-cae56827-b1b0-4b7d-819d-c34685e667a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530329713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1530329713
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3993341995
Short name T774
Test name
Test status
Simulation time 67183738 ps
CPU time 1.82 seconds
Started Jul 11 06:52:04 PM PDT 24
Finished Jul 11 06:52:06 PM PDT 24
Peak memory 240176 kb
Host smart-6f8d3ced-cd9d-4ccf-ab84-1d465ed03117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993341995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3993341995
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3674243336
Short name T549
Test name
Test status
Simulation time 2067797691 ps
CPU time 26.76 seconds
Started Jul 11 06:51:44 PM PDT 24
Finished Jul 11 06:52:12 PM PDT 24
Peak memory 242716 kb
Host smart-0153a710-b6d0-49b8-a70c-eb26d378407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674243336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3674243336
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3276518846
Short name T1178
Test name
Test status
Simulation time 673692118 ps
CPU time 13.78 seconds
Started Jul 11 06:51:54 PM PDT 24
Finished Jul 11 06:52:09 PM PDT 24
Peak memory 248792 kb
Host smart-1c724d75-1187-41a5-a14b-2ff4e7a6b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276518846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3276518846
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.3225588488
Short name T1140
Test name
Test status
Simulation time 1151034471 ps
CPU time 15.15 seconds
Started Jul 11 06:51:50 PM PDT 24
Finished Jul 11 06:52:06 PM PDT 24
Peak memory 242428 kb
Host smart-021f402f-e64d-4518-8f97-db1d0b259e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225588488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3225588488
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.1387670179
Short name T391
Test name
Test status
Simulation time 1407211760 ps
CPU time 21.74 seconds
Started Jul 11 06:51:49 PM PDT 24
Finished Jul 11 06:52:11 PM PDT 24
Peak memory 242452 kb
Host smart-fbb596bf-acd7-41ba-8839-44f6ceda4d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387670179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1387670179
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3244700072
Short name T871
Test name
Test status
Simulation time 175839875 ps
CPU time 5.03 seconds
Started Jul 11 06:51:45 PM PDT 24
Finished Jul 11 06:51:50 PM PDT 24
Peak memory 242100 kb
Host smart-f4d545c9-0ab8-4441-82fb-def72d095e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244700072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3244700072
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3061704183
Short name T1177
Test name
Test status
Simulation time 3066629372 ps
CPU time 13.37 seconds
Started Jul 11 06:51:43 PM PDT 24
Finished Jul 11 06:51:57 PM PDT 24
Peak memory 241800 kb
Host smart-4c427f66-f446-4f3b-9744-c9b2c78fea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061704183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3061704183
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3713756122
Short name T787
Test name
Test status
Simulation time 2076602023 ps
CPU time 37.56 seconds
Started Jul 11 06:51:51 PM PDT 24
Finished Jul 11 06:52:29 PM PDT 24
Peak memory 242612 kb
Host smart-9f3981da-8636-4c2f-8e2b-11c72dcedb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713756122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3713756122
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3491098310
Short name T957
Test name
Test status
Simulation time 270547333 ps
CPU time 7.13 seconds
Started Jul 11 06:51:49 PM PDT 24
Finished Jul 11 06:51:56 PM PDT 24
Peak memory 242212 kb
Host smart-4bb8dc22-b00a-4b1f-8a71-efcec5ab4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491098310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3491098310
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3041389681
Short name T1059
Test name
Test status
Simulation time 945689553 ps
CPU time 25.42 seconds
Started Jul 11 06:51:43 PM PDT 24
Finished Jul 11 06:52:09 PM PDT 24
Peak memory 242240 kb
Host smart-da11d606-81dd-4c05-ac92-3d584cc4c539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041389681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3041389681
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.3652580305
Short name T442
Test name
Test status
Simulation time 1220649873 ps
CPU time 20.02 seconds
Started Jul 11 06:51:39 PM PDT 24
Finished Jul 11 06:52:00 PM PDT 24
Peak memory 241824 kb
Host smart-f6f9dddd-cddb-4185-a7b2-e7aeafa37ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652580305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3652580305
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3009079271
Short name T594
Test name
Test status
Simulation time 302637292 ps
CPU time 9.46 seconds
Started Jul 11 06:51:54 PM PDT 24
Finished Jul 11 06:52:04 PM PDT 24
Peak memory 242320 kb
Host smart-e921f19c-4f1b-4c27-ac9c-0e4bec36a354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009079271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3009079271
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3116228863
Short name T235
Test name
Test status
Simulation time 154600983448 ps
CPU time 220.08 seconds
Started Jul 11 06:52:07 PM PDT 24
Finished Jul 11 06:55:48 PM PDT 24
Peak memory 266188 kb
Host smart-ef7b5d39-a36f-478f-9089-5c5056721a57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116228863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3116228863
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.3539057192
Short name T158
Test name
Test status
Simulation time 3697020463 ps
CPU time 6.24 seconds
Started Jul 11 06:51:40 PM PDT 24
Finished Jul 11 06:51:47 PM PDT 24
Peak memory 242616 kb
Host smart-80fe06b3-b8be-4a95-9c1e-8ce0b31c4b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539057192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3539057192
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.156768966
Short name T1070
Test name
Test status
Simulation time 19028788862 ps
CPU time 165.15 seconds
Started Jul 11 06:51:58 PM PDT 24
Finished Jul 11 06:54:44 PM PDT 24
Peak memory 257096 kb
Host smart-de4f1d2f-7193-46ce-aed9-7e2807664928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156768966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.156768966
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3197182349
Short name T320
Test name
Test status
Simulation time 233789864633 ps
CPU time 950.09 seconds
Started Jul 11 06:51:52 PM PDT 24
Finished Jul 11 07:07:43 PM PDT 24
Peak memory 274744 kb
Host smart-a23d7e9c-2d73-4265-8473-2740d5a974e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197182349 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3197182349
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.539670058
Short name T421
Test name
Test status
Simulation time 290864286 ps
CPU time 5.84 seconds
Started Jul 11 06:51:53 PM PDT 24
Finished Jul 11 06:51:59 PM PDT 24
Peak memory 242444 kb
Host smart-7f394033-55fc-403f-970a-e65a17ce8d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539670058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.539670058
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3142418969
Short name T896
Test name
Test status
Simulation time 153154212 ps
CPU time 1.9 seconds
Started Jul 11 06:52:20 PM PDT 24
Finished Jul 11 06:52:22 PM PDT 24
Peak memory 240392 kb
Host smart-c0d28b01-2209-4cab-8145-b69f7402b535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142418969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3142418969
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1074556376
Short name T393
Test name
Test status
Simulation time 1448379825 ps
CPU time 12.63 seconds
Started Jul 11 06:52:03 PM PDT 24
Finished Jul 11 06:52:16 PM PDT 24
Peak memory 242120 kb
Host smart-7429d5d3-c81f-4520-88a0-071a15cf85de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074556376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1074556376
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1864445694
Short name T1023
Test name
Test status
Simulation time 499780143 ps
CPU time 5.41 seconds
Started Jul 11 06:52:06 PM PDT 24
Finished Jul 11 06:52:13 PM PDT 24
Peak memory 246428 kb
Host smart-137091e8-7182-48d4-a066-48cec3d1510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864445694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1864445694
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2040613100
Short name T340
Test name
Test status
Simulation time 1154099012 ps
CPU time 24.37 seconds
Started Jul 11 06:52:07 PM PDT 24
Finished Jul 11 06:52:33 PM PDT 24
Peak memory 242264 kb
Host smart-c563e886-9b44-4d7b-a460-3a71bb237bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040613100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2040613100
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3193670210
Short name T415
Test name
Test status
Simulation time 3210706927 ps
CPU time 22.99 seconds
Started Jul 11 06:52:07 PM PDT 24
Finished Jul 11 06:52:31 PM PDT 24
Peak memory 242348 kb
Host smart-707154a7-405b-4294-a4e3-d4d53fac5aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193670210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3193670210
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.636405710
Short name T802
Test name
Test status
Simulation time 439292609 ps
CPU time 4.85 seconds
Started Jul 11 06:52:02 PM PDT 24
Finished Jul 11 06:52:08 PM PDT 24
Peak memory 242152 kb
Host smart-b2b337c9-0dd9-4939-ba34-5383a703e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636405710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.636405710
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2381400068
Short name T580
Test name
Test status
Simulation time 3549729198 ps
CPU time 24.23 seconds
Started Jul 11 06:52:06 PM PDT 24
Finished Jul 11 06:52:31 PM PDT 24
Peak memory 246976 kb
Host smart-8d178bdd-c347-4792-9c12-03ce97e13ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381400068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2381400068
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3111652027
Short name T261
Test name
Test status
Simulation time 26253948330 ps
CPU time 81.57 seconds
Started Jul 11 06:52:07 PM PDT 24
Finished Jul 11 06:53:30 PM PDT 24
Peak memory 248864 kb
Host smart-5e4fb1ea-8ec4-4367-bff1-848d7ec05bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111652027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3111652027
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2765185774
Short name T262
Test name
Test status
Simulation time 2656720108 ps
CPU time 13.71 seconds
Started Jul 11 06:52:02 PM PDT 24
Finished Jul 11 06:52:17 PM PDT 24
Peak memory 242292 kb
Host smart-e84e83b8-841e-46ff-86ae-2e0f5ac4afdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765185774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2765185774
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.868993097
Short name T236
Test name
Test status
Simulation time 48347493102 ps
CPU time 197.83 seconds
Started Jul 11 06:52:17 PM PDT 24
Finished Jul 11 06:55:36 PM PDT 24
Peak memory 266456 kb
Host smart-30f8e785-fd84-47b5-8352-cc549288fb66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868993097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.868993097
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2661162629
Short name T567
Test name
Test status
Simulation time 126352578 ps
CPU time 3.61 seconds
Started Jul 11 06:52:01 PM PDT 24
Finished Jul 11 06:52:06 PM PDT 24
Peak memory 242020 kb
Host smart-6dda7650-6e89-40aa-8345-33b42acc7e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661162629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2661162629
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3970721241
Short name T286
Test name
Test status
Simulation time 14924950103 ps
CPU time 207.36 seconds
Started Jul 11 06:53:28 PM PDT 24
Finished Jul 11 06:56:56 PM PDT 24
Peak memory 248732 kb
Host smart-915325dd-6e3f-4790-bc70-882fb00e0c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970721241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3970721241
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.246799897
Short name T915
Test name
Test status
Simulation time 70504833276 ps
CPU time 1864.55 seconds
Started Jul 11 06:52:10 PM PDT 24
Finished Jul 11 07:23:16 PM PDT 24
Peak memory 273528 kb
Host smart-0099e030-13de-45bf-bbce-3751507e85d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246799897 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.246799897
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.1035524079
Short name T1142
Test name
Test status
Simulation time 711796720 ps
CPU time 15.61 seconds
Started Jul 11 06:52:08 PM PDT 24
Finished Jul 11 06:52:24 PM PDT 24
Peak memory 242372 kb
Host smart-609f771c-35e7-459f-a4fe-ceac1f078cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035524079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1035524079
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.1884959314
Short name T727
Test name
Test status
Simulation time 177480299 ps
CPU time 1.97 seconds
Started Jul 11 06:54:25 PM PDT 24
Finished Jul 11 06:54:27 PM PDT 24
Peak memory 240516 kb
Host smart-e4b0d7a3-30e4-47fb-b6f6-825b8f6e37e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884959314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1884959314
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.4080223708
Short name T41
Test name
Test status
Simulation time 14359303478 ps
CPU time 32.93 seconds
Started Jul 11 06:54:18 PM PDT 24
Finished Jul 11 06:54:51 PM PDT 24
Peak memory 243004 kb
Host smart-cbf44c75-9580-4808-b8e9-909ef1013b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080223708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.4080223708
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1153491809
Short name T339
Test name
Test status
Simulation time 549046282 ps
CPU time 14.12 seconds
Started Jul 11 06:54:18 PM PDT 24
Finished Jul 11 06:54:33 PM PDT 24
Peak memory 242372 kb
Host smart-7ccca9d7-0c32-486b-95be-9ce1425cbe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153491809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1153491809
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.1641566771
Short name T953
Test name
Test status
Simulation time 30013191801 ps
CPU time 66.36 seconds
Started Jul 11 06:54:14 PM PDT 24
Finished Jul 11 06:55:21 PM PDT 24
Peak memory 248860 kb
Host smart-d4cc072b-8556-440e-a1e9-6db451f49f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641566771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1641566771
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.426059899
Short name T768
Test name
Test status
Simulation time 20452424841 ps
CPU time 50.71 seconds
Started Jul 11 06:54:15 PM PDT 24
Finished Jul 11 06:55:06 PM PDT 24
Peak memory 257104 kb
Host smart-c42f1ef7-09eb-4833-bc63-03f894c4cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426059899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.426059899
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.582534329
Short name T374
Test name
Test status
Simulation time 1088531789 ps
CPU time 15.34 seconds
Started Jul 11 06:54:14 PM PDT 24
Finished Jul 11 06:54:30 PM PDT 24
Peak memory 242648 kb
Host smart-428caf60-ab48-4076-b1d1-f2d8947026b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582534329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.582534329
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1993180210
Short name T935
Test name
Test status
Simulation time 462891012 ps
CPU time 3.59 seconds
Started Jul 11 06:54:16 PM PDT 24
Finished Jul 11 06:54:20 PM PDT 24
Peak memory 242188 kb
Host smart-9027881a-1a14-4f70-be04-77745a4f78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993180210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1993180210
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.1018873776
Short name T380
Test name
Test status
Simulation time 3317355840 ps
CPU time 26.21 seconds
Started Jul 11 06:54:08 PM PDT 24
Finished Jul 11 06:54:35 PM PDT 24
Peak memory 241944 kb
Host smart-c37f662f-0bb4-4c03-afdc-d9b2731fb6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018873776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1018873776
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.4049383875
Short name T12
Test name
Test status
Simulation time 2278536532 ps
CPU time 6.53 seconds
Started Jul 11 06:54:09 PM PDT 24
Finished Jul 11 06:54:17 PM PDT 24
Peak memory 242420 kb
Host smart-258dd515-54b4-4c91-a9b0-11809731c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049383875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.4049383875
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1923407712
Short name T220
Test name
Test status
Simulation time 26967379619 ps
CPU time 184.69 seconds
Started Jul 11 06:54:19 PM PDT 24
Finished Jul 11 06:57:24 PM PDT 24
Peak memory 258400 kb
Host smart-503d62e6-6caf-4707-8e06-c8dea76db198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923407712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1923407712
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3224009943
Short name T253
Test name
Test status
Simulation time 53557198031 ps
CPU time 495.64 seconds
Started Jul 11 06:54:20 PM PDT 24
Finished Jul 11 07:02:36 PM PDT 24
Peak memory 257140 kb
Host smart-70328c52-fe1c-44b4-99ee-18f215d9a224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224009943 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3224009943
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2903815339
Short name T912
Test name
Test status
Simulation time 564449849 ps
CPU time 16.91 seconds
Started Jul 11 06:54:22 PM PDT 24
Finished Jul 11 06:54:40 PM PDT 24
Peak memory 248728 kb
Host smart-fab0a290-5c2b-4b6e-9d9e-59ea75b8c88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903815339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2903815339
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.3559470532
Short name T689
Test name
Test status
Simulation time 1949150238 ps
CPU time 4.81 seconds
Started Jul 11 06:59:58 PM PDT 24
Finished Jul 11 07:00:03 PM PDT 24
Peak memory 242096 kb
Host smart-38c67987-68a6-4a48-b0f3-7f075e81f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559470532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3559470532
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.3946464582
Short name T485
Test name
Test status
Simulation time 1767308547 ps
CPU time 10.81 seconds
Started Jul 11 07:00:00 PM PDT 24
Finished Jul 11 07:00:11 PM PDT 24
Peak memory 241880 kb
Host smart-804c250c-e359-4da8-a2ab-cd8e1a9ead57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946464582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3946464582
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.1088718216
Short name T514
Test name
Test status
Simulation time 180644859 ps
CPU time 4.43 seconds
Started Jul 11 07:00:01 PM PDT 24
Finished Jul 11 07:00:06 PM PDT 24
Peak memory 242084 kb
Host smart-aa548e59-e3e3-472e-a473-498d641ba1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088718216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1088718216
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.3880747062
Short name T651
Test name
Test status
Simulation time 183311575 ps
CPU time 4.98 seconds
Started Jul 11 07:00:00 PM PDT 24
Finished Jul 11 07:00:05 PM PDT 24
Peak memory 242332 kb
Host smart-8036744a-b459-4a84-8e92-1884f1d8624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880747062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.3880747062
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.523545060
Short name T441
Test name
Test status
Simulation time 368323074 ps
CPU time 3.92 seconds
Started Jul 11 07:00:02 PM PDT 24
Finished Jul 11 07:00:07 PM PDT 24
Peak memory 242016 kb
Host smart-ed747cf2-fb62-4c77-8519-be4d0bbe5955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523545060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.523545060
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2134229470
Short name T219
Test name
Test status
Simulation time 226971955 ps
CPU time 5.57 seconds
Started Jul 11 07:00:03 PM PDT 24
Finished Jul 11 07:00:09 PM PDT 24
Peak memory 241848 kb
Host smart-13219ad2-9b38-48a4-b85d-a215b00547a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134229470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2134229470
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1458543079
Short name T1071
Test name
Test status
Simulation time 493942351 ps
CPU time 4.14 seconds
Started Jul 11 07:00:00 PM PDT 24
Finished Jul 11 07:00:05 PM PDT 24
Peak memory 241844 kb
Host smart-89b2b3d0-35e0-497b-a053-09cb7f72c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458543079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1458543079
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.920862310
Short name T416
Test name
Test status
Simulation time 474881808 ps
CPU time 8.42 seconds
Started Jul 11 06:59:58 PM PDT 24
Finished Jul 11 07:00:07 PM PDT 24
Peak memory 242272 kb
Host smart-4e23c026-3419-4525-a0f3-70518bd73d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920862310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.920862310
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.501241514
Short name T208
Test name
Test status
Simulation time 1593468531 ps
CPU time 6.81 seconds
Started Jul 11 06:59:59 PM PDT 24
Finished Jul 11 07:00:06 PM PDT 24
Peak memory 241920 kb
Host smart-7aab1082-dd4a-47c2-b578-72254abffaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501241514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.501241514
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.1742374085
Short name T707
Test name
Test status
Simulation time 565004021 ps
CPU time 8.36 seconds
Started Jul 11 07:00:02 PM PDT 24
Finished Jul 11 07:00:11 PM PDT 24
Peak memory 248544 kb
Host smart-9ad1b783-7810-4bf3-8acf-da315d98a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742374085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1742374085
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1375170970
Short name T503
Test name
Test status
Simulation time 171238062 ps
CPU time 3.69 seconds
Started Jul 11 07:00:02 PM PDT 24
Finished Jul 11 07:00:06 PM PDT 24
Peak memory 242220 kb
Host smart-2711c2c4-fa8b-47c0-89fc-127066266f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375170970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1375170970
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1077517271
Short name T164
Test name
Test status
Simulation time 351747105 ps
CPU time 4.15 seconds
Started Jul 11 07:00:01 PM PDT 24
Finished Jul 11 07:00:06 PM PDT 24
Peak memory 241980 kb
Host smart-834b2a6c-09bc-402d-a9b1-d5b22ef9e9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077517271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1077517271
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2225052789
Short name T1043
Test name
Test status
Simulation time 567423287 ps
CPU time 9.07 seconds
Started Jul 11 07:00:04 PM PDT 24
Finished Jul 11 07:00:14 PM PDT 24
Peak memory 242016 kb
Host smart-327bafde-2bf3-4c55-94e1-2ba2e40e82c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225052789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2225052789
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2608354530
Short name T132
Test name
Test status
Simulation time 528821575 ps
CPU time 4.68 seconds
Started Jul 11 07:00:04 PM PDT 24
Finished Jul 11 07:00:10 PM PDT 24
Peak memory 241988 kb
Host smart-6241b1a5-ebb7-4fe0-ba54-e1bb5c5c39cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608354530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2608354530
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.2562585923
Short name T265
Test name
Test status
Simulation time 296638801 ps
CPU time 4.26 seconds
Started Jul 11 07:00:05 PM PDT 24
Finished Jul 11 07:00:10 PM PDT 24
Peak memory 242204 kb
Host smart-0870273a-a03a-40a6-8872-b07e422c5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562585923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.2562585923
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.648269055
Short name T862
Test name
Test status
Simulation time 132968981 ps
CPU time 3.69 seconds
Started Jul 11 07:00:05 PM PDT 24
Finished Jul 11 07:00:10 PM PDT 24
Peak memory 242400 kb
Host smart-3083e0ec-5fd5-466e-8279-e4a68023e81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648269055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.648269055
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.4079398033
Short name T721
Test name
Test status
Simulation time 2753913958 ps
CPU time 12.31 seconds
Started Jul 11 07:00:06 PM PDT 24
Finished Jul 11 07:00:19 PM PDT 24
Peak memory 241876 kb
Host smart-e9dfb4e8-16b8-455e-962c-07c2cdddaa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079398033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.4079398033
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.317508918
Short name T1018
Test name
Test status
Simulation time 2023194324 ps
CPU time 6.01 seconds
Started Jul 11 07:00:07 PM PDT 24
Finished Jul 11 07:00:14 PM PDT 24
Peak memory 241932 kb
Host smart-c578e74f-800d-4f6c-93c5-2fd0af2c852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317508918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.317508918
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.385953113
Short name T685
Test name
Test status
Simulation time 147941933 ps
CPU time 4.67 seconds
Started Jul 11 07:00:04 PM PDT 24
Finished Jul 11 07:00:09 PM PDT 24
Peak memory 242216 kb
Host smart-2a690632-90dc-4c1a-8f2c-c0d156d929f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385953113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.385953113
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.1347291327
Short name T1073
Test name
Test status
Simulation time 274700086 ps
CPU time 3.5 seconds
Started Jul 11 06:54:33 PM PDT 24
Finished Jul 11 06:54:37 PM PDT 24
Peak memory 240176 kb
Host smart-ff46ebdd-6292-4772-a206-bb6af2be867c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347291327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1347291327
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1287521930
Short name T498
Test name
Test status
Simulation time 1106086379 ps
CPU time 18.61 seconds
Started Jul 11 06:54:29 PM PDT 24
Finished Jul 11 06:54:48 PM PDT 24
Peak memory 242128 kb
Host smart-cdfe6e76-62c5-4297-ade7-34779cb4aaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287521930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1287521930
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2632272537
Short name T888
Test name
Test status
Simulation time 1020725851 ps
CPU time 23.8 seconds
Started Jul 11 06:54:29 PM PDT 24
Finished Jul 11 06:54:53 PM PDT 24
Peak memory 242080 kb
Host smart-6733bf60-7e5d-444d-be95-aad6447b0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632272537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2632272537
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.399471478
Short name T993
Test name
Test status
Simulation time 420273491 ps
CPU time 4.72 seconds
Started Jul 11 06:54:25 PM PDT 24
Finished Jul 11 06:54:31 PM PDT 24
Peak memory 242080 kb
Host smart-1f6b2662-9aa5-4f96-96e7-db5bf9b4cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399471478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.399471478
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.479146139
Short name T658
Test name
Test status
Simulation time 2395088229 ps
CPU time 23.12 seconds
Started Jul 11 06:54:27 PM PDT 24
Finished Jul 11 06:54:51 PM PDT 24
Peak memory 245284 kb
Host smart-cf08a9fe-9aa2-443d-b2dc-93f397b37739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479146139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.479146139
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.330453594
Short name T1091
Test name
Test status
Simulation time 1025322815 ps
CPU time 20.55 seconds
Started Jul 11 06:54:29 PM PDT 24
Finished Jul 11 06:54:51 PM PDT 24
Peak memory 242120 kb
Host smart-03d39e55-6a0a-497d-9d80-dd9229291b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330453594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.330453594
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.3179651393
Short name T868
Test name
Test status
Simulation time 465532824 ps
CPU time 11.45 seconds
Started Jul 11 06:54:28 PM PDT 24
Finished Jul 11 06:54:40 PM PDT 24
Peak memory 242276 kb
Host smart-1804ee91-972b-4c4d-839a-15ce45c664a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179651393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3179651393
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1399633075
Short name T820
Test name
Test status
Simulation time 11068087541 ps
CPU time 24.37 seconds
Started Jul 11 06:54:25 PM PDT 24
Finished Jul 11 06:54:50 PM PDT 24
Peak memory 242160 kb
Host smart-58e1381e-5fbc-4900-b1d3-1936aff33a40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399633075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1399633075
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2460683386
Short name T1080
Test name
Test status
Simulation time 559608118 ps
CPU time 8.98 seconds
Started Jul 11 06:54:33 PM PDT 24
Finished Jul 11 06:54:43 PM PDT 24
Peak memory 242188 kb
Host smart-6008bc41-ba9e-4754-a79b-b65432454db4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460683386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2460683386
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1878415613
Short name T836
Test name
Test status
Simulation time 135680505 ps
CPU time 3.46 seconds
Started Jul 11 06:54:29 PM PDT 24
Finished Jul 11 06:54:33 PM PDT 24
Peak memory 242332 kb
Host smart-7feea2e5-1c44-46b5-9a47-2e26dfb16faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878415613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1878415613
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2021740386
Short name T280
Test name
Test status
Simulation time 96993107075 ps
CPU time 1423.22 seconds
Started Jul 11 06:54:31 PM PDT 24
Finished Jul 11 07:18:15 PM PDT 24
Peak memory 262396 kb
Host smart-d8f1462f-f0a9-44bd-bb2a-247128167b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021740386 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.2021740386
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.1326636050
Short name T372
Test name
Test status
Simulation time 645747587 ps
CPU time 27.02 seconds
Started Jul 11 06:54:33 PM PDT 24
Finished Jul 11 06:55:01 PM PDT 24
Peak memory 242484 kb
Host smart-e826735f-2d2d-42de-a815-674b95839f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326636050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1326636050
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.3425259254
Short name T127
Test name
Test status
Simulation time 516995789 ps
CPU time 4.1 seconds
Started Jul 11 07:00:05 PM PDT 24
Finished Jul 11 07:00:11 PM PDT 24
Peak memory 242400 kb
Host smart-54b164a4-ac7d-4acd-bbae-317504e3c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425259254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3425259254
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3414389988
Short name T1105
Test name
Test status
Simulation time 159763299 ps
CPU time 3.48 seconds
Started Jul 11 07:00:06 PM PDT 24
Finished Jul 11 07:00:10 PM PDT 24
Peak memory 241896 kb
Host smart-a740d423-656c-4523-8e1f-2c2a4edf0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414389988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3414389988
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.2923279847
Short name T1078
Test name
Test status
Simulation time 176119737 ps
CPU time 4.03 seconds
Started Jul 11 07:00:06 PM PDT 24
Finished Jul 11 07:00:11 PM PDT 24
Peak memory 242088 kb
Host smart-0899cde0-55f2-40ad-91db-074e76fa2326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923279847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2923279847
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.191195285
Short name T129
Test name
Test status
Simulation time 943804533 ps
CPU time 13.36 seconds
Started Jul 11 07:00:03 PM PDT 24
Finished Jul 11 07:00:17 PM PDT 24
Peak memory 242188 kb
Host smart-93f42497-3b56-445c-973b-abeac86dcd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191195285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.191195285
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.4234704843
Short name T55
Test name
Test status
Simulation time 347384973 ps
CPU time 4.64 seconds
Started Jul 11 07:00:09 PM PDT 24
Finished Jul 11 07:00:14 PM PDT 24
Peak memory 242236 kb
Host smart-fda1c0fc-907f-4c96-8070-73d358a9d9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234704843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4234704843
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.1403068189
Short name T334
Test name
Test status
Simulation time 796531008 ps
CPU time 13.87 seconds
Started Jul 11 07:00:10 PM PDT 24
Finished Jul 11 07:00:25 PM PDT 24
Peak memory 241896 kb
Host smart-485ad9fe-d23d-49c3-8b6d-8c6581e6cca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403068189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1403068189
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.1243474429
Short name T1104
Test name
Test status
Simulation time 182436500 ps
CPU time 3.86 seconds
Started Jul 11 07:00:10 PM PDT 24
Finished Jul 11 07:00:15 PM PDT 24
Peak memory 242016 kb
Host smart-fd49862c-4844-4b90-bbe4-f57974060f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243474429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1243474429
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2208965462
Short name T91
Test name
Test status
Simulation time 1153016911 ps
CPU time 17.09 seconds
Started Jul 11 07:00:10 PM PDT 24
Finished Jul 11 07:00:28 PM PDT 24
Peak memory 242316 kb
Host smart-6fd8d454-f050-445d-ba5b-389611ce5677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208965462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2208965462
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.361106863
Short name T681
Test name
Test status
Simulation time 435316911 ps
CPU time 3.34 seconds
Started Jul 11 07:00:10 PM PDT 24
Finished Jul 11 07:00:15 PM PDT 24
Peak memory 242292 kb
Host smart-dafa65aa-f71c-4521-aeac-c3364eb5c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361106863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.361106863
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.863078425
Short name T674
Test name
Test status
Simulation time 598267696 ps
CPU time 8.42 seconds
Started Jul 11 07:00:11 PM PDT 24
Finished Jul 11 07:00:20 PM PDT 24
Peak memory 242092 kb
Host smart-fdc456cd-be08-4fd4-825a-f47e3c425c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863078425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.863078425
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.111400985
Short name T775
Test name
Test status
Simulation time 602237411 ps
CPU time 20.28 seconds
Started Jul 11 07:00:10 PM PDT 24
Finished Jul 11 07:00:31 PM PDT 24
Peak memory 242216 kb
Host smart-a96deeb4-1f78-4ac2-af4f-27de7af36908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111400985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.111400985
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.721992726
Short name T456
Test name
Test status
Simulation time 220291738 ps
CPU time 4.24 seconds
Started Jul 11 07:00:07 PM PDT 24
Finished Jul 11 07:00:12 PM PDT 24
Peak memory 242120 kb
Host smart-d0ae1111-cfcb-408b-832b-47f01cff9a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721992726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.721992726
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.734426692
Short name T769
Test name
Test status
Simulation time 1571407935 ps
CPU time 2.86 seconds
Started Jul 11 07:00:15 PM PDT 24
Finished Jul 11 07:00:18 PM PDT 24
Peak memory 245424 kb
Host smart-4b039269-da80-488a-847c-3052f1a04b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734426692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.734426692
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.565309645
Short name T1013
Test name
Test status
Simulation time 667871998 ps
CPU time 5.73 seconds
Started Jul 11 07:00:14 PM PDT 24
Finished Jul 11 07:00:20 PM PDT 24
Peak memory 242156 kb
Host smart-c3eb5f70-43e4-4219-b76d-70ac940ced4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565309645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.565309645
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.4235287097
Short name T981
Test name
Test status
Simulation time 1239767686 ps
CPU time 19.01 seconds
Started Jul 11 07:00:16 PM PDT 24
Finished Jul 11 07:00:36 PM PDT 24
Peak memory 242320 kb
Host smart-c6c45b71-039c-4095-8bea-7f6b4b90be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235287097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.4235287097
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.954533379
Short name T797
Test name
Test status
Simulation time 272739315 ps
CPU time 3.98 seconds
Started Jul 11 07:00:15 PM PDT 24
Finished Jul 11 07:00:20 PM PDT 24
Peak memory 242592 kb
Host smart-d70d3774-633b-4ccd-8fe9-15182c25f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954533379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.954533379
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2682295491
Short name T908
Test name
Test status
Simulation time 212957468 ps
CPU time 4.92 seconds
Started Jul 11 07:00:13 PM PDT 24
Finished Jul 11 07:00:19 PM PDT 24
Peak memory 242292 kb
Host smart-8df994fb-6926-49b1-ac0d-ccefb4e37bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682295491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2682295491
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1167949750
Short name T250
Test name
Test status
Simulation time 323354851 ps
CPU time 18.74 seconds
Started Jul 11 07:00:18 PM PDT 24
Finished Jul 11 07:00:37 PM PDT 24
Peak memory 241888 kb
Host smart-22dd3cf4-a9b8-4e89-9e63-03c6516cdfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167949750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1167949750
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.679491721
Short name T9
Test name
Test status
Simulation time 52796654 ps
CPU time 1.67 seconds
Started Jul 11 06:54:45 PM PDT 24
Finished Jul 11 06:54:48 PM PDT 24
Peak memory 240184 kb
Host smart-b09a2838-a056-4576-a47e-019f798803b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679491721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.679491721
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.579302334
Short name T87
Test name
Test status
Simulation time 6220716909 ps
CPU time 9.39 seconds
Started Jul 11 06:54:36 PM PDT 24
Finished Jul 11 06:54:47 PM PDT 24
Peak memory 242996 kb
Host smart-08a09055-8696-42c1-91f5-984820bed690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579302334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.579302334
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.282573765
Short name T1079
Test name
Test status
Simulation time 499466463 ps
CPU time 23.71 seconds
Started Jul 11 06:54:38 PM PDT 24
Finished Jul 11 06:55:03 PM PDT 24
Peak memory 242032 kb
Host smart-061bbbf0-9e94-48c7-8167-417b132bc165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282573765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.282573765
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.3038960355
Short name T614
Test name
Test status
Simulation time 3138783656 ps
CPU time 5.54 seconds
Started Jul 11 06:54:39 PM PDT 24
Finished Jul 11 06:54:46 PM PDT 24
Peak memory 242092 kb
Host smart-7e886754-fef1-41d6-baf5-8cbd09106ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038960355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3038960355
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1618979407
Short name T660
Test name
Test status
Simulation time 1796114699 ps
CPU time 3.35 seconds
Started Jul 11 06:54:38 PM PDT 24
Finished Jul 11 06:54:43 PM PDT 24
Peak memory 242040 kb
Host smart-c8254636-5e24-4a7b-8767-5009cc79ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618979407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1618979407
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.3276256358
Short name T143
Test name
Test status
Simulation time 2493480549 ps
CPU time 19.72 seconds
Started Jul 11 06:54:41 PM PDT 24
Finished Jul 11 06:55:01 PM PDT 24
Peak memory 244564 kb
Host smart-67fc0895-2daf-477d-8ca5-89a5cebc164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276256358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3276256358
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.4260055276
Short name T239
Test name
Test status
Simulation time 514446658 ps
CPU time 13.84 seconds
Started Jul 11 06:54:38 PM PDT 24
Finished Jul 11 06:54:53 PM PDT 24
Peak memory 241968 kb
Host smart-e418e996-a542-4cb9-b0c6-e365d4bf3088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260055276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.4260055276
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1114024169
Short name T445
Test name
Test status
Simulation time 3258060874 ps
CPU time 7.65 seconds
Started Jul 11 06:54:37 PM PDT 24
Finished Jul 11 06:54:45 PM PDT 24
Peak memory 242032 kb
Host smart-db6ce14e-d565-4cce-b275-477a11403bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114024169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1114024169
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2159237783
Short name T449
Test name
Test status
Simulation time 578219923 ps
CPU time 8.95 seconds
Started Jul 11 06:54:44 PM PDT 24
Finished Jul 11 06:54:54 PM PDT 24
Peak memory 242116 kb
Host smart-a09c14ac-76fb-406c-882e-d9be6323adbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159237783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2159237783
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3573329170
Short name T553
Test name
Test status
Simulation time 927446028 ps
CPU time 8.86 seconds
Started Jul 11 06:54:39 PM PDT 24
Finished Jul 11 06:54:49 PM PDT 24
Peak memory 242092 kb
Host smart-67bc32ea-2ee0-443a-8061-f2b93ba8c255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573329170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3573329170
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.2243612403
Short name T945
Test name
Test status
Simulation time 458702248051 ps
CPU time 828.29 seconds
Started Jul 11 06:54:45 PM PDT 24
Finished Jul 11 07:08:35 PM PDT 24
Peak memory 328628 kb
Host smart-29dca7fa-3a3d-420b-a510-e0835725e8c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243612403 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.2243612403
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1671961255
Short name T1001
Test name
Test status
Simulation time 20044791599 ps
CPU time 42.76 seconds
Started Jul 11 06:54:39 PM PDT 24
Finished Jul 11 06:55:23 PM PDT 24
Peak memory 243208 kb
Host smart-1ca4017c-8063-44a4-88cc-e50a2ec932a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671961255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1671961255
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.860666407
Short name T734
Test name
Test status
Simulation time 148799881 ps
CPU time 4.83 seconds
Started Jul 11 07:00:20 PM PDT 24
Finished Jul 11 07:00:25 PM PDT 24
Peak memory 242108 kb
Host smart-339d341c-b2ef-48cd-9c18-153a64e50b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860666407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.860666407
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.866667674
Short name T773
Test name
Test status
Simulation time 1843381575 ps
CPU time 7.54 seconds
Started Jul 11 07:00:15 PM PDT 24
Finished Jul 11 07:00:23 PM PDT 24
Peak memory 241964 kb
Host smart-286b8f87-05c8-42c4-8b01-5fcaba12ded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866667674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.866667674
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.1025392177
Short name T1126
Test name
Test status
Simulation time 131619751 ps
CPU time 3.2 seconds
Started Jul 11 07:00:20 PM PDT 24
Finished Jul 11 07:00:24 PM PDT 24
Peak memory 241928 kb
Host smart-49720194-168c-4d7d-84db-3b61f514855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025392177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1025392177
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3083143562
Short name T423
Test name
Test status
Simulation time 1161346282 ps
CPU time 27.03 seconds
Started Jul 11 07:00:19 PM PDT 24
Finished Jul 11 07:00:47 PM PDT 24
Peak memory 242228 kb
Host smart-340eea1d-8705-4a0b-9d82-fb74e564745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083143562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3083143562
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.2426870891
Short name T1114
Test name
Test status
Simulation time 263654471 ps
CPU time 3.74 seconds
Started Jul 11 07:00:23 PM PDT 24
Finished Jul 11 07:00:28 PM PDT 24
Peak memory 242344 kb
Host smart-fe24ea43-3c39-40df-921b-959308612255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426870891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2426870891
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3362982021
Short name T726
Test name
Test status
Simulation time 522537245 ps
CPU time 5.77 seconds
Started Jul 11 07:00:22 PM PDT 24
Finished Jul 11 07:00:29 PM PDT 24
Peak memory 242040 kb
Host smart-520522de-fd38-47dd-bcb8-d1550539abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362982021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3362982021
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1779310365
Short name T569
Test name
Test status
Simulation time 413876710 ps
CPU time 4.49 seconds
Started Jul 11 07:00:22 PM PDT 24
Finished Jul 11 07:00:28 PM PDT 24
Peak memory 241948 kb
Host smart-e51fd01a-8005-49d0-8098-52c7919150c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779310365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1779310365
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.1785600475
Short name T668
Test name
Test status
Simulation time 321353423 ps
CPU time 6.18 seconds
Started Jul 11 07:00:21 PM PDT 24
Finished Jul 11 07:00:28 PM PDT 24
Peak memory 241924 kb
Host smart-d3715312-550b-4a2d-8063-757b27987545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785600475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1785600475
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1418658208
Short name T753
Test name
Test status
Simulation time 360065668 ps
CPU time 4.89 seconds
Started Jul 11 07:00:28 PM PDT 24
Finished Jul 11 07:00:34 PM PDT 24
Peak memory 242096 kb
Host smart-f66b69d4-2c0f-4e8f-9853-9f1d19d87be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418658208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1418658208
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.4090028748
Short name T1014
Test name
Test status
Simulation time 311302824 ps
CPU time 16.71 seconds
Started Jul 11 07:00:23 PM PDT 24
Finished Jul 11 07:00:41 PM PDT 24
Peak memory 242140 kb
Host smart-0d084579-5c18-4255-8b6f-95f76d964478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090028748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.4090028748
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3421153822
Short name T1087
Test name
Test status
Simulation time 198895867 ps
CPU time 4.3 seconds
Started Jul 11 07:00:24 PM PDT 24
Finished Jul 11 07:00:29 PM PDT 24
Peak memory 242476 kb
Host smart-50fdb7a3-31e6-4374-9455-d91d9d22b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421153822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3421153822
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.4100768701
Short name T626
Test name
Test status
Simulation time 266232733 ps
CPU time 7.36 seconds
Started Jul 11 07:00:21 PM PDT 24
Finished Jul 11 07:00:30 PM PDT 24
Peak memory 242200 kb
Host smart-095e8a39-6126-4e8b-9d79-a482a463258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100768701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.4100768701
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3003058357
Short name T131
Test name
Test status
Simulation time 154560969 ps
CPU time 4.28 seconds
Started Jul 11 07:00:20 PM PDT 24
Finished Jul 11 07:00:25 PM PDT 24
Peak memory 242184 kb
Host smart-53e25cde-b75c-4486-be2e-a265aeb24df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003058357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3003058357
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2167584514
Short name T480
Test name
Test status
Simulation time 269687962 ps
CPU time 6.56 seconds
Started Jul 11 07:00:29 PM PDT 24
Finished Jul 11 07:00:37 PM PDT 24
Peak memory 241820 kb
Host smart-58d3610c-3a39-42b0-a3e8-db303d5d78f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167584514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2167584514
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2551502029
Short name T610
Test name
Test status
Simulation time 104070622 ps
CPU time 3.83 seconds
Started Jul 11 07:00:31 PM PDT 24
Finished Jul 11 07:00:36 PM PDT 24
Peak memory 241888 kb
Host smart-da4e7e54-f023-4313-9384-c594b7efd7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551502029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2551502029
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2956520836
Short name T192
Test name
Test status
Simulation time 131544749 ps
CPU time 4.15 seconds
Started Jul 11 07:00:27 PM PDT 24
Finished Jul 11 07:00:32 PM PDT 24
Peak memory 241792 kb
Host smart-a4a32489-d3a3-4f34-abbd-9dc54aad4043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956520836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2956520836
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.932862332
Short name T865
Test name
Test status
Simulation time 504353388 ps
CPU time 3.26 seconds
Started Jul 11 07:00:27 PM PDT 24
Finished Jul 11 07:00:31 PM PDT 24
Peak memory 241984 kb
Host smart-1280fae7-accb-4b89-b371-a33f43a81584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932862332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.932862332
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.911227168
Short name T602
Test name
Test status
Simulation time 142151046 ps
CPU time 4.27 seconds
Started Jul 11 07:00:32 PM PDT 24
Finished Jul 11 07:00:37 PM PDT 24
Peak memory 241960 kb
Host smart-ce6abca1-15e4-43d1-9a0b-cee63298720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911227168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.911227168
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1623752636
Short name T1194
Test name
Test status
Simulation time 238602535 ps
CPU time 4.81 seconds
Started Jul 11 07:00:24 PM PDT 24
Finished Jul 11 07:00:30 PM PDT 24
Peak memory 242492 kb
Host smart-c266dc58-c5b6-4ef0-b899-3f75a2555fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623752636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1623752636
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.382151992
Short name T823
Test name
Test status
Simulation time 110103642 ps
CPU time 2.55 seconds
Started Jul 11 07:00:24 PM PDT 24
Finished Jul 11 07:00:28 PM PDT 24
Peak memory 242056 kb
Host smart-6b440354-4cdb-42fe-abcf-6d53f60b00e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382151992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.382151992
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.4097761872
Short name T693
Test name
Test status
Simulation time 71556166 ps
CPU time 2.05 seconds
Started Jul 11 06:54:55 PM PDT 24
Finished Jul 11 06:54:58 PM PDT 24
Peak memory 240484 kb
Host smart-d185bfea-7c13-4e84-8a35-d6d271edad86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097761872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.4097761872
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2356948674
Short name T57
Test name
Test status
Simulation time 2068457820 ps
CPU time 11.8 seconds
Started Jul 11 06:54:50 PM PDT 24
Finished Jul 11 06:55:02 PM PDT 24
Peak memory 248728 kb
Host smart-5f1e4661-7616-4bbb-b738-c02916074b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356948674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2356948674
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.1847775559
Short name T620
Test name
Test status
Simulation time 354361304 ps
CPU time 8.22 seconds
Started Jul 11 06:54:51 PM PDT 24
Finished Jul 11 06:55:00 PM PDT 24
Peak memory 242356 kb
Host smart-983943ac-6d8c-41ff-8854-34d6690d6150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847775559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1847775559
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.1077929166
Short name T793
Test name
Test status
Simulation time 525642233 ps
CPU time 13.03 seconds
Started Jul 11 06:54:50 PM PDT 24
Finished Jul 11 06:55:04 PM PDT 24
Peak memory 242000 kb
Host smart-774b9395-b75b-4247-ad42-4094390b305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077929166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1077929166
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.4203137334
Short name T534
Test name
Test status
Simulation time 652393349 ps
CPU time 4.6 seconds
Started Jul 11 06:54:43 PM PDT 24
Finished Jul 11 06:54:49 PM PDT 24
Peak memory 242136 kb
Host smart-dcf52760-adea-4af6-bcb8-98c8290af2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203137334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.4203137334
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.1553600619
Short name T1053
Test name
Test status
Simulation time 207500201 ps
CPU time 4.19 seconds
Started Jul 11 06:54:50 PM PDT 24
Finished Jul 11 06:54:55 PM PDT 24
Peak memory 242168 kb
Host smart-19a263a7-e9d6-462d-8820-64572a15dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553600619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1553600619
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3565944493
Short name T176
Test name
Test status
Simulation time 629285527 ps
CPU time 10.75 seconds
Started Jul 11 06:54:51 PM PDT 24
Finished Jul 11 06:55:02 PM PDT 24
Peak memory 242080 kb
Host smart-9eda6a33-75fd-4058-b8a8-68be846066c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565944493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3565944493
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.451883113
Short name T857
Test name
Test status
Simulation time 317395039 ps
CPU time 9.84 seconds
Started Jul 11 06:54:45 PM PDT 24
Finished Jul 11 06:54:56 PM PDT 24
Peak memory 242160 kb
Host smart-613b637c-26fd-4117-9e0d-1893fc270f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451883113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.451883113
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.319170359
Short name T932
Test name
Test status
Simulation time 406074077 ps
CPU time 12.47 seconds
Started Jul 11 06:54:45 PM PDT 24
Finished Jul 11 06:54:59 PM PDT 24
Peak memory 242280 kb
Host smart-82fb21df-0e2f-4440-b05b-c4977919afba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319170359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.319170359
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.1832507240
Short name T152
Test name
Test status
Simulation time 1823195665 ps
CPU time 4.75 seconds
Started Jul 11 06:54:50 PM PDT 24
Finished Jul 11 06:54:56 PM PDT 24
Peak memory 248756 kb
Host smart-dcd97599-e005-4076-be27-2beec0bf64b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832507240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1832507240
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.288759507
Short name T729
Test name
Test status
Simulation time 536608769 ps
CPU time 6.1 seconds
Started Jul 11 06:54:45 PM PDT 24
Finished Jul 11 06:54:52 PM PDT 24
Peak memory 248596 kb
Host smart-accf7d2a-af86-4888-a5bc-07682a5a6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288759507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.288759507
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3363551152
Short name T196
Test name
Test status
Simulation time 41213334781 ps
CPU time 210.52 seconds
Started Jul 11 06:54:53 PM PDT 24
Finished Jul 11 06:58:24 PM PDT 24
Peak memory 262288 kb
Host smart-ff445c31-22e7-4f80-a6e3-1d108228f272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363551152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3363551152
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.938330602
Short name T506
Test name
Test status
Simulation time 301129157083 ps
CPU time 468.95 seconds
Started Jul 11 06:54:49 PM PDT 24
Finished Jul 11 07:02:39 PM PDT 24
Peak memory 278580 kb
Host smart-ddf96a7f-5cc5-4af2-b0c1-a641c7fc0dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938330602 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.938330602
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3022400109
Short name T850
Test name
Test status
Simulation time 667872623 ps
CPU time 23.19 seconds
Started Jul 11 06:54:51 PM PDT 24
Finished Jul 11 06:55:15 PM PDT 24
Peak memory 242084 kb
Host smart-7a1f1335-746a-4aa2-b971-668916f07816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022400109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3022400109
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.1538651281
Short name T1012
Test name
Test status
Simulation time 111179813 ps
CPU time 4.32 seconds
Started Jul 11 07:00:31 PM PDT 24
Finished Jul 11 07:00:36 PM PDT 24
Peak memory 241968 kb
Host smart-2505e02f-8e67-4452-a4a6-cb2999f5b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538651281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1538651281
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.358401433
Short name T431
Test name
Test status
Simulation time 1204131557 ps
CPU time 10.13 seconds
Started Jul 11 07:00:27 PM PDT 24
Finished Jul 11 07:00:38 PM PDT 24
Peak memory 241912 kb
Host smart-c97591a6-9ff1-4269-8892-e3a9a1e3b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358401433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.358401433
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2797441444
Short name T509
Test name
Test status
Simulation time 136133395 ps
CPU time 4.21 seconds
Started Jul 11 07:00:32 PM PDT 24
Finished Jul 11 07:00:37 PM PDT 24
Peak memory 242008 kb
Host smart-ab24d661-82ff-4ffe-a7d8-5598ea0e29ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797441444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2797441444
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.1241555136
Short name T589
Test name
Test status
Simulation time 774436573 ps
CPU time 18.16 seconds
Started Jul 11 07:00:26 PM PDT 24
Finished Jul 11 07:00:45 PM PDT 24
Peak memory 242040 kb
Host smart-e0fa3242-c5cd-4354-bea0-230508039399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241555136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1241555136
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.4014827835
Short name T1030
Test name
Test status
Simulation time 1641874988 ps
CPU time 3.56 seconds
Started Jul 11 07:00:26 PM PDT 24
Finished Jul 11 07:00:31 PM PDT 24
Peak memory 242380 kb
Host smart-934c5f01-6175-4ac3-8822-8f19a9da0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014827835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.4014827835
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2793741769
Short name T491
Test name
Test status
Simulation time 171231546 ps
CPU time 5 seconds
Started Jul 11 07:00:29 PM PDT 24
Finished Jul 11 07:00:34 PM PDT 24
Peak memory 241836 kb
Host smart-c6eb1fad-c476-40a8-a297-df16f97bed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793741769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2793741769
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.4207878408
Short name T1050
Test name
Test status
Simulation time 1779889168 ps
CPU time 3.84 seconds
Started Jul 11 07:00:27 PM PDT 24
Finished Jul 11 07:00:32 PM PDT 24
Peak memory 242096 kb
Host smart-c33131d0-7964-4ae5-8b96-44440228c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207878408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.4207878408
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2957593197
Short name T612
Test name
Test status
Simulation time 241026206 ps
CPU time 3.28 seconds
Started Jul 11 07:00:34 PM PDT 24
Finished Jul 11 07:00:38 PM PDT 24
Peak memory 241796 kb
Host smart-c091357b-f516-4ee4-9c68-c313a3a6087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957593197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2957593197
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1868516886
Short name T162
Test name
Test status
Simulation time 90456631 ps
CPU time 3.29 seconds
Started Jul 11 07:00:32 PM PDT 24
Finished Jul 11 07:00:36 PM PDT 24
Peak memory 242376 kb
Host smart-1992a594-7a13-476b-a4bf-bba506a5eaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868516886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1868516886
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3800476006
Short name T492
Test name
Test status
Simulation time 4290589848 ps
CPU time 11.66 seconds
Started Jul 11 07:00:31 PM PDT 24
Finished Jul 11 07:00:43 PM PDT 24
Peak memory 242016 kb
Host smart-f3b112e7-ccc6-4076-8b2e-03ae27972948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800476006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3800476006
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.2431277564
Short name T78
Test name
Test status
Simulation time 99005480 ps
CPU time 4.38 seconds
Started Jul 11 07:00:34 PM PDT 24
Finished Jul 11 07:00:39 PM PDT 24
Peak memory 242024 kb
Host smart-44c934ec-905f-40c7-b11c-2f19bb89b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431277564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2431277564
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.4019573333
Short name T455
Test name
Test status
Simulation time 348440429 ps
CPU time 20.5 seconds
Started Jul 11 07:00:31 PM PDT 24
Finished Jul 11 07:00:53 PM PDT 24
Peak memory 241792 kb
Host smart-0d4f1b08-f780-4423-af68-10fc24282f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019573333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.4019573333
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2380997683
Short name T1179
Test name
Test status
Simulation time 2534707109 ps
CPU time 6.1 seconds
Started Jul 11 07:00:31 PM PDT 24
Finished Jul 11 07:00:38 PM PDT 24
Peak memory 241836 kb
Host smart-a7a219bd-0a32-4905-a86e-8429857bbc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380997683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2380997683
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2987412647
Short name T121
Test name
Test status
Simulation time 120862612 ps
CPU time 3.26 seconds
Started Jul 11 07:00:34 PM PDT 24
Finished Jul 11 07:00:38 PM PDT 24
Peak memory 242064 kb
Host smart-8e81f8c8-c2d8-44e2-9f34-f607b1323477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987412647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2987412647
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1965783659
Short name T504
Test name
Test status
Simulation time 240506157 ps
CPU time 7.2 seconds
Started Jul 11 07:00:35 PM PDT 24
Finished Jul 11 07:00:44 PM PDT 24
Peak memory 241968 kb
Host smart-ff6882c0-955d-4473-8193-cdedfe48aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965783659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1965783659
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1391520750
Short name T987
Test name
Test status
Simulation time 307283838 ps
CPU time 4.24 seconds
Started Jul 11 07:00:34 PM PDT 24
Finished Jul 11 07:00:39 PM PDT 24
Peak memory 241956 kb
Host smart-b824937d-49ec-4002-924d-29f30d4f4c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391520750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1391520750
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.3218647364
Short name T323
Test name
Test status
Simulation time 287996815 ps
CPU time 4.67 seconds
Started Jul 11 07:01:25 PM PDT 24
Finished Jul 11 07:01:31 PM PDT 24
Peak memory 242296 kb
Host smart-588b5793-9b93-4002-b3c3-2c6b4f91224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218647364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3218647364
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.888258405
Short name T691
Test name
Test status
Simulation time 745984748 ps
CPU time 2.17 seconds
Started Jul 11 06:55:06 PM PDT 24
Finished Jul 11 06:55:09 PM PDT 24
Peak memory 240140 kb
Host smart-3016b0a4-ceb6-4b4a-837e-47cce962c145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888258405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.888258405
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.258754025
Short name T16
Test name
Test status
Simulation time 1596643881 ps
CPU time 19.76 seconds
Started Jul 11 06:54:54 PM PDT 24
Finished Jul 11 06:55:14 PM PDT 24
Peak memory 241916 kb
Host smart-44b1711d-00a6-4f5d-999f-71ec3ab474ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258754025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.258754025
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.535304545
Short name T245
Test name
Test status
Simulation time 434717986 ps
CPU time 4.6 seconds
Started Jul 11 06:54:55 PM PDT 24
Finished Jul 11 06:55:00 PM PDT 24
Peak memory 242648 kb
Host smart-3b4d300f-bd04-4f21-b40b-e9018a384324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535304545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.535304545
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.692974301
Short name T1044
Test name
Test status
Simulation time 522252782 ps
CPU time 5.91 seconds
Started Jul 11 06:54:53 PM PDT 24
Finished Jul 11 06:54:59 PM PDT 24
Peak memory 242020 kb
Host smart-5f60d5eb-7830-473a-99e9-652488154f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692974301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.692974301
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.3402887481
Short name T905
Test name
Test status
Simulation time 332460754 ps
CPU time 7.77 seconds
Started Jul 11 06:54:55 PM PDT 24
Finished Jul 11 06:55:04 PM PDT 24
Peak memory 248744 kb
Host smart-2d9d0f99-7a7d-409e-b82a-287dc1a9e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402887481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.3402887481
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.1225861743
Short name T387
Test name
Test status
Simulation time 1294088587 ps
CPU time 31.97 seconds
Started Jul 11 06:54:59 PM PDT 24
Finished Jul 11 06:55:31 PM PDT 24
Peak memory 242252 kb
Host smart-10f2f47d-7a45-4ef6-8fe7-c991866c7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225861743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1225861743
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.184080686
Short name T1088
Test name
Test status
Simulation time 761692328 ps
CPU time 6.12 seconds
Started Jul 11 06:54:54 PM PDT 24
Finished Jul 11 06:55:01 PM PDT 24
Peak memory 242192 kb
Host smart-58f23442-4b79-4e3d-8597-c3103b8d5ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184080686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.184080686
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1928327339
Short name T551
Test name
Test status
Simulation time 3753447472 ps
CPU time 10.06 seconds
Started Jul 11 06:54:53 PM PDT 24
Finished Jul 11 06:55:04 PM PDT 24
Peak memory 242372 kb
Host smart-00b7fa85-c5c5-4fc4-af4b-e671e6535d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928327339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1928327339
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.1526240915
Short name T654
Test name
Test status
Simulation time 120251472 ps
CPU time 4.13 seconds
Started Jul 11 06:54:58 PM PDT 24
Finished Jul 11 06:55:03 PM PDT 24
Peak memory 242480 kb
Host smart-74711a64-86cd-408e-b05a-4b6407d47c0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526240915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1526240915
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1106793932
Short name T922
Test name
Test status
Simulation time 321915186 ps
CPU time 6.28 seconds
Started Jul 11 06:54:54 PM PDT 24
Finished Jul 11 06:55:01 PM PDT 24
Peak memory 241964 kb
Host smart-fdac1bef-3f1f-45c0-9cc4-cad696b84d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106793932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1106793932
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.2335549161
Short name T1048
Test name
Test status
Simulation time 1066988098 ps
CPU time 2.59 seconds
Started Jul 11 06:55:02 PM PDT 24
Finished Jul 11 06:55:06 PM PDT 24
Peak memory 241660 kb
Host smart-f18c0c93-7ad7-4578-a119-7826436f8723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335549161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.2335549161
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.2832885434
Short name T670
Test name
Test status
Simulation time 101196661288 ps
CPU time 1277.46 seconds
Started Jul 11 06:55:02 PM PDT 24
Finished Jul 11 07:16:20 PM PDT 24
Peak memory 365584 kb
Host smart-edc66709-f627-4aae-a91c-45e134fafb47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832885434 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.2832885434
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.1215757586
Short name T547
Test name
Test status
Simulation time 2138214394 ps
CPU time 15.79 seconds
Started Jul 11 06:55:02 PM PDT 24
Finished Jul 11 06:55:19 PM PDT 24
Peak memory 242244 kb
Host smart-8a75b0ce-ffc2-470e-a05c-823087c42f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215757586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1215757586
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.4126508825
Short name T704
Test name
Test status
Simulation time 640398112 ps
CPU time 4.53 seconds
Started Jul 11 07:00:43 PM PDT 24
Finished Jul 11 07:00:48 PM PDT 24
Peak memory 241904 kb
Host smart-39e1d672-6b94-4e7c-a6c5-dc71d123ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126508825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.4126508825
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1019092446
Short name T970
Test name
Test status
Simulation time 2491875910 ps
CPU time 6.96 seconds
Started Jul 11 07:00:35 PM PDT 24
Finished Jul 11 07:00:43 PM PDT 24
Peak memory 242412 kb
Host smart-973b48ca-09f4-444a-b7f2-344dd05ce20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019092446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1019092446
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2966528285
Short name T511
Test name
Test status
Simulation time 280982857 ps
CPU time 4.47 seconds
Started Jul 11 07:00:36 PM PDT 24
Finished Jul 11 07:00:42 PM PDT 24
Peak memory 241852 kb
Host smart-902eec66-2f39-44af-9f3c-b4dfdb0ad17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966528285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2966528285
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3464633440
Short name T426
Test name
Test status
Simulation time 122210483 ps
CPU time 3.18 seconds
Started Jul 11 07:00:36 PM PDT 24
Finished Jul 11 07:00:42 PM PDT 24
Peak memory 242220 kb
Host smart-647b4114-4717-460d-8bb9-1af8c32d51db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464633440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3464633440
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3945782380
Short name T159
Test name
Test status
Simulation time 283603823 ps
CPU time 4.38 seconds
Started Jul 11 07:00:41 PM PDT 24
Finished Jul 11 07:00:46 PM PDT 24
Peak memory 241804 kb
Host smart-6630d886-99ce-4630-a5d8-24cb1555518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945782380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3945782380
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.310285977
Short name T744
Test name
Test status
Simulation time 432305321 ps
CPU time 9.32 seconds
Started Jul 11 07:00:39 PM PDT 24
Finished Jul 11 07:00:49 PM PDT 24
Peak memory 241904 kb
Host smart-c8118d4f-10d8-40c0-876a-06f247063181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310285977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.310285977
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3787403269
Short name T1027
Test name
Test status
Simulation time 2215113478 ps
CPU time 5.87 seconds
Started Jul 11 07:00:47 PM PDT 24
Finished Jul 11 07:00:54 PM PDT 24
Peak memory 242060 kb
Host smart-bfc18d4a-8388-4689-91fb-da942751602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787403269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3787403269
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.2880356466
Short name T867
Test name
Test status
Simulation time 617922941 ps
CPU time 5.1 seconds
Started Jul 11 07:00:47 PM PDT 24
Finished Jul 11 07:00:54 PM PDT 24
Peak memory 241764 kb
Host smart-667b6b31-5ff2-4162-9207-30be91a7641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880356466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2880356466
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.968569864
Short name T414
Test name
Test status
Simulation time 404089645 ps
CPU time 3.94 seconds
Started Jul 11 07:00:46 PM PDT 24
Finished Jul 11 07:00:51 PM PDT 24
Peak memory 241932 kb
Host smart-1ff8436e-d435-4184-bc52-dac243f9158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968569864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.968569864
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.3134100481
Short name T919
Test name
Test status
Simulation time 1805693595 ps
CPU time 4.85 seconds
Started Jul 11 07:00:48 PM PDT 24
Finished Jul 11 07:00:54 PM PDT 24
Peak memory 242400 kb
Host smart-726142c9-69c1-4f9f-8df5-dc639a44e0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134100481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3134100481
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.2893983470
Short name T630
Test name
Test status
Simulation time 629021419 ps
CPU time 17.3 seconds
Started Jul 11 07:00:46 PM PDT 24
Finished Jul 11 07:01:04 PM PDT 24
Peak memory 241824 kb
Host smart-45ec22e5-2dc0-4234-8a11-52c358751e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893983470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2893983470
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.424356301
Short name T921
Test name
Test status
Simulation time 739145010 ps
CPU time 5.23 seconds
Started Jul 11 07:00:44 PM PDT 24
Finished Jul 11 07:00:50 PM PDT 24
Peak memory 242332 kb
Host smart-7424aae8-ab43-4866-8565-94794d357ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424356301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.424356301
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.1149500158
Short name T238
Test name
Test status
Simulation time 5679976738 ps
CPU time 13.45 seconds
Started Jul 11 07:00:47 PM PDT 24
Finished Jul 11 07:01:02 PM PDT 24
Peak memory 242384 kb
Host smart-1d49e33b-22a7-4f2b-a9ad-26aac34897d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149500158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1149500158
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.3073438590
Short name T500
Test name
Test status
Simulation time 289885057 ps
CPU time 5.04 seconds
Started Jul 11 07:00:46 PM PDT 24
Finished Jul 11 07:00:53 PM PDT 24
Peak memory 241972 kb
Host smart-7de5269b-75b3-404d-ab1d-427dd8edd92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073438590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3073438590
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1470740397
Short name T420
Test name
Test status
Simulation time 159082641 ps
CPU time 4.47 seconds
Started Jul 11 07:00:45 PM PDT 24
Finished Jul 11 07:00:50 PM PDT 24
Peak memory 241868 kb
Host smart-c8572b56-7110-4da5-b8eb-6d1dff451517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470740397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1470740397
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.471509505
Short name T1173
Test name
Test status
Simulation time 192969735 ps
CPU time 4.56 seconds
Started Jul 11 07:00:49 PM PDT 24
Finished Jul 11 07:00:55 PM PDT 24
Peak memory 241788 kb
Host smart-29bb8e2b-e8d5-4b0b-b8a3-ec6e1e0498aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471509505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.471509505
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2957741378
Short name T848
Test name
Test status
Simulation time 102875008 ps
CPU time 3.32 seconds
Started Jul 11 07:00:46 PM PDT 24
Finished Jul 11 07:00:50 PM PDT 24
Peak memory 242128 kb
Host smart-1215ae53-b0c4-45f7-a421-025f1f00d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957741378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2957741378
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1330335960
Short name T1102
Test name
Test status
Simulation time 389988954 ps
CPU time 5.02 seconds
Started Jul 11 07:00:44 PM PDT 24
Finished Jul 11 07:00:50 PM PDT 24
Peak memory 241780 kb
Host smart-38892956-e369-4203-abe8-88054d45b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330335960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1330335960
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1904694865
Short name T1096
Test name
Test status
Simulation time 201320318 ps
CPU time 2.42 seconds
Started Jul 11 06:55:14 PM PDT 24
Finished Jul 11 06:55:18 PM PDT 24
Peak memory 240236 kb
Host smart-45512cd2-4bd5-414d-8ec9-f6baa8b7d296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904694865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1904694865
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1326059066
Short name T946
Test name
Test status
Simulation time 3431227041 ps
CPU time 23.81 seconds
Started Jul 11 06:55:07 PM PDT 24
Finished Jul 11 06:55:32 PM PDT 24
Peak memory 244072 kb
Host smart-02a4fa81-111a-4933-a093-cbd85e4b3d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326059066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1326059066
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.276042778
Short name T1045
Test name
Test status
Simulation time 4625220516 ps
CPU time 32.76 seconds
Started Jul 11 06:55:08 PM PDT 24
Finished Jul 11 06:55:42 PM PDT 24
Peak memory 243712 kb
Host smart-ccdb23bf-11f8-4915-8cbe-530248b07c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276042778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.276042778
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3839571513
Short name T375
Test name
Test status
Simulation time 1622151505 ps
CPU time 16.27 seconds
Started Jul 11 06:55:07 PM PDT 24
Finished Jul 11 06:55:25 PM PDT 24
Peak memory 242340 kb
Host smart-2d3b804a-14c8-40e4-b262-ecfa58e8fa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839571513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3839571513
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1503711414
Short name T720
Test name
Test status
Simulation time 304777171 ps
CPU time 3.75 seconds
Started Jul 11 06:55:06 PM PDT 24
Finished Jul 11 06:55:11 PM PDT 24
Peak memory 241824 kb
Host smart-ccc00d99-d5c7-4d40-9904-0dd45de02996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503711414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1503711414
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.1473154433
Short name T642
Test name
Test status
Simulation time 1751296466 ps
CPU time 16.99 seconds
Started Jul 11 06:55:10 PM PDT 24
Finished Jul 11 06:55:28 PM PDT 24
Peak memory 245892 kb
Host smart-3abb17a6-db83-42db-9bb0-9ad27c2803ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473154433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1473154433
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.310836566
Short name T605
Test name
Test status
Simulation time 919836069 ps
CPU time 26.22 seconds
Started Jul 11 06:55:11 PM PDT 24
Finished Jul 11 06:55:38 PM PDT 24
Peak memory 242376 kb
Host smart-d329e884-7b12-4fb4-90bd-fa8be269be9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310836566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.310836566
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.1021098248
Short name T444
Test name
Test status
Simulation time 392507992 ps
CPU time 15.65 seconds
Started Jul 11 06:55:06 PM PDT 24
Finished Jul 11 06:55:22 PM PDT 24
Peak memory 241776 kb
Host smart-ae9f91e8-a028-4945-81ad-762404f38a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021098248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1021098248
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3965868956
Short name T592
Test name
Test status
Simulation time 223814440 ps
CPU time 5.23 seconds
Started Jul 11 06:55:07 PM PDT 24
Finished Jul 11 06:55:13 PM PDT 24
Peak memory 242012 kb
Host smart-31635d59-3255-42f5-b65a-3ff6edd26263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965868956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3965868956
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.3026352416
Short name T1165
Test name
Test status
Simulation time 338610854 ps
CPU time 6.98 seconds
Started Jul 11 06:55:12 PM PDT 24
Finished Jul 11 06:55:20 PM PDT 24
Peak memory 242360 kb
Host smart-08f6d59d-2d67-46ff-bc31-70a81152b5d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026352416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3026352416
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.306784689
Short name T472
Test name
Test status
Simulation time 264334359 ps
CPU time 3.75 seconds
Started Jul 11 06:55:08 PM PDT 24
Finished Jul 11 06:55:13 PM PDT 24
Peak memory 242156 kb
Host smart-fb3c7459-ce74-411a-b39f-0af1b630a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306784689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.306784689
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2766516567
Short name T561
Test name
Test status
Simulation time 4278276539 ps
CPU time 54.28 seconds
Started Jul 11 06:55:14 PM PDT 24
Finished Jul 11 06:56:09 PM PDT 24
Peak memory 251836 kb
Host smart-0c3ef86a-127e-4a24-8445-59cac0de1437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766516567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2766516567
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.1101458260
Short name T785
Test name
Test status
Simulation time 133275897221 ps
CPU time 987.61 seconds
Started Jul 11 06:55:10 PM PDT 24
Finished Jul 11 07:11:38 PM PDT 24
Peak memory 346532 kb
Host smart-0a6e4e74-9d7d-4d43-a27d-13f2df2fbfac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101458260 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.1101458260
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3693455260
Short name T399
Test name
Test status
Simulation time 675217645 ps
CPU time 22.48 seconds
Started Jul 11 06:55:10 PM PDT 24
Finished Jul 11 06:55:33 PM PDT 24
Peak memory 242496 kb
Host smart-a81c7e81-dc0f-43a0-b95b-1e2675ca1ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693455260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3693455260
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.2961700045
Short name T68
Test name
Test status
Simulation time 379527228 ps
CPU time 4.5 seconds
Started Jul 11 07:00:52 PM PDT 24
Finished Jul 11 07:00:57 PM PDT 24
Peak memory 241828 kb
Host smart-9bfcac61-5ef6-48ba-be95-c6b9393d1734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961700045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.2961700045
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.964643006
Short name T783
Test name
Test status
Simulation time 510248152 ps
CPU time 5.63 seconds
Started Jul 11 07:00:52 PM PDT 24
Finished Jul 11 07:00:59 PM PDT 24
Peak memory 242216 kb
Host smart-5586ac01-9dee-411f-8cfb-7da3662c8062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964643006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.964643006
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.909061697
Short name T70
Test name
Test status
Simulation time 501394819 ps
CPU time 4.99 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:57 PM PDT 24
Peak memory 242036 kb
Host smart-f666a4ed-f88c-4ca5-b2ca-4f7931d80f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909061697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.909061697
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.3893077625
Short name T653
Test name
Test status
Simulation time 2371969412 ps
CPU time 9.27 seconds
Started Jul 11 07:00:48 PM PDT 24
Finished Jul 11 07:00:58 PM PDT 24
Peak memory 241960 kb
Host smart-87d722d1-2bf6-4074-8573-6bd1db6f2c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893077625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3893077625
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.480776932
Short name T432
Test name
Test status
Simulation time 143537434 ps
CPU time 4.34 seconds
Started Jul 11 07:00:51 PM PDT 24
Finished Jul 11 07:00:57 PM PDT 24
Peak memory 241928 kb
Host smart-1c2492bf-a542-40fc-bf9e-2ddfda193147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480776932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.480776932
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2474704777
Short name T596
Test name
Test status
Simulation time 1431190300 ps
CPU time 14.59 seconds
Started Jul 11 07:00:51 PM PDT 24
Finished Jul 11 07:01:07 PM PDT 24
Peak memory 242320 kb
Host smart-245a8bd4-d4c2-449d-aab3-4adcc3dc6597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474704777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2474704777
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.2058786190
Short name T494
Test name
Test status
Simulation time 363925141 ps
CPU time 4.87 seconds
Started Jul 11 07:00:48 PM PDT 24
Finished Jul 11 07:00:54 PM PDT 24
Peak memory 241908 kb
Host smart-fa427298-0987-45dd-b38b-d7bb8ce94e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058786190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2058786190
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.901299822
Short name T640
Test name
Test status
Simulation time 117734653 ps
CPU time 4.14 seconds
Started Jul 11 07:00:45 PM PDT 24
Finished Jul 11 07:00:50 PM PDT 24
Peak memory 241932 kb
Host smart-faceafcd-7fe3-4c60-923b-07f74110a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901299822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.901299822
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.4084788210
Short name T222
Test name
Test status
Simulation time 365293339 ps
CPU time 8.23 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:01:00 PM PDT 24
Peak memory 241896 kb
Host smart-7debdf2e-bef5-48b7-9edb-78ecf2671619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084788210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.4084788210
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2993424509
Short name T1090
Test name
Test status
Simulation time 514004534 ps
CPU time 5.27 seconds
Started Jul 11 07:00:46 PM PDT 24
Finished Jul 11 07:00:53 PM PDT 24
Peak memory 242064 kb
Host smart-083166c7-f899-4d57-bebe-106545b5f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993424509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2993424509
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2069598004
Short name T940
Test name
Test status
Simulation time 11444479598 ps
CPU time 33.55 seconds
Started Jul 11 07:00:47 PM PDT 24
Finished Jul 11 07:01:22 PM PDT 24
Peak memory 241964 kb
Host smart-43fbad2b-8b26-4829-a271-31770b67c13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069598004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2069598004
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3149665813
Short name T1075
Test name
Test status
Simulation time 288944515 ps
CPU time 3.83 seconds
Started Jul 11 07:00:51 PM PDT 24
Finished Jul 11 07:00:56 PM PDT 24
Peak memory 241956 kb
Host smart-9c6ba855-f0d8-42dc-9403-1eccb0c8e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149665813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3149665813
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.4004355047
Short name T969
Test name
Test status
Simulation time 6068654873 ps
CPU time 18.07 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:01:09 PM PDT 24
Peak memory 241988 kb
Host smart-e6f39603-cec4-48af-abf2-235c0833d4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004355047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.4004355047
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2178057180
Short name T604
Test name
Test status
Simulation time 230335953 ps
CPU time 13.27 seconds
Started Jul 11 07:00:55 PM PDT 24
Finished Jul 11 07:01:09 PM PDT 24
Peak memory 242032 kb
Host smart-451a005e-b46e-4940-8ed4-b4719a301aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178057180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2178057180
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.792872491
Short name T697
Test name
Test status
Simulation time 259448545 ps
CPU time 3.71 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:55 PM PDT 24
Peak memory 242316 kb
Host smart-979a1eac-6ce0-4682-bde4-4f2a5431766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792872491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.792872491
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.3448410098
Short name T564
Test name
Test status
Simulation time 214492903 ps
CPU time 3.79 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:55 PM PDT 24
Peak memory 241976 kb
Host smart-23b00d19-5ad3-4f98-a39a-d5351576001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448410098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3448410098
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2039945395
Short name T1055
Test name
Test status
Simulation time 147559818 ps
CPU time 3.56 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:55 PM PDT 24
Peak memory 242196 kb
Host smart-fe46b83a-efd0-4371-9c98-7c2ea69c248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039945395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2039945395
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.3471119663
Short name T1180
Test name
Test status
Simulation time 372604896 ps
CPU time 4.82 seconds
Started Jul 11 07:00:57 PM PDT 24
Finished Jul 11 07:01:03 PM PDT 24
Peak memory 242364 kb
Host smart-9a6b9551-d1b3-4418-87e5-292a4450e5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471119663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3471119663
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.1665231746
Short name T194
Test name
Test status
Simulation time 95761886 ps
CPU time 1.8 seconds
Started Jul 11 06:55:24 PM PDT 24
Finished Jul 11 06:55:27 PM PDT 24
Peak memory 240156 kb
Host smart-96bca8dc-c25b-43b3-b7f3-27402c002619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665231746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.1665231746
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1190608181
Short name T754
Test name
Test status
Simulation time 1587268736 ps
CPU time 34.18 seconds
Started Jul 11 06:55:20 PM PDT 24
Finished Jul 11 06:55:55 PM PDT 24
Peak memory 248736 kb
Host smart-78cb9666-5896-4283-b836-ce805f258b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190608181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1190608181
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.3010253367
Short name T1008
Test name
Test status
Simulation time 2676082375 ps
CPU time 26.92 seconds
Started Jul 11 06:55:20 PM PDT 24
Finished Jul 11 06:55:48 PM PDT 24
Peak memory 241984 kb
Host smart-535d52f1-09e3-4063-b452-7c74dbe8bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010253367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3010253367
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.103932834
Short name T884
Test name
Test status
Simulation time 405782289 ps
CPU time 13.2 seconds
Started Jul 11 06:55:19 PM PDT 24
Finished Jul 11 06:55:33 PM PDT 24
Peak memory 248724 kb
Host smart-03cf3ad1-c60c-411d-a3ef-32dcdd513990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103932834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.103932834
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.3909245786
Short name T723
Test name
Test status
Simulation time 142010361 ps
CPU time 4.83 seconds
Started Jul 11 06:55:16 PM PDT 24
Finished Jul 11 06:55:22 PM PDT 24
Peak memory 241836 kb
Host smart-3c534adf-732c-4564-8f6d-5a1ab5820460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909245786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.3909245786
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.713542679
Short name T335
Test name
Test status
Simulation time 12089158588 ps
CPU time 27.99 seconds
Started Jul 11 06:55:18 PM PDT 24
Finished Jul 11 06:55:47 PM PDT 24
Peak memory 245732 kb
Host smart-60a809c9-5e44-4541-a75a-62ed19b53809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713542679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.713542679
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4223348645
Short name T438
Test name
Test status
Simulation time 1509702241 ps
CPU time 20.41 seconds
Started Jul 11 06:55:20 PM PDT 24
Finished Jul 11 06:55:41 PM PDT 24
Peak memory 242452 kb
Host smart-77dd7ec8-d60f-42d5-ae51-9d61fbab9b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223348645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4223348645
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3074344398
Short name T803
Test name
Test status
Simulation time 376959844 ps
CPU time 8.18 seconds
Started Jul 11 06:55:12 PM PDT 24
Finished Jul 11 06:55:21 PM PDT 24
Peak memory 241992 kb
Host smart-2149041a-a3b4-4bf2-9bc0-298b3de73d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074344398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3074344398
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3810255960
Short name T555
Test name
Test status
Simulation time 12356713922 ps
CPU time 43.13 seconds
Started Jul 11 06:55:14 PM PDT 24
Finished Jul 11 06:55:58 PM PDT 24
Peak memory 242076 kb
Host smart-f242b30a-7d69-4668-8f47-85d3c3bfdda5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810255960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3810255960
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.3848582208
Short name T358
Test name
Test status
Simulation time 200858204 ps
CPU time 3.29 seconds
Started Jul 11 06:55:18 PM PDT 24
Finished Jul 11 06:55:22 PM PDT 24
Peak memory 242036 kb
Host smart-2b61e482-fd5e-435d-8f2d-a5fbed365cdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848582208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3848582208
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1516154860
Short name T834
Test name
Test status
Simulation time 355551963 ps
CPU time 8.63 seconds
Started Jul 11 06:55:15 PM PDT 24
Finished Jul 11 06:55:24 PM PDT 24
Peak memory 248752 kb
Host smart-6045258f-0eb9-4d1d-b0a5-46e28ccc0de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516154860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1516154860
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.4174731431
Short name T385
Test name
Test status
Simulation time 2905948641 ps
CPU time 17.61 seconds
Started Jul 11 06:55:25 PM PDT 24
Finished Jul 11 06:55:43 PM PDT 24
Peak memory 242160 kb
Host smart-9b064068-05c0-4a50-838a-4e93c63242ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174731431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.4174731431
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.831742610
Short name T646
Test name
Test status
Simulation time 2752499243 ps
CPU time 32.19 seconds
Started Jul 11 06:55:20 PM PDT 24
Finished Jul 11 06:55:53 PM PDT 24
Peak memory 248848 kb
Host smart-6857594d-5e63-452a-a873-442d5c2d9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831742610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.831742610
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.2828282002
Short name T53
Test name
Test status
Simulation time 163430083 ps
CPU time 4.31 seconds
Started Jul 11 07:00:49 PM PDT 24
Finished Jul 11 07:00:54 PM PDT 24
Peak memory 242080 kb
Host smart-d29feaac-57fb-470c-9955-68078b9b122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828282002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2828282002
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2893750454
Short name T508
Test name
Test status
Simulation time 455062823 ps
CPU time 13.18 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:01:05 PM PDT 24
Peak memory 241920 kb
Host smart-8bbbb72a-064f-4132-83e3-abed9ac42e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893750454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2893750454
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.2899070390
Short name T955
Test name
Test status
Simulation time 310743726 ps
CPU time 4.31 seconds
Started Jul 11 07:00:51 PM PDT 24
Finished Jul 11 07:00:56 PM PDT 24
Peak memory 242152 kb
Host smart-6119c045-48d0-470d-af7c-16bce76f337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899070390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2899070390
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.4073135167
Short name T332
Test name
Test status
Simulation time 627100393 ps
CPU time 14.76 seconds
Started Jul 11 07:00:49 PM PDT 24
Finished Jul 11 07:01:04 PM PDT 24
Peak memory 241900 kb
Host smart-b95b27c7-63db-426c-8c21-2e62ca3d8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073135167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.4073135167
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.783991040
Short name T263
Test name
Test status
Simulation time 232840223 ps
CPU time 6.57 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:58 PM PDT 24
Peak memory 241972 kb
Host smart-800c151a-d080-4aed-961f-b3db942575f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783991040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.783991040
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3659013704
Short name T241
Test name
Test status
Simulation time 135218169 ps
CPU time 4.82 seconds
Started Jul 11 07:00:50 PM PDT 24
Finished Jul 11 07:00:56 PM PDT 24
Peak memory 242192 kb
Host smart-d31eb913-52fd-4aa5-9661-0ef14db9cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659013704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3659013704
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2866444352
Short name T948
Test name
Test status
Simulation time 379596398 ps
CPU time 4.29 seconds
Started Jul 11 07:00:53 PM PDT 24
Finished Jul 11 07:00:58 PM PDT 24
Peak memory 241896 kb
Host smart-d4d416c2-4d87-44a8-9875-a7aeac4489c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866444352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2866444352
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.351458425
Short name T996
Test name
Test status
Simulation time 273286127 ps
CPU time 8.86 seconds
Started Jul 11 07:00:55 PM PDT 24
Finished Jul 11 07:01:04 PM PDT 24
Peak memory 242144 kb
Host smart-c9314b9c-3433-4153-9379-bf7f6f1af588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351458425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.351458425
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2636315616
Short name T992
Test name
Test status
Simulation time 444660344 ps
CPU time 3.81 seconds
Started Jul 11 07:00:59 PM PDT 24
Finished Jul 11 07:01:04 PM PDT 24
Peak memory 242168 kb
Host smart-73b96f91-af46-472f-9a06-fd8a6bffe944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636315616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2636315616
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.354459526
Short name T679
Test name
Test status
Simulation time 788370063 ps
CPU time 5.7 seconds
Started Jul 11 07:00:55 PM PDT 24
Finished Jul 11 07:01:01 PM PDT 24
Peak memory 242160 kb
Host smart-2ed7512d-9c5c-491b-9d25-3923b71245b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354459526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.354459526
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.941020356
Short name T247
Test name
Test status
Simulation time 247783159 ps
CPU time 6.62 seconds
Started Jul 11 07:00:53 PM PDT 24
Finished Jul 11 07:01:00 PM PDT 24
Peak memory 242012 kb
Host smart-c76fbf0e-2b98-453d-907e-20d4016f2525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941020356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.941020356
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.57478424
Short name T1192
Test name
Test status
Simulation time 129460861 ps
CPU time 3.57 seconds
Started Jul 11 07:00:54 PM PDT 24
Finished Jul 11 07:00:59 PM PDT 24
Peak memory 241912 kb
Host smart-2a4c3d64-4470-4e48-9028-2cd2de1cba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57478424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.57478424
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.307715985
Short name T218
Test name
Test status
Simulation time 1426089950 ps
CPU time 11.96 seconds
Started Jul 11 07:00:58 PM PDT 24
Finished Jul 11 07:01:11 PM PDT 24
Peak memory 241844 kb
Host smart-2b93dd9d-b5a6-4c3d-a358-e516e7be935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307715985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.307715985
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3062971587
Short name T10
Test name
Test status
Simulation time 532276980 ps
CPU time 4.56 seconds
Started Jul 11 07:00:58 PM PDT 24
Finished Jul 11 07:01:04 PM PDT 24
Peak memory 242088 kb
Host smart-e638d6f1-1b64-47d5-aa06-e5bb72218f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062971587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3062971587
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.347266236
Short name T557
Test name
Test status
Simulation time 96449128 ps
CPU time 1.94 seconds
Started Jul 11 06:55:27 PM PDT 24
Finished Jul 11 06:55:30 PM PDT 24
Peak memory 240540 kb
Host smart-61310a5d-a246-4fe9-8097-005b394b9a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347266236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.347266236
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1316763618
Short name T1170
Test name
Test status
Simulation time 3096830985 ps
CPU time 12.91 seconds
Started Jul 11 06:55:23 PM PDT 24
Finished Jul 11 06:55:37 PM PDT 24
Peak memory 241896 kb
Host smart-cf2f29a8-ff8d-4bdd-81db-62b59f84bee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316763618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1316763618
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.782685822
Short name T1058
Test name
Test status
Simulation time 6234027460 ps
CPU time 14.45 seconds
Started Jul 11 06:55:23 PM PDT 24
Finished Jul 11 06:55:38 PM PDT 24
Peak memory 242604 kb
Host smart-40620561-b58d-4342-9e9d-1ad1f29f221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782685822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.782685822
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.4108056995
Short name T770
Test name
Test status
Simulation time 594309080 ps
CPU time 4.57 seconds
Started Jul 11 06:55:22 PM PDT 24
Finished Jul 11 06:55:27 PM PDT 24
Peak memory 242408 kb
Host smart-a2dddda4-251e-4457-a1a7-67efc87fb153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108056995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.4108056995
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.379455283
Short name T453
Test name
Test status
Simulation time 453547872 ps
CPU time 4.14 seconds
Started Jul 11 06:55:22 PM PDT 24
Finished Jul 11 06:55:27 PM PDT 24
Peak memory 247092 kb
Host smart-2536adbe-a797-4079-a1fb-0c95fd51adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379455283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.379455283
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.3723725195
Short name T1038
Test name
Test status
Simulation time 2236317050 ps
CPU time 45.75 seconds
Started Jul 11 06:55:25 PM PDT 24
Finished Jul 11 06:56:12 PM PDT 24
Peak memory 241956 kb
Host smart-b191273c-e6e6-4e3f-a49f-f1b7dd15ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723725195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3723725195
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.203517760
Short name T1188
Test name
Test status
Simulation time 363182544 ps
CPU time 9.43 seconds
Started Jul 11 06:55:24 PM PDT 24
Finished Jul 11 06:55:35 PM PDT 24
Peak memory 241852 kb
Host smart-8b43ca65-5992-4f55-9b76-b7df2d35d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203517760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.203517760
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.264333257
Short name T383
Test name
Test status
Simulation time 578361530 ps
CPU time 16.22 seconds
Started Jul 11 06:55:24 PM PDT 24
Finished Jul 11 06:55:42 PM PDT 24
Peak memory 248676 kb
Host smart-5ccc4514-d78a-4338-bbf3-96fcef510179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264333257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.264333257
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1114200823
Short name T1010
Test name
Test status
Simulation time 3278440306 ps
CPU time 7.74 seconds
Started Jul 11 06:55:27 PM PDT 24
Finished Jul 11 06:55:36 PM PDT 24
Peak memory 242280 kb
Host smart-db65d209-08a3-43b5-af83-8069b1b246dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114200823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1114200823
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2861471789
Short name T459
Test name
Test status
Simulation time 182804265 ps
CPU time 5.22 seconds
Started Jul 11 06:55:23 PM PDT 24
Finished Jul 11 06:55:29 PM PDT 24
Peak memory 241896 kb
Host smart-98f884d1-9f51-43de-9586-ffcd405c262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861471789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2861471789
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.462859673
Short name T705
Test name
Test status
Simulation time 118471565067 ps
CPU time 799.2 seconds
Started Jul 11 06:55:28 PM PDT 24
Finished Jul 11 07:08:48 PM PDT 24
Peak memory 308460 kb
Host smart-8e4971c0-4d2e-4e45-8c9e-cdfc805aded2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462859673 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.462859673
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3848775855
Short name T1185
Test name
Test status
Simulation time 878263247 ps
CPU time 11.68 seconds
Started Jul 11 06:55:27 PM PDT 24
Finished Jul 11 06:55:40 PM PDT 24
Peak memory 242340 kb
Host smart-4fc97b9c-cb16-4333-b23f-ae64711249a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848775855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3848775855
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.2462942663
Short name T925
Test name
Test status
Simulation time 147873622 ps
CPU time 3.94 seconds
Started Jul 11 07:00:59 PM PDT 24
Finished Jul 11 07:01:05 PM PDT 24
Peak memory 242172 kb
Host smart-08456c91-00dd-4780-8aa1-da6a70e7e4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462942663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2462942663
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.446414181
Short name T647
Test name
Test status
Simulation time 288696807 ps
CPU time 19.53 seconds
Started Jul 11 07:00:57 PM PDT 24
Finished Jul 11 07:01:18 PM PDT 24
Peak memory 242272 kb
Host smart-6a437b00-4afe-4185-886f-a37c3271afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446414181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.446414181
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3795106571
Short name T656
Test name
Test status
Simulation time 162930964 ps
CPU time 4.86 seconds
Started Jul 11 07:00:56 PM PDT 24
Finished Jul 11 07:01:02 PM PDT 24
Peak memory 241944 kb
Host smart-b67eb510-f09c-478a-ad38-5a553423ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795106571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3795106571
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.4243533391
Short name T73
Test name
Test status
Simulation time 773180069 ps
CPU time 14 seconds
Started Jul 11 07:00:58 PM PDT 24
Finished Jul 11 07:01:13 PM PDT 24
Peak memory 242220 kb
Host smart-29f7257f-cbee-4348-aebd-695b95d3b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243533391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.4243533391
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.944147365
Short name T779
Test name
Test status
Simulation time 615852367 ps
CPU time 4.89 seconds
Started Jul 11 07:00:59 PM PDT 24
Finished Jul 11 07:01:06 PM PDT 24
Peak memory 242084 kb
Host smart-d25befd5-b2fe-49de-ab2d-6eec5bae4382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944147365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.944147365
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1077049730
Short name T493
Test name
Test status
Simulation time 256602936 ps
CPU time 5.99 seconds
Started Jul 11 07:00:59 PM PDT 24
Finished Jul 11 07:01:07 PM PDT 24
Peak memory 241668 kb
Host smart-8897ccec-df41-4534-ac20-160f6688bdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077049730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1077049730
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.2730410941
Short name T771
Test name
Test status
Simulation time 121115478 ps
CPU time 4.23 seconds
Started Jul 11 07:00:56 PM PDT 24
Finished Jul 11 07:01:01 PM PDT 24
Peak memory 241928 kb
Host smart-f2c1b424-3c7d-4dc4-a910-1d6908f822e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730410941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2730410941
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.384854982
Short name T266
Test name
Test status
Simulation time 168163724 ps
CPU time 9 seconds
Started Jul 11 07:00:58 PM PDT 24
Finished Jul 11 07:01:08 PM PDT 24
Peak memory 241880 kb
Host smart-a5a7638c-4648-440d-b121-4ab085b1d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384854982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.384854982
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.3610381991
Short name T1139
Test name
Test status
Simulation time 289833838 ps
CPU time 4.36 seconds
Started Jul 11 07:01:02 PM PDT 24
Finished Jul 11 07:01:07 PM PDT 24
Peak memory 242120 kb
Host smart-ff7addbf-b5d1-4665-9683-3215096d6c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610381991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3610381991
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1263872920
Short name T881
Test name
Test status
Simulation time 2780670364 ps
CPU time 8.11 seconds
Started Jul 11 07:01:04 PM PDT 24
Finished Jul 11 07:01:13 PM PDT 24
Peak memory 242216 kb
Host smart-8599a02e-4c47-4318-9bd9-fe697665795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263872920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1263872920
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.487778160
Short name T755
Test name
Test status
Simulation time 278910175 ps
CPU time 4.44 seconds
Started Jul 11 07:01:04 PM PDT 24
Finished Jul 11 07:01:10 PM PDT 24
Peak memory 242356 kb
Host smart-9c167ddc-6162-4e52-9c39-7b2e96514087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487778160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.487778160
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.4114432801
Short name T798
Test name
Test status
Simulation time 575987902 ps
CPU time 4.35 seconds
Started Jul 11 07:01:03 PM PDT 24
Finished Jul 11 07:01:08 PM PDT 24
Peak memory 241896 kb
Host smart-c2a53975-d3a8-427b-be80-a4f560511341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114432801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.4114432801
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.4075678262
Short name T951
Test name
Test status
Simulation time 305156905 ps
CPU time 4.54 seconds
Started Jul 11 07:01:04 PM PDT 24
Finished Jul 11 07:01:10 PM PDT 24
Peak memory 242392 kb
Host smart-c2ade864-9f4e-4f75-ad67-9fbd2976cd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075678262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4075678262
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.174997393
Short name T471
Test name
Test status
Simulation time 3287691182 ps
CPU time 25.8 seconds
Started Jul 11 07:01:05 PM PDT 24
Finished Jul 11 07:01:32 PM PDT 24
Peak memory 241948 kb
Host smart-29a06505-15ce-44a1-a8a1-4e1cb91143d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174997393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.174997393
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2762922763
Short name T956
Test name
Test status
Simulation time 533676762 ps
CPU time 6.46 seconds
Started Jul 11 07:01:07 PM PDT 24
Finished Jul 11 07:01:14 PM PDT 24
Peak memory 242168 kb
Host smart-9146424e-d0db-4749-82e3-a919557d0d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762922763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2762922763
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3284133943
Short name T124
Test name
Test status
Simulation time 229433115 ps
CPU time 7.41 seconds
Started Jul 11 07:01:02 PM PDT 24
Finished Jul 11 07:01:10 PM PDT 24
Peak memory 241976 kb
Host smart-e661d53d-fffa-48bf-9c30-47da8dc83481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284133943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3284133943
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.4210788952
Short name T947
Test name
Test status
Simulation time 851594118 ps
CPU time 7.4 seconds
Started Jul 11 07:01:03 PM PDT 24
Finished Jul 11 07:01:11 PM PDT 24
Peak memory 241896 kb
Host smart-87878b50-324e-4f44-9fcf-c280d8d2d45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210788952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.4210788952
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3859661097
Short name T682
Test name
Test status
Simulation time 492638799 ps
CPU time 5.56 seconds
Started Jul 11 07:01:01 PM PDT 24
Finished Jul 11 07:01:08 PM PDT 24
Peak memory 241792 kb
Host smart-17fd0e3d-d754-4684-b278-ddd252fbef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859661097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3859661097
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1488569345
Short name T991
Test name
Test status
Simulation time 2667528090 ps
CPU time 9.04 seconds
Started Jul 11 07:01:13 PM PDT 24
Finished Jul 11 07:01:23 PM PDT 24
Peak memory 242260 kb
Host smart-f3353a1f-9d19-4722-ac48-b78018bfcfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488569345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1488569345
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1112843990
Short name T473
Test name
Test status
Simulation time 1031179208 ps
CPU time 2.8 seconds
Started Jul 11 06:55:35 PM PDT 24
Finished Jul 11 06:55:39 PM PDT 24
Peak memory 240148 kb
Host smart-3e7c24a1-46a9-4a1d-a748-b41c1c70f6e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112843990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1112843990
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1602353583
Short name T659
Test name
Test status
Simulation time 2783604278 ps
CPU time 21.17 seconds
Started Jul 11 06:55:30 PM PDT 24
Finished Jul 11 06:55:52 PM PDT 24
Peak memory 243104 kb
Host smart-6f51349f-2961-4722-b6ac-d9624e6d6ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602353583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1602353583
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.2349054937
Short name T699
Test name
Test status
Simulation time 14108046516 ps
CPU time 37.92 seconds
Started Jul 11 06:55:30 PM PDT 24
Finished Jul 11 06:56:09 PM PDT 24
Peak memory 245896 kb
Host smart-dc5fe30e-a3ff-4571-b6f4-7c68d9308fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349054937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2349054937
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2884677227
Short name T437
Test name
Test status
Simulation time 806726686 ps
CPU time 13.75 seconds
Started Jul 11 06:55:31 PM PDT 24
Finished Jul 11 06:55:46 PM PDT 24
Peak memory 248784 kb
Host smart-420a3197-d0b1-4fbe-848a-cbbf045372cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884677227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2884677227
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.995599532
Short name T1128
Test name
Test status
Simulation time 173579806 ps
CPU time 3.56 seconds
Started Jul 11 06:55:28 PM PDT 24
Finished Jul 11 06:55:33 PM PDT 24
Peak memory 241936 kb
Host smart-f2aa597a-c0e1-4e8a-8225-e9db2e759173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995599532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.995599532
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.4030215286
Short name T172
Test name
Test status
Simulation time 662330219 ps
CPU time 24.04 seconds
Started Jul 11 06:55:30 PM PDT 24
Finished Jul 11 06:55:55 PM PDT 24
Peak memory 245268 kb
Host smart-2639195e-226b-4622-96f1-1db939ed3e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030215286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.4030215286
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1558772102
Short name T989
Test name
Test status
Simulation time 18987111736 ps
CPU time 43.46 seconds
Started Jul 11 06:55:33 PM PDT 24
Finished Jul 11 06:56:19 PM PDT 24
Peak memory 242940 kb
Host smart-871fc1ab-8148-469b-b6b4-d1b19746169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558772102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1558772102
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.1537719350
Short name T1132
Test name
Test status
Simulation time 12771303923 ps
CPU time 31.96 seconds
Started Jul 11 06:55:31 PM PDT 24
Finished Jul 11 06:56:04 PM PDT 24
Peak memory 241972 kb
Host smart-e2c3422f-fdcf-49ba-b65a-995a87d9f134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537719350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1537719350
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3908821604
Short name T1157
Test name
Test status
Simulation time 598761086 ps
CPU time 5.28 seconds
Started Jul 11 06:55:32 PM PDT 24
Finished Jul 11 06:55:39 PM PDT 24
Peak memory 241900 kb
Host smart-e8e037f5-616f-43a7-942a-59bf3dc01c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3908821604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3908821604
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.4275526266
Short name T357
Test name
Test status
Simulation time 723461397 ps
CPU time 10.5 seconds
Started Jul 11 06:55:35 PM PDT 24
Finished Jul 11 06:55:48 PM PDT 24
Peak memory 242468 kb
Host smart-1ce15ab0-188c-45d4-8f9f-b2728234f58d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275526266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.4275526266
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.116745990
Short name T552
Test name
Test status
Simulation time 437727576 ps
CPU time 6.52 seconds
Started Jul 11 06:55:27 PM PDT 24
Finished Jul 11 06:55:34 PM PDT 24
Peak memory 242164 kb
Host smart-f1a5fe47-f1ed-44a5-ac6e-76c6bfcc4497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116745990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.116745990
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2236780981
Short name T675
Test name
Test status
Simulation time 2684937891 ps
CPU time 29.31 seconds
Started Jul 11 06:55:35 PM PDT 24
Finished Jul 11 06:56:06 PM PDT 24
Peak memory 242976 kb
Host smart-380df735-7c69-4dec-9c29-38528877f248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236780981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2236780981
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.937073185
Short name T566
Test name
Test status
Simulation time 108885173600 ps
CPU time 2443.89 seconds
Started Jul 11 06:55:34 PM PDT 24
Finished Jul 11 07:36:20 PM PDT 24
Peak memory 286752 kb
Host smart-1556733a-d950-495c-bf91-57b402d321bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937073185 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.937073185
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.1940350849
Short name T1118
Test name
Test status
Simulation time 337442987 ps
CPU time 6.17 seconds
Started Jul 11 06:55:35 PM PDT 24
Finished Jul 11 06:55:43 PM PDT 24
Peak memory 242036 kb
Host smart-f851f8f4-0484-4a6e-b11a-101e934b4445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940350849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1940350849
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.224228085
Short name T1120
Test name
Test status
Simulation time 2398324964 ps
CPU time 25.83 seconds
Started Jul 11 07:01:06 PM PDT 24
Finished Jul 11 07:01:32 PM PDT 24
Peak memory 242264 kb
Host smart-5ca27fee-297f-4f6d-8992-2c29a71706da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224228085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.224228085
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3474720435
Short name T82
Test name
Test status
Simulation time 270442915 ps
CPU time 3.55 seconds
Started Jul 11 07:01:08 PM PDT 24
Finished Jul 11 07:01:13 PM PDT 24
Peak memory 242400 kb
Host smart-f688536a-135a-4d47-aa5f-23993f3e843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474720435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3474720435
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1090142851
Short name T579
Test name
Test status
Simulation time 110169371 ps
CPU time 4.44 seconds
Started Jul 11 07:01:07 PM PDT 24
Finished Jul 11 07:01:12 PM PDT 24
Peak memory 241888 kb
Host smart-ad79d2ac-795a-430a-8648-d37a20488b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090142851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1090142851
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3585223440
Short name T741
Test name
Test status
Simulation time 278179368 ps
CPU time 4.32 seconds
Started Jul 11 07:01:12 PM PDT 24
Finished Jul 11 07:01:17 PM PDT 24
Peak memory 242156 kb
Host smart-1d91e757-9690-4fea-91c9-efcefe5b9036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585223440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3585223440
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.2031281367
Short name T217
Test name
Test status
Simulation time 5685951841 ps
CPU time 20.91 seconds
Started Jul 11 07:01:08 PM PDT 24
Finished Jul 11 07:01:30 PM PDT 24
Peak memory 241984 kb
Host smart-24c0a3c4-bad9-4222-ad05-adafeb81984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031281367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2031281367
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1369617893
Short name T1097
Test name
Test status
Simulation time 114649525 ps
CPU time 3.4 seconds
Started Jul 11 07:01:13 PM PDT 24
Finished Jul 11 07:01:18 PM PDT 24
Peak memory 242032 kb
Host smart-6036bda8-d2a6-4a4d-829c-f8c1fd193690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369617893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1369617893
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.427060657
Short name T483
Test name
Test status
Simulation time 662336185 ps
CPU time 10.04 seconds
Started Jul 11 07:01:06 PM PDT 24
Finished Jul 11 07:01:16 PM PDT 24
Peak memory 242280 kb
Host smart-1c2f76b4-5e12-40b2-9d77-6d35292ed483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427060657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.427060657
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.3923483823
Short name T1082
Test name
Test status
Simulation time 177346526 ps
CPU time 3.56 seconds
Started Jul 11 07:01:14 PM PDT 24
Finished Jul 11 07:01:19 PM PDT 24
Peak memory 241996 kb
Host smart-d60f45cd-9242-4b85-8dc0-2963362d7a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923483823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3923483823
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2584021372
Short name T918
Test name
Test status
Simulation time 2017338443 ps
CPU time 19.76 seconds
Started Jul 11 07:01:13 PM PDT 24
Finished Jul 11 07:01:33 PM PDT 24
Peak memory 241636 kb
Host smart-c8e804a5-08cf-4a1a-bd09-c71af3749662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584021372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2584021372
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.3825111705
Short name T634
Test name
Test status
Simulation time 484642162 ps
CPU time 5.83 seconds
Started Jul 11 07:01:14 PM PDT 24
Finished Jul 11 07:01:21 PM PDT 24
Peak memory 242060 kb
Host smart-5c59e5bd-ecd4-4841-80f0-fc348e778b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825111705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3825111705
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3176384474
Short name T246
Test name
Test status
Simulation time 433311246 ps
CPU time 12.69 seconds
Started Jul 11 07:01:12 PM PDT 24
Finished Jul 11 07:01:26 PM PDT 24
Peak memory 241980 kb
Host smart-55224eec-2e6d-4c20-9cfc-4d89d4d90887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176384474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3176384474
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.4189508221
Short name T542
Test name
Test status
Simulation time 218795936 ps
CPU time 3.87 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:21 PM PDT 24
Peak memory 242428 kb
Host smart-34dc06d0-88c3-4c8e-ab4c-844b749760ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189508221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.4189508221
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.2302974961
Short name T784
Test name
Test status
Simulation time 208269562 ps
CPU time 4.74 seconds
Started Jul 11 07:01:13 PM PDT 24
Finished Jul 11 07:01:18 PM PDT 24
Peak memory 242108 kb
Host smart-c0cab012-e46e-436e-acc3-02da55b3f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302974961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2302974961
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.4036310012
Short name T590
Test name
Test status
Simulation time 296654876 ps
CPU time 3.97 seconds
Started Jul 11 07:01:12 PM PDT 24
Finished Jul 11 07:01:16 PM PDT 24
Peak memory 242104 kb
Host smart-69776b20-f71c-4b68-8be5-867de09b65b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036310012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.4036310012
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.1668003226
Short name T825
Test name
Test status
Simulation time 969501389 ps
CPU time 15.69 seconds
Started Jul 11 07:01:13 PM PDT 24
Finished Jul 11 07:01:29 PM PDT 24
Peak memory 242212 kb
Host smart-ca5a1242-a187-442d-ad8c-bc706020040d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668003226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1668003226
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.808713020
Short name T893
Test name
Test status
Simulation time 394874596 ps
CPU time 4.99 seconds
Started Jul 11 07:01:17 PM PDT 24
Finished Jul 11 07:01:23 PM PDT 24
Peak memory 242420 kb
Host smart-57431469-4585-4ff1-8f0c-d53ed0d4ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808713020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.808713020
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.929097663
Short name T974
Test name
Test status
Simulation time 766483668 ps
CPU time 22.43 seconds
Started Jul 11 07:01:15 PM PDT 24
Finished Jul 11 07:01:39 PM PDT 24
Peak memory 241900 kb
Host smart-5d09993b-b9cf-4fa6-ba18-f59ffae4b140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929097663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.929097663
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2038317915
Short name T891
Test name
Test status
Simulation time 708960196 ps
CPU time 5.88 seconds
Started Jul 11 07:01:12 PM PDT 24
Finished Jul 11 07:01:18 PM PDT 24
Peak memory 241992 kb
Host smart-1f7b1971-fd1a-4dab-927c-0a0dc3d47378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038317915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2038317915
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.2951322782
Short name T462
Test name
Test status
Simulation time 591000662 ps
CPU time 9.32 seconds
Started Jul 11 07:01:12 PM PDT 24
Finished Jul 11 07:01:23 PM PDT 24
Peak memory 242220 kb
Host smart-ab81a6bd-7984-4736-ae3a-0a12b7561253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951322782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2951322782
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2459386342
Short name T890
Test name
Test status
Simulation time 238060664 ps
CPU time 2.33 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 06:55:47 PM PDT 24
Peak memory 240316 kb
Host smart-b6a7a278-2abd-4705-9d05-bb3279d53d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459386342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2459386342
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1967951832
Short name T79
Test name
Test status
Simulation time 224633914 ps
CPU time 5.74 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 06:55:51 PM PDT 24
Peak memory 242348 kb
Host smart-538dd53b-882c-49fa-aa97-6d04917a6b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967951832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1967951832
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.2736937210
Short name T895
Test name
Test status
Simulation time 228909298 ps
CPU time 12.71 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:55:58 PM PDT 24
Peak memory 241896 kb
Host smart-6dd90e6c-0424-4530-977b-aa2e4d68011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736937210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2736937210
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.1036216878
Short name T745
Test name
Test status
Simulation time 1369297659 ps
CPU time 8.94 seconds
Started Jul 11 06:55:34 PM PDT 24
Finished Jul 11 06:55:45 PM PDT 24
Peak memory 242312 kb
Host smart-2705dcd7-3fc8-420c-8dad-6f7f5ddf29fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036216878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1036216878
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.963179221
Short name T995
Test name
Test status
Simulation time 112067919 ps
CPU time 4.25 seconds
Started Jul 11 06:55:34 PM PDT 24
Finished Jul 11 06:55:40 PM PDT 24
Peak memory 241920 kb
Host smart-fecb01bc-b3e9-409c-a134-8b6d5f8f0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963179221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.963179221
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.2133679221
Short name T749
Test name
Test status
Simulation time 1185431714 ps
CPU time 27.37 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 06:56:12 PM PDT 24
Peak memory 245884 kb
Host smart-14464c55-cbd3-483f-90f0-9c1102985274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133679221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2133679221
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.4039769165
Short name T475
Test name
Test status
Simulation time 139779147 ps
CPU time 6.59 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 06:55:52 PM PDT 24
Peak memory 242244 kb
Host smart-33128835-19ca-4693-b648-cb1d3ab1e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039769165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.4039769165
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2033768816
Short name T478
Test name
Test status
Simulation time 2755574485 ps
CPU time 8.93 seconds
Started Jul 11 06:55:38 PM PDT 24
Finished Jul 11 06:55:50 PM PDT 24
Peak memory 242012 kb
Host smart-7cc13095-c8b4-45d1-ac2e-e3d1d18da4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033768816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2033768816
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2916246276
Short name T777
Test name
Test status
Simulation time 1876960163 ps
CPU time 29.83 seconds
Started Jul 11 06:55:35 PM PDT 24
Finished Jul 11 06:56:07 PM PDT 24
Peak memory 242140 kb
Host smart-4630b6c4-c1ce-489f-b37b-97b2b3eceb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916246276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2916246276
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.4005091902
Short name T149
Test name
Test status
Simulation time 4537962265 ps
CPU time 11.9 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:55:57 PM PDT 24
Peak memory 242548 kb
Host smart-3554df5d-7461-4347-b703-5b55aaca11ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005091902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.4005091902
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.1831742794
Short name T411
Test name
Test status
Simulation time 1288224326 ps
CPU time 8.49 seconds
Started Jul 11 06:55:38 PM PDT 24
Finished Jul 11 06:55:49 PM PDT 24
Peak memory 242456 kb
Host smart-8f5c2479-d5ad-439e-8b50-1bd9a46cd5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831742794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1831742794
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.195768955
Short name T1147
Test name
Test status
Simulation time 13346707157 ps
CPU time 162.78 seconds
Started Jul 11 06:55:41 PM PDT 24
Finished Jul 11 06:58:26 PM PDT 24
Peak memory 247468 kb
Host smart-ddc73349-17d9-4b8b-80b5-207ab9dd6a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195768955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.
195768955
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.2952616950
Short name T772
Test name
Test status
Simulation time 265672505994 ps
CPU time 620.78 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 07:06:06 PM PDT 24
Peak memory 317648 kb
Host smart-e333b335-a2d8-44ae-b118-e93319a2d555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952616950 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.2952616950
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.410963075
Short name T781
Test name
Test status
Simulation time 2810575016 ps
CPU time 32.18 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:56:18 PM PDT 24
Peak memory 242420 kb
Host smart-42444539-9b40-4169-9cea-2c2116e1fe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410963075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.410963075
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.3317697498
Short name T142
Test name
Test status
Simulation time 230421904 ps
CPU time 4.66 seconds
Started Jul 11 07:01:17 PM PDT 24
Finished Jul 11 07:01:23 PM PDT 24
Peak memory 241780 kb
Host smart-f985c939-4a7f-448c-bdf4-13e8f29ff433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317697498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.3317697498
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.1107627422
Short name T687
Test name
Test status
Simulation time 417590656 ps
CPU time 5.81 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:24 PM PDT 24
Peak memory 241892 kb
Host smart-eb27be0c-80d9-4288-9e9d-33e5428b4e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107627422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1107627422
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1616479131
Short name T904
Test name
Test status
Simulation time 653341470 ps
CPU time 5.22 seconds
Started Jul 11 07:01:15 PM PDT 24
Finished Jul 11 07:01:21 PM PDT 24
Peak memory 241932 kb
Host smart-39fb8782-b492-4ab2-bc46-0bf1566eb8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616479131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1616479131
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.3470651704
Short name T113
Test name
Test status
Simulation time 147286339 ps
CPU time 2.76 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:20 PM PDT 24
Peak memory 241988 kb
Host smart-be837b3e-4042-4e14-b261-27b1cc92ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470651704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.3470651704
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.1165116472
Short name T490
Test name
Test status
Simulation time 136024313 ps
CPU time 3.83 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:21 PM PDT 24
Peak memory 242264 kb
Host smart-4f1436e3-8e23-4933-b320-b60c1aa0a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165116472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1165116472
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3322996144
Short name T669
Test name
Test status
Simulation time 2962026687 ps
CPU time 28.65 seconds
Started Jul 11 07:01:18 PM PDT 24
Finished Jul 11 07:01:48 PM PDT 24
Peak memory 241832 kb
Host smart-392bebde-dcab-4df5-9878-b25f75d32093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322996144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3322996144
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.368316799
Short name T663
Test name
Test status
Simulation time 149114843 ps
CPU time 4.74 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:23 PM PDT 24
Peak memory 241764 kb
Host smart-cd429a41-c7d0-42bb-862a-090b8ef4e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368316799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.368316799
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1393428415
Short name T882
Test name
Test status
Simulation time 274364457 ps
CPU time 4.7 seconds
Started Jul 11 07:01:18 PM PDT 24
Finished Jul 11 07:01:24 PM PDT 24
Peak memory 241960 kb
Host smart-986fb224-20f7-40e8-b364-7369ab03b8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393428415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1393428415
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.425419280
Short name T443
Test name
Test status
Simulation time 143374394 ps
CPU time 4.31 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:22 PM PDT 24
Peak memory 242416 kb
Host smart-c8e83384-c2b4-4245-b51a-db3f3ca80332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425419280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.425419280
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.1664659220
Short name T402
Test name
Test status
Simulation time 955456256 ps
CPU time 25 seconds
Started Jul 11 07:01:16 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 241912 kb
Host smart-7515075b-5b0a-4604-9969-7e8e1c4be4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664659220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1664659220
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.334632288
Short name T36
Test name
Test status
Simulation time 1759015495 ps
CPU time 5.44 seconds
Started Jul 11 07:01:22 PM PDT 24
Finished Jul 11 07:01:29 PM PDT 24
Peak memory 242060 kb
Host smart-f93b1a47-9372-48cc-a1ef-f053ccadcc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334632288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.334632288
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3114489517
Short name T924
Test name
Test status
Simulation time 979561785 ps
CPU time 28.31 seconds
Started Jul 11 07:01:21 PM PDT 24
Finished Jul 11 07:01:51 PM PDT 24
Peak memory 241820 kb
Host smart-a60935af-3a27-400a-88e9-8de4fd9b3062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114489517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3114489517
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1508809784
Short name T1150
Test name
Test status
Simulation time 148536852 ps
CPU time 4.02 seconds
Started Jul 11 07:01:19 PM PDT 24
Finished Jul 11 07:01:24 PM PDT 24
Peak memory 241996 kb
Host smart-1ef5c8a8-1187-474e-8f5c-c033d18d6e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508809784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1508809784
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.47242480
Short name T1172
Test name
Test status
Simulation time 1601073696 ps
CPU time 10.96 seconds
Started Jul 11 07:01:21 PM PDT 24
Finished Jul 11 07:01:33 PM PDT 24
Peak memory 241776 kb
Host smart-88f431f4-276c-46ae-be38-a7f0acbd6637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47242480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.47242480
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1940604787
Short name T686
Test name
Test status
Simulation time 3581366194 ps
CPU time 18.12 seconds
Started Jul 11 07:01:23 PM PDT 24
Finished Jul 11 07:01:42 PM PDT 24
Peak memory 242424 kb
Host smart-b966e452-069e-44b9-9271-dd04cca54a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940604787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1940604787
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.4121229777
Short name T540
Test name
Test status
Simulation time 586993479 ps
CPU time 4.37 seconds
Started Jul 11 07:01:23 PM PDT 24
Finished Jul 11 07:01:28 PM PDT 24
Peak memory 241828 kb
Host smart-0abe6dbd-2e52-4e5b-acf4-955817deb822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121229777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.4121229777
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2736297003
Short name T229
Test name
Test status
Simulation time 2541626392 ps
CPU time 10.61 seconds
Started Jul 11 07:01:26 PM PDT 24
Finished Jul 11 07:01:38 PM PDT 24
Peak memory 241892 kb
Host smart-f744bfb6-0cd1-461a-ad93-5e2f5afe984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736297003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2736297003
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3451132644
Short name T114
Test name
Test status
Simulation time 134851333 ps
CPU time 4.84 seconds
Started Jul 11 07:01:25 PM PDT 24
Finished Jul 11 07:01:31 PM PDT 24
Peak memory 241948 kb
Host smart-8a9cb3f6-3ec2-47f4-86ca-aa1c4cded745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451132644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3451132644
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.3447401574
Short name T860
Test name
Test status
Simulation time 110486458 ps
CPU time 5.49 seconds
Started Jul 11 07:01:27 PM PDT 24
Finished Jul 11 07:01:33 PM PDT 24
Peak memory 242160 kb
Host smart-4c3cc6b3-4449-4035-8cc4-6e535a980357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447401574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3447401574
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2912063250
Short name T465
Test name
Test status
Simulation time 59210859 ps
CPU time 1.82 seconds
Started Jul 11 06:52:45 PM PDT 24
Finished Jul 11 06:52:48 PM PDT 24
Peak memory 240072 kb
Host smart-568455ae-2992-4773-9777-da91be090fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912063250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2912063250
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.2803423714
Short name T730
Test name
Test status
Simulation time 1256307595 ps
CPU time 16.75 seconds
Started Jul 11 06:52:24 PM PDT 24
Finished Jul 11 06:52:42 PM PDT 24
Peak memory 242512 kb
Host smart-5806e33c-c937-48a6-a2e3-694deb8805f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803423714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2803423714
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.4233154219
Short name T1066
Test name
Test status
Simulation time 2177880291 ps
CPU time 13.51 seconds
Started Jul 11 06:52:27 PM PDT 24
Finished Jul 11 06:52:41 PM PDT 24
Peak memory 248836 kb
Host smart-f957c28b-cfd9-4dec-8a27-5ab940cb5e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233154219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.4233154219
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3629267641
Short name T92
Test name
Test status
Simulation time 245868562 ps
CPU time 4.6 seconds
Started Jul 11 06:52:25 PM PDT 24
Finished Jul 11 06:52:30 PM PDT 24
Peak memory 248628 kb
Host smart-95ecc61d-2ad9-4f5b-b1b1-b07ec5a9b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629267641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3629267641
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.1614726370
Short name T1109
Test name
Test status
Simulation time 143881664 ps
CPU time 4.68 seconds
Started Jul 11 06:52:18 PM PDT 24
Finished Jul 11 06:52:24 PM PDT 24
Peak memory 241880 kb
Host smart-3db8d045-9cb3-491f-ab3a-71da6c989b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614726370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1614726370
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.3269372286
Short name T900
Test name
Test status
Simulation time 8349176520 ps
CPU time 53.67 seconds
Started Jul 11 06:52:26 PM PDT 24
Finished Jul 11 06:53:20 PM PDT 24
Peak memory 257068 kb
Host smart-2778566e-d5b2-4859-ab1e-549fcb87ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269372286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3269372286
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3816260969
Short name T1112
Test name
Test status
Simulation time 1243078257 ps
CPU time 29.63 seconds
Started Jul 11 06:52:30 PM PDT 24
Finished Jul 11 06:53:00 PM PDT 24
Peak memory 242248 kb
Host smart-9e5e68f4-4af4-45a7-922c-0bd765e96eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816260969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3816260969
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.3677129678
Short name T813
Test name
Test status
Simulation time 1360152978 ps
CPU time 12.83 seconds
Started Jul 11 06:52:26 PM PDT 24
Finished Jul 11 06:52:39 PM PDT 24
Peak memory 241960 kb
Host smart-004d6da0-2237-4014-b0b7-2531ab6d0cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677129678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3677129678
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.4257654721
Short name T525
Test name
Test status
Simulation time 1460052799 ps
CPU time 15.8 seconds
Started Jul 11 06:52:25 PM PDT 24
Finished Jul 11 06:52:41 PM PDT 24
Peak memory 242016 kb
Host smart-8c9b2390-fd4d-48dd-b75e-31dbb2383226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257654721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.4257654721
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.2686358927
Short name T767
Test name
Test status
Simulation time 445165646 ps
CPU time 4.15 seconds
Started Jul 11 06:52:45 PM PDT 24
Finished Jul 11 06:52:50 PM PDT 24
Peak memory 242428 kb
Host smart-b9a3e7df-02de-4f38-a6d9-50a77217c993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686358927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2686358927
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3152624088
Short name T27
Test name
Test status
Simulation time 34401585346 ps
CPU time 212.99 seconds
Started Jul 11 06:52:33 PM PDT 24
Finished Jul 11 06:56:07 PM PDT 24
Peak memory 266132 kb
Host smart-24abcca2-4adb-415c-8dd2-7242ed1b965a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152624088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3152624088
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3861688551
Short name T440
Test name
Test status
Simulation time 770686054 ps
CPU time 11.97 seconds
Started Jul 11 06:52:24 PM PDT 24
Finished Jul 11 06:52:36 PM PDT 24
Peak memory 241980 kb
Host smart-3e3ec924-4bbb-44e2-9824-400f182c58fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861688551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3861688551
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2436178821
Short name T719
Test name
Test status
Simulation time 22847307583 ps
CPU time 194.84 seconds
Started Jul 11 06:52:34 PM PDT 24
Finished Jul 11 06:55:50 PM PDT 24
Peak memory 257256 kb
Host smart-643c162f-92f4-455d-b27d-8dfe543d4a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436178821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2436178821
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.3327011882
Short name T326
Test name
Test status
Simulation time 50222424230 ps
CPU time 941.78 seconds
Started Jul 11 06:52:33 PM PDT 24
Finished Jul 11 07:08:16 PM PDT 24
Peak memory 364300 kb
Host smart-64752a83-6697-49e5-950e-76c6309c0709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327011882 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.3327011882
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.1687867479
Short name T573
Test name
Test status
Simulation time 612931294 ps
CPU time 15.29 seconds
Started Jul 11 06:52:43 PM PDT 24
Finished Jul 11 06:52:59 PM PDT 24
Peak memory 242452 kb
Host smart-41067130-fa14-4626-8fe9-9dd52604af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687867479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1687867479
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.2324429199
Short name T782
Test name
Test status
Simulation time 863862809 ps
CPU time 2.44 seconds
Started Jul 11 06:55:48 PM PDT 24
Finished Jul 11 06:55:51 PM PDT 24
Peak memory 240088 kb
Host smart-c1fb4146-c022-4106-8e03-90c4a24cb722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324429199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2324429199
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.1179840853
Short name T81
Test name
Test status
Simulation time 309301040 ps
CPU time 11.91 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:55:58 PM PDT 24
Peak memory 248684 kb
Host smart-57375d56-2649-4a0c-a772-9c463151f414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179840853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1179840853
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2126300132
Short name T558
Test name
Test status
Simulation time 1783748797 ps
CPU time 27.24 seconds
Started Jul 11 06:55:44 PM PDT 24
Finished Jul 11 06:56:14 PM PDT 24
Peak memory 242284 kb
Host smart-fbef87b4-6fed-447c-8a34-a57e3919869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126300132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2126300132
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.2624400452
Short name T209
Test name
Test status
Simulation time 8295320951 ps
CPU time 22.51 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:56:08 PM PDT 24
Peak memory 243176 kb
Host smart-a0d5ba70-bee4-46ea-9beb-d4c37f7eb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624400452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2624400452
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.3941146924
Short name T29
Test name
Test status
Simulation time 358605873 ps
CPU time 4.65 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 06:55:49 PM PDT 24
Peak memory 242248 kb
Host smart-1fb5eaf0-2263-4f57-8a0a-057cedafe66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941146924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3941146924
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.172665304
Short name T988
Test name
Test status
Simulation time 191874533 ps
CPU time 6.1 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:55:52 PM PDT 24
Peak memory 243032 kb
Host smart-45676f44-fadf-4571-84c6-e7b6b11e4a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172665304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.172665304
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2662709795
Short name T588
Test name
Test status
Simulation time 2226883841 ps
CPU time 14.53 seconds
Started Jul 11 06:55:45 PM PDT 24
Finished Jul 11 06:56:01 PM PDT 24
Peak memory 242640 kb
Host smart-7d903c55-5284-47d4-82fc-b1068c4bbaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662709795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2662709795
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.702792197
Short name T902
Test name
Test status
Simulation time 572783154 ps
CPU time 14.27 seconds
Started Jul 11 06:55:44 PM PDT 24
Finished Jul 11 06:56:01 PM PDT 24
Peak memory 241892 kb
Host smart-9e9b397f-2892-426d-9d7d-3717aa440fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702792197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.702792197
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2513997868
Short name T624
Test name
Test status
Simulation time 2912222666 ps
CPU time 25.33 seconds
Started Jul 11 06:55:43 PM PDT 24
Finished Jul 11 06:56:11 PM PDT 24
Peak memory 248740 kb
Host smart-17792ad1-fbea-4695-b4df-8bb1b75b79bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513997868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2513997868
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.604938942
Short name T822
Test name
Test status
Simulation time 480381719 ps
CPU time 4.71 seconds
Started Jul 11 06:55:44 PM PDT 24
Finished Jul 11 06:55:51 PM PDT 24
Peak memory 242016 kb
Host smart-e2d44df9-d598-4744-a421-0051b5c0fd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604938942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.604938942
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.1293394033
Short name T410
Test name
Test status
Simulation time 200991335 ps
CPU time 4.4 seconds
Started Jul 11 06:55:42 PM PDT 24
Finished Jul 11 06:55:49 PM PDT 24
Peak memory 248440 kb
Host smart-e4b933fb-3914-47ab-af95-eb537ad9596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293394033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1293394033
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.1247788723
Short name T1160
Test name
Test status
Simulation time 1271761143 ps
CPU time 15.92 seconds
Started Jul 11 06:55:47 PM PDT 24
Finished Jul 11 06:56:04 PM PDT 24
Peak memory 248752 kb
Host smart-b511397e-ea22-4b5f-a674-845d30cd71ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247788723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.1247788723
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1368265189
Short name T289
Test name
Test status
Simulation time 199482748979 ps
CPU time 1679.16 seconds
Started Jul 11 06:55:47 PM PDT 24
Finished Jul 11 07:23:47 PM PDT 24
Peak memory 457808 kb
Host smart-759a86ad-40cd-4aed-aa4f-69735cc63213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368265189 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1368265189
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1904466291
Short name T1168
Test name
Test status
Simulation time 2658087330 ps
CPU time 19 seconds
Started Jul 11 06:55:47 PM PDT 24
Finished Jul 11 06:56:07 PM PDT 24
Peak memory 242488 kb
Host smart-ba4860b6-cb44-4536-aaa4-a00d5696c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904466291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1904466291
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3877356243
Short name T202
Test name
Test status
Simulation time 414647810 ps
CPU time 3.93 seconds
Started Jul 11 07:01:25 PM PDT 24
Finished Jul 11 07:01:30 PM PDT 24
Peak memory 241928 kb
Host smart-5cea2849-8a20-40ce-adbc-e41eb075b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877356243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3877356243
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.4052908923
Short name T147
Test name
Test status
Simulation time 403078719 ps
CPU time 4.41 seconds
Started Jul 11 07:01:28 PM PDT 24
Finished Jul 11 07:01:34 PM PDT 24
Peak memory 241928 kb
Host smart-afffbda9-7637-46f3-bf58-e12f6e731d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052908923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.4052908923
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.956208786
Short name T598
Test name
Test status
Simulation time 400937339 ps
CPU time 4.46 seconds
Started Jul 11 07:01:27 PM PDT 24
Finished Jul 11 07:01:33 PM PDT 24
Peak memory 242108 kb
Host smart-c0949a02-e392-4c7d-9107-87af0f649e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956208786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.956208786
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1578864387
Short name T424
Test name
Test status
Simulation time 125993028 ps
CPU time 4.33 seconds
Started Jul 11 07:01:27 PM PDT 24
Finished Jul 11 07:01:33 PM PDT 24
Peak memory 242016 kb
Host smart-0603c5f5-9a45-470a-9fd2-40d116c168a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578864387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1578864387
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.3423754977
Short name T163
Test name
Test status
Simulation time 225925774 ps
CPU time 3.89 seconds
Started Jul 11 07:01:24 PM PDT 24
Finished Jul 11 07:01:29 PM PDT 24
Peak memory 242068 kb
Host smart-193d05d2-33f2-49be-8834-1995a479907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423754977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3423754977
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2872639146
Short name T487
Test name
Test status
Simulation time 1856070491 ps
CPU time 5.7 seconds
Started Jul 11 07:01:25 PM PDT 24
Finished Jul 11 07:01:32 PM PDT 24
Peak memory 242052 kb
Host smart-915f2ab8-5120-4a0c-ba28-7a4e2f6a899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872639146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2872639146
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.833671909
Short name T758
Test name
Test status
Simulation time 108931937 ps
CPU time 3.39 seconds
Started Jul 11 07:01:27 PM PDT 24
Finished Jul 11 07:01:31 PM PDT 24
Peak memory 241984 kb
Host smart-769070b7-c719-4216-bf6b-35df26e2fa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833671909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.833671909
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.3211823910
Short name T1111
Test name
Test status
Simulation time 554465686 ps
CPU time 5.15 seconds
Started Jul 11 07:01:29 PM PDT 24
Finished Jul 11 07:01:35 PM PDT 24
Peak memory 242404 kb
Host smart-df415dbc-56fe-4e79-a0c2-0d87614256f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211823910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3211823910
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1060497573
Short name T1101
Test name
Test status
Simulation time 1138521262 ps
CPU time 2.08 seconds
Started Jul 11 06:55:58 PM PDT 24
Finished Jul 11 06:56:01 PM PDT 24
Peak memory 240544 kb
Host smart-5d1972ce-7e96-485e-9640-a60be892c133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060497573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1060497573
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3924774014
Short name T556
Test name
Test status
Simulation time 408005923 ps
CPU time 5.41 seconds
Started Jul 11 06:55:53 PM PDT 24
Finished Jul 11 06:55:59 PM PDT 24
Peak memory 248700 kb
Host smart-fca5a762-f272-400d-ac9c-97836890ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924774014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3924774014
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.726857589
Short name T804
Test name
Test status
Simulation time 935525824 ps
CPU time 21.94 seconds
Started Jul 11 06:55:55 PM PDT 24
Finished Jul 11 06:56:18 PM PDT 24
Peak memory 241860 kb
Host smart-a97561e6-7e48-471f-a66c-78687e9e9be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726857589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.726857589
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.3421716831
Short name T864
Test name
Test status
Simulation time 4856457844 ps
CPU time 27.37 seconds
Started Jul 11 06:55:53 PM PDT 24
Finished Jul 11 06:56:21 PM PDT 24
Peak memory 242636 kb
Host smart-8468e356-85f2-47b2-ac0c-6922cf60f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421716831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3421716831
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.2374116407
Short name T742
Test name
Test status
Simulation time 352137736 ps
CPU time 4.86 seconds
Started Jul 11 06:55:51 PM PDT 24
Finished Jul 11 06:55:57 PM PDT 24
Peak memory 241896 kb
Host smart-5e55f9dc-fb3f-4df6-9e4c-ff1d6ceabd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374116407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2374116407
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.3966301622
Short name T636
Test name
Test status
Simulation time 8245641613 ps
CPU time 64.31 seconds
Started Jul 11 06:55:54 PM PDT 24
Finished Jul 11 06:56:59 PM PDT 24
Peak memory 265200 kb
Host smart-6e42cebd-1d83-4d5a-856f-671cf4e069a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966301622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3966301622
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.847685903
Short name T1060
Test name
Test status
Simulation time 1338635301 ps
CPU time 25.01 seconds
Started Jul 11 06:55:55 PM PDT 24
Finished Jul 11 06:56:21 PM PDT 24
Peak memory 248808 kb
Host smart-2b59a518-202d-44c5-b647-9a28aa2736b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847685903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.847685903
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.4077183990
Short name T488
Test name
Test status
Simulation time 481697181 ps
CPU time 14.58 seconds
Started Jul 11 06:55:51 PM PDT 24
Finished Jul 11 06:56:07 PM PDT 24
Peak memory 242044 kb
Host smart-1d40f4b2-9b79-4edb-b7be-6c7d3702164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077183990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.4077183990
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.340549668
Short name T353
Test name
Test status
Simulation time 2256320444 ps
CPU time 5.9 seconds
Started Jul 11 06:55:57 PM PDT 24
Finished Jul 11 06:56:03 PM PDT 24
Peak memory 242172 kb
Host smart-43764f5a-d7c4-46c2-aa25-30b97c29f1cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340549668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.340549668
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.2698675415
Short name T933
Test name
Test status
Simulation time 152418638 ps
CPU time 4.99 seconds
Started Jul 11 06:55:53 PM PDT 24
Finished Jul 11 06:55:58 PM PDT 24
Peak memory 248672 kb
Host smart-e94c350d-6a9c-48b0-9f6d-273ff7d3dab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698675415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2698675415
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.634840463
Short name T1164
Test name
Test status
Simulation time 38947709121 ps
CPU time 314.14 seconds
Started Jul 11 06:55:57 PM PDT 24
Finished Jul 11 07:01:12 PM PDT 24
Peak memory 281352 kb
Host smart-2bc06359-035a-49e5-b52c-5e5e3638f854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634840463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
634840463
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2453022867
Short name T548
Test name
Test status
Simulation time 48133512145 ps
CPU time 631.76 seconds
Started Jul 11 06:55:56 PM PDT 24
Finished Jul 11 07:06:29 PM PDT 24
Peak memory 323632 kb
Host smart-15d93874-052e-445a-8efb-766ef3f9b647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453022867 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2453022867
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.2728257259
Short name T98
Test name
Test status
Simulation time 3274454505 ps
CPU time 19.62 seconds
Started Jul 11 06:55:55 PM PDT 24
Finished Jul 11 06:56:15 PM PDT 24
Peak memory 242304 kb
Host smart-afbb6ead-daa3-4671-958c-eb64fa060eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728257259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2728257259
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.167921685
Short name T641
Test name
Test status
Simulation time 194308462 ps
CPU time 4.75 seconds
Started Jul 11 07:01:30 PM PDT 24
Finished Jul 11 07:01:36 PM PDT 24
Peak memory 242060 kb
Host smart-7f8f631a-3153-407e-ac67-814dcf057d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167921685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.167921685
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.3086251976
Short name T1186
Test name
Test status
Simulation time 276081703 ps
CPU time 4.63 seconds
Started Jul 11 07:01:29 PM PDT 24
Finished Jul 11 07:01:36 PM PDT 24
Peak memory 242196 kb
Host smart-14df45c4-e13c-41f9-a876-aa7f91a6e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086251976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3086251976
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.944185669
Short name T1163
Test name
Test status
Simulation time 286257922 ps
CPU time 3.91 seconds
Started Jul 11 07:01:31 PM PDT 24
Finished Jul 11 07:01:36 PM PDT 24
Peak memory 241920 kb
Host smart-a6919ce3-9927-4d64-aebe-ae6a1ab142d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944185669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.944185669
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.168001731
Short name T570
Test name
Test status
Simulation time 556192998 ps
CPU time 4.1 seconds
Started Jul 11 07:01:33 PM PDT 24
Finished Jul 11 07:01:38 PM PDT 24
Peak memory 242084 kb
Host smart-3e52fb3b-47fd-46b8-9897-05e06baf744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168001731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.168001731
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.4099338144
Short name T883
Test name
Test status
Simulation time 153096999 ps
CPU time 4.4 seconds
Started Jul 11 07:01:33 PM PDT 24
Finished Jul 11 07:01:38 PM PDT 24
Peak memory 242172 kb
Host smart-dd024172-6bfc-4172-b82d-58c99bc3a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099338144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.4099338144
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.1380097095
Short name T535
Test name
Test status
Simulation time 227828100 ps
CPU time 4.62 seconds
Started Jul 11 07:01:29 PM PDT 24
Finished Jul 11 07:01:36 PM PDT 24
Peak memory 242040 kb
Host smart-33332416-2bc5-4f9b-bd0f-95917a4f51f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380097095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1380097095
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.481346668
Short name T1041
Test name
Test status
Simulation time 271950962 ps
CPU time 4.08 seconds
Started Jul 11 07:01:29 PM PDT 24
Finished Jul 11 07:01:35 PM PDT 24
Peak memory 241896 kb
Host smart-2111b2a6-e63c-4143-a280-9099371bcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481346668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.481346668
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2227612729
Short name T198
Test name
Test status
Simulation time 2503871969 ps
CPU time 7.47 seconds
Started Jul 11 07:01:31 PM PDT 24
Finished Jul 11 07:01:39 PM PDT 24
Peak memory 242000 kb
Host smart-dbe8b487-34fc-4a9f-b1a2-44ea7501c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227612729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2227612729
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.4227487462
Short name T150
Test name
Test status
Simulation time 588701213 ps
CPU time 4.49 seconds
Started Jul 11 07:01:37 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 241932 kb
Host smart-b9cb27bc-6ba7-420e-a77f-c1129ddbd92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227487462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.4227487462
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.2674166179
Short name T817
Test name
Test status
Simulation time 671116174 ps
CPU time 2.02 seconds
Started Jul 11 06:56:03 PM PDT 24
Finished Jul 11 06:56:05 PM PDT 24
Peak memory 240264 kb
Host smart-7efdad8e-7a0d-403d-9333-9f942d6b568a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674166179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2674166179
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.1340726013
Short name T616
Test name
Test status
Simulation time 267280525 ps
CPU time 4.3 seconds
Started Jul 11 06:56:03 PM PDT 24
Finished Jul 11 06:56:08 PM PDT 24
Peak memory 248712 kb
Host smart-f97a4dcb-8dfc-4249-8b1b-5a059b3355d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340726013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1340726013
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.2864694560
Short name T1119
Test name
Test status
Simulation time 234037074 ps
CPU time 12.59 seconds
Started Jul 11 06:56:00 PM PDT 24
Finished Jul 11 06:56:13 PM PDT 24
Peak memory 242176 kb
Host smart-da630568-f8f4-4034-8c59-9907ed7b7ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864694560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2864694560
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1095022721
Short name T736
Test name
Test status
Simulation time 732654234 ps
CPU time 17.9 seconds
Started Jul 11 06:56:00 PM PDT 24
Finished Jul 11 06:56:19 PM PDT 24
Peak memory 242396 kb
Host smart-31968a4b-af81-45b4-ae00-8663c6e2f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095022721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1095022721
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1294716723
Short name T122
Test name
Test status
Simulation time 317230177 ps
CPU time 4.2 seconds
Started Jul 11 06:56:00 PM PDT 24
Finished Jul 11 06:56:04 PM PDT 24
Peak memory 242432 kb
Host smart-061f96a9-09e1-4e19-bdbd-b5cf09662dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294716723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1294716723
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.2312987815
Short name T998
Test name
Test status
Simulation time 2787129359 ps
CPU time 23.26 seconds
Started Jul 11 06:56:03 PM PDT 24
Finished Jul 11 06:56:27 PM PDT 24
Peak memory 245480 kb
Host smart-433aefcc-a9fc-4ee2-9f69-5d638f67a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312987815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2312987815
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.4077453800
Short name T665
Test name
Test status
Simulation time 20000115697 ps
CPU time 60.19 seconds
Started Jul 11 06:56:04 PM PDT 24
Finished Jul 11 06:57:05 PM PDT 24
Peak memory 242936 kb
Host smart-9e2e3626-88cc-4e22-9b7e-b2a4b774eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077453800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.4077453800
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1163934476
Short name T839
Test name
Test status
Simulation time 3866066014 ps
CPU time 11.64 seconds
Started Jul 11 06:55:58 PM PDT 24
Finished Jul 11 06:56:10 PM PDT 24
Peak memory 241984 kb
Host smart-8c26f255-5d36-4010-8af0-23e3dc4db8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163934476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1163934476
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.624183515
Short name T481
Test name
Test status
Simulation time 280004611 ps
CPU time 8.83 seconds
Started Jul 11 06:55:59 PM PDT 24
Finished Jul 11 06:56:08 PM PDT 24
Peak memory 241980 kb
Host smart-cd8735d1-a53a-4a51-9574-3fe096d04381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624183515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.624183515
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.2377570676
Short name T364
Test name
Test status
Simulation time 481888541 ps
CPU time 4.53 seconds
Started Jul 11 06:56:03 PM PDT 24
Finished Jul 11 06:56:08 PM PDT 24
Peak memory 242412 kb
Host smart-d2bb3434-941d-4ecb-ad4f-fd79fe8dc7d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377570676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2377570676
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.940707190
Short name T1113
Test name
Test status
Simulation time 743533196 ps
CPU time 6.95 seconds
Started Jul 11 06:55:58 PM PDT 24
Finished Jul 11 06:56:06 PM PDT 24
Peak memory 242092 kb
Host smart-cb5ce4c8-8560-499d-8ec3-8e0fe38c58ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940707190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.940707190
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.1993458020
Short name T978
Test name
Test status
Simulation time 44069892363 ps
CPU time 191.52 seconds
Started Jul 11 06:56:11 PM PDT 24
Finished Jul 11 06:59:23 PM PDT 24
Peak memory 251548 kb
Host smart-8b779889-43b1-4b3b-9fce-9054e8b6ffd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993458020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.1993458020
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3832743378
Short name T23
Test name
Test status
Simulation time 69535520608 ps
CPU time 1509.51 seconds
Started Jul 11 06:56:10 PM PDT 24
Finished Jul 11 07:21:20 PM PDT 24
Peak memory 379980 kb
Host smart-3a25a771-3086-408a-ae3a-4b493ceef2e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832743378 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.3832743378
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.4125042958
Short name T713
Test name
Test status
Simulation time 410659124 ps
CPU time 4.46 seconds
Started Jul 11 07:01:38 PM PDT 24
Finished Jul 11 07:01:44 PM PDT 24
Peak memory 241912 kb
Host smart-86f1530d-15ef-4718-b2ac-c87f3a5aefb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125042958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.4125042958
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.2281305783
Short name T451
Test name
Test status
Simulation time 1861477961 ps
CPU time 5.48 seconds
Started Jul 11 07:01:34 PM PDT 24
Finished Jul 11 07:01:40 PM PDT 24
Peak memory 242100 kb
Host smart-bb9f2589-ef98-4472-b2a0-61bad6201fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281305783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.2281305783
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2980101445
Short name T463
Test name
Test status
Simulation time 468801639 ps
CPU time 5.09 seconds
Started Jul 11 07:01:35 PM PDT 24
Finished Jul 11 07:01:41 PM PDT 24
Peak memory 241956 kb
Host smart-4fefa7a2-367e-4914-b172-bf8c9b24b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980101445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2980101445
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1010831251
Short name T95
Test name
Test status
Simulation time 1456955951 ps
CPU time 3.84 seconds
Started Jul 11 07:01:36 PM PDT 24
Finished Jul 11 07:01:41 PM PDT 24
Peak memory 242376 kb
Host smart-1ec1036c-291e-45d8-893a-914839940d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010831251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1010831251
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3356626272
Short name T205
Test name
Test status
Simulation time 261491925 ps
CPU time 3.28 seconds
Started Jul 11 07:01:34 PM PDT 24
Finished Jul 11 07:01:38 PM PDT 24
Peak memory 242024 kb
Host smart-d01fd78a-6b1b-4018-b4f7-6500bd6c9487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356626272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3356626272
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1044973021
Short name T452
Test name
Test status
Simulation time 383735570 ps
CPU time 4.5 seconds
Started Jul 11 07:01:35 PM PDT 24
Finished Jul 11 07:01:41 PM PDT 24
Peak memory 241948 kb
Host smart-d81dc23f-664f-4fbf-b84f-b7ff91f47542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044973021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1044973021
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.2137994026
Short name T166
Test name
Test status
Simulation time 235654254 ps
CPU time 3.68 seconds
Started Jul 11 07:01:34 PM PDT 24
Finished Jul 11 07:01:38 PM PDT 24
Peak memory 241996 kb
Host smart-02def692-e3cc-455c-8eae-4bc07073b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137994026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2137994026
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1341738383
Short name T623
Test name
Test status
Simulation time 107331262 ps
CPU time 3.25 seconds
Started Jul 11 07:01:36 PM PDT 24
Finished Jul 11 07:01:40 PM PDT 24
Peak memory 241912 kb
Host smart-fe116dd1-81d0-495a-b1a5-1cb6704e0a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341738383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1341738383
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.641012562
Short name T818
Test name
Test status
Simulation time 456687323 ps
CPU time 4.63 seconds
Started Jul 11 07:01:41 PM PDT 24
Finished Jul 11 07:01:47 PM PDT 24
Peak memory 241920 kb
Host smart-829eb425-e921-4113-8b46-abdc12046ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641012562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.641012562
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.1152756797
Short name T899
Test name
Test status
Simulation time 87998302 ps
CPU time 1.99 seconds
Started Jul 11 06:56:10 PM PDT 24
Finished Jul 11 06:56:13 PM PDT 24
Peak memory 240556 kb
Host smart-576dce91-3bc6-486c-9060-145e654f01d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152756797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1152756797
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1722438066
Short name T684
Test name
Test status
Simulation time 969871039 ps
CPU time 23.42 seconds
Started Jul 11 06:56:06 PM PDT 24
Finished Jul 11 06:56:31 PM PDT 24
Peak memory 242364 kb
Host smart-63cf9516-26d3-4fe3-9ec1-af6729cddbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722438066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1722438066
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.876983225
Short name T635
Test name
Test status
Simulation time 2717344240 ps
CPU time 29.67 seconds
Started Jul 11 06:56:07 PM PDT 24
Finished Jul 11 06:56:38 PM PDT 24
Peak memory 242604 kb
Host smart-883eb848-355c-4fe8-ac5e-d3b19ecda2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876983225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.876983225
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2960031069
Short name T786
Test name
Test status
Simulation time 96218422 ps
CPU time 3.3 seconds
Started Jul 11 06:56:07 PM PDT 24
Finished Jul 11 06:56:11 PM PDT 24
Peak memory 242216 kb
Host smart-fc4e6c15-62f0-43f7-be90-22173f3d253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960031069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2960031069
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.1858582267
Short name T1085
Test name
Test status
Simulation time 636012149 ps
CPU time 8.26 seconds
Started Jul 11 06:56:06 PM PDT 24
Finished Jul 11 06:56:15 PM PDT 24
Peak memory 242312 kb
Host smart-bdf72cc1-8574-4d04-b004-0d8469f3a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858582267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.1858582267
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.2813049879
Short name T944
Test name
Test status
Simulation time 1387528069 ps
CPU time 26.43 seconds
Started Jul 11 06:56:12 PM PDT 24
Finished Jul 11 06:56:40 PM PDT 24
Peak memory 242608 kb
Host smart-2c0a65ed-c71c-4d6c-876f-6a40b6b1ad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813049879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2813049879
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2754428405
Short name T419
Test name
Test status
Simulation time 937766321 ps
CPU time 14.67 seconds
Started Jul 11 06:56:06 PM PDT 24
Finished Jul 11 06:56:22 PM PDT 24
Peak memory 241880 kb
Host smart-9f50d1ae-18bc-4e01-b9e9-5ca95731a413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754428405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2754428405
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2583247150
Short name T842
Test name
Test status
Simulation time 369498726 ps
CPU time 6.15 seconds
Started Jul 11 06:56:10 PM PDT 24
Finished Jul 11 06:56:17 PM PDT 24
Peak memory 242160 kb
Host smart-9b35dce2-5d3b-41ac-b846-0eceaa3f2c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583247150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2583247150
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.2593499555
Short name T363
Test name
Test status
Simulation time 265173125 ps
CPU time 9.64 seconds
Started Jul 11 06:56:10 PM PDT 24
Finished Jul 11 06:56:20 PM PDT 24
Peak memory 242140 kb
Host smart-a86b327c-c0aa-4c47-94cb-0fca731dec2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593499555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2593499555
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2315094034
Short name T959
Test name
Test status
Simulation time 220694143 ps
CPU time 5.57 seconds
Started Jul 11 06:56:07 PM PDT 24
Finished Jul 11 06:56:13 PM PDT 24
Peak memory 242140 kb
Host smart-757d0434-a748-4d44-a6f7-15ae2670cf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315094034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2315094034
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1140207481
Short name T1137
Test name
Test status
Simulation time 96855151080 ps
CPU time 1382.83 seconds
Started Jul 11 06:56:12 PM PDT 24
Finished Jul 11 07:19:15 PM PDT 24
Peak memory 265308 kb
Host smart-91085e38-4be5-4d09-9bc4-81088c52855e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140207481 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.1140207481
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3881166488
Short name T298
Test name
Test status
Simulation time 7333423631 ps
CPU time 14.43 seconds
Started Jul 11 06:56:12 PM PDT 24
Finished Jul 11 06:56:27 PM PDT 24
Peak memory 243232 kb
Host smart-e64778fd-e8a0-4ec2-ab89-fdf90e3a1207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881166488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3881166488
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2915553785
Short name T1
Test name
Test status
Simulation time 385788245 ps
CPU time 3.28 seconds
Started Jul 11 07:01:38 PM PDT 24
Finished Jul 11 07:01:42 PM PDT 24
Peak memory 242052 kb
Host smart-aceda7ba-447d-43b9-bb78-ec502df70043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915553785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2915553785
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.939843955
Short name T130
Test name
Test status
Simulation time 124369495 ps
CPU time 4.31 seconds
Started Jul 11 07:01:37 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 241920 kb
Host smart-325e209f-e38d-4db5-ab99-c524572bbf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939843955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.939843955
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.2255024261
Short name T1116
Test name
Test status
Simulation time 1300578983 ps
CPU time 4.98 seconds
Started Jul 11 07:01:35 PM PDT 24
Finished Jul 11 07:01:40 PM PDT 24
Peak memory 242324 kb
Host smart-29b69ead-e27a-4d45-a901-8325ca2d0cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255024261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2255024261
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.4166776545
Short name T903
Test name
Test status
Simulation time 153754173 ps
CPU time 4.22 seconds
Started Jul 11 07:01:35 PM PDT 24
Finished Jul 11 07:01:41 PM PDT 24
Peak memory 242052 kb
Host smart-2ad4614c-2838-4c01-acea-b1ff7ec33c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166776545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.4166776545
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.427915084
Short name T799
Test name
Test status
Simulation time 152987979 ps
CPU time 4.15 seconds
Started Jul 11 07:01:35 PM PDT 24
Finished Jul 11 07:01:40 PM PDT 24
Peak memory 242000 kb
Host smart-31eede10-4010-44d3-886e-0f80c3d19eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427915084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.427915084
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2902257853
Short name T907
Test name
Test status
Simulation time 127417085 ps
CPU time 4.81 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242188 kb
Host smart-cdd3dcbd-6c4a-4f9a-8934-04d2a46d48d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902257853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2902257853
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.4068666781
Short name T1029
Test name
Test status
Simulation time 1442062199 ps
CPU time 4.64 seconds
Started Jul 11 07:01:35 PM PDT 24
Finished Jul 11 07:01:40 PM PDT 24
Peak memory 242100 kb
Host smart-e9d6078c-a3ba-475a-8208-5687e1be889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068666781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.4068666781
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.4294809264
Short name T806
Test name
Test status
Simulation time 1854461471 ps
CPU time 5.45 seconds
Started Jul 11 07:01:38 PM PDT 24
Finished Jul 11 07:01:45 PM PDT 24
Peak memory 241900 kb
Host smart-ff4f7eeb-da20-4a30-ab69-6c8a7f306ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294809264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4294809264
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2098976805
Short name T430
Test name
Test status
Simulation time 123355853 ps
CPU time 5.04 seconds
Started Jul 11 07:01:34 PM PDT 24
Finished Jul 11 07:01:39 PM PDT 24
Peak memory 242016 kb
Host smart-94e137df-35e9-4351-9ae8-9b98ec76a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098976805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2098976805
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.522901977
Short name T199
Test name
Test status
Simulation time 2597130228 ps
CPU time 6.93 seconds
Started Jul 11 07:01:37 PM PDT 24
Finished Jul 11 07:01:44 PM PDT 24
Peak memory 242128 kb
Host smart-d4688a33-d7d2-41b2-8d45-0fed78b9b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522901977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.522901977
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.1941637636
Short name T405
Test name
Test status
Simulation time 799896056 ps
CPU time 2.85 seconds
Started Jul 11 06:56:19 PM PDT 24
Finished Jul 11 06:56:23 PM PDT 24
Peak memory 240544 kb
Host smart-43db3a11-e756-4269-9882-1cd1d871c8db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941637636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1941637636
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.2858925994
Short name T748
Test name
Test status
Simulation time 2442774879 ps
CPU time 21.24 seconds
Started Jul 11 06:56:14 PM PDT 24
Finished Jul 11 06:56:37 PM PDT 24
Peak memory 242608 kb
Host smart-9bb011fa-e2fa-446f-9808-f89744e538db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858925994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2858925994
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.3112862631
Short name T619
Test name
Test status
Simulation time 5589184758 ps
CPU time 25.78 seconds
Started Jul 11 06:56:15 PM PDT 24
Finished Jul 11 06:56:42 PM PDT 24
Peak memory 242168 kb
Host smart-b04c1c5e-0410-44d0-8a2f-fc7873e22cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112862631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3112862631
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.1327482959
Short name T572
Test name
Test status
Simulation time 4352185942 ps
CPU time 13.65 seconds
Started Jul 11 06:56:15 PM PDT 24
Finished Jul 11 06:56:30 PM PDT 24
Peak memory 242424 kb
Host smart-5c17ed16-1985-47a1-9fb3-3e07fc09dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327482959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1327482959
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.3921217919
Short name T1095
Test name
Test status
Simulation time 1952558653 ps
CPU time 4.82 seconds
Started Jul 11 06:56:15 PM PDT 24
Finished Jul 11 06:56:21 PM PDT 24
Peak memory 242372 kb
Host smart-25c53c5c-e633-45ca-91b8-f040fede4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921217919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3921217919
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.2691951621
Short name T985
Test name
Test status
Simulation time 1160756004 ps
CPU time 13.18 seconds
Started Jul 11 06:56:16 PM PDT 24
Finished Jul 11 06:56:30 PM PDT 24
Peak memory 242020 kb
Host smart-3c87fb9d-6ef8-4e27-b56e-77cf55a89fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691951621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2691951621
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.705266720
Short name T369
Test name
Test status
Simulation time 12632629469 ps
CPU time 32.14 seconds
Started Jul 11 06:56:14 PM PDT 24
Finished Jul 11 06:56:47 PM PDT 24
Peak memory 242760 kb
Host smart-91a18a3a-c79d-42b1-a235-bbe5f54eab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705266720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.705266720
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.2251350395
Short name T613
Test name
Test status
Simulation time 732199087 ps
CPU time 6.09 seconds
Started Jul 11 06:56:14 PM PDT 24
Finished Jul 11 06:56:22 PM PDT 24
Peak memory 241900 kb
Host smart-8e875275-4af3-477c-a658-daa6abcae316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251350395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.2251350395
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.3969506290
Short name T382
Test name
Test status
Simulation time 733039734 ps
CPU time 23.69 seconds
Started Jul 11 06:56:15 PM PDT 24
Finished Jul 11 06:56:40 PM PDT 24
Peak memory 242156 kb
Host smart-cfd41816-42e0-41db-8f4b-8d14aa2bbb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969506290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3969506290
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.3988160139
Short name T412
Test name
Test status
Simulation time 146791777 ps
CPU time 3.91 seconds
Started Jul 11 06:56:16 PM PDT 24
Finished Jul 11 06:56:21 PM PDT 24
Peak memory 242044 kb
Host smart-1861b18e-bae6-41d2-96ad-02fc8f2c07da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988160139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3988160139
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.469594369
Short name T496
Test name
Test status
Simulation time 7001500632 ps
CPU time 18.73 seconds
Started Jul 11 06:56:15 PM PDT 24
Finished Jul 11 06:56:35 PM PDT 24
Peak memory 242040 kb
Host smart-08bb1e1f-5427-4662-aecf-b5be1dbaa545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469594369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.469594369
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.1798617426
Short name T1103
Test name
Test status
Simulation time 18381625913 ps
CPU time 179.41 seconds
Started Jul 11 06:56:19 PM PDT 24
Finished Jul 11 06:59:19 PM PDT 24
Peak memory 257332 kb
Host smart-c2e26210-3d9a-4e81-bfac-9e154c9ce1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798617426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.1798617426
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.799014301
Short name T586
Test name
Test status
Simulation time 197316800 ps
CPU time 5.55 seconds
Started Jul 11 06:56:18 PM PDT 24
Finished Jul 11 06:56:25 PM PDT 24
Peak memory 241932 kb
Host smart-ee93a734-be00-48c4-b533-17e56bfeaa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799014301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.799014301
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.1029730671
Short name T11
Test name
Test status
Simulation time 630301261 ps
CPU time 4.65 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242376 kb
Host smart-f74582d5-52b1-4dae-89c7-c58aa1b283ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029730671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1029730671
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.1749910296
Short name T1169
Test name
Test status
Simulation time 196443274 ps
CPU time 4.02 seconds
Started Jul 11 07:01:39 PM PDT 24
Finished Jul 11 07:01:44 PM PDT 24
Peak memory 242160 kb
Host smart-aba51c4b-64da-48be-a9bb-10b6c7dc781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749910296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1749910296
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.3341130498
Short name T427
Test name
Test status
Simulation time 113957189 ps
CPU time 3.69 seconds
Started Jul 11 07:01:38 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 242088 kb
Host smart-bfecf386-fdb0-4fea-a427-5e37f4efb8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341130498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3341130498
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.360063614
Short name T845
Test name
Test status
Simulation time 198116060 ps
CPU time 3.85 seconds
Started Jul 11 07:01:39 PM PDT 24
Finished Jul 11 07:01:44 PM PDT 24
Peak memory 241912 kb
Host smart-1ac383fc-5f34-43ac-82c3-4a9f6026fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360063614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.360063614
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2424809620
Short name T484
Test name
Test status
Simulation time 105142865 ps
CPU time 4.36 seconds
Started Jul 11 07:01:37 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 242400 kb
Host smart-5623bb14-7eec-4547-b745-f4ab8fd657cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424809620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2424809620
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1984583419
Short name T1176
Test name
Test status
Simulation time 257979845 ps
CPU time 4.19 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:47 PM PDT 24
Peak memory 242092 kb
Host smart-ef6b69ab-9ef2-4a43-9f6c-00bded37b547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984583419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1984583419
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.238406265
Short name T38
Test name
Test status
Simulation time 327643320 ps
CPU time 4.52 seconds
Started Jul 11 07:01:44 PM PDT 24
Finished Jul 11 07:01:50 PM PDT 24
Peak memory 242272 kb
Host smart-eda3f667-f20f-4c01-a4cb-505a64e3a46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238406265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.238406265
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.1990346619
Short name T138
Test name
Test status
Simulation time 288542316 ps
CPU time 3.94 seconds
Started Jul 11 07:01:38 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 241828 kb
Host smart-1ffe7db8-340d-498e-8a0b-5556ee9c966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990346619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1990346619
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.4232741143
Short name T1024
Test name
Test status
Simulation time 2316877474 ps
CPU time 7.5 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:51 PM PDT 24
Peak memory 242480 kb
Host smart-967b7352-b8f3-4f8a-9167-eac8884b80d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232741143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4232741143
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.96215654
Short name T934
Test name
Test status
Simulation time 521573981 ps
CPU time 3.8 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242076 kb
Host smart-b96abd64-309c-4b2f-a91e-9dff8f5deebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96215654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.96215654
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1908423002
Short name T408
Test name
Test status
Simulation time 760616935 ps
CPU time 2.22 seconds
Started Jul 11 06:56:22 PM PDT 24
Finished Jul 11 06:56:24 PM PDT 24
Peak memory 240272 kb
Host smart-d8d7afd8-3699-4f84-ab3d-b38fa0d722c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908423002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1908423002
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3816304437
Short name T627
Test name
Test status
Simulation time 1654885989 ps
CPU time 15.1 seconds
Started Jul 11 06:56:23 PM PDT 24
Finished Jul 11 06:56:39 PM PDT 24
Peak memory 242784 kb
Host smart-09e77ce1-59bf-40b7-bc20-3f5d7230c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816304437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3816304437
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.877091720
Short name T1007
Test name
Test status
Simulation time 934186430 ps
CPU time 14.97 seconds
Started Jul 11 06:56:23 PM PDT 24
Finished Jul 11 06:56:38 PM PDT 24
Peak memory 242064 kb
Host smart-526c2c91-206e-4fa8-a7e3-24f45d051d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877091720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.877091720
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.3595701555
Short name T544
Test name
Test status
Simulation time 2628222795 ps
CPU time 24.62 seconds
Started Jul 11 06:56:23 PM PDT 24
Finished Jul 11 06:56:49 PM PDT 24
Peak memory 242644 kb
Host smart-e5b81ac7-ab3a-4d98-be25-b914d6e8bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595701555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3595701555
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.4285831233
Short name T1155
Test name
Test status
Simulation time 626937631 ps
CPU time 4.26 seconds
Started Jul 11 06:56:23 PM PDT 24
Finished Jul 11 06:56:29 PM PDT 24
Peak memory 242212 kb
Host smart-702a3e81-caeb-4b51-9a42-f584ac0b43d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285831233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.4285831233
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.411222293
Short name T901
Test name
Test status
Simulation time 30331160178 ps
CPU time 65.94 seconds
Started Jul 11 06:56:23 PM PDT 24
Finished Jul 11 06:57:30 PM PDT 24
Peak memory 261164 kb
Host smart-61adffb5-c1f2-44af-b1de-5d9e8b39ce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411222293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.411222293
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.2207473616
Short name T1141
Test name
Test status
Simulation time 2707765452 ps
CPU time 22.49 seconds
Started Jul 11 06:56:25 PM PDT 24
Finished Jul 11 06:56:48 PM PDT 24
Peak memory 242468 kb
Host smart-92509b4f-5fd5-4403-9b84-a806104d9c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207473616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2207473616
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.104343534
Short name T637
Test name
Test status
Simulation time 167014108 ps
CPU time 4.46 seconds
Started Jul 11 06:56:30 PM PDT 24
Finished Jul 11 06:56:35 PM PDT 24
Peak memory 241924 kb
Host smart-29d526dd-faaa-4b38-9a83-4819c9f72524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104343534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.104343534
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.1116008081
Short name T611
Test name
Test status
Simulation time 760843727 ps
CPU time 17.78 seconds
Started Jul 11 06:56:31 PM PDT 24
Finished Jul 11 06:56:49 PM PDT 24
Peak memory 241992 kb
Host smart-3d875e37-4e35-4bc1-ae76-f622924dda9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116008081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1116008081
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3787672076
Short name T760
Test name
Test status
Simulation time 346158965 ps
CPU time 3.66 seconds
Started Jul 11 06:56:31 PM PDT 24
Finished Jul 11 06:56:35 PM PDT 24
Peak memory 242100 kb
Host smart-315573c9-cfc7-48fb-9513-5b559ea71ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787672076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3787672076
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2178403441
Short name T447
Test name
Test status
Simulation time 159149043 ps
CPU time 4.96 seconds
Started Jul 11 06:56:18 PM PDT 24
Finished Jul 11 06:56:24 PM PDT 24
Peak memory 242112 kb
Host smart-4db34a41-45f4-4904-b3e2-cb53be4d1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178403441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2178403441
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3113715838
Short name T688
Test name
Test status
Simulation time 22470920349 ps
CPU time 164.07 seconds
Started Jul 11 06:56:26 PM PDT 24
Finished Jul 11 06:59:11 PM PDT 24
Peak memory 249076 kb
Host smart-42207212-8aec-4308-b863-03ac635b611b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113715838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3113715838
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2886037188
Short name T213
Test name
Test status
Simulation time 609183317518 ps
CPU time 1553.62 seconds
Started Jul 11 06:56:31 PM PDT 24
Finished Jul 11 07:22:26 PM PDT 24
Peak memory 284232 kb
Host smart-1790b270-f02b-46b4-ac3b-e0f810cbad39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886037188 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2886037188
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2637950724
Short name T97
Test name
Test status
Simulation time 2214718275 ps
CPU time 18.7 seconds
Started Jul 11 06:56:24 PM PDT 24
Finished Jul 11 06:56:44 PM PDT 24
Peak memory 242104 kb
Host smart-fa902a91-93a3-47d5-a7b7-c86c8c0ee477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637950724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2637950724
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.3672145740
Short name T107
Test name
Test status
Simulation time 221235840 ps
CPU time 4.27 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 241944 kb
Host smart-d6082091-9aa6-44b7-9443-0190209dff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672145740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3672145740
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.3487813292
Short name T936
Test name
Test status
Simulation time 149765885 ps
CPU time 4.43 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:48 PM PDT 24
Peak memory 241928 kb
Host smart-c22eff17-9d64-415a-a416-d6981f3a74dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487813292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3487813292
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3733832390
Short name T457
Test name
Test status
Simulation time 300964999 ps
CPU time 4.41 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242160 kb
Host smart-36884f3a-04f1-429a-b3d5-11f17086c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733832390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3733832390
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2939999808
Short name T722
Test name
Test status
Simulation time 156321288 ps
CPU time 4.62 seconds
Started Jul 11 07:01:44 PM PDT 24
Finished Jul 11 07:01:50 PM PDT 24
Peak memory 242156 kb
Host smart-72e76466-c174-4799-8089-7ec6091af98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939999808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2939999808
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1439344167
Short name T1121
Test name
Test status
Simulation time 264713642 ps
CPU time 4.78 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 241964 kb
Host smart-5e2a85a7-399a-433e-b3e3-1f4a57b75dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439344167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1439344167
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.143723249
Short name T1134
Test name
Test status
Simulation time 268227810 ps
CPU time 3.4 seconds
Started Jul 11 07:01:38 PM PDT 24
Finished Jul 11 07:01:43 PM PDT 24
Peak memory 242024 kb
Host smart-de31cb71-b729-4ddd-a5a9-96a896ba98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143723249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.143723249
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.1313381403
Short name T563
Test name
Test status
Simulation time 177260935 ps
CPU time 4.6 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242008 kb
Host smart-b45bb7c7-01d9-484f-8711-366e223131ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313381403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1313381403
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2863010251
Short name T1193
Test name
Test status
Simulation time 404648472 ps
CPU time 4.59 seconds
Started Jul 11 07:01:44 PM PDT 24
Finished Jul 11 07:01:50 PM PDT 24
Peak memory 241928 kb
Host smart-bdcec168-109e-4713-8cdb-a10bca51ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863010251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2863010251
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.506162809
Short name T764
Test name
Test status
Simulation time 2202498678 ps
CPU time 6.07 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:50 PM PDT 24
Peak memory 241992 kb
Host smart-ef124879-fe13-48a2-b426-214977526126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506162809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.506162809
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.1392163590
Short name T1144
Test name
Test status
Simulation time 151854307 ps
CPU time 4.08 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:48 PM PDT 24
Peak memory 242220 kb
Host smart-53fe51da-1f41-4742-a7ea-2bf69deeddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392163590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1392163590
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3853493227
Short name T805
Test name
Test status
Simulation time 76343354 ps
CPU time 1.52 seconds
Started Jul 11 06:56:32 PM PDT 24
Finished Jul 11 06:56:35 PM PDT 24
Peak memory 240176 kb
Host smart-0ff05a9c-5aa4-4a82-b3dc-5182bafc45f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853493227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3853493227
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3938246817
Short name T855
Test name
Test status
Simulation time 4014254694 ps
CPU time 11.48 seconds
Started Jul 11 06:56:28 PM PDT 24
Finished Jul 11 06:56:40 PM PDT 24
Peak memory 243116 kb
Host smart-e9bbe03d-f3cd-4f3f-8d19-6ab859868267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938246817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3938246817
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3319136885
Short name T1072
Test name
Test status
Simulation time 12233904392 ps
CPU time 43.98 seconds
Started Jul 11 06:56:28 PM PDT 24
Finished Jul 11 06:57:12 PM PDT 24
Peak memory 242604 kb
Host smart-3c3701d2-8ed2-4937-b185-2ac264809518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319136885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3319136885
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.1700669363
Short name T633
Test name
Test status
Simulation time 2178315198 ps
CPU time 25.45 seconds
Started Jul 11 06:56:27 PM PDT 24
Finished Jul 11 06:56:53 PM PDT 24
Peak memory 242484 kb
Host smart-b1abfbce-48a5-448d-95a9-e649603cc3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700669363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1700669363
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2636220003
Short name T711
Test name
Test status
Simulation time 94349189 ps
CPU time 3.99 seconds
Started Jul 11 06:56:30 PM PDT 24
Finished Jul 11 06:56:35 PM PDT 24
Peak memory 242368 kb
Host smart-9eb908b0-7205-4260-b60b-1b9786df7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636220003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2636220003
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1165756535
Short name T403
Test name
Test status
Simulation time 2091910588 ps
CPU time 49.25 seconds
Started Jul 11 06:56:29 PM PDT 24
Finished Jul 11 06:57:19 PM PDT 24
Peak memory 242280 kb
Host smart-d42bbd9f-28c5-4c68-a983-ad2b08e7b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165756535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1165756535
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.3351100088
Short name T264
Test name
Test status
Simulation time 185987977 ps
CPU time 5.21 seconds
Started Jul 11 06:56:29 PM PDT 24
Finished Jul 11 06:56:35 PM PDT 24
Peak memory 242132 kb
Host smart-365e148a-038f-4dc4-9794-1733a1fa4316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351100088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3351100088
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3843266869
Short name T102
Test name
Test status
Simulation time 540121861 ps
CPU time 16.55 seconds
Started Jul 11 06:56:24 PM PDT 24
Finished Jul 11 06:56:42 PM PDT 24
Peak memory 248704 kb
Host smart-1d86148b-e4e1-4239-b851-cebdffee575e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843266869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3843266869
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.4003152070
Short name T407
Test name
Test status
Simulation time 1794044836 ps
CPU time 5.2 seconds
Started Jul 11 06:56:26 PM PDT 24
Finished Jul 11 06:56:32 PM PDT 24
Peak memory 242336 kb
Host smart-1829b121-6a45-40f2-9cc1-c7bd98972942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003152070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.4003152070
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.289740277
Short name T1148
Test name
Test status
Simulation time 488939041 ps
CPU time 5.9 seconds
Started Jul 11 06:56:34 PM PDT 24
Finished Jul 11 06:56:40 PM PDT 24
Peak memory 242300 kb
Host smart-491d74c9-ab0b-48e7-a345-55780a7d0a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289740277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.289740277
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.1167800846
Short name T17
Test name
Test status
Simulation time 7857030568 ps
CPU time 40.13 seconds
Started Jul 11 06:56:33 PM PDT 24
Finished Jul 11 06:57:14 PM PDT 24
Peak memory 244128 kb
Host smart-f66915ab-252d-4abd-bcbe-68b64af0101d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167800846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.1167800846
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.865284150
Short name T294
Test name
Test status
Simulation time 122917321577 ps
CPU time 1472.33 seconds
Started Jul 11 06:56:33 PM PDT 24
Finished Jul 11 07:21:06 PM PDT 24
Peak memory 319084 kb
Host smart-c9460d77-ea99-466d-ad20-dd05a49d19c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865284150 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.865284150
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.306534533
Short name T279
Test name
Test status
Simulation time 2932430415 ps
CPU time 25.75 seconds
Started Jul 11 06:56:28 PM PDT 24
Finished Jul 11 06:56:55 PM PDT 24
Peak memory 242496 kb
Host smart-e535a953-53cd-495e-acab-ff7d9231378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306534533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.306534533
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.3668592024
Short name T464
Test name
Test status
Simulation time 291414112 ps
CPU time 4.54 seconds
Started Jul 11 07:01:44 PM PDT 24
Finished Jul 11 07:01:50 PM PDT 24
Peak memory 241928 kb
Host smart-b3f30451-bd35-44e0-a22e-f6765be1afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668592024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3668592024
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3573713695
Short name T1115
Test name
Test status
Simulation time 356016292 ps
CPU time 4.31 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:48 PM PDT 24
Peak memory 242412 kb
Host smart-57744580-3010-494a-967b-087f2c2f4b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573713695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3573713695
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.4038034895
Short name T191
Test name
Test status
Simulation time 266323860 ps
CPU time 3.71 seconds
Started Jul 11 07:01:41 PM PDT 24
Finished Jul 11 07:01:46 PM PDT 24
Peak memory 242260 kb
Host smart-68fb2c64-bbe0-4f47-874c-982e7aa309bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038034895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.4038034895
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.3752856992
Short name T606
Test name
Test status
Simulation time 2166485790 ps
CPU time 4.35 seconds
Started Jul 11 07:01:44 PM PDT 24
Finished Jul 11 07:01:50 PM PDT 24
Peak memory 242468 kb
Host smart-3d96a994-d76f-4dee-9f52-6c167823f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752856992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.3752856992
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.3240961299
Short name T673
Test name
Test status
Simulation time 313350186 ps
CPU time 4.18 seconds
Started Jul 11 07:01:43 PM PDT 24
Finished Jul 11 07:01:49 PM PDT 24
Peak memory 242172 kb
Host smart-8b3d2816-36b8-4506-b075-361979f67ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240961299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.3240961299
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.2581655840
Short name T1086
Test name
Test status
Simulation time 479498425 ps
CPU time 4.37 seconds
Started Jul 11 07:01:41 PM PDT 24
Finished Jul 11 07:01:47 PM PDT 24
Peak memory 242080 kb
Host smart-4f08fba9-7862-4414-9b16-80b02ddbb39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581655840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2581655840
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.2017835388
Short name T807
Test name
Test status
Simulation time 108608451 ps
CPU time 3.69 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:48 PM PDT 24
Peak memory 242128 kb
Host smart-6df71a41-f16d-47eb-9969-07e8083ac6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017835388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2017835388
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.616068356
Short name T146
Test name
Test status
Simulation time 221536167 ps
CPU time 4.21 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:51 PM PDT 24
Peak memory 242168 kb
Host smart-2796f54b-96dd-45ef-85af-dbd3b2110c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616068356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.616068356
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.923981349
Short name T80
Test name
Test status
Simulation time 419382277 ps
CPU time 3.84 seconds
Started Jul 11 07:01:42 PM PDT 24
Finished Jul 11 07:01:47 PM PDT 24
Peak memory 242196 kb
Host smart-8a9775a3-54b8-4ae1-a43b-5ca2eede3809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923981349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.923981349
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.3232143234
Short name T1067
Test name
Test status
Simulation time 183370356 ps
CPU time 1.75 seconds
Started Jul 11 06:56:37 PM PDT 24
Finished Jul 11 06:56:40 PM PDT 24
Peak memory 240476 kb
Host smart-4153d536-ebe2-46ec-b9ef-68c69e3d216b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232143234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.3232143234
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.3652893066
Short name T32
Test name
Test status
Simulation time 10277918550 ps
CPU time 30.48 seconds
Started Jul 11 06:56:36 PM PDT 24
Finished Jul 11 06:57:07 PM PDT 24
Peak memory 244052 kb
Host smart-114bdaef-a717-46ed-b5b2-b95c2570ab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652893066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.3652893066
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1675080221
Short name T524
Test name
Test status
Simulation time 2787411339 ps
CPU time 40.4 seconds
Started Jul 11 06:56:41 PM PDT 24
Finished Jul 11 06:57:23 PM PDT 24
Peak memory 249452 kb
Host smart-5ec10a69-7d0a-42d3-8d42-a265417dab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675080221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1675080221
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.570258164
Short name T4
Test name
Test status
Simulation time 492887850 ps
CPU time 11.98 seconds
Started Jul 11 06:56:33 PM PDT 24
Finished Jul 11 06:56:46 PM PDT 24
Peak memory 248808 kb
Host smart-b79b0369-e015-4749-9c3c-9bcd5a3d2b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570258164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.570258164
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.4211037599
Short name T873
Test name
Test status
Simulation time 151395881 ps
CPU time 3.93 seconds
Started Jul 11 06:56:32 PM PDT 24
Finished Jul 11 06:56:37 PM PDT 24
Peak memory 241896 kb
Host smart-bbf83214-3e36-4afb-8932-f871687024e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211037599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.4211037599
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3289197057
Short name T188
Test name
Test status
Simulation time 29694104142 ps
CPU time 88.98 seconds
Started Jul 11 06:56:32 PM PDT 24
Finished Jul 11 06:58:02 PM PDT 24
Peak memory 260236 kb
Host smart-5ba10ea8-7142-46fb-8836-41853e2e303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289197057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3289197057
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2670396037
Short name T1184
Test name
Test status
Simulation time 16075809714 ps
CPU time 39.38 seconds
Started Jul 11 06:56:41 PM PDT 24
Finished Jul 11 06:57:22 PM PDT 24
Peak memory 243508 kb
Host smart-5958bc82-602b-4926-807f-0773ce4e2c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670396037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2670396037
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.2994556738
Short name T725
Test name
Test status
Simulation time 305533678 ps
CPU time 18.07 seconds
Started Jul 11 06:56:31 PM PDT 24
Finished Jul 11 06:56:50 PM PDT 24
Peak memory 241820 kb
Host smart-a814a965-9cd2-4a36-88e2-31f247ac8ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994556738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2994556738
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.4264076485
Short name T1100
Test name
Test status
Simulation time 1323379367 ps
CPU time 19.95 seconds
Started Jul 11 06:56:30 PM PDT 24
Finished Jul 11 06:56:51 PM PDT 24
Peak memory 248732 kb
Host smart-e5654ced-6db5-404d-a599-708856dd1cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264076485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.4264076485
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.1970498485
Short name T521
Test name
Test status
Simulation time 173307748 ps
CPU time 4.81 seconds
Started Jul 11 06:56:41 PM PDT 24
Finished Jul 11 06:56:47 PM PDT 24
Peak memory 241960 kb
Host smart-56211b81-3394-4bb3-b50a-6c56409e4309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970498485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1970498485
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.711777777
Short name T809
Test name
Test status
Simulation time 428905371 ps
CPU time 5.77 seconds
Started Jul 11 06:56:32 PM PDT 24
Finished Jul 11 06:56:39 PM PDT 24
Peak memory 242116 kb
Host smart-dd7b875e-c137-44b9-aa3e-1a08b72bce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711777777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.711777777
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3243951033
Short name T750
Test name
Test status
Simulation time 111874005446 ps
CPU time 226.76 seconds
Started Jul 11 06:56:38 PM PDT 24
Finished Jul 11 07:00:26 PM PDT 24
Peak memory 279496 kb
Host smart-9120798d-eb68-4fb2-ae7f-57743ab5af1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243951033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3243951033
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.594719204
Short name T284
Test name
Test status
Simulation time 83369410975 ps
CPU time 1404.63 seconds
Started Jul 11 06:56:41 PM PDT 24
Finished Jul 11 07:20:07 PM PDT 24
Peak memory 389560 kb
Host smart-8fd9f619-d107-4d60-89b1-20cbda31195e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594719204 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.594719204
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.84516957
Short name T964
Test name
Test status
Simulation time 626867003 ps
CPU time 5.43 seconds
Started Jul 11 06:56:36 PM PDT 24
Finished Jul 11 06:56:42 PM PDT 24
Peak memory 242252 kb
Host smart-2a4ce16f-5628-4d32-bd40-3fe93583594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84516957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.84516957
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2710858335
Short name T538
Test name
Test status
Simulation time 388622809 ps
CPU time 5.18 seconds
Started Jul 11 07:01:48 PM PDT 24
Finished Jul 11 07:01:54 PM PDT 24
Peak memory 242200 kb
Host smart-36e541f7-9055-455a-a1f0-ea1e9697fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710858335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2710858335
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2316303853
Short name T141
Test name
Test status
Simulation time 174640915 ps
CPU time 4.05 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:52 PM PDT 24
Peak memory 242092 kb
Host smart-a0e83272-4a0d-4321-911d-42fb2ddbe6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316303853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2316303853
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1418353628
Short name T1049
Test name
Test status
Simulation time 429226012 ps
CPU time 4.11 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:51 PM PDT 24
Peak memory 241824 kb
Host smart-887ac6ae-33cc-423c-8c2e-dc680a8c3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418353628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1418353628
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.1908031386
Short name T621
Test name
Test status
Simulation time 105628108 ps
CPU time 3.48 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:51 PM PDT 24
Peak memory 241908 kb
Host smart-b1f6d465-b89d-42f0-9f4a-10660bb72881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908031386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1908031386
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.234154437
Short name T35
Test name
Test status
Simulation time 342820017 ps
CPU time 4.44 seconds
Started Jul 11 07:01:52 PM PDT 24
Finished Jul 11 07:01:58 PM PDT 24
Peak memory 241916 kb
Host smart-3b7fd885-32fa-4894-9520-5c7b50eeee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234154437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.234154437
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1681161076
Short name T1094
Test name
Test status
Simulation time 199634062 ps
CPU time 5.12 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:52 PM PDT 24
Peak memory 242188 kb
Host smart-4d73994f-ff03-4cf2-8413-1ea5b0ba9e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681161076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1681161076
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3008825135
Short name T1156
Test name
Test status
Simulation time 226939799 ps
CPU time 4.05 seconds
Started Jul 11 07:01:47 PM PDT 24
Finished Jul 11 07:01:52 PM PDT 24
Peak memory 242396 kb
Host smart-b8e37514-524f-4b8c-94b3-e6c6172ae65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008825135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3008825135
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.301715489
Short name T966
Test name
Test status
Simulation time 448783930 ps
CPU time 3.49 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:51 PM PDT 24
Peak memory 242080 kb
Host smart-0843e159-ebbd-4354-838c-9f2ea20b31b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301715489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.301715489
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.2318316372
Short name T136
Test name
Test status
Simulation time 1795047021 ps
CPU time 5.04 seconds
Started Jul 11 07:01:47 PM PDT 24
Finished Jul 11 07:01:53 PM PDT 24
Peak memory 242172 kb
Host smart-e8a8f181-a76e-41f2-9617-5d5cfdb6261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318316372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2318316372
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.2771885491
Short name T877
Test name
Test status
Simulation time 324842276 ps
CPU time 4.98 seconds
Started Jul 11 07:01:46 PM PDT 24
Finished Jul 11 07:01:52 PM PDT 24
Peak memory 242028 kb
Host smart-9c13407c-58d5-485b-b5f3-506eee9781f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771885491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2771885491
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1667091398
Short name T897
Test name
Test status
Simulation time 97735322 ps
CPU time 1.74 seconds
Started Jul 11 06:56:44 PM PDT 24
Finished Jul 11 06:56:46 PM PDT 24
Peak memory 240160 kb
Host smart-d69f85af-130d-456d-a39f-d1b5bda13be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667091398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1667091398
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.2975567086
Short name T49
Test name
Test status
Simulation time 950143830 ps
CPU time 18.26 seconds
Started Jul 11 06:56:43 PM PDT 24
Finished Jul 11 06:57:02 PM PDT 24
Peak memory 242324 kb
Host smart-e1d5b0b3-e23e-4f42-a5f1-8c01938c86a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975567086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2975567086
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.1439708881
Short name T1159
Test name
Test status
Simulation time 10166146704 ps
CPU time 26.8 seconds
Started Jul 11 06:56:43 PM PDT 24
Finished Jul 11 06:57:10 PM PDT 24
Peak memory 242596 kb
Host smart-06949cb1-7393-4a3a-abc5-c85fe50803b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439708881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1439708881
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.4150171432
Short name T1035
Test name
Test status
Simulation time 2057074083 ps
CPU time 9.94 seconds
Started Jul 11 06:56:38 PM PDT 24
Finished Jul 11 06:56:49 PM PDT 24
Peak memory 242312 kb
Host smart-f6e5c545-fbe0-42be-ba32-242537c87a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150171432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.4150171432
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3160797248
Short name T60
Test name
Test status
Simulation time 138006566 ps
CPU time 5.06 seconds
Started Jul 11 06:56:39 PM PDT 24
Finished Jul 11 06:56:45 PM PDT 24
Peak memory 242184 kb
Host smart-b0c59237-43ca-48ee-ab20-25e594cd3237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160797248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3160797248
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.931077353
Short name T622
Test name
Test status
Simulation time 1999053457 ps
CPU time 22.53 seconds
Started Jul 11 06:56:43 PM PDT 24
Finished Jul 11 06:57:07 PM PDT 24
Peak memory 242260 kb
Host smart-130f5602-ac6f-425f-affb-fa9abdc93e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931077353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.931077353
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.386479470
Short name T740
Test name
Test status
Simulation time 2751494772 ps
CPU time 8.2 seconds
Started Jul 11 06:56:43 PM PDT 24
Finished Jul 11 06:56:52 PM PDT 24
Peak memory 242436 kb
Host smart-a07c1928-5026-41a9-89ba-42acddf02bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386479470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.386479470
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1929022390
Short name T517
Test name
Test status
Simulation time 237211064 ps
CPU time 4.36 seconds
Started Jul 11 06:56:39 PM PDT 24
Finished Jul 11 06:56:44 PM PDT 24
Peak memory 242156 kb
Host smart-82eeb37c-6d8a-4e07-8db2-0e28c7724cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929022390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1929022390
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1652252235
Short name T330
Test name
Test status
Simulation time 731637542 ps
CPU time 11.84 seconds
Started Jul 11 06:56:38 PM PDT 24
Finished Jul 11 06:56:51 PM PDT 24
Peak memory 242028 kb
Host smart-142988c7-5d9d-4216-bf6e-d849c5b30738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652252235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1652252235
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.135969981
Short name T1145
Test name
Test status
Simulation time 250600309 ps
CPU time 8.64 seconds
Started Jul 11 06:56:45 PM PDT 24
Finished Jul 11 06:56:54 PM PDT 24
Peak memory 242476 kb
Host smart-b71ab865-efba-4df1-969b-096647c682d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135969981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.135969981
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.41959182
Short name T195
Test name
Test status
Simulation time 252164354 ps
CPU time 8.22 seconds
Started Jul 11 06:56:41 PM PDT 24
Finished Jul 11 06:56:51 PM PDT 24
Peak memory 242464 kb
Host smart-b6cd669a-1bcc-4681-8a2d-f1c95e3c8e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41959182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.41959182
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.2804569588
Short name T954
Test name
Test status
Simulation time 13981403319 ps
CPU time 34.98 seconds
Started Jul 11 06:56:44 PM PDT 24
Finished Jul 11 06:57:19 PM PDT 24
Peak memory 243116 kb
Host smart-0bb0f6c3-a13c-4955-8c66-702ad609604d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804569588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.2804569588
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.1428719284
Short name T950
Test name
Test status
Simulation time 3757163085 ps
CPU time 47.65 seconds
Started Jul 11 06:56:43 PM PDT 24
Finished Jul 11 06:57:31 PM PDT 24
Peak memory 243672 kb
Host smart-0058fa23-ff4a-4b87-9fd3-07d1d0b977fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428719284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1428719284
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.1128627487
Short name T1099
Test name
Test status
Simulation time 119199536 ps
CPU time 3.96 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:01:58 PM PDT 24
Peak memory 242048 kb
Host smart-ee8b7f46-3693-4a61-a288-1a25d4879e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128627487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1128627487
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.4013066879
Short name T169
Test name
Test status
Simulation time 292894181 ps
CPU time 3.63 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:01:58 PM PDT 24
Peak memory 242064 kb
Host smart-598c9bff-e1a7-42d4-80de-a30457cbc25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013066879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.4013066879
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1756081198
Short name T197
Test name
Test status
Simulation time 2175990471 ps
CPU time 5.06 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:01:59 PM PDT 24
Peak memory 242480 kb
Host smart-93768842-9501-440f-9290-db738161a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756081198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1756081198
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1532483247
Short name T527
Test name
Test status
Simulation time 2984050931 ps
CPU time 8.2 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:02:02 PM PDT 24
Peak memory 242224 kb
Host smart-a595171d-1934-4ecb-bdeb-cb69e8facf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532483247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1532483247
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.4002402979
Short name T45
Test name
Test status
Simulation time 1563781509 ps
CPU time 5.59 seconds
Started Jul 11 07:01:51 PM PDT 24
Finished Jul 11 07:01:58 PM PDT 24
Peak memory 242088 kb
Host smart-e4688c6b-2e7e-4075-8f68-14d400551c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002402979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.4002402979
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3124586322
Short name T454
Test name
Test status
Simulation time 131000624 ps
CPU time 3.58 seconds
Started Jul 11 07:01:51 PM PDT 24
Finished Jul 11 07:01:56 PM PDT 24
Peak memory 242028 kb
Host smart-164270de-ccea-42e4-942a-41f28d7eaef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124586322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3124586322
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.122282287
Short name T816
Test name
Test status
Simulation time 1554243591 ps
CPU time 6.14 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:02:00 PM PDT 24
Peak memory 241964 kb
Host smart-6c98bf67-741a-42b9-9fac-a4d205f7a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122282287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.122282287
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.455471671
Short name T528
Test name
Test status
Simulation time 1692501994 ps
CPU time 5.25 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:02:00 PM PDT 24
Peak memory 242020 kb
Host smart-d6d5c25b-d074-4171-8552-620eee725be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455471671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.455471671
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.3960154763
Short name T89
Test name
Test status
Simulation time 299306435 ps
CPU time 4.27 seconds
Started Jul 11 07:01:54 PM PDT 24
Finished Jul 11 07:02:00 PM PDT 24
Peak memory 242076 kb
Host smart-db2028cb-e89f-495a-9e5a-53c2e4e202e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960154763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.3960154763
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2098804390
Short name T329
Test name
Test status
Simulation time 49748386 ps
CPU time 1.75 seconds
Started Jul 11 06:56:52 PM PDT 24
Finished Jul 11 06:56:55 PM PDT 24
Peak memory 240572 kb
Host smart-c197367a-b524-4694-9009-dfb387ff9b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098804390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2098804390
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.149887325
Short name T63
Test name
Test status
Simulation time 1364988620 ps
CPU time 31.88 seconds
Started Jul 11 06:56:46 PM PDT 24
Finished Jul 11 06:57:19 PM PDT 24
Peak memory 248776 kb
Host smart-671be77e-65fe-4b2b-a058-b7062edeaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149887325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.149887325
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.772605731
Short name T920
Test name
Test status
Simulation time 5430579488 ps
CPU time 50.84 seconds
Started Jul 11 06:56:47 PM PDT 24
Finished Jul 11 06:57:39 PM PDT 24
Peak memory 255364 kb
Host smart-597cf472-5080-4a2a-84e6-68ecb6d54a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772605731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.772605731
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.4156273165
Short name T595
Test name
Test status
Simulation time 666216894 ps
CPU time 12.63 seconds
Started Jul 11 06:56:47 PM PDT 24
Finished Jul 11 06:57:01 PM PDT 24
Peak memory 242412 kb
Host smart-f7074e1d-40f3-489a-bba8-50ae67becd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156273165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.4156273165
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3284541968
Short name T662
Test name
Test status
Simulation time 1671555257 ps
CPU time 6.57 seconds
Started Jul 11 06:56:41 PM PDT 24
Finished Jul 11 06:56:49 PM PDT 24
Peak memory 242068 kb
Host smart-7d60edc3-ae19-4cbe-a79c-7e2282e2dd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284541968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3284541968
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.2150144653
Short name T203
Test name
Test status
Simulation time 710396852 ps
CPU time 12.21 seconds
Started Jul 11 06:56:48 PM PDT 24
Finished Jul 11 06:57:01 PM PDT 24
Peak memory 242184 kb
Host smart-f4da7dde-62e3-4944-b279-8f66cb746bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150144653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2150144653
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3955562908
Short name T259
Test name
Test status
Simulation time 20084724613 ps
CPU time 54.47 seconds
Started Jul 11 06:56:48 PM PDT 24
Finished Jul 11 06:57:44 PM PDT 24
Peak memory 248868 kb
Host smart-e4c27027-25cc-4120-aa61-c2ef7edee1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955562908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3955562908
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.1559515611
Short name T223
Test name
Test status
Simulation time 597576381 ps
CPU time 17.2 seconds
Started Jul 11 06:56:46 PM PDT 24
Finished Jul 11 06:57:04 PM PDT 24
Peak memory 241920 kb
Host smart-ff4dca15-d315-49e5-9a50-8bb33400d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559515611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1559515611
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1436703240
Short name T1069
Test name
Test status
Simulation time 501786605 ps
CPU time 17.4 seconds
Started Jul 11 06:56:49 PM PDT 24
Finished Jul 11 06:57:07 PM PDT 24
Peak memory 241968 kb
Host smart-5956fd9c-e244-47b2-904e-1edad4ff3e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436703240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1436703240
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.822929172
Short name T568
Test name
Test status
Simulation time 3930704707 ps
CPU time 10.68 seconds
Started Jul 11 06:56:48 PM PDT 24
Finished Jul 11 06:57:00 PM PDT 24
Peak memory 242172 kb
Host smart-49a1506b-14cc-4b4a-b155-9d558eacc221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822929172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.822929172
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.2810997070
Short name T104
Test name
Test status
Simulation time 1863545951 ps
CPU time 9.46 seconds
Started Jul 11 06:56:46 PM PDT 24
Finished Jul 11 06:56:56 PM PDT 24
Peak memory 242112 kb
Host smart-e94de6d7-ad8a-4cff-a7c4-29133d8a7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810997070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2810997070
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.1410126386
Short name T231
Test name
Test status
Simulation time 95274154089 ps
CPU time 208.4 seconds
Started Jul 11 06:56:51 PM PDT 24
Finished Jul 11 07:00:20 PM PDT 24
Peak memory 259300 kb
Host smart-e0432292-761a-40ba-9916-113af590f6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410126386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.1410126386
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1325908237
Short name T325
Test name
Test status
Simulation time 168265651519 ps
CPU time 825.2 seconds
Started Jul 11 06:56:47 PM PDT 24
Finished Jul 11 07:10:33 PM PDT 24
Peak memory 351252 kb
Host smart-2b62005d-2b72-471b-a6ac-202de382f56e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325908237 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1325908237
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.2555933204
Short name T477
Test name
Test status
Simulation time 944835924 ps
CPU time 14.51 seconds
Started Jul 11 06:56:47 PM PDT 24
Finished Jul 11 06:57:02 PM PDT 24
Peak memory 242464 kb
Host smart-cf20c51f-eb89-4d3d-86f0-e2936272bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555933204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2555933204
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1792687570
Short name T999
Test name
Test status
Simulation time 358154297 ps
CPU time 3.68 seconds
Started Jul 11 07:01:55 PM PDT 24
Finished Jul 11 07:02:00 PM PDT 24
Peak memory 242168 kb
Host smart-e582f1dd-7093-4196-a508-277d4f94e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792687570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1792687570
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.61248056
Short name T703
Test name
Test status
Simulation time 182865611 ps
CPU time 3.9 seconds
Started Jul 11 07:02:01 PM PDT 24
Finished Jul 11 07:02:05 PM PDT 24
Peak memory 242180 kb
Host smart-22c86a25-a9db-45cf-b7fd-375ffa323ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61248056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.61248056
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3386732272
Short name T1183
Test name
Test status
Simulation time 312342564 ps
CPU time 4.59 seconds
Started Jul 11 07:01:55 PM PDT 24
Finished Jul 11 07:02:01 PM PDT 24
Peak memory 242224 kb
Host smart-a028ea25-d258-4028-827a-12b6f27ebd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386732272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3386732272
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.2422977039
Short name T958
Test name
Test status
Simulation time 141884257 ps
CPU time 3.78 seconds
Started Jul 11 07:01:58 PM PDT 24
Finished Jul 11 07:02:02 PM PDT 24
Peak memory 242408 kb
Host smart-efbdd40b-c5ce-4f9e-aa27-70785cc6f2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422977039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2422977039
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.816954327
Short name T499
Test name
Test status
Simulation time 496929555 ps
CPU time 4.52 seconds
Started Jul 11 07:01:58 PM PDT 24
Finished Jul 11 07:02:04 PM PDT 24
Peak memory 241988 kb
Host smart-e2f3abdd-c563-4197-8e69-e260a4af75a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816954327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.816954327
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3179088774
Short name T601
Test name
Test status
Simulation time 2128555820 ps
CPU time 6.04 seconds
Started Jul 11 07:01:55 PM PDT 24
Finished Jul 11 07:02:02 PM PDT 24
Peak memory 241996 kb
Host smart-d9b5c961-6db9-4816-8bcc-fc1c9cdb8ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179088774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3179088774
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.1926847976
Short name T1162
Test name
Test status
Simulation time 554226852 ps
CPU time 4.77 seconds
Started Jul 11 07:01:55 PM PDT 24
Finished Jul 11 07:02:01 PM PDT 24
Peak memory 242276 kb
Host smart-73558b7f-77e7-4402-bd01-b5089e4a48d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926847976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.1926847976
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3265525946
Short name T759
Test name
Test status
Simulation time 207384819 ps
CPU time 4.16 seconds
Started Jul 11 07:01:53 PM PDT 24
Finished Jul 11 07:01:59 PM PDT 24
Peak memory 241824 kb
Host smart-269490af-7429-43c0-8f7e-8d27d94da60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265525946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3265525946
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.1480368611
Short name T906
Test name
Test status
Simulation time 1585639334 ps
CPU time 7.26 seconds
Started Jul 11 07:01:54 PM PDT 24
Finished Jul 11 07:02:02 PM PDT 24
Peak memory 241912 kb
Host smart-8ffc0845-0a6b-4db9-a259-caefc1d109d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480368611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1480368611
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.1589687441
Short name T237
Test name
Test status
Simulation time 699443210 ps
CPU time 2.04 seconds
Started Jul 11 06:52:47 PM PDT 24
Finished Jul 11 06:52:50 PM PDT 24
Peak memory 240156 kb
Host smart-35b4f00d-4a4e-4836-854a-f01994ab22a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589687441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1589687441
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3684940668
Short name T398
Test name
Test status
Simulation time 2266284209 ps
CPU time 31.24 seconds
Started Jul 11 06:52:45 PM PDT 24
Finished Jul 11 06:53:17 PM PDT 24
Peak memory 242664 kb
Host smart-215055dd-8174-4a16-b4a1-c7e04f945e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684940668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3684940668
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1513787955
Short name T116
Test name
Test status
Simulation time 552064141 ps
CPU time 14.04 seconds
Started Jul 11 06:52:43 PM PDT 24
Finished Jul 11 06:52:58 PM PDT 24
Peak memory 248792 kb
Host smart-a39e6099-090f-4812-a6d9-1d0e6eb1699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513787955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1513787955
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1407031397
Short name T1146
Test name
Test status
Simulation time 17057197445 ps
CPU time 48.93 seconds
Started Jul 11 06:52:43 PM PDT 24
Finished Jul 11 06:53:33 PM PDT 24
Peak memory 250180 kb
Host smart-0de76943-0d0a-4c78-95fd-addfe75c0f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407031397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1407031397
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.4183515564
Short name T1034
Test name
Test status
Simulation time 507081845 ps
CPU time 5.4 seconds
Started Jul 11 06:52:43 PM PDT 24
Finished Jul 11 06:52:49 PM PDT 24
Peak memory 242292 kb
Host smart-6b92ad29-7ad8-46dd-9d8c-a0079e109aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183515564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4183515564
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2322072718
Short name T30
Test name
Test status
Simulation time 470213034 ps
CPU time 4.71 seconds
Started Jul 11 06:52:36 PM PDT 24
Finished Jul 11 06:52:42 PM PDT 24
Peak memory 242076 kb
Host smart-77f91e48-8d02-41bc-9adf-3a0ae6c07087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322072718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2322072718
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1557329089
Short name T1187
Test name
Test status
Simulation time 3133133343 ps
CPU time 41.81 seconds
Started Jul 11 06:52:43 PM PDT 24
Finished Jul 11 06:53:26 PM PDT 24
Peak memory 244676 kb
Host smart-da40e37a-65e0-4ea1-b84d-acaea0b48300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557329089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1557329089
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.4011319415
Short name T386
Test name
Test status
Simulation time 850938804 ps
CPU time 10.61 seconds
Started Jul 11 06:52:44 PM PDT 24
Finished Jul 11 06:52:56 PM PDT 24
Peak memory 242240 kb
Host smart-5a8471b2-b646-4c06-8145-dba588a3ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011319415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.4011319415
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.3464394395
Short name T1131
Test name
Test status
Simulation time 275318064 ps
CPU time 4.06 seconds
Started Jul 11 06:52:42 PM PDT 24
Finished Jul 11 06:52:46 PM PDT 24
Peak memory 242072 kb
Host smart-2d64f085-e019-4227-9ffc-f3ee913a02b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464394395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3464394395
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2596379819
Short name T1056
Test name
Test status
Simulation time 729736994 ps
CPU time 12.65 seconds
Started Jul 11 06:52:38 PM PDT 24
Finished Jul 11 06:52:51 PM PDT 24
Peak memory 241892 kb
Host smart-29d16aff-0c56-4b12-b324-5b7a013b1da1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596379819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2596379819
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.776240621
Short name T801
Test name
Test status
Simulation time 572989631 ps
CPU time 9.22 seconds
Started Jul 11 06:52:47 PM PDT 24
Finished Jul 11 06:52:57 PM PDT 24
Peak memory 242320 kb
Host smart-46d1ec76-9246-4e0e-9744-cc59b2449443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776240621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.776240621
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2579838554
Short name T25
Test name
Test status
Simulation time 42122063468 ps
CPU time 169.05 seconds
Started Jul 11 06:52:46 PM PDT 24
Finished Jul 11 06:55:36 PM PDT 24
Peak memory 276064 kb
Host smart-e4abf074-4894-4493-ac82-5beffd14ffcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579838554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2579838554
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.268568131
Short name T971
Test name
Test status
Simulation time 3495005978 ps
CPU time 10.67 seconds
Started Jul 11 06:52:45 PM PDT 24
Finished Jul 11 06:52:57 PM PDT 24
Peak memory 242092 kb
Host smart-7acc2c80-14aa-425a-acdd-2b3918926ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268568131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.268568131
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.2613814946
Short name T917
Test name
Test status
Simulation time 10200517816 ps
CPU time 64.98 seconds
Started Jul 11 06:52:47 PM PDT 24
Finished Jul 11 06:53:52 PM PDT 24
Peak memory 243164 kb
Host smart-79ce1474-4752-4d3f-a0f6-ea163f90b064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613814946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
2613814946
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3345930752
Short name T790
Test name
Test status
Simulation time 234142148265 ps
CPU time 1223.73 seconds
Started Jul 11 06:52:45 PM PDT 24
Finished Jul 11 07:13:10 PM PDT 24
Peak memory 258236 kb
Host smart-8824d6da-449b-4119-b308-fe293f22ddb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345930752 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3345930752
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.617416536
Short name T826
Test name
Test status
Simulation time 412069818 ps
CPU time 12.86 seconds
Started Jul 11 06:52:47 PM PDT 24
Finished Jul 11 06:53:01 PM PDT 24
Peak memory 242556 kb
Host smart-98b27570-a928-4a28-8eae-a8e0aff9f310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617416536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.617416536
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.454760485
Short name T667
Test name
Test status
Simulation time 201825988 ps
CPU time 1.76 seconds
Started Jul 11 06:56:56 PM PDT 24
Finished Jul 11 06:56:59 PM PDT 24
Peak memory 240104 kb
Host smart-51d7ca25-1e79-4f40-b250-879329558e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454760485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.454760485
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1034626770
Short name T1110
Test name
Test status
Simulation time 483817210 ps
CPU time 8.81 seconds
Started Jul 11 06:56:56 PM PDT 24
Finished Jul 11 06:57:06 PM PDT 24
Peak memory 242392 kb
Host smart-51e51f61-db31-4c5b-b8a3-51a379677f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034626770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1034626770
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.3068715794
Short name T859
Test name
Test status
Simulation time 5288411053 ps
CPU time 23.32 seconds
Started Jul 11 06:56:53 PM PDT 24
Finished Jul 11 06:57:17 PM PDT 24
Peak memory 242412 kb
Host smart-b175ebf1-eceb-4775-b9a1-00dda54e1a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068715794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3068715794
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.1685795523
Short name T513
Test name
Test status
Simulation time 194286877 ps
CPU time 4.64 seconds
Started Jul 11 06:56:53 PM PDT 24
Finished Jul 11 06:56:58 PM PDT 24
Peak memory 242080 kb
Host smart-abf8d6f5-000e-4957-8c48-cf3dd0dea762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685795523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1685795523
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1168903486
Short name T819
Test name
Test status
Simulation time 112798491 ps
CPU time 4.22 seconds
Started Jul 11 06:56:52 PM PDT 24
Finished Jul 11 06:56:57 PM PDT 24
Peak memory 242200 kb
Host smart-71526124-03e7-4576-bb7c-c565d4abff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168903486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1168903486
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.3958763098
Short name T930
Test name
Test status
Simulation time 2408514485 ps
CPU time 18.51 seconds
Started Jul 11 06:56:56 PM PDT 24
Finished Jul 11 06:57:16 PM PDT 24
Peak memory 242264 kb
Host smart-3bae491a-28b0-4e26-bdf0-97d3ddebe245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958763098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3958763098
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.907753750
Short name T600
Test name
Test status
Simulation time 354118982 ps
CPU time 7.34 seconds
Started Jul 11 06:56:54 PM PDT 24
Finished Jul 11 06:57:03 PM PDT 24
Peak memory 242248 kb
Host smart-7914b00d-094f-44a8-a30c-9ce3f92fd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907753750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.907753750
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3953226421
Short name T582
Test name
Test status
Simulation time 249937097 ps
CPU time 14.64 seconds
Started Jul 11 06:56:51 PM PDT 24
Finished Jul 11 06:57:07 PM PDT 24
Peak memory 242028 kb
Host smart-05f4b476-d109-439c-aac5-90b114ebc5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953226421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3953226421
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.2270760247
Short name T1074
Test name
Test status
Simulation time 6757404601 ps
CPU time 21.72 seconds
Started Jul 11 06:56:51 PM PDT 24
Finished Jul 11 06:57:13 PM PDT 24
Peak memory 242308 kb
Host smart-26820459-e350-419b-96e7-41efb6fa6d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270760247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.2270760247
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.2598495646
Short name T894
Test name
Test status
Simulation time 3111550046 ps
CPU time 7.73 seconds
Started Jul 11 06:56:56 PM PDT 24
Finished Jul 11 06:57:05 PM PDT 24
Peak memory 242280 kb
Host smart-cbe1bd11-1bc0-4e45-b1cb-7922ff8db997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598495646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2598495646
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2616413130
Short name T962
Test name
Test status
Simulation time 280590501 ps
CPU time 3.89 seconds
Started Jul 11 06:56:50 PM PDT 24
Finished Jul 11 06:56:54 PM PDT 24
Peak memory 242104 kb
Host smart-13b96fb8-5059-4e72-9343-9adc6e0b269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616413130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2616413130
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2816696680
Short name T378
Test name
Test status
Simulation time 12316559622 ps
CPU time 123.2 seconds
Started Jul 11 06:56:55 PM PDT 24
Finished Jul 11 06:59:00 PM PDT 24
Peak memory 248784 kb
Host smart-69d778ce-7a01-4690-ba63-4184a2b1023f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816696680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2816696680
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.1910748295
Short name T1081
Test name
Test status
Simulation time 146198655 ps
CPU time 5.25 seconds
Started Jul 11 06:56:57 PM PDT 24
Finished Jul 11 06:57:03 PM PDT 24
Peak memory 242084 kb
Host smart-0ce20de2-cc5d-4a7f-b3ec-dd2b58e2c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910748295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1910748295
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.2050834909
Short name T173
Test name
Test status
Simulation time 136005345 ps
CPU time 2.07 seconds
Started Jul 11 06:57:04 PM PDT 24
Finished Jul 11 06:57:07 PM PDT 24
Peak memory 240412 kb
Host smart-f48eaaf7-c4cc-4fb5-b162-11579993701c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050834909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2050834909
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.3704753710
Short name T468
Test name
Test status
Simulation time 5973922486 ps
CPU time 13.35 seconds
Started Jul 11 06:57:02 PM PDT 24
Finished Jul 11 06:57:15 PM PDT 24
Peak memory 241828 kb
Host smart-0acc6480-686e-4891-8526-60efb8fa5614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704753710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3704753710
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.123379418
Short name T1108
Test name
Test status
Simulation time 4128010822 ps
CPU time 28.95 seconds
Started Jul 11 06:57:00 PM PDT 24
Finished Jul 11 06:57:29 PM PDT 24
Peak memory 242308 kb
Host smart-b164e457-79c4-4fea-8447-2c6c6d7e8548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123379418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.123379418
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.2909121629
Short name T649
Test name
Test status
Simulation time 141542992 ps
CPU time 4.11 seconds
Started Jul 11 06:56:56 PM PDT 24
Finished Jul 11 06:57:02 PM PDT 24
Peak memory 241904 kb
Host smart-17fb7da7-8340-49ba-bd7a-ada8634ff49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909121629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2909121629
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2721677894
Short name T474
Test name
Test status
Simulation time 758127307 ps
CPU time 11.08 seconds
Started Jul 11 06:57:00 PM PDT 24
Finished Jul 11 06:57:11 PM PDT 24
Peak memory 244536 kb
Host smart-45e21f5d-eab5-492c-8fde-a96c3112749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721677894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2721677894
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.3989868716
Short name T965
Test name
Test status
Simulation time 615636646 ps
CPU time 9.86 seconds
Started Jul 11 06:57:04 PM PDT 24
Finished Jul 11 06:57:14 PM PDT 24
Peak memory 242000 kb
Host smart-b0ebf169-ece4-4f7b-b51d-5134f88cac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989868716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3989868716
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1333051576
Short name T1077
Test name
Test status
Simulation time 622889873 ps
CPU time 17.18 seconds
Started Jul 11 06:57:00 PM PDT 24
Finished Jul 11 06:57:17 PM PDT 24
Peak memory 241696 kb
Host smart-b739d74e-a307-42da-bdc0-b3878979a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333051576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1333051576
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2290545137
Short name T1129
Test name
Test status
Simulation time 10236987235 ps
CPU time 26.32 seconds
Started Jul 11 06:57:44 PM PDT 24
Finished Jul 11 06:58:13 PM PDT 24
Peak memory 242096 kb
Host smart-de14acbb-f803-49bd-990c-32f2edace7e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290545137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2290545137
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2126196021
Short name T607
Test name
Test status
Simulation time 1788952824 ps
CPU time 4.74 seconds
Started Jul 11 06:57:05 PM PDT 24
Finished Jul 11 06:57:10 PM PDT 24
Peak memory 241848 kb
Host smart-e02eac22-bfd6-4da6-84a5-e715c6707446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126196021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2126196021
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.1815708377
Short name T510
Test name
Test status
Simulation time 1117593011 ps
CPU time 8.08 seconds
Started Jul 11 06:56:57 PM PDT 24
Finished Jul 11 06:57:06 PM PDT 24
Peak memory 248848 kb
Host smart-f35a2b45-e4e4-4d4b-8f6c-caf3a30b48aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815708377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.1815708377
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2615493903
Short name T295
Test name
Test status
Simulation time 107680982731 ps
CPU time 2416.9 seconds
Started Jul 11 06:57:04 PM PDT 24
Finished Jul 11 07:37:21 PM PDT 24
Peak memory 535420 kb
Host smart-7300af99-4bcc-4f40-a760-543961c437d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615493903 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.2615493903
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.1152368491
Short name T661
Test name
Test status
Simulation time 229297348 ps
CPU time 4.82 seconds
Started Jul 11 06:57:05 PM PDT 24
Finished Jul 11 06:57:11 PM PDT 24
Peak memory 242056 kb
Host smart-61b0cf84-6d3f-4aa3-9838-db3d09f7397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152368491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1152368491
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.1890624795
Short name T676
Test name
Test status
Simulation time 183023808 ps
CPU time 1.7 seconds
Started Jul 11 06:57:12 PM PDT 24
Finished Jul 11 06:57:15 PM PDT 24
Peak memory 240232 kb
Host smart-2466a1bf-4f74-40b0-b2e2-a2120a9c2022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890624795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1890624795
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.2944703613
Short name T1124
Test name
Test status
Simulation time 3888424066 ps
CPU time 28.53 seconds
Started Jul 11 06:57:09 PM PDT 24
Finished Jul 11 06:57:38 PM PDT 24
Peak memory 242164 kb
Host smart-20138734-0746-49ba-a9bf-c82e7b25f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944703613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2944703613
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1897560888
Short name T856
Test name
Test status
Simulation time 1520223322 ps
CPU time 27.16 seconds
Started Jul 11 06:57:08 PM PDT 24
Finished Jul 11 06:57:36 PM PDT 24
Peak memory 242208 kb
Host smart-0ab23f8e-464a-4922-abac-3f14a1be7467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897560888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1897560888
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2615404486
Short name T1083
Test name
Test status
Simulation time 3788759291 ps
CPU time 30.38 seconds
Started Jul 11 06:57:06 PM PDT 24
Finished Jul 11 06:57:37 PM PDT 24
Peak memory 242492 kb
Host smart-41a77d9b-f578-4d06-af52-368e401cff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615404486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2615404486
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.1763007316
Short name T201
Test name
Test status
Simulation time 333112517 ps
CPU time 3.22 seconds
Started Jul 11 06:57:04 PM PDT 24
Finished Jul 11 06:57:08 PM PDT 24
Peak memory 242084 kb
Host smart-9e4c448e-74c1-4d5a-ad32-42bce48c4c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763007316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1763007316
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.1232320621
Short name T2
Test name
Test status
Simulation time 686644800 ps
CPU time 15.84 seconds
Started Jul 11 06:57:12 PM PDT 24
Finished Jul 11 06:57:29 PM PDT 24
Peak memory 245144 kb
Host smart-04471c83-253b-4f08-91a7-659b4a1f0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232320621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1232320621
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3402879269
Short name T810
Test name
Test status
Simulation time 478811375 ps
CPU time 12.6 seconds
Started Jul 11 06:57:12 PM PDT 24
Finished Jul 11 06:57:25 PM PDT 24
Peak memory 242504 kb
Host smart-b3c9db9d-fe83-4403-a7a6-7a682857ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402879269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3402879269
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3125173027
Short name T189
Test name
Test status
Simulation time 205393375 ps
CPU time 5.77 seconds
Started Jul 11 06:57:08 PM PDT 24
Finished Jul 11 06:57:14 PM PDT 24
Peak memory 241768 kb
Host smart-d1d8a141-2d2f-44fa-b64b-b9cb59883418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125173027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3125173027
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1464064541
Short name T664
Test name
Test status
Simulation time 390578216 ps
CPU time 11.63 seconds
Started Jul 11 06:57:09 PM PDT 24
Finished Jul 11 06:57:21 PM PDT 24
Peak memory 242244 kb
Host smart-1c568d2d-ad19-40bd-b301-6f672db0aac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464064541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1464064541
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.812078777
Short name T886
Test name
Test status
Simulation time 154533615 ps
CPU time 6.59 seconds
Started Jul 11 06:57:12 PM PDT 24
Finished Jul 11 06:57:19 PM PDT 24
Peak memory 242208 kb
Host smart-9a3e8e45-3e00-41b4-b1d6-cbfd3847e442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812078777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.812078777
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.4032473997
Short name T982
Test name
Test status
Simulation time 692059614 ps
CPU time 6.71 seconds
Started Jul 11 06:57:06 PM PDT 24
Finished Jul 11 06:57:13 PM PDT 24
Peak memory 242116 kb
Host smart-381581f7-d40b-4aba-b42c-9c05e8ee304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032473997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.4032473997
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.3112165361
Short name T795
Test name
Test status
Simulation time 83896911061 ps
CPU time 227.21 seconds
Started Jul 11 06:57:15 PM PDT 24
Finished Jul 11 07:01:03 PM PDT 24
Peak memory 263580 kb
Host smart-beb1ee43-9561-433c-9b5b-df900efc869f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112165361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.3112165361
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.328022561
Short name T321
Test name
Test status
Simulation time 268866119360 ps
CPU time 739.27 seconds
Started Jul 11 06:57:11 PM PDT 24
Finished Jul 11 07:09:32 PM PDT 24
Peak memory 275048 kb
Host smart-1e176629-5354-402e-845b-476829ab022c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328022561 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.328022561
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.621677316
Short name T100
Test name
Test status
Simulation time 852985665 ps
CPU time 19.32 seconds
Started Jul 11 06:57:14 PM PDT 24
Finished Jul 11 06:57:34 PM PDT 24
Peak memory 242828 kb
Host smart-fb0ca2a2-9619-4404-9679-25ac8d9e8a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621677316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.621677316
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3818414213
Short name T460
Test name
Test status
Simulation time 645300931 ps
CPU time 1.67 seconds
Started Jul 11 06:57:19 PM PDT 24
Finished Jul 11 06:57:22 PM PDT 24
Peak memory 240236 kb
Host smart-bd8329cb-1281-47d5-b5b2-8d178c6c9025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818414213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3818414213
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.78563171
Short name T66
Test name
Test status
Simulation time 683141886 ps
CPU time 5.9 seconds
Started Jul 11 06:57:15 PM PDT 24
Finished Jul 11 06:57:22 PM PDT 24
Peak memory 242140 kb
Host smart-4e5c2ced-b8f4-4858-9343-432d15c242aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78563171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.78563171
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.4077260679
Short name T644
Test name
Test status
Simulation time 4194510039 ps
CPU time 35.49 seconds
Started Jul 11 06:57:17 PM PDT 24
Finished Jul 11 06:57:54 PM PDT 24
Peak memory 246580 kb
Host smart-01803b18-cdf2-439d-9e28-b34cf8705dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077260679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.4077260679
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.2346307710
Short name T395
Test name
Test status
Simulation time 210071536 ps
CPU time 5.98 seconds
Started Jul 11 06:57:18 PM PDT 24
Finished Jul 11 06:57:25 PM PDT 24
Peak memory 242240 kb
Host smart-54209a0c-9f88-4538-94e1-df068b9844e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346307710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2346307710
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.859343024
Short name T973
Test name
Test status
Simulation time 212085224 ps
CPU time 3.41 seconds
Started Jul 11 06:57:13 PM PDT 24
Finished Jul 11 06:57:17 PM PDT 24
Peak memory 242160 kb
Host smart-d0b4cf00-5c22-4490-a6f0-4ff2784a535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859343024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.859343024
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.979356042
Short name T185
Test name
Test status
Simulation time 6712661621 ps
CPU time 48.78 seconds
Started Jul 11 06:57:18 PM PDT 24
Finished Jul 11 06:58:08 PM PDT 24
Peak memory 257248 kb
Host smart-f6bba2a4-46cd-4451-9593-e1a0602902a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979356042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.979356042
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2488096481
Short name T757
Test name
Test status
Simulation time 678090802 ps
CPU time 5.07 seconds
Started Jul 11 06:57:17 PM PDT 24
Finished Jul 11 06:57:23 PM PDT 24
Peak memory 242376 kb
Host smart-a63d3dbe-ce32-485d-866b-7021c4474122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488096481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2488096481
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.617887562
Short name T72
Test name
Test status
Simulation time 222665979 ps
CPU time 10.45 seconds
Started Jul 11 06:57:16 PM PDT 24
Finished Jul 11 06:57:27 PM PDT 24
Peak memory 242012 kb
Host smart-8097e091-d42d-4dcf-9851-6812f0cf9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617887562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.617887562
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.3226595025
Short name T994
Test name
Test status
Simulation time 1458898004 ps
CPU time 19.35 seconds
Started Jul 11 06:57:16 PM PDT 24
Finished Jul 11 06:57:36 PM PDT 24
Peak memory 242232 kb
Host smart-616ef5b2-2712-445e-b0b3-ada165651e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226595025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3226595025
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.1237148112
Short name T1135
Test name
Test status
Simulation time 2296270137 ps
CPU time 6.3 seconds
Started Jul 11 06:57:16 PM PDT 24
Finished Jul 11 06:57:23 PM PDT 24
Peak memory 242152 kb
Host smart-16ac0245-3901-4a2f-9550-1131055dcbdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237148112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1237148112
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.219955757
Short name T160
Test name
Test status
Simulation time 1816636496 ps
CPU time 5.19 seconds
Started Jul 11 06:57:12 PM PDT 24
Finished Jul 11 06:57:18 PM PDT 24
Peak memory 242280 kb
Host smart-21de8701-6cec-4600-895c-4b33b3377f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219955757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.219955757
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2511076788
Short name T1028
Test name
Test status
Simulation time 10357334432 ps
CPU time 52.51 seconds
Started Jul 11 06:57:15 PM PDT 24
Finished Jul 11 06:58:08 PM PDT 24
Peak memory 246624 kb
Host smart-632574d3-c5c9-46fe-bf7f-fa123a8a1f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511076788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2511076788
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.4186723608
Short name T977
Test name
Test status
Simulation time 79008667303 ps
CPU time 1643.59 seconds
Started Jul 11 06:57:16 PM PDT 24
Finished Jul 11 07:24:41 PM PDT 24
Peak memory 304276 kb
Host smart-3dba6fef-6643-49cc-9ce5-0f31b874945b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186723608 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.4186723608
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.631996590
Short name T849
Test name
Test status
Simulation time 1274207892 ps
CPU time 22.79 seconds
Started Jul 11 06:57:17 PM PDT 24
Finished Jul 11 06:57:41 PM PDT 24
Peak memory 242240 kb
Host smart-d19ac204-37d3-4b24-952d-9bd9dd3dba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631996590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.631996590
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3520310998
Short name T628
Test name
Test status
Simulation time 88641397 ps
CPU time 1.9 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:28 PM PDT 24
Peak memory 240244 kb
Host smart-252f1fc5-5a6d-45a7-ad56-5879b8d31f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520310998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3520310998
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.414192452
Short name T84
Test name
Test status
Simulation time 636632311 ps
CPU time 12.8 seconds
Started Jul 11 06:57:19 PM PDT 24
Finished Jul 11 06:57:33 PM PDT 24
Peak memory 242224 kb
Host smart-4a61606c-4867-443c-b048-7afe1fa127c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414192452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.414192452
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2255612966
Short name T715
Test name
Test status
Simulation time 9261699181 ps
CPU time 24.63 seconds
Started Jul 11 06:57:20 PM PDT 24
Finished Jul 11 06:57:45 PM PDT 24
Peak memory 242112 kb
Host smart-6300bf33-a372-4534-ac9e-2564a9a2f819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255612966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2255612966
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.651990586
Short name T898
Test name
Test status
Simulation time 3631287946 ps
CPU time 33.65 seconds
Started Jul 11 06:57:20 PM PDT 24
Finished Jul 11 06:57:55 PM PDT 24
Peak memory 242728 kb
Host smart-5613ebd1-f073-40cb-a31d-aa4a78439c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651990586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.651990586
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.1151526460
Short name T821
Test name
Test status
Simulation time 436239870 ps
CPU time 5.12 seconds
Started Jul 11 06:57:21 PM PDT 24
Finished Jul 11 06:57:27 PM PDT 24
Peak memory 241840 kb
Host smart-a338ae4f-8095-4b98-b7f2-3ad52ad3a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151526460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1151526460
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.2669105047
Short name T1133
Test name
Test status
Simulation time 2633600940 ps
CPU time 33.12 seconds
Started Jul 11 06:57:24 PM PDT 24
Finished Jul 11 06:57:58 PM PDT 24
Peak memory 243496 kb
Host smart-54de731c-455c-4da9-8bc0-18bcc775db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669105047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2669105047
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3857835457
Short name T368
Test name
Test status
Simulation time 984593645 ps
CPU time 26.26 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:53 PM PDT 24
Peak memory 242624 kb
Host smart-a597da63-c01a-4fce-8049-1d883ed9da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857835457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3857835457
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2633106430
Short name T732
Test name
Test status
Simulation time 2251816546 ps
CPU time 8.46 seconds
Started Jul 11 06:57:22 PM PDT 24
Finished Jul 11 06:57:31 PM PDT 24
Peak memory 241880 kb
Host smart-0faa77d6-9840-4bc0-b100-a5dfe4fbc414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633106430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2633106430
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1155379495
Short name T373
Test name
Test status
Simulation time 1337551355 ps
CPU time 20.02 seconds
Started Jul 11 06:57:20 PM PDT 24
Finished Jul 11 06:57:41 PM PDT 24
Peak memory 241968 kb
Host smart-56b300d6-8456-422f-934e-3af75f796972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155379495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1155379495
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2853627268
Short name T878
Test name
Test status
Simulation time 2133655902 ps
CPU time 6.07 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:32 PM PDT 24
Peak memory 242068 kb
Host smart-59beec2f-1cb9-4d46-af55-fb4deae88044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853627268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2853627268
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.2923378395
Short name T571
Test name
Test status
Simulation time 214613505 ps
CPU time 3.51 seconds
Started Jul 11 06:57:21 PM PDT 24
Finished Jul 11 06:57:25 PM PDT 24
Peak memory 242296 kb
Host smart-59cc5248-779e-4fcc-85a6-273d92635c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923378395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2923378395
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.3323456357
Short name T735
Test name
Test status
Simulation time 43123175520 ps
CPU time 545.59 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 07:06:32 PM PDT 24
Peak memory 248836 kb
Host smart-2c1c4126-083a-43df-8778-5dece4ce9ea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323456357 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.3323456357
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.3805047388
Short name T1089
Test name
Test status
Simulation time 546819426 ps
CPU time 7.11 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:33 PM PDT 24
Peak memory 242420 kb
Host smart-83e550fc-1c84-41a8-b59d-721f4214d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805047388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3805047388
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2668364655
Short name T645
Test name
Test status
Simulation time 77477622 ps
CPU time 2.07 seconds
Started Jul 11 06:57:35 PM PDT 24
Finished Jul 11 06:57:37 PM PDT 24
Peak memory 240472 kb
Host smart-ae42f0e0-d6e2-4e51-a3bd-5c8b84a34e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668364655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2668364655
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.4280151034
Short name T530
Test name
Test status
Simulation time 530400277 ps
CPU time 9.36 seconds
Started Jul 11 06:57:27 PM PDT 24
Finished Jul 11 06:57:37 PM PDT 24
Peak memory 242244 kb
Host smart-0c2bc38c-7a80-475d-9479-c0da741ea0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280151034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.4280151034
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.2331850200
Short name T1033
Test name
Test status
Simulation time 576154092 ps
CPU time 16.86 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:43 PM PDT 24
Peak memory 242120 kb
Host smart-a7c868f9-5d85-4a68-923a-b93d1d037f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331850200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2331850200
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1661325846
Short name T976
Test name
Test status
Simulation time 290843713 ps
CPU time 5.45 seconds
Started Jul 11 06:57:24 PM PDT 24
Finished Jul 11 06:57:30 PM PDT 24
Peak memory 242576 kb
Host smart-7adf03ba-2b46-4912-a3fe-35a176a7cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661325846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1661325846
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.3990647806
Short name T599
Test name
Test status
Simulation time 285765162 ps
CPU time 4.29 seconds
Started Jul 11 06:57:26 PM PDT 24
Finished Jul 11 06:57:31 PM PDT 24
Peak memory 242004 kb
Host smart-56259109-e9f2-4e7a-ad2f-dc6fc0f4c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990647806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3990647806
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.320947680
Short name T550
Test name
Test status
Simulation time 328101236 ps
CPU time 4.81 seconds
Started Jul 11 06:57:32 PM PDT 24
Finished Jul 11 06:57:37 PM PDT 24
Peak memory 242432 kb
Host smart-ff733fae-b2de-49da-88b4-3e5f79d1c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320947680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.320947680
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1201867896
Short name T94
Test name
Test status
Simulation time 1906260038 ps
CPU time 31.75 seconds
Started Jul 11 06:57:28 PM PDT 24
Finished Jul 11 06:58:00 PM PDT 24
Peak memory 242720 kb
Host smart-dc45f4b4-a6e0-44aa-b738-d77366139077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201867896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1201867896
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.1655863089
Short name T833
Test name
Test status
Simulation time 231212420 ps
CPU time 9.26 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:36 PM PDT 24
Peak memory 242100 kb
Host smart-20d4f102-c756-4810-8423-6dd512da7f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655863089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1655863089
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.1333961484
Short name T469
Test name
Test status
Simulation time 543527394 ps
CPU time 5.49 seconds
Started Jul 11 06:57:25 PM PDT 24
Finished Jul 11 06:57:32 PM PDT 24
Peak memory 248568 kb
Host smart-a21f39e3-5f6c-4205-9ad3-bd17fc74327d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333961484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1333961484
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.3635499891
Short name T914
Test name
Test status
Simulation time 567100594 ps
CPU time 12.5 seconds
Started Jul 11 06:57:29 PM PDT 24
Finished Jul 11 06:57:43 PM PDT 24
Peak memory 242348 kb
Host smart-94e4cc94-fcc1-4fbc-9503-a3f8be2381e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635499891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3635499891
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1426589558
Short name T733
Test name
Test status
Simulation time 893806178 ps
CPU time 6.29 seconds
Started Jul 11 06:57:24 PM PDT 24
Finished Jul 11 06:57:31 PM PDT 24
Peak memory 242160 kb
Host smart-8b8128f2-72af-4dd6-bb10-4af6886d2f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426589558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1426589558
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.1852369787
Short name T835
Test name
Test status
Simulation time 6750082457 ps
CPU time 61.24 seconds
Started Jul 11 06:57:30 PM PDT 24
Finished Jul 11 06:58:33 PM PDT 24
Peak memory 244672 kb
Host smart-3908c443-1f6e-4ad6-a50d-3806e024899c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852369787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.1852369787
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.4242051720
Short name T376
Test name
Test status
Simulation time 18382891877 ps
CPU time 52.97 seconds
Started Jul 11 06:57:29 PM PDT 24
Finished Jul 11 06:58:23 PM PDT 24
Peak memory 248856 kb
Host smart-684863a8-9889-4b09-bc7a-189ef1023028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242051720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.4242051720
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1120525860
Short name T328
Test name
Test status
Simulation time 61324352 ps
CPU time 1.69 seconds
Started Jul 11 06:57:37 PM PDT 24
Finished Jul 11 06:57:39 PM PDT 24
Peak memory 240444 kb
Host smart-8122011f-4613-4671-9ea7-6928f0c4987e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120525860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1120525860
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.2995810169
Short name T1130
Test name
Test status
Simulation time 485938882 ps
CPU time 14.77 seconds
Started Jul 11 06:57:45 PM PDT 24
Finished Jul 11 06:58:02 PM PDT 24
Peak memory 242316 kb
Host smart-2e0399a4-8fe9-41a8-b156-0bfe5b5d9d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995810169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2995810169
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.3621983392
Short name T939
Test name
Test status
Simulation time 367331433 ps
CPU time 9.44 seconds
Started Jul 11 06:57:36 PM PDT 24
Finished Jul 11 06:57:46 PM PDT 24
Peak memory 242092 kb
Host smart-aaaa1a00-23a8-4a55-bbc0-930a5e68de8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621983392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3621983392
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1189223316
Short name T531
Test name
Test status
Simulation time 849391905 ps
CPU time 31.52 seconds
Started Jul 11 06:57:34 PM PDT 24
Finished Jul 11 06:58:06 PM PDT 24
Peak memory 248800 kb
Host smart-bc0a6b3b-c409-45db-8c59-825613b99d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189223316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1189223316
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.392721995
Short name T554
Test name
Test status
Simulation time 365988007 ps
CPU time 4.85 seconds
Started Jul 11 06:57:32 PM PDT 24
Finished Jul 11 06:57:38 PM PDT 24
Peak memory 242396 kb
Host smart-3eaebb87-439f-4f2b-abfc-78f0d4cc5187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392721995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.392721995
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.497032212
Short name T435
Test name
Test status
Simulation time 9664886533 ps
CPU time 24.08 seconds
Started Jul 11 06:57:38 PM PDT 24
Finished Jul 11 06:58:03 PM PDT 24
Peak memory 245268 kb
Host smart-5984fa6c-99de-484e-8fb0-980251d0fa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497032212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.497032212
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.2567016528
Short name T529
Test name
Test status
Simulation time 1102318694 ps
CPU time 25.48 seconds
Started Jul 11 06:57:39 PM PDT 24
Finished Jul 11 06:58:05 PM PDT 24
Peak memory 241976 kb
Host smart-e51f66fc-a0ec-439b-8ad3-3041ef6d9b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567016528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.2567016528
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3319992532
Short name T638
Test name
Test status
Simulation time 485086092 ps
CPU time 10.97 seconds
Started Jul 11 06:57:33 PM PDT 24
Finished Jul 11 06:57:45 PM PDT 24
Peak memory 242376 kb
Host smart-4425818e-937c-4eca-8ecf-572133adcbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319992532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3319992532
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2146150740
Short name T1068
Test name
Test status
Simulation time 230907275 ps
CPU time 6.5 seconds
Started Jul 11 06:57:33 PM PDT 24
Finished Jul 11 06:57:40 PM PDT 24
Peak memory 241904 kb
Host smart-a915bb02-24e8-4470-90eb-01441239bf54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146150740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2146150740
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.280157605
Short name T354
Test name
Test status
Simulation time 712416580 ps
CPU time 9.75 seconds
Started Jul 11 06:57:37 PM PDT 24
Finished Jul 11 06:57:47 PM PDT 24
Peak memory 242104 kb
Host smart-19417426-74c7-4559-b858-6eaccddf067d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280157605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.280157605
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.106194263
Short name T417
Test name
Test status
Simulation time 5924294580 ps
CPU time 13.44 seconds
Started Jul 11 06:57:32 PM PDT 24
Finished Jul 11 06:57:46 PM PDT 24
Peak memory 242168 kb
Host smart-c8cc2502-e4ed-48c3-8394-603a6c94449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106194263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.106194263
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.282534831
Short name T694
Test name
Test status
Simulation time 226876349 ps
CPU time 1.99 seconds
Started Jul 11 06:57:43 PM PDT 24
Finished Jul 11 06:57:47 PM PDT 24
Peak memory 240140 kb
Host smart-32a50d24-d3f0-4fbe-916f-45caa48beca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282534831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.282534831
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.4146958751
Short name T56
Test name
Test status
Simulation time 857369642 ps
CPU time 25.36 seconds
Started Jul 11 06:57:44 PM PDT 24
Finished Jul 11 06:58:11 PM PDT 24
Peak memory 242952 kb
Host smart-7bdc1be6-b261-49b3-9f32-aa38ded45a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146958751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4146958751
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.477372330
Short name T1174
Test name
Test status
Simulation time 1203713996 ps
CPU time 30.95 seconds
Started Jul 11 06:57:39 PM PDT 24
Finished Jul 11 06:58:11 PM PDT 24
Peak memory 242748 kb
Host smart-d74ca8d9-2326-4b11-879c-f204e62ddc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477372330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.477372330
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.363423012
Short name T892
Test name
Test status
Simulation time 1774353092 ps
CPU time 12.74 seconds
Started Jul 11 06:57:42 PM PDT 24
Finished Jul 11 06:57:55 PM PDT 24
Peak memory 242492 kb
Host smart-7e21a8be-f3de-421d-9693-5549df6b0fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363423012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.363423012
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.276399565
Short name T841
Test name
Test status
Simulation time 175345165 ps
CPU time 3.62 seconds
Started Jul 11 06:57:42 PM PDT 24
Finished Jul 11 06:57:47 PM PDT 24
Peak memory 242396 kb
Host smart-d7e99e9f-ebd4-468a-acf4-4e11103309f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276399565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.276399565
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.2294289465
Short name T1196
Test name
Test status
Simulation time 1901787990 ps
CPU time 13.92 seconds
Started Jul 11 06:57:43 PM PDT 24
Finished Jul 11 06:57:59 PM PDT 24
Peak memory 242060 kb
Host smart-19edd13a-723d-45a0-b12b-eaa25a5a110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294289465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2294289465
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.332933003
Short name T808
Test name
Test status
Simulation time 1788835906 ps
CPU time 22.57 seconds
Started Jul 11 06:57:45 PM PDT 24
Finished Jul 11 06:58:09 PM PDT 24
Peak memory 242072 kb
Host smart-13fd68a1-d895-46cd-8db5-9b0cc9e972bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332933003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.332933003
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.3372001749
Short name T333
Test name
Test status
Simulation time 3780028836 ps
CPU time 28.02 seconds
Started Jul 11 06:57:58 PM PDT 24
Finished Jul 11 06:58:27 PM PDT 24
Peak memory 242384 kb
Host smart-c317380a-ba46-4f59-91f4-26114d7ab3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372001749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3372001749
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.184705141
Short name T476
Test name
Test status
Simulation time 464490615 ps
CPU time 9.35 seconds
Started Jul 11 06:57:43 PM PDT 24
Finished Jul 11 06:57:54 PM PDT 24
Peak memory 242168 kb
Host smart-c39905ce-044d-4c5f-9ad4-fc763b6c4df9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184705141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.184705141
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.911311408
Short name T267
Test name
Test status
Simulation time 5897648239 ps
CPU time 10.76 seconds
Started Jul 11 06:57:37 PM PDT 24
Finished Jul 11 06:57:49 PM PDT 24
Peak memory 242608 kb
Host smart-f65ffe62-7787-43fb-8f5b-562ef6feebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911311408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.911311408
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2078353110
Short name T1084
Test name
Test status
Simulation time 6507747471 ps
CPU time 68.53 seconds
Started Jul 11 06:57:39 PM PDT 24
Finished Jul 11 06:58:49 PM PDT 24
Peak memory 248744 kb
Host smart-feb8dc44-ac2e-47f0-9459-eeb1186ffa14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078353110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2078353110
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1146844907
Short name T928
Test name
Test status
Simulation time 51000442228 ps
CPU time 855.87 seconds
Started Jul 11 06:57:43 PM PDT 24
Finished Jul 11 07:12:01 PM PDT 24
Peak memory 248972 kb
Host smart-aef4d3fd-9477-4758-8a4f-6858dc1830c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146844907 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.1146844907
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3416042055
Short name T885
Test name
Test status
Simulation time 737905282 ps
CPU time 17.81 seconds
Started Jul 11 06:57:46 PM PDT 24
Finished Jul 11 06:58:05 PM PDT 24
Peak memory 248808 kb
Host smart-6831de0d-97e5-47b8-9642-d5438c00c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416042055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3416042055
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.2410662223
Short name T961
Test name
Test status
Simulation time 71945403 ps
CPU time 1.84 seconds
Started Jul 11 06:57:55 PM PDT 24
Finished Jul 11 06:57:58 PM PDT 24
Peak memory 240188 kb
Host smart-7c37141d-8716-4090-9892-e55d74811350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410662223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2410662223
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.2484525191
Short name T210
Test name
Test status
Simulation time 4843045347 ps
CPU time 22.83 seconds
Started Jul 11 06:57:49 PM PDT 24
Finished Jul 11 06:58:13 PM PDT 24
Peak memory 248832 kb
Host smart-1b7b7a13-29ed-4ea8-8251-84efd56af482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484525191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2484525191
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.94274093
Short name T875
Test name
Test status
Simulation time 487128267 ps
CPU time 6.03 seconds
Started Jul 11 06:57:48 PM PDT 24
Finished Jul 11 06:57:55 PM PDT 24
Peak memory 242288 kb
Host smart-d631cd96-6ae4-47bb-9e33-86ad5f92e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94274093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.94274093
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.1130337716
Short name T559
Test name
Test status
Simulation time 510668690 ps
CPU time 5.48 seconds
Started Jul 11 06:57:45 PM PDT 24
Finished Jul 11 06:57:52 PM PDT 24
Peak memory 242196 kb
Host smart-ef4161b4-9747-48e4-97b8-7132824f6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130337716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1130337716
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3120215882
Short name T186
Test name
Test status
Simulation time 5052977647 ps
CPU time 61.71 seconds
Started Jul 11 06:57:48 PM PDT 24
Finished Jul 11 06:58:52 PM PDT 24
Peak memory 256996 kb
Host smart-19b08267-164a-419a-bb1e-d22c2ce7c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120215882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3120215882
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1963027706
Short name T260
Test name
Test status
Simulation time 1984327848 ps
CPU time 35.73 seconds
Started Jul 11 06:57:50 PM PDT 24
Finished Jul 11 06:58:27 PM PDT 24
Peak memory 242676 kb
Host smart-bca05b99-8ebb-45a5-ad2f-fd969ab4c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963027706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1963027706
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.1082438626
Short name T889
Test name
Test status
Simulation time 282329501 ps
CPU time 6.2 seconds
Started Jul 11 06:57:47 PM PDT 24
Finished Jul 11 06:57:54 PM PDT 24
Peak memory 241636 kb
Host smart-604339f4-8ffa-410c-82a9-d2c8bf8b100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082438626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.1082438626
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.728616924
Short name T578
Test name
Test status
Simulation time 884199311 ps
CPU time 14.21 seconds
Started Jul 11 06:57:45 PM PDT 24
Finished Jul 11 06:58:01 PM PDT 24
Peak memory 248636 kb
Host smart-5a61ac29-3d69-47bd-b536-2d1c1eb4aaad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728616924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.728616924
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3178998731
Short name T576
Test name
Test status
Simulation time 111084200 ps
CPU time 4.11 seconds
Started Jul 11 06:57:50 PM PDT 24
Finished Jul 11 06:57:55 PM PDT 24
Peak memory 242208 kb
Host smart-c52808f8-117b-45d8-b42a-3f9c79b916fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178998731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3178998731
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1914953479
Short name T1026
Test name
Test status
Simulation time 622268921 ps
CPU time 6.49 seconds
Started Jul 11 06:57:47 PM PDT 24
Finished Jul 11 06:57:55 PM PDT 24
Peak memory 241996 kb
Host smart-498f5e2a-70e5-4801-9df4-d5b754746387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914953479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1914953479
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.3566756869
Short name T931
Test name
Test status
Simulation time 363475298340 ps
CPU time 861.93 seconds
Started Jul 11 06:57:50 PM PDT 24
Finished Jul 11 07:12:13 PM PDT 24
Peak memory 342788 kb
Host smart-ac63b530-516d-4907-9527-9d6104dbf481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566756869 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.3566756869
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3126140559
Short name T746
Test name
Test status
Simulation time 305755576 ps
CPU time 6.04 seconds
Started Jul 11 06:57:51 PM PDT 24
Finished Jul 11 06:57:58 PM PDT 24
Peak memory 242232 kb
Host smart-b213a094-ea66-4096-af5f-edd90eb7bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126140559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3126140559
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.1656655052
Short name T1154
Test name
Test status
Simulation time 55023043 ps
CPU time 1.89 seconds
Started Jul 11 06:57:57 PM PDT 24
Finished Jul 11 06:58:00 PM PDT 24
Peak memory 240540 kb
Host smart-6e77549f-65be-4f16-b144-75ef04ed8c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656655052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1656655052
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3760152755
Short name T337
Test name
Test status
Simulation time 417036853 ps
CPU time 26.58 seconds
Started Jul 11 06:57:53 PM PDT 24
Finished Jul 11 06:58:22 PM PDT 24
Peak memory 242012 kb
Host smart-871511e0-3681-46a6-860c-d04eedbd8e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760152755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3760152755
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.3491401245
Short name T178
Test name
Test status
Simulation time 799510481 ps
CPU time 19.43 seconds
Started Jul 11 06:57:53 PM PDT 24
Finished Jul 11 06:58:14 PM PDT 24
Peak memory 242564 kb
Host smart-17cae95f-7295-492e-8a90-a92806614874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491401245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3491401245
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3250638786
Short name T74
Test name
Test status
Simulation time 133940773 ps
CPU time 4.24 seconds
Started Jul 11 06:57:51 PM PDT 24
Finished Jul 11 06:57:56 PM PDT 24
Peak memory 242092 kb
Host smart-d0b94748-05ab-45ef-9712-8686caa7e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250638786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3250638786
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2232705217
Short name T170
Test name
Test status
Simulation time 545406747 ps
CPU time 9.64 seconds
Started Jul 11 06:57:52 PM PDT 24
Finished Jul 11 06:58:03 PM PDT 24
Peak memory 242464 kb
Host smart-fb61ac2e-fa9f-4a23-95a1-a4079085eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232705217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2232705217
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2632992158
Short name T1175
Test name
Test status
Simulation time 942124130 ps
CPU time 13.18 seconds
Started Jul 11 06:57:54 PM PDT 24
Finished Jul 11 06:58:09 PM PDT 24
Peak memory 242320 kb
Host smart-4f2c7f33-a100-40e4-9a4b-331e7cc0cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632992158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2632992158
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.258169350
Short name T331
Test name
Test status
Simulation time 3140092486 ps
CPU time 9.56 seconds
Started Jul 11 06:57:52 PM PDT 24
Finished Jul 11 06:58:03 PM PDT 24
Peak memory 242084 kb
Host smart-c53904b5-0299-44ee-a341-0a4af422f38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258169350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.258169350
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1060932937
Short name T268
Test name
Test status
Simulation time 3370136702 ps
CPU time 22.64 seconds
Started Jul 11 06:57:53 PM PDT 24
Finished Jul 11 06:58:18 PM PDT 24
Peak memory 241924 kb
Host smart-f763cac2-dd8f-49ee-9059-b1a064e615a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060932937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1060932937
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.2068728822
Short name T990
Test name
Test status
Simulation time 557701219 ps
CPU time 10.85 seconds
Started Jul 11 06:57:57 PM PDT 24
Finished Jul 11 06:58:10 PM PDT 24
Peak memory 242016 kb
Host smart-f90d5b64-37c2-469b-a29b-18380fc4208a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068728822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.2068728822
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1462291124
Short name T1136
Test name
Test status
Simulation time 3582943118 ps
CPU time 5.69 seconds
Started Jul 11 06:57:54 PM PDT 24
Finished Jul 11 06:58:02 PM PDT 24
Peak memory 242468 kb
Host smart-94a917f0-f5d5-48d8-8866-70d332f08562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462291124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1462291124
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2964364131
Short name T751
Test name
Test status
Simulation time 1261664326 ps
CPU time 15.03 seconds
Started Jul 11 06:57:56 PM PDT 24
Finished Jul 11 06:58:13 PM PDT 24
Peak memory 242424 kb
Host smart-704bfdb2-47cc-4c52-8c88-a1eaa62c651b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964364131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2964364131
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2571462605
Short name T7
Test name
Test status
Simulation time 66457224095 ps
CPU time 572.49 seconds
Started Jul 11 06:57:56 PM PDT 24
Finished Jul 11 07:07:31 PM PDT 24
Peak memory 298104 kb
Host smart-855ebeb5-a3fd-4713-96e4-d6e8ece419d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571462605 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2571462605
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.3783305393
Short name T1189
Test name
Test status
Simulation time 1090689726 ps
CPU time 11.82 seconds
Started Jul 11 06:57:56 PM PDT 24
Finished Jul 11 06:58:09 PM PDT 24
Peak memory 242556 kb
Host smart-d471dd53-ab0b-4a28-98d8-2b4add86ca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783305393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3783305393
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3558326629
Short name T815
Test name
Test status
Simulation time 57865081 ps
CPU time 1.83 seconds
Started Jul 11 06:53:10 PM PDT 24
Finished Jul 11 06:53:13 PM PDT 24
Peak memory 240180 kb
Host smart-195f3497-bf65-4ea8-8f0a-e741abec5f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558326629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3558326629
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3919762766
Short name T615
Test name
Test status
Simulation time 2730649717 ps
CPU time 34.67 seconds
Started Jul 11 06:52:51 PM PDT 24
Finished Jul 11 06:53:27 PM PDT 24
Peak memory 242328 kb
Host smart-ffd2650e-a96f-4193-bf41-a757f1b91d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919762766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3919762766
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.1492968957
Short name T123
Test name
Test status
Simulation time 1813957857 ps
CPU time 25.53 seconds
Started Jul 11 06:53:00 PM PDT 24
Finished Jul 11 06:53:26 PM PDT 24
Peak memory 248816 kb
Host smart-8c22830b-eb79-4315-866b-0cceb2ab6e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492968957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1492968957
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.895564868
Short name T505
Test name
Test status
Simulation time 820829554 ps
CPU time 20.71 seconds
Started Jul 11 06:53:01 PM PDT 24
Finished Jul 11 06:53:24 PM PDT 24
Peak memory 242192 kb
Host smart-5e2e104c-3b80-46f2-90fb-b26ec550ed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895564868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.895564868
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2937791639
Short name T796
Test name
Test status
Simulation time 1210223273 ps
CPU time 26.88 seconds
Started Jul 11 06:52:57 PM PDT 24
Finished Jul 11 06:53:25 PM PDT 24
Peak memory 242420 kb
Host smart-ffe2e517-bd35-4209-99d2-116e2a0da2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937791639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2937791639
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.2412872304
Short name T171
Test name
Test status
Simulation time 328555370 ps
CPU time 4.45 seconds
Started Jul 11 06:52:51 PM PDT 24
Finished Jul 11 06:52:56 PM PDT 24
Peak memory 242012 kb
Host smart-8213bc7a-5589-4f83-bb4e-ba7ab083657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412872304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2412872304
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3852347295
Short name T968
Test name
Test status
Simulation time 384544095 ps
CPU time 4.07 seconds
Started Jul 11 06:52:59 PM PDT 24
Finished Jul 11 06:53:04 PM PDT 24
Peak memory 242280 kb
Host smart-0577b165-3091-42c8-9b0d-617e8db4b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852347295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3852347295
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3274150448
Short name T31
Test name
Test status
Simulation time 481503930 ps
CPU time 6.85 seconds
Started Jul 11 06:52:59 PM PDT 24
Finished Jul 11 06:53:07 PM PDT 24
Peak memory 241932 kb
Host smart-bfd909d8-95eb-4e36-aef4-94527a7d21a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274150448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3274150448
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.483870476
Short name T829
Test name
Test status
Simulation time 331971348 ps
CPU time 16.09 seconds
Started Jul 11 06:52:56 PM PDT 24
Finished Jul 11 06:53:13 PM PDT 24
Peak memory 241832 kb
Host smart-f62bd67f-12d0-4c75-8e45-69c3e5e9abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483870476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.483870476
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1814243353
Short name T428
Test name
Test status
Simulation time 688681468 ps
CPU time 10.17 seconds
Started Jul 11 06:52:57 PM PDT 24
Finished Jul 11 06:53:08 PM PDT 24
Peak memory 248744 kb
Host smart-52d04246-f684-4ce7-afd6-73434dc5d6eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814243353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1814243353
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1509769644
Short name T1152
Test name
Test status
Simulation time 378490256 ps
CPU time 7.94 seconds
Started Jul 11 06:53:00 PM PDT 24
Finished Jul 11 06:53:09 PM PDT 24
Peak memory 248752 kb
Host smart-07f861de-418c-482b-a2b1-6a577201c720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509769644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1509769644
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.993599958
Short name T861
Test name
Test status
Simulation time 608408353 ps
CPU time 7.66 seconds
Started Jul 11 06:52:49 PM PDT 24
Finished Jul 11 06:52:58 PM PDT 24
Peak memory 242156 kb
Host smart-590afe2d-fb40-487f-90c1-cbc8ad56f123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993599958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.993599958
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.3518224227
Short name T1015
Test name
Test status
Simulation time 6220410324 ps
CPU time 157.85 seconds
Started Jul 11 06:53:04 PM PDT 24
Finished Jul 11 06:55:43 PM PDT 24
Peak memory 257092 kb
Host smart-fd4d6286-d54a-4a0d-991a-74366e574616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518224227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
3518224227
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.632047148
Short name T288
Test name
Test status
Simulation time 2701667113 ps
CPU time 27.64 seconds
Started Jul 11 06:53:05 PM PDT 24
Finished Jul 11 06:53:34 PM PDT 24
Peak memory 242240 kb
Host smart-678c7c41-c26f-4bc5-b18f-518bae8dc534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632047148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.632047148
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.3583573697
Short name T565
Test name
Test status
Simulation time 168182032 ps
CPU time 2.25 seconds
Started Jul 11 06:58:06 PM PDT 24
Finished Jul 11 06:58:10 PM PDT 24
Peak memory 240108 kb
Host smart-ec66c58c-a7ab-46e2-8590-de4d68bd997f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583573697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3583573697
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.283150755
Short name T8
Test name
Test status
Simulation time 1433175120 ps
CPU time 26.38 seconds
Started Jul 11 06:58:01 PM PDT 24
Finished Jul 11 06:58:28 PM PDT 24
Peak memory 242360 kb
Host smart-2a02e4aa-c38c-4d55-880f-1024656f1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283150755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.283150755
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.3742785835
Short name T379
Test name
Test status
Simulation time 5844102408 ps
CPU time 63.63 seconds
Started Jul 11 06:57:57 PM PDT 24
Finished Jul 11 06:59:03 PM PDT 24
Peak memory 242304 kb
Host smart-e913e46b-2f3a-4f55-8ca1-bb9ff77b3204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742785835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3742785835
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.2668328033
Short name T139
Test name
Test status
Simulation time 182030999 ps
CPU time 3.44 seconds
Started Jul 11 06:57:57 PM PDT 24
Finished Jul 11 06:58:02 PM PDT 24
Peak memory 242088 kb
Host smart-daf83936-5e97-44b2-8080-2b89453a3b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668328033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2668328033
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.2568620487
Short name T562
Test name
Test status
Simulation time 801935739 ps
CPU time 11.94 seconds
Started Jul 11 06:58:01 PM PDT 24
Finished Jul 11 06:58:14 PM PDT 24
Peak memory 242508 kb
Host smart-1357ad3f-3688-4e03-9182-6363a53ff0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568620487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2568620487
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.2577759058
Short name T880
Test name
Test status
Simulation time 2164118513 ps
CPU time 3.87 seconds
Started Jul 11 06:58:02 PM PDT 24
Finished Jul 11 06:58:07 PM PDT 24
Peak memory 242280 kb
Host smart-4ed8e796-c146-497d-a73e-3e3c80dd948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577759058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2577759058
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3524630596
Short name T1182
Test name
Test status
Simulation time 565537990 ps
CPU time 17.89 seconds
Started Jul 11 06:57:57 PM PDT 24
Finished Jul 11 06:58:16 PM PDT 24
Peak memory 242360 kb
Host smart-5f4262f9-4306-4075-a4d5-21e57a429216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524630596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3524630596
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.2014462435
Short name T695
Test name
Test status
Simulation time 2532378169 ps
CPU time 9.85 seconds
Started Jul 11 06:57:57 PM PDT 24
Finished Jul 11 06:58:08 PM PDT 24
Peak memory 242568 kb
Host smart-828bbb70-f870-4f78-81cd-5a7e4b59292d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014462435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2014462435
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3227070563
Short name T1171
Test name
Test status
Simulation time 1011838491 ps
CPU time 8.43 seconds
Started Jul 11 06:58:02 PM PDT 24
Finished Jul 11 06:58:11 PM PDT 24
Peak memory 242400 kb
Host smart-195fa519-a2c8-4f92-9647-1f3b67d7b70a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227070563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3227070563
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.2694788421
Short name T1022
Test name
Test status
Simulation time 786524467 ps
CPU time 5.61 seconds
Started Jul 11 06:57:56 PM PDT 24
Finished Jul 11 06:58:03 PM PDT 24
Peak memory 248188 kb
Host smart-1447638f-5fdf-41d4-a19d-2a50728a1d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694788421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2694788421
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.599756830
Short name T975
Test name
Test status
Simulation time 186210696 ps
CPU time 5.47 seconds
Started Jul 11 06:58:06 PM PDT 24
Finished Jul 11 06:58:12 PM PDT 24
Peak memory 242188 kb
Host smart-8abcc7f2-3a59-4935-b7c6-a390665e521c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599756830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.
599756830
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2779375191
Short name T756
Test name
Test status
Simulation time 1086750908 ps
CPU time 19.74 seconds
Started Jul 11 06:58:00 PM PDT 24
Finished Jul 11 06:58:20 PM PDT 24
Peak memory 242184 kb
Host smart-fd36fde9-6d72-4b7d-9eb2-10e576e3296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779375191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2779375191
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.1896620872
Short name T625
Test name
Test status
Simulation time 46346842 ps
CPU time 1.69 seconds
Started Jul 11 06:58:09 PM PDT 24
Finished Jul 11 06:58:12 PM PDT 24
Peak memory 240048 kb
Host smart-1d2e41c3-ca26-465c-8e4f-fe0f802d9c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896620872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1896620872
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.2027713447
Short name T716
Test name
Test status
Simulation time 1116191403 ps
CPU time 24.41 seconds
Started Jul 11 06:58:07 PM PDT 24
Finished Jul 11 06:58:32 PM PDT 24
Peak memory 248732 kb
Host smart-c3fd16b6-dbee-4236-a08a-a2824b741eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027713447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2027713447
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.1595348728
Short name T336
Test name
Test status
Simulation time 229527488 ps
CPU time 8.78 seconds
Started Jul 11 06:58:05 PM PDT 24
Finished Jul 11 06:58:15 PM PDT 24
Peak memory 241784 kb
Host smart-f99cd8e6-93fa-4998-997c-7022978b1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595348728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1595348728
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.440227761
Short name T1117
Test name
Test status
Simulation time 1865361356 ps
CPU time 34.57 seconds
Started Jul 11 06:58:06 PM PDT 24
Finished Jul 11 06:58:42 PM PDT 24
Peak memory 242628 kb
Host smart-1352c267-040a-46c1-bc14-078f92742a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440227761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.440227761
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.1636671574
Short name T980
Test name
Test status
Simulation time 485786755 ps
CPU time 4.68 seconds
Started Jul 11 06:58:05 PM PDT 24
Finished Jul 11 06:58:11 PM PDT 24
Peak memory 242448 kb
Host smart-b53372e0-d328-479d-844d-fc784a6ff9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636671574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1636671574
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2771727677
Short name T1032
Test name
Test status
Simulation time 4555492230 ps
CPU time 29.58 seconds
Started Jul 11 06:58:07 PM PDT 24
Finished Jul 11 06:58:38 PM PDT 24
Peak memory 248872 kb
Host smart-fc000973-909e-4eb4-bc68-e872f151ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771727677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2771727677
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1995254980
Short name T1106
Test name
Test status
Simulation time 7225245555 ps
CPU time 12.7 seconds
Started Jul 11 06:58:09 PM PDT 24
Finished Jul 11 06:58:23 PM PDT 24
Peak memory 243372 kb
Host smart-c32024fd-e207-4c56-b9eb-1af4ac558ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995254980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1995254980
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3929339939
Short name T125
Test name
Test status
Simulation time 1019888620 ps
CPU time 12.8 seconds
Started Jul 11 06:58:06 PM PDT 24
Finished Jul 11 06:58:20 PM PDT 24
Peak memory 241888 kb
Host smart-9a3fcee7-2a26-44fc-98f7-4b1a3fd93cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929339939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3929339939
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1306082618
Short name T522
Test name
Test status
Simulation time 1431546623 ps
CPU time 25.9 seconds
Started Jul 11 06:58:06 PM PDT 24
Finished Jul 11 06:58:33 PM PDT 24
Peak memory 242196 kb
Host smart-2c6fd0a1-812a-4116-ac50-5befe6779f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306082618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1306082618
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.2441338883
Short name T1190
Test name
Test status
Simulation time 420000632 ps
CPU time 10.48 seconds
Started Jul 11 06:58:08 PM PDT 24
Finished Jul 11 06:58:19 PM PDT 24
Peak memory 242212 kb
Host smart-6e49eaa8-34c6-4313-a4b6-a064e8d18bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441338883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2441338883
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.2763974037
Short name T776
Test name
Test status
Simulation time 1097289219 ps
CPU time 8.66 seconds
Started Jul 11 06:58:04 PM PDT 24
Finished Jul 11 06:58:13 PM PDT 24
Peak memory 242392 kb
Host smart-48bcc347-2389-4f24-a878-c4f74f69714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763974037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2763974037
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.2353996881
Short name T929
Test name
Test status
Simulation time 13359895470 ps
CPU time 42.25 seconds
Started Jul 11 06:58:09 PM PDT 24
Finished Jul 11 06:58:53 PM PDT 24
Peak memory 243808 kb
Host smart-6e044d30-9252-49f4-9f59-72d07b8bcb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353996881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2353996881
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.3851703903
Short name T155
Test name
Test status
Simulation time 166487174 ps
CPU time 1.61 seconds
Started Jul 11 06:58:18 PM PDT 24
Finished Jul 11 06:58:20 PM PDT 24
Peak memory 240548 kb
Host smart-02f49c03-a5fc-422a-916e-c0be8ece81f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851703903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3851703903
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.128010380
Short name T972
Test name
Test status
Simulation time 10688677844 ps
CPU time 18.09 seconds
Started Jul 11 06:58:15 PM PDT 24
Finished Jul 11 06:58:33 PM PDT 24
Peak memory 248868 kb
Host smart-c0bce3f0-e7c9-4458-87cf-d1d8cc331aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128010380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.128010380
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.1235649887
Short name T672
Test name
Test status
Simulation time 972684246 ps
CPU time 27.48 seconds
Started Jul 11 06:58:15 PM PDT 24
Finished Jul 11 06:58:44 PM PDT 24
Peak memory 241896 kb
Host smart-781977a5-7875-4184-85ff-29d074f3cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235649887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1235649887
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.490307399
Short name T396
Test name
Test status
Simulation time 606668439 ps
CPU time 10.53 seconds
Started Jul 11 06:58:16 PM PDT 24
Finished Jul 11 06:58:27 PM PDT 24
Peak memory 242096 kb
Host smart-9507ec4f-0374-453c-aba0-5a877db91895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490307399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.490307399
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.4249448862
Short name T200
Test name
Test status
Simulation time 283474870 ps
CPU time 4.28 seconds
Started Jul 11 06:58:10 PM PDT 24
Finished Jul 11 06:58:16 PM PDT 24
Peak memory 242136 kb
Host smart-c0fa8aa6-bb98-4ae1-9ae2-52de59c1414c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249448862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4249448862
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.3728919961
Short name T844
Test name
Test status
Simulation time 441302762 ps
CPU time 5.07 seconds
Started Jul 11 06:58:13 PM PDT 24
Finished Jul 11 06:58:19 PM PDT 24
Peak memory 242524 kb
Host smart-9bf28b5c-6f21-43af-98dc-3345a336120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728919961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3728919961
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.705771043
Short name T911
Test name
Test status
Simulation time 1117444649 ps
CPU time 15.88 seconds
Started Jul 11 06:58:15 PM PDT 24
Finished Jul 11 06:58:31 PM PDT 24
Peak memory 241988 kb
Host smart-507299e1-bfdb-4a67-a027-a95d6462256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705771043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.705771043
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1139933154
Short name T228
Test name
Test status
Simulation time 622808111 ps
CPU time 10.22 seconds
Started Jul 11 06:58:13 PM PDT 24
Finished Jul 11 06:58:24 PM PDT 24
Peak memory 241784 kb
Host smart-cec38c43-99c0-487a-96e0-3832339d8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139933154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1139933154
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.400697484
Short name T700
Test name
Test status
Simulation time 401230185 ps
CPU time 12.45 seconds
Started Jul 11 06:58:13 PM PDT 24
Finished Jul 11 06:58:26 PM PDT 24
Peak memory 241892 kb
Host smart-b75b87e0-e1c1-4264-8740-f337d4d05383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400697484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.400697484
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3919345237
Short name T609
Test name
Test status
Simulation time 865935770 ps
CPU time 8.98 seconds
Started Jul 11 06:58:13 PM PDT 24
Finished Jul 11 06:58:23 PM PDT 24
Peak memory 242028 kb
Host smart-c5f690b9-8b7d-4504-ab9e-da18cc1c7383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919345237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3919345237
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.3887518805
Short name T418
Test name
Test status
Simulation time 486935982 ps
CPU time 9.84 seconds
Started Jul 11 06:58:10 PM PDT 24
Finished Jul 11 06:58:21 PM PDT 24
Peak memory 241900 kb
Host smart-e7578114-2ae9-4a40-a90c-5197af6c7766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887518805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3887518805
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2572249320
Short name T655
Test name
Test status
Simulation time 859587026 ps
CPU time 33.04 seconds
Started Jul 11 06:58:18 PM PDT 24
Finished Jul 11 06:58:52 PM PDT 24
Peak memory 243720 kb
Host smart-61f5d043-2015-404b-a662-12025b4f6376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572249320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2572249320
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2749609733
Short name T581
Test name
Test status
Simulation time 196169837074 ps
CPU time 2473.66 seconds
Started Jul 11 06:58:18 PM PDT 24
Finished Jul 11 07:39:33 PM PDT 24
Peak memory 281396 kb
Host smart-f2c9f3ed-2404-43e7-848f-c1e319681cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749609733 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2749609733
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3986511020
Short name T910
Test name
Test status
Simulation time 467093850 ps
CPU time 5.85 seconds
Started Jul 11 06:58:16 PM PDT 24
Finished Jul 11 06:58:22 PM PDT 24
Peak memory 242480 kb
Host smart-17c122b0-a3c8-4af7-a895-f98cd6d8560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986511020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3986511020
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.2857977684
Short name T1017
Test name
Test status
Simulation time 1880065404 ps
CPU time 32.65 seconds
Started Jul 11 06:58:21 PM PDT 24
Finished Jul 11 06:58:55 PM PDT 24
Peak memory 242316 kb
Host smart-72d92395-0717-4041-84de-c5e587b7cf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857977684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.2857977684
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3606392331
Short name T1021
Test name
Test status
Simulation time 1219147964 ps
CPU time 19.58 seconds
Started Jul 11 06:58:21 PM PDT 24
Finished Jul 11 06:58:41 PM PDT 24
Peak memory 242452 kb
Host smart-96292b7a-117b-47e5-ab4b-42a84ca5c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606392331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3606392331
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.472382363
Short name T986
Test name
Test status
Simulation time 11884557954 ps
CPU time 24.46 seconds
Started Jul 11 06:58:16 PM PDT 24
Finished Jul 11 06:58:41 PM PDT 24
Peak memory 242756 kb
Host smart-c1cfaec6-ea17-49e6-8f0c-4034b3dc699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472382363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.472382363
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.2270237001
Short name T587
Test name
Test status
Simulation time 243100446 ps
CPU time 3.27 seconds
Started Jul 11 06:58:17 PM PDT 24
Finished Jul 11 06:58:21 PM PDT 24
Peak memory 241860 kb
Host smart-e6367252-5768-412b-b3bc-fa2e247314b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270237001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2270237001
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2942352629
Short name T183
Test name
Test status
Simulation time 21314411160 ps
CPU time 43.08 seconds
Started Jul 11 06:58:21 PM PDT 24
Finished Jul 11 06:59:05 PM PDT 24
Peak memory 248832 kb
Host smart-cf74c42c-a361-4199-8776-f805c36f0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942352629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2942352629
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2286326192
Short name T1020
Test name
Test status
Simulation time 1157117800 ps
CPU time 33.66 seconds
Started Jul 11 06:58:21 PM PDT 24
Finished Jul 11 06:58:55 PM PDT 24
Peak memory 242140 kb
Host smart-08a54a92-7b37-4fbe-97ba-d4befc25aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286326192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2286326192
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3618883601
Short name T175
Test name
Test status
Simulation time 1486627198 ps
CPU time 23.35 seconds
Started Jul 11 06:58:17 PM PDT 24
Finished Jul 11 06:58:41 PM PDT 24
Peak memory 241764 kb
Host smart-80b1b31a-facf-4f5d-8cf6-6a46b73f9ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618883601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3618883601
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.1590066895
Short name T778
Test name
Test status
Simulation time 122527391 ps
CPU time 4.09 seconds
Started Jul 11 06:58:16 PM PDT 24
Finished Jul 11 06:58:21 PM PDT 24
Peak memory 242216 kb
Host smart-64a7da6e-900e-4935-a353-a5429e0d35fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590066895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1590066895
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2197573363
Short name T429
Test name
Test status
Simulation time 975365744 ps
CPU time 9.2 seconds
Started Jul 11 06:58:20 PM PDT 24
Finished Jul 11 06:58:30 PM PDT 24
Peak memory 242532 kb
Host smart-aec6e59c-de98-4dfa-8089-3348fa652580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197573363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2197573363
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.2388518185
Short name T1127
Test name
Test status
Simulation time 107663712 ps
CPU time 2.86 seconds
Started Jul 11 06:58:19 PM PDT 24
Finished Jul 11 06:58:22 PM PDT 24
Peak memory 242164 kb
Host smart-13b3b7ed-17d1-43b6-a685-fd47b812ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388518185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2388518185
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3434391440
Short name T381
Test name
Test status
Simulation time 44408597125 ps
CPU time 109.4 seconds
Started Jul 11 06:58:20 PM PDT 24
Finished Jul 11 07:00:10 PM PDT 24
Peak memory 244604 kb
Host smart-b3ffe010-8836-4a09-bc0f-416bd627c167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434391440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3434391440
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2690317459
Short name T338
Test name
Test status
Simulation time 690475746182 ps
CPU time 1235.55 seconds
Started Jul 11 06:58:21 PM PDT 24
Finished Jul 11 07:18:57 PM PDT 24
Peak memory 265256 kb
Host smart-a2a2b099-37da-47bf-9262-7752bc77ed10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690317459 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2690317459
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.234862925
Short name T650
Test name
Test status
Simulation time 1579267463 ps
CPU time 7.52 seconds
Started Jul 11 06:58:22 PM PDT 24
Finished Jul 11 06:58:31 PM PDT 24
Peak memory 242344 kb
Host smart-9f677db8-fdfe-445e-945f-817401e68af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234862925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.234862925
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3637084173
Short name T788
Test name
Test status
Simulation time 77118392 ps
CPU time 2.09 seconds
Started Jul 11 06:58:31 PM PDT 24
Finished Jul 11 06:58:34 PM PDT 24
Peak memory 240172 kb
Host smart-70870195-ad7f-4a81-9c5e-a1aabcdde2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637084173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3637084173
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3713119707
Short name T979
Test name
Test status
Simulation time 277855089 ps
CPU time 6.77 seconds
Started Jul 11 06:58:31 PM PDT 24
Finished Jul 11 06:58:39 PM PDT 24
Peak memory 242500 kb
Host smart-43474459-a1bd-449a-bf6c-fb1dc988b4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713119707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3713119707
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1773627048
Short name T461
Test name
Test status
Simulation time 1127956293 ps
CPU time 17.76 seconds
Started Jul 11 06:58:29 PM PDT 24
Finished Jul 11 06:58:47 PM PDT 24
Peak memory 242252 kb
Host smart-403a06e1-fb0e-4243-94bb-9ff2980abe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773627048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1773627048
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2212643299
Short name T680
Test name
Test status
Simulation time 519274012 ps
CPU time 6.25 seconds
Started Jul 11 06:58:24 PM PDT 24
Finished Jul 11 06:58:31 PM PDT 24
Peak memory 242408 kb
Host smart-8bd1653a-90bb-4258-b96a-db79101b100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212643299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2212643299
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.2065345820
Short name T717
Test name
Test status
Simulation time 418054711 ps
CPU time 4.74 seconds
Started Jul 11 06:58:25 PM PDT 24
Finished Jul 11 06:58:31 PM PDT 24
Peak memory 242160 kb
Host smart-8ab5abc3-38c8-4ce9-9dd0-5feca189c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065345820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2065345820
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.1267263124
Short name T341
Test name
Test status
Simulation time 2484473938 ps
CPU time 30.09 seconds
Started Jul 11 06:58:29 PM PDT 24
Finished Jul 11 06:59:00 PM PDT 24
Peak memory 248384 kb
Host smart-15986460-3fa3-47aa-b6d6-3bc6d82fa017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267263124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.1267263124
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.3777183162
Short name T177
Test name
Test status
Simulation time 977484920 ps
CPU time 15.65 seconds
Started Jul 11 06:58:29 PM PDT 24
Finished Jul 11 06:58:46 PM PDT 24
Peak memory 242332 kb
Host smart-e9b07a06-ebff-4661-89af-db7377b40a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777183162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3777183162
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.4290328634
Short name T479
Test name
Test status
Simulation time 595712081 ps
CPU time 5.3 seconds
Started Jul 11 06:58:27 PM PDT 24
Finished Jul 11 06:58:33 PM PDT 24
Peak memory 242320 kb
Host smart-f9b9243e-c7d8-4d38-b571-6e262d681655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290328634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.4290328634
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3242592126
Short name T360
Test name
Test status
Simulation time 339938605 ps
CPU time 6.21 seconds
Started Jul 11 06:58:29 PM PDT 24
Finished Jul 11 06:58:36 PM PDT 24
Peak memory 242120 kb
Host smart-9399d373-7e82-4b76-9514-6dea9b60ca0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242592126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3242592126
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1665957853
Short name T874
Test name
Test status
Simulation time 287565524 ps
CPU time 9.95 seconds
Started Jul 11 06:58:24 PM PDT 24
Finished Jul 11 06:58:34 PM PDT 24
Peak memory 242072 kb
Host smart-07f8bdac-c336-4fc2-9b88-4d4756b8f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665957853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1665957853
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3964795781
Short name T156
Test name
Test status
Simulation time 3387265235 ps
CPU time 81.23 seconds
Started Jul 11 06:58:31 PM PDT 24
Finished Jul 11 06:59:53 PM PDT 24
Peak memory 244008 kb
Host smart-e07aa667-1b8d-4a85-a749-0278322a9246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964795781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3964795781
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2891268421
Short name T539
Test name
Test status
Simulation time 194998496179 ps
CPU time 1558.94 seconds
Started Jul 11 06:58:29 PM PDT 24
Finished Jul 11 07:24:29 PM PDT 24
Peak memory 380912 kb
Host smart-fa8fc134-bf64-42fd-aef6-6eb6a37e2c9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891268421 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2891268421
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1281577975
Short name T1138
Test name
Test status
Simulation time 732393045 ps
CPU time 9.82 seconds
Started Jul 11 06:58:29 PM PDT 24
Finished Jul 11 06:58:40 PM PDT 24
Peak memory 242584 kb
Host smart-cfcaa3e9-fc87-4297-8b05-b224f66bb8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281577975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1281577975
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1889815006
Short name T838
Test name
Test status
Simulation time 72726912 ps
CPU time 1.89 seconds
Started Jul 11 06:58:37 PM PDT 24
Finished Jul 11 06:58:40 PM PDT 24
Peak memory 240112 kb
Host smart-d7b1f5ea-c229-48b6-a732-8696373e4a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889815006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1889815006
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1668071487
Short name T65
Test name
Test status
Simulation time 1256768745 ps
CPU time 9.84 seconds
Started Jul 11 06:58:33 PM PDT 24
Finished Jul 11 06:58:44 PM PDT 24
Peak memory 242416 kb
Host smart-c9d08911-c7ee-449d-93df-5d4775b11d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668071487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1668071487
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.1355471219
Short name T997
Test name
Test status
Simulation time 3923303405 ps
CPU time 32.56 seconds
Started Jul 11 06:58:34 PM PDT 24
Finished Jul 11 06:59:07 PM PDT 24
Peak memory 244240 kb
Host smart-26cfabf8-6afc-4007-90a0-2042346a1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355471219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1355471219
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.2404003074
Short name T526
Test name
Test status
Simulation time 399966362 ps
CPU time 6.38 seconds
Started Jul 11 06:58:32 PM PDT 24
Finished Jul 11 06:58:40 PM PDT 24
Peak memory 241972 kb
Host smart-bd834acd-717a-43df-b907-7a2ce70f75a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404003074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2404003074
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.3659266141
Short name T739
Test name
Test status
Simulation time 1894374508 ps
CPU time 26.43 seconds
Started Jul 11 06:58:33 PM PDT 24
Finished Jul 11 06:59:01 PM PDT 24
Peak memory 242832 kb
Host smart-e45ff393-b75a-4690-8162-59613d444d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659266141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3659266141
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.15746113
Short name T696
Test name
Test status
Simulation time 5302538978 ps
CPU time 43.06 seconds
Started Jul 11 06:58:33 PM PDT 24
Finished Jul 11 06:59:17 PM PDT 24
Peak memory 248860 kb
Host smart-3fd7602d-5a4c-49d8-bb75-410b2d47e384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15746113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.15746113
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.874905909
Short name T249
Test name
Test status
Simulation time 1536987622 ps
CPU time 5.62 seconds
Started Jul 11 06:58:33 PM PDT 24
Finished Jul 11 06:58:40 PM PDT 24
Peak memory 242008 kb
Host smart-4c6e699e-8467-494b-a2f1-e9870c8a013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874905909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.874905909
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.4255505735
Short name T706
Test name
Test status
Simulation time 413579929 ps
CPU time 10.58 seconds
Started Jul 11 06:58:34 PM PDT 24
Finished Jul 11 06:58:46 PM PDT 24
Peak memory 242228 kb
Host smart-ddeee2e8-8cc3-401c-ba66-84008dec7a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255505735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.4255505735
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.257561868
Short name T763
Test name
Test status
Simulation time 413342629 ps
CPU time 5.26 seconds
Started Jul 11 06:58:32 PM PDT 24
Finished Jul 11 06:58:39 PM PDT 24
Peak memory 241940 kb
Host smart-d5eb67b2-dcc5-46a4-b994-a27b4f976b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257561868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.257561868
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.923403167
Short name T523
Test name
Test status
Simulation time 3176471247 ps
CPU time 9.34 seconds
Started Jul 11 06:58:31 PM PDT 24
Finished Jul 11 06:58:41 PM PDT 24
Peak memory 242124 kb
Host smart-b7bb9bdf-8186-4ea3-8c51-d82de7ea990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923403167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.923403167
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2075149513
Short name T394
Test name
Test status
Simulation time 16956888034 ps
CPU time 96.28 seconds
Started Jul 11 06:58:40 PM PDT 24
Finished Jul 11 07:00:17 PM PDT 24
Peak memory 245884 kb
Host smart-d69e30aa-5c93-406b-9a20-92fbb521261a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075149513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2075149513
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1734966693
Short name T1004
Test name
Test status
Simulation time 53689823636 ps
CPU time 340.78 seconds
Started Jul 11 06:58:38 PM PDT 24
Finished Jul 11 07:04:19 PM PDT 24
Peak memory 281192 kb
Host smart-cc6a0452-9112-4131-b6ba-ad75879a9224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734966693 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1734966693
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.2321945922
Short name T507
Test name
Test status
Simulation time 1149449151 ps
CPU time 7.74 seconds
Started Jul 11 06:58:36 PM PDT 24
Finished Jul 11 06:58:45 PM PDT 24
Peak memory 248592 kb
Host smart-43e65d2b-5eec-492c-a1da-c83b6bf053a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321945922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2321945922
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.613036968
Short name T909
Test name
Test status
Simulation time 69588378 ps
CPU time 1.75 seconds
Started Jul 11 06:58:44 PM PDT 24
Finished Jul 11 06:58:46 PM PDT 24
Peak memory 240012 kb
Host smart-4f2d4f95-19c3-43f5-bfea-1d589b99b2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613036968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.613036968
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.3753207602
Short name T34
Test name
Test status
Simulation time 4129575187 ps
CPU time 9.38 seconds
Started Jul 11 06:58:44 PM PDT 24
Finished Jul 11 06:58:54 PM PDT 24
Peak memory 242848 kb
Host smart-17fe2812-4e1f-4c08-aaec-42fefbd0ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753207602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3753207602
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3642010204
Short name T617
Test name
Test status
Simulation time 859704247 ps
CPU time 23.74 seconds
Started Jul 11 06:58:41 PM PDT 24
Finished Jul 11 06:59:05 PM PDT 24
Peak memory 242448 kb
Host smart-2fc6c6e0-855f-4a53-9c46-1167e9fe79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642010204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3642010204
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2157540510
Short name T791
Test name
Test status
Simulation time 257869150 ps
CPU time 3.52 seconds
Started Jul 11 06:58:39 PM PDT 24
Finished Jul 11 06:58:43 PM PDT 24
Peak memory 242400 kb
Host smart-0b282e4c-488a-466b-b803-3e28ac44493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157540510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2157540510
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3046747457
Short name T1002
Test name
Test status
Simulation time 15022608725 ps
CPU time 25.96 seconds
Started Jul 11 06:58:40 PM PDT 24
Finished Jul 11 06:59:07 PM PDT 24
Peak memory 244620 kb
Host smart-85efda99-c8c7-4e0d-bb0f-7485714066a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046747457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3046747457
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1243069001
Short name T244
Test name
Test status
Simulation time 379762237 ps
CPU time 15.54 seconds
Started Jul 11 06:58:42 PM PDT 24
Finished Jul 11 06:58:58 PM PDT 24
Peak memory 248800 kb
Host smart-83b65d70-ea3d-49ce-ac6f-f8a2e7e8d9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243069001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1243069001
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.3360959743
Short name T1065
Test name
Test status
Simulation time 244551324 ps
CPU time 13.96 seconds
Started Jul 11 06:58:37 PM PDT 24
Finished Jul 11 06:58:52 PM PDT 24
Peak memory 242132 kb
Host smart-bc283dd7-9ad0-46bb-84af-24088b09f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360959743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3360959743
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3382224918
Short name T377
Test name
Test status
Simulation time 759440831 ps
CPU time 23.68 seconds
Started Jul 11 06:58:38 PM PDT 24
Finished Jul 11 06:59:03 PM PDT 24
Peak memory 248744 kb
Host smart-4441ee20-c111-49ca-9191-13c5811d4050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382224918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3382224918
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3279534324
Short name T466
Test name
Test status
Simulation time 641997054 ps
CPU time 5.41 seconds
Started Jul 11 06:58:38 PM PDT 24
Finished Jul 11 06:58:45 PM PDT 24
Peak memory 242608 kb
Host smart-5a782246-9458-420a-b24f-61f71feec64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279534324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3279534324
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2150817981
Short name T938
Test name
Test status
Simulation time 3214780445 ps
CPU time 12.01 seconds
Started Jul 11 06:58:41 PM PDT 24
Finished Jul 11 06:58:54 PM PDT 24
Peak memory 241844 kb
Host smart-36a432f6-6840-452e-a7a1-aca299e1b045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150817981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2150817981
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.667404689
Short name T718
Test name
Test status
Simulation time 39764008959 ps
CPU time 444.32 seconds
Started Jul 11 06:58:43 PM PDT 24
Finished Jul 11 07:06:08 PM PDT 24
Peak memory 257112 kb
Host smart-729d555d-ca72-4262-80ca-ef454fbb0a91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667404689 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.667404689
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.2769482485
Short name T1046
Test name
Test status
Simulation time 3553301308 ps
CPU time 33.4 seconds
Started Jul 11 06:58:43 PM PDT 24
Finished Jul 11 06:59:17 PM PDT 24
Peak memory 242968 kb
Host smart-174f285a-d6a0-4d24-b343-ab2296eb9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769482485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2769482485
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3082217020
Short name T648
Test name
Test status
Simulation time 83542882 ps
CPU time 2.04 seconds
Started Jul 11 06:58:52 PM PDT 24
Finished Jul 11 06:58:54 PM PDT 24
Peak memory 240764 kb
Host smart-cb3d9cf0-151e-4414-af6b-1596384c77a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082217020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3082217020
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.289132849
Short name T1047
Test name
Test status
Simulation time 1726469808 ps
CPU time 18.01 seconds
Started Jul 11 06:58:45 PM PDT 24
Finished Jul 11 06:59:04 PM PDT 24
Peak memory 242868 kb
Host smart-10151932-6742-40f9-836b-d033eafd03ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289132849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.289132849
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3994557010
Short name T212
Test name
Test status
Simulation time 270079312 ps
CPU time 15.43 seconds
Started Jul 11 06:58:48 PM PDT 24
Finished Jul 11 06:59:04 PM PDT 24
Peak memory 242192 kb
Host smart-dbfe3f6b-a202-46b1-a5c5-20289dea76ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994557010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3994557010
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3741587891
Short name T1052
Test name
Test status
Simulation time 1709644481 ps
CPU time 10.08 seconds
Started Jul 11 06:58:44 PM PDT 24
Finished Jul 11 06:58:55 PM PDT 24
Peak memory 248800 kb
Host smart-3a2701f8-25e9-471e-bc54-105e8496ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741587891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3741587891
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.1966494131
Short name T168
Test name
Test status
Simulation time 529162624 ps
CPU time 4.56 seconds
Started Jul 11 06:58:52 PM PDT 24
Finished Jul 11 06:58:57 PM PDT 24
Peak memory 242184 kb
Host smart-87224149-2d69-4e0f-a9c0-d09aa4c3ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966494131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.1966494131
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3309644151
Short name T187
Test name
Test status
Simulation time 2701439609 ps
CPU time 17.73 seconds
Started Jul 11 06:58:45 PM PDT 24
Finished Jul 11 06:59:03 PM PDT 24
Peak memory 242372 kb
Host smart-b72d3a20-1d81-4901-baa9-2fcae65f8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309644151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3309644151
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2510557001
Short name T794
Test name
Test status
Simulation time 908071351 ps
CPU time 7.07 seconds
Started Jul 11 06:58:49 PM PDT 24
Finished Jul 11 06:58:57 PM PDT 24
Peak memory 242632 kb
Host smart-1fadca37-bba8-404f-a02f-014f954eedba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510557001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2510557001
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.1432675590
Short name T470
Test name
Test status
Simulation time 842893574 ps
CPU time 5.99 seconds
Started Jul 11 06:58:48 PM PDT 24
Finished Jul 11 06:58:55 PM PDT 24
Peak memory 241800 kb
Host smart-cdbcd19d-6d54-442f-b88d-414530d6769f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432675590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1432675590
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1701261433
Short name T101
Test name
Test status
Simulation time 664825707 ps
CPU time 21.68 seconds
Started Jul 11 06:58:44 PM PDT 24
Finished Jul 11 06:59:07 PM PDT 24
Peak memory 242252 kb
Host smart-7c0da96f-848b-4123-9528-648471b65668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701261433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1701261433
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.1512276105
Short name T359
Test name
Test status
Simulation time 102184460 ps
CPU time 4.63 seconds
Started Jul 11 06:58:46 PM PDT 24
Finished Jul 11 06:58:52 PM PDT 24
Peak memory 241952 kb
Host smart-29c0db85-ea01-4741-982c-cdc75d4b1d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512276105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1512276105
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3786376558
Short name T863
Test name
Test status
Simulation time 1688899012 ps
CPU time 12.83 seconds
Started Jul 11 06:58:49 PM PDT 24
Finished Jul 11 06:59:02 PM PDT 24
Peak memory 242264 kb
Host smart-535bace4-d80b-4666-b401-0c47789fc438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786376558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3786376558
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.326406667
Short name T1042
Test name
Test status
Simulation time 599840674 ps
CPU time 18.53 seconds
Started Jul 11 06:58:47 PM PDT 24
Finished Jul 11 06:59:06 PM PDT 24
Peak memory 242616 kb
Host smart-1921ff56-c683-4aa5-bb0a-ac73c4fd74fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326406667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.
326406667
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1694737765
Short name T287
Test name
Test status
Simulation time 340032235900 ps
CPU time 1871.78 seconds
Started Jul 11 06:58:46 PM PDT 24
Finished Jul 11 07:29:59 PM PDT 24
Peak memory 651016 kb
Host smart-27910109-ddd2-4168-8510-51bd0ccc6f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694737765 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.1694737765
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.4167342251
Short name T93
Test name
Test status
Simulation time 1852297227 ps
CPU time 4.84 seconds
Started Jul 11 06:58:52 PM PDT 24
Finished Jul 11 06:58:58 PM PDT 24
Peak memory 242316 kb
Host smart-27fc0d95-99d7-46ea-8223-94e299f71b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167342251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4167342251
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.93371429
Short name T413
Test name
Test status
Simulation time 174544477 ps
CPU time 1.96 seconds
Started Jul 11 06:58:57 PM PDT 24
Finished Jul 11 06:59:00 PM PDT 24
Peak memory 240428 kb
Host smart-478a9df2-d3fc-4a36-94a8-312b71c1d039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93371429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.93371429
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1011271170
Short name T872
Test name
Test status
Simulation time 822941958 ps
CPU time 11.67 seconds
Started Jul 11 06:58:51 PM PDT 24
Finished Jul 11 06:59:03 PM PDT 24
Peak memory 242552 kb
Host smart-b429acad-ca2e-4091-9d38-1eda687b44ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011271170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1011271170
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2229340822
Short name T1143
Test name
Test status
Simulation time 1022394735 ps
CPU time 17.39 seconds
Started Jul 11 06:58:53 PM PDT 24
Finished Jul 11 06:59:11 PM PDT 24
Peak memory 242320 kb
Host smart-9ca609e5-335b-443b-912c-3d2641bafb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229340822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2229340822
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.719041817
Short name T984
Test name
Test status
Simulation time 8429295995 ps
CPU time 21.12 seconds
Started Jul 11 06:58:49 PM PDT 24
Finished Jul 11 06:59:11 PM PDT 24
Peak memory 242952 kb
Host smart-7b33f1ab-4a07-46d1-894c-91a820ceb64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719041817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.719041817
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1911214660
Short name T1040
Test name
Test status
Simulation time 2422894663 ps
CPU time 5.12 seconds
Started Jul 11 06:58:50 PM PDT 24
Finished Jul 11 06:58:56 PM PDT 24
Peak memory 241972 kb
Host smart-82713646-f2c9-4b6c-8b7a-79e5c69c25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911214660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1911214660
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.81483165
Short name T629
Test name
Test status
Simulation time 461495179 ps
CPU time 10.47 seconds
Started Jul 11 06:58:48 PM PDT 24
Finished Jul 11 06:59:00 PM PDT 24
Peak memory 242340 kb
Host smart-b7e64053-c23b-4ea1-acf1-c18a43d2489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81483165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.81483165
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.947324650
Short name T949
Test name
Test status
Simulation time 8943440477 ps
CPU time 29.07 seconds
Started Jul 11 06:58:55 PM PDT 24
Finished Jul 11 06:59:25 PM PDT 24
Peak memory 242144 kb
Host smart-8a72475a-332f-4304-afb7-3ac684be21dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947324650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.947324650
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2138192094
Short name T180
Test name
Test status
Simulation time 423372604 ps
CPU time 12.51 seconds
Started Jul 11 06:58:50 PM PDT 24
Finished Jul 11 06:59:03 PM PDT 24
Peak memory 241720 kb
Host smart-f6e3b7b0-fa6d-4872-a571-705c59c4489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138192094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2138192094
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.961783095
Short name T153
Test name
Test status
Simulation time 2847183292 ps
CPU time 23.05 seconds
Started Jul 11 06:58:50 PM PDT 24
Finished Jul 11 06:59:14 PM PDT 24
Peak memory 242312 kb
Host smart-5201f1f6-65a8-43c9-9584-c39d4f2fad55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961783095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.961783095
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.619622954
Short name T467
Test name
Test status
Simulation time 357696212 ps
CPU time 10.79 seconds
Started Jul 11 06:58:55 PM PDT 24
Finished Jul 11 06:59:06 PM PDT 24
Peak memory 242096 kb
Host smart-4b33daf4-42dc-4028-9a8c-3496b7649376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619622954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.619622954
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.2281859806
Short name T866
Test name
Test status
Simulation time 371317904 ps
CPU time 5.23 seconds
Started Jul 11 06:58:49 PM PDT 24
Finished Jul 11 06:58:55 PM PDT 24
Peak memory 242340 kb
Host smart-f409154f-2519-4840-bed1-ab0f09377a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281859806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.2281859806
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.547474846
Short name T258
Test name
Test status
Simulation time 69931281009 ps
CPU time 101.55 seconds
Started Jul 11 06:58:56 PM PDT 24
Finished Jul 11 07:00:38 PM PDT 24
Peak memory 249148 kb
Host smart-d767d9a8-8c11-40cc-92f5-ca68eeddcd13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547474846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
547474846
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.556503810
Short name T242
Test name
Test status
Simulation time 802487345118 ps
CPU time 2671.98 seconds
Started Jul 11 06:58:53 PM PDT 24
Finished Jul 11 07:43:26 PM PDT 24
Peak memory 337424 kb
Host smart-5ad72520-6d7f-49f4-960e-86ad219da8cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556503810 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.556503810
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1893844180
Short name T724
Test name
Test status
Simulation time 229492769 ps
CPU time 9.26 seconds
Started Jul 11 06:58:57 PM PDT 24
Finished Jul 11 06:59:07 PM PDT 24
Peak memory 242320 kb
Host smart-360f8e7d-9c05-43cb-992b-c04ebe58c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893844180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1893844180
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.4106597050
Short name T489
Test name
Test status
Simulation time 41618486 ps
CPU time 1.49 seconds
Started Jul 11 06:58:59 PM PDT 24
Finished Jul 11 06:59:01 PM PDT 24
Peak memory 240100 kb
Host smart-c665f50c-ccbd-4bbe-92b1-e1ab3af4e034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106597050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.4106597050
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3118341537
Short name T48
Test name
Test status
Simulation time 4427579565 ps
CPU time 49.66 seconds
Started Jul 11 06:58:57 PM PDT 24
Finished Jul 11 06:59:48 PM PDT 24
Peak memory 243188 kb
Host smart-da9ab716-833d-4779-a062-f5dacb714325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118341537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3118341537
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.1493406407
Short name T701
Test name
Test status
Simulation time 716652920 ps
CPU time 22.28 seconds
Started Jul 11 06:58:58 PM PDT 24
Finished Jul 11 06:59:22 PM PDT 24
Peak memory 241592 kb
Host smart-b9ec6b4f-c5ec-4a7f-994f-622ce7831988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493406407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1493406407
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.912871319
Short name T1063
Test name
Test status
Simulation time 14899997868 ps
CPU time 38.19 seconds
Started Jul 11 06:58:56 PM PDT 24
Finished Jul 11 06:59:35 PM PDT 24
Peak memory 243312 kb
Host smart-5adcc41a-fc31-40ef-b552-6a51025e43bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912871319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.912871319
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.70707065
Short name T1195
Test name
Test status
Simulation time 207282770 ps
CPU time 3.96 seconds
Started Jul 11 06:58:55 PM PDT 24
Finished Jul 11 06:59:00 PM PDT 24
Peak memory 242260 kb
Host smart-cab4876c-e55c-4fb8-9b58-c223d56a0a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70707065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.70707065
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.425165816
Short name T683
Test name
Test status
Simulation time 519122336 ps
CPU time 6.88 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 06:59:10 PM PDT 24
Peak memory 242232 kb
Host smart-aebccb32-861d-4d17-91cc-748ad7963a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425165816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.425165816
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.69544172
Short name T666
Test name
Test status
Simulation time 226063078 ps
CPU time 7.92 seconds
Started Jul 11 06:58:57 PM PDT 24
Finished Jul 11 06:59:06 PM PDT 24
Peak memory 242248 kb
Host smart-0f1b7dc9-bf0a-4378-bccc-06d5e7efbec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69544172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.69544172
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.1778932802
Short name T766
Test name
Test status
Simulation time 1905369075 ps
CPU time 7.07 seconds
Started Jul 11 06:58:55 PM PDT 24
Finished Jul 11 06:59:02 PM PDT 24
Peak memory 242320 kb
Host smart-1ba49948-9b66-42c0-add7-726eb5980617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778932802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.1778932802
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2103016801
Short name T1025
Test name
Test status
Simulation time 419980796 ps
CPU time 4.03 seconds
Started Jul 11 06:58:57 PM PDT 24
Finished Jul 11 06:59:01 PM PDT 24
Peak memory 241972 kb
Host smart-04b86c80-9f5f-4562-b3ac-a9f36ddb519c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103016801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2103016801
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2954800503
Short name T792
Test name
Test status
Simulation time 310164012 ps
CPU time 6.02 seconds
Started Jul 11 06:58:56 PM PDT 24
Finished Jul 11 06:59:02 PM PDT 24
Peak memory 241800 kb
Host smart-8c12cdc7-c592-4744-9f0a-a692787ac34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954800503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2954800503
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.238623697
Short name T560
Test name
Test status
Simulation time 20578483957 ps
CPU time 179.5 seconds
Started Jul 11 06:58:59 PM PDT 24
Finished Jul 11 07:01:59 PM PDT 24
Peak memory 266696 kb
Host smart-9bd76340-ae2c-41f2-b185-d2c933cb0ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238623697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.
238623697
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.512963848
Short name T327
Test name
Test status
Simulation time 98094622685 ps
CPU time 1494.95 seconds
Started Jul 11 06:58:58 PM PDT 24
Finished Jul 11 07:23:54 PM PDT 24
Peak memory 287400 kb
Host smart-cf55d4c5-da17-453e-a0ab-ae4b2f9a2d76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512963848 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.512963848
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1906860350
Short name T811
Test name
Test status
Simulation time 11908132565 ps
CPU time 25.33 seconds
Started Jul 11 06:58:57 PM PDT 24
Finished Jul 11 06:59:23 PM PDT 24
Peak memory 242456 kb
Host smart-8c107156-9c9e-4810-8cb8-69a539fdaad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906860350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1906860350
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1953962726
Short name T618
Test name
Test status
Simulation time 691437611 ps
CPU time 2.15 seconds
Started Jul 11 06:53:20 PM PDT 24
Finished Jul 11 06:53:23 PM PDT 24
Peak memory 240416 kb
Host smart-34bcafd8-a8a9-4571-bc65-0478bd3fdf98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953962726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1953962726
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.1920816388
Short name T533
Test name
Test status
Simulation time 1075568507 ps
CPU time 20.66 seconds
Started Jul 11 06:53:09 PM PDT 24
Finished Jul 11 06:53:31 PM PDT 24
Peak memory 241960 kb
Host smart-7be0bef5-8a01-4983-a3b1-882e3e0ae70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920816388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1920816388
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3821450177
Short name T593
Test name
Test status
Simulation time 1257178674 ps
CPU time 17.6 seconds
Started Jul 11 06:53:24 PM PDT 24
Finished Jul 11 06:53:42 PM PDT 24
Peak memory 248448 kb
Host smart-801ca224-872f-4f66-85b8-7c1ceaab8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821450177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3821450177
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.4094754077
Short name T843
Test name
Test status
Simulation time 3680017247 ps
CPU time 19.57 seconds
Started Jul 11 06:53:24 PM PDT 24
Finished Jul 11 06:53:44 PM PDT 24
Peak memory 242336 kb
Host smart-0feed7e2-ea07-476b-9512-f37aada0ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094754077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.4094754077
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.1164549981
Short name T1006
Test name
Test status
Simulation time 197810597 ps
CPU time 4.74 seconds
Started Jul 11 06:53:09 PM PDT 24
Finished Jul 11 06:53:14 PM PDT 24
Peak memory 242168 kb
Host smart-027c6812-9c70-4172-8ef4-f4d9b5f50553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164549981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1164549981
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.208926966
Short name T446
Test name
Test status
Simulation time 594071650 ps
CPU time 13.43 seconds
Started Jul 11 06:53:25 PM PDT 24
Finished Jul 11 06:53:40 PM PDT 24
Peak memory 242352 kb
Host smart-80211341-51a3-4716-baeb-adb998c6e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208926966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.208926966
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3254735836
Short name T1019
Test name
Test status
Simulation time 330736634 ps
CPU time 5.04 seconds
Started Jul 11 06:53:17 PM PDT 24
Finished Jul 11 06:53:23 PM PDT 24
Peak memory 242564 kb
Host smart-d6ff14af-578c-4b5f-b78f-8ae35d32802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254735836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3254735836
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.3701337856
Short name T1061
Test name
Test status
Simulation time 633095676 ps
CPU time 4.26 seconds
Started Jul 11 06:53:13 PM PDT 24
Finished Jul 11 06:53:18 PM PDT 24
Peak memory 242224 kb
Host smart-5b22f5e0-7f25-411d-a810-1376457d3dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701337856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3701337856
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.78756005
Short name T433
Test name
Test status
Simulation time 561694423 ps
CPU time 4.82 seconds
Started Jul 11 06:53:11 PM PDT 24
Finished Jul 11 06:53:17 PM PDT 24
Peak memory 242348 kb
Host smart-9771f0c9-c23f-4089-adc4-1f3650728f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78756005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.78756005
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.2971349063
Short name T870
Test name
Test status
Simulation time 200027356 ps
CPU time 6.62 seconds
Started Jul 11 06:53:14 PM PDT 24
Finished Jul 11 06:53:21 PM PDT 24
Peak memory 241988 kb
Host smart-752408ca-f2d5-4a2f-96d1-d73bcd0f8cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971349063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2971349063
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.38586743
Short name T698
Test name
Test status
Simulation time 1649016942 ps
CPU time 3.95 seconds
Started Jul 11 06:53:10 PM PDT 24
Finished Jul 11 06:53:15 PM PDT 24
Peak memory 242120 kb
Host smart-f29e5231-e602-4378-bcc5-5762f834c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38586743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.38586743
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.240913347
Short name T519
Test name
Test status
Simulation time 1122396269 ps
CPU time 2.16 seconds
Started Jul 11 06:53:25 PM PDT 24
Finished Jul 11 06:53:28 PM PDT 24
Peak memory 241172 kb
Host smart-56801b50-f0b9-4115-806d-3b30c64a585d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240913347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.240913347
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2752564722
Short name T254
Test name
Test status
Simulation time 408042514985 ps
CPU time 2497.39 seconds
Started Jul 11 06:53:15 PM PDT 24
Finished Jul 11 07:34:54 PM PDT 24
Peak memory 461952 kb
Host smart-e15c45c4-70fa-46b1-aec0-30b6ed9d5ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752564722 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.2752564722
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3439742284
Short name T847
Test name
Test status
Simulation time 16474989562 ps
CPU time 36.91 seconds
Started Jul 11 06:53:17 PM PDT 24
Finished Jul 11 06:53:55 PM PDT 24
Peak memory 243132 kb
Host smart-daebd36a-7c20-4beb-8bb7-12a110a75615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439742284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3439742284
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.3833649741
Short name T879
Test name
Test status
Simulation time 112275275 ps
CPU time 4.41 seconds
Started Jul 11 06:58:58 PM PDT 24
Finished Jul 11 06:59:04 PM PDT 24
Peak memory 242004 kb
Host smart-594f0dd2-8233-444e-89c9-d4340c396c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833649741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3833649741
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2917714226
Short name T495
Test name
Test status
Simulation time 474392906 ps
CPU time 19.41 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 06:59:23 PM PDT 24
Peak memory 241800 kb
Host smart-69909db0-6eef-47dc-9d2b-acc2b2ae4abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917714226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2917714226
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.3844483213
Short name T448
Test name
Test status
Simulation time 1525492055 ps
CPU time 4.74 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 06:59:08 PM PDT 24
Peak memory 241948 kb
Host smart-f0566221-9cca-4f52-990a-cb675ec90171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844483213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3844483213
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.3518401303
Short name T1005
Test name
Test status
Simulation time 501581141 ps
CPU time 6.75 seconds
Started Jul 11 06:59:01 PM PDT 24
Finished Jul 11 06:59:08 PM PDT 24
Peak memory 242224 kb
Host smart-faaaf3f2-0db1-4ede-9628-37897bd5e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518401303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3518401303
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3749229485
Short name T828
Test name
Test status
Simulation time 185426127 ps
CPU time 3.75 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 06:59:07 PM PDT 24
Peak memory 242128 kb
Host smart-ec129a26-771c-4ba8-b159-7036958ca82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749229485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3749229485
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.721565416
Short name T731
Test name
Test status
Simulation time 170323989 ps
CPU time 3.93 seconds
Started Jul 11 06:59:01 PM PDT 24
Finished Jul 11 06:59:06 PM PDT 24
Peak memory 241880 kb
Host smart-260ce878-bb78-43b4-80e5-507399a3ff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721565416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.721565416
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3667399898
Short name T643
Test name
Test status
Simulation time 2944073793 ps
CPU time 10.55 seconds
Started Jul 11 06:59:02 PM PDT 24
Finished Jul 11 06:59:14 PM PDT 24
Peak memory 241812 kb
Host smart-fdf50681-fe68-4aa0-816d-a7d77efff776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667399898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3667399898
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3102639267
Short name T324
Test name
Test status
Simulation time 693284462454 ps
CPU time 1449.3 seconds
Started Jul 11 06:59:07 PM PDT 24
Finished Jul 11 07:23:17 PM PDT 24
Peak memory 368152 kb
Host smart-e11754de-306f-46a6-957c-c1807c75cd44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102639267 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3102639267
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3080345697
Short name T436
Test name
Test status
Simulation time 455198660 ps
CPU time 5.26 seconds
Started Jul 11 06:59:07 PM PDT 24
Finished Jul 11 06:59:13 PM PDT 24
Peak memory 241920 kb
Host smart-cf1cbfd4-a802-4e99-9923-3790aab8202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080345697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3080345697
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.2585573391
Short name T512
Test name
Test status
Simulation time 268873685 ps
CPU time 6.6 seconds
Started Jul 11 06:59:11 PM PDT 24
Finished Jul 11 06:59:18 PM PDT 24
Peak memory 242560 kb
Host smart-4ec6a019-50e7-4914-b8f0-9e35142705ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585573391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2585573391
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.1146761477
Short name T671
Test name
Test status
Simulation time 14826919309 ps
CPU time 389.01 seconds
Started Jul 11 06:59:06 PM PDT 24
Finished Jul 11 07:05:36 PM PDT 24
Peak memory 257076 kb
Host smart-d288d1b6-4d73-4885-aac6-eccda3183eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146761477 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.1146761477
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2783292564
Short name T1191
Test name
Test status
Simulation time 169175858 ps
CPU time 4.1 seconds
Started Jul 11 06:59:07 PM PDT 24
Finished Jul 11 06:59:12 PM PDT 24
Peak memory 242368 kb
Host smart-3eb8751e-6f79-4737-9706-e4292c1ca6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783292564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2783292564
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3203504029
Short name T1016
Test name
Test status
Simulation time 2066520376 ps
CPU time 9.23 seconds
Started Jul 11 06:59:05 PM PDT 24
Finished Jul 11 06:59:14 PM PDT 24
Peak memory 241900 kb
Host smart-3e1accbc-93ff-484c-a7ab-b669e0c5c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203504029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3203504029
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.900214258
Short name T46
Test name
Test status
Simulation time 297753374 ps
CPU time 4.26 seconds
Started Jul 11 06:59:05 PM PDT 24
Finished Jul 11 06:59:11 PM PDT 24
Peak memory 242332 kb
Host smart-e7a7bb75-23bb-409b-8f66-79d95dafee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900214258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.900214258
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.1793858116
Short name T942
Test name
Test status
Simulation time 1591229771 ps
CPU time 20.62 seconds
Started Jul 11 06:59:06 PM PDT 24
Finished Jul 11 06:59:28 PM PDT 24
Peak memory 242200 kb
Host smart-c6b49f1f-1507-4bd9-95bb-f1e6350c5279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793858116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1793858116
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.4230068529
Short name T292
Test name
Test status
Simulation time 941177914807 ps
CPU time 2113.15 seconds
Started Jul 11 06:59:06 PM PDT 24
Finished Jul 11 07:34:20 PM PDT 24
Peak memory 278184 kb
Host smart-14d76acf-8bef-4085-9a42-a2fc16341097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230068529 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.4230068529
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.3372951230
Short name T858
Test name
Test status
Simulation time 218667150 ps
CPU time 4.74 seconds
Started Jul 11 06:59:11 PM PDT 24
Finished Jul 11 06:59:17 PM PDT 24
Peak memory 242296 kb
Host smart-2b4b9179-b8b4-4513-bc83-ad6cb52abad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372951230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3372951230
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1561294065
Short name T181
Test name
Test status
Simulation time 319390508 ps
CPU time 8.06 seconds
Started Jul 11 06:59:10 PM PDT 24
Finished Jul 11 06:59:20 PM PDT 24
Peak memory 242100 kb
Host smart-9c3b8433-edd9-46ae-b21f-28c03e07ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561294065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1561294065
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.515063024
Short name T851
Test name
Test status
Simulation time 1395251918286 ps
CPU time 1596.31 seconds
Started Jul 11 06:59:11 PM PDT 24
Finished Jul 11 07:25:49 PM PDT 24
Peak memory 293668 kb
Host smart-8be7f801-34f7-4dcd-9e92-ec21e0141395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515063024 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.515063024
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1844707061
Short name T174
Test name
Test status
Simulation time 177468183 ps
CPU time 7.74 seconds
Started Jul 11 06:59:09 PM PDT 24
Finished Jul 11 06:59:17 PM PDT 24
Peak memory 241840 kb
Host smart-15818eca-3123-4a5f-b83b-de323702c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844707061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1844707061
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.2119171952
Short name T425
Test name
Test status
Simulation time 141588184 ps
CPU time 4.22 seconds
Started Jul 11 06:59:10 PM PDT 24
Finished Jul 11 06:59:16 PM PDT 24
Peak memory 241864 kb
Host smart-c54c3d41-861d-457c-970f-651f642181ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119171952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2119171952
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1724630604
Short name T608
Test name
Test status
Simulation time 550408908916 ps
CPU time 970.57 seconds
Started Jul 11 06:59:12 PM PDT 24
Finished Jul 11 07:15:23 PM PDT 24
Peak memory 309560 kb
Host smart-a139c042-6807-4f26-af33-d4c9bbf2f7e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724630604 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1724630604
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1226946904
Short name T752
Test name
Test status
Simulation time 169683514 ps
CPU time 2.62 seconds
Started Jul 11 06:53:35 PM PDT 24
Finished Jul 11 06:53:38 PM PDT 24
Peak memory 240408 kb
Host smart-029b94c1-4ca6-4bcd-990e-df03cba0ba42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226946904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1226946904
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.216929221
Short name T1093
Test name
Test status
Simulation time 2784391964 ps
CPU time 27.93 seconds
Started Jul 11 06:53:24 PM PDT 24
Finished Jul 11 06:53:53 PM PDT 24
Peak memory 242336 kb
Host smart-a98a53e4-8800-4392-8e5c-4d7c2955806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216929221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.216929221
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.3438369795
Short name T532
Test name
Test status
Simulation time 274258489 ps
CPU time 8.41 seconds
Started Jul 11 06:53:29 PM PDT 24
Finished Jul 11 06:53:38 PM PDT 24
Peak memory 248764 kb
Host smart-6aa7c842-0721-466d-aa92-15e2002afdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438369795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3438369795
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1689414077
Short name T916
Test name
Test status
Simulation time 757586494 ps
CPU time 10.47 seconds
Started Jul 11 06:53:24 PM PDT 24
Finished Jul 11 06:53:35 PM PDT 24
Peak memory 241924 kb
Host smart-62258aa8-de6b-4de9-b801-67ae3ccfe335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689414077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1689414077
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.1236447998
Short name T728
Test name
Test status
Simulation time 1564921739 ps
CPU time 23.47 seconds
Started Jul 11 06:53:25 PM PDT 24
Finished Jul 11 06:53:49 PM PDT 24
Peak memory 242452 kb
Host smart-023ad2cc-a794-4b46-a317-ec013ed26590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236447998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1236447998
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1321865837
Short name T13
Test name
Test status
Simulation time 112136336 ps
CPU time 3.39 seconds
Started Jul 11 06:53:24 PM PDT 24
Finished Jul 11 06:53:28 PM PDT 24
Peak memory 242032 kb
Host smart-6d0077f6-309f-4bf9-849c-d8055f245aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321865837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1321865837
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2413637047
Short name T941
Test name
Test status
Simulation time 948014767 ps
CPU time 25.89 seconds
Started Jul 11 06:53:30 PM PDT 24
Finished Jul 11 06:53:56 PM PDT 24
Peak memory 243924 kb
Host smart-11498678-2751-41e6-98d6-332abb209628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413637047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2413637047
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.552432605
Short name T708
Test name
Test status
Simulation time 1674061267 ps
CPU time 41.71 seconds
Started Jul 11 06:53:33 PM PDT 24
Finished Jul 11 06:54:16 PM PDT 24
Peak memory 242840 kb
Host smart-a068926a-0937-4b5a-9204-1fea9069b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552432605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.552432605
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.3201421533
Short name T120
Test name
Test status
Simulation time 761517758 ps
CPU time 12.68 seconds
Started Jul 11 06:53:26 PM PDT 24
Finished Jul 11 06:53:39 PM PDT 24
Peak memory 241884 kb
Host smart-4d996d32-7811-4d3d-b012-cca6a082804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201421533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3201421533
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.2777590936
Short name T450
Test name
Test status
Simulation time 756346526 ps
CPU time 8.41 seconds
Started Jul 11 06:53:25 PM PDT 24
Finished Jul 11 06:53:34 PM PDT 24
Peak memory 241848 kb
Host smart-c1144b50-1a2b-4338-8289-f195d55f638e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777590936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2777590936
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1799950555
Short name T361
Test name
Test status
Simulation time 157855273 ps
CPU time 4 seconds
Started Jul 11 06:53:35 PM PDT 24
Finished Jul 11 06:53:40 PM PDT 24
Peak memory 241956 kb
Host smart-951186bf-9220-4ff8-aac6-930ca3cbf691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799950555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1799950555
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2262397538
Short name T837
Test name
Test status
Simulation time 685786380 ps
CPU time 9.09 seconds
Started Jul 11 06:53:25 PM PDT 24
Finished Jul 11 06:53:35 PM PDT 24
Peak memory 242092 kb
Host smart-2475cc4c-4f80-4a19-9d7f-545079bfd9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262397538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2262397538
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.316082988
Short name T632
Test name
Test status
Simulation time 1241426181 ps
CPU time 26.58 seconds
Started Jul 11 06:53:34 PM PDT 24
Finished Jul 11 06:54:01 PM PDT 24
Peak memory 242696 kb
Host smart-9891b648-f05d-4fa2-ab7e-e49ebeef7826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316082988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.316082988
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.904244782
Short name T575
Test name
Test status
Simulation time 9858745351 ps
CPU time 56.43 seconds
Started Jul 11 06:53:33 PM PDT 24
Finished Jul 11 06:54:30 PM PDT 24
Peak memory 243040 kb
Host smart-95174b6e-d082-4b0e-9981-f10fc1f6a39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904244782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.904244782
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.3329276372
Short name T1166
Test name
Test status
Simulation time 326251624 ps
CPU time 4.51 seconds
Started Jul 11 06:59:14 PM PDT 24
Finished Jul 11 06:59:20 PM PDT 24
Peak memory 242036 kb
Host smart-c9a0ad3c-d44a-400b-941d-c5e3c18af822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329276372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3329276372
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.3233350934
Short name T1158
Test name
Test status
Simulation time 141223878 ps
CPU time 6.18 seconds
Started Jul 11 06:59:18 PM PDT 24
Finished Jul 11 06:59:26 PM PDT 24
Peak memory 242368 kb
Host smart-b42ed1a2-7e2f-4792-8b2d-9dfc7d1dc5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233350934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.3233350934
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3862515463
Short name T342
Test name
Test status
Simulation time 61916132811 ps
CPU time 748.45 seconds
Started Jul 11 06:59:16 PM PDT 24
Finished Jul 11 07:11:45 PM PDT 24
Peak memory 249616 kb
Host smart-9d017706-d32b-437b-b7e0-e4165862c1f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862515463 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3862515463
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2460815508
Short name T543
Test name
Test status
Simulation time 135284715 ps
CPU time 3.89 seconds
Started Jul 11 06:59:16 PM PDT 24
Finished Jul 11 06:59:21 PM PDT 24
Peak memory 242004 kb
Host smart-0a4ba02b-e342-4143-a10f-0faf86ca9260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460815508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2460815508
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.1414038181
Short name T712
Test name
Test status
Simulation time 1403531805 ps
CPU time 4.52 seconds
Started Jul 11 06:59:20 PM PDT 24
Finished Jul 11 06:59:26 PM PDT 24
Peak memory 241692 kb
Host smart-e418c8af-83ef-4cf6-a0ea-f79df949135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414038181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1414038181
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1197465872
Short name T738
Test name
Test status
Simulation time 194522831807 ps
CPU time 1154.65 seconds
Started Jul 11 06:59:15 PM PDT 24
Finished Jul 11 07:18:31 PM PDT 24
Peak memory 362940 kb
Host smart-413fac37-742f-4c4f-853e-fab03a62d027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197465872 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.1197465872
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2037256512
Short name T3
Test name
Test status
Simulation time 144007118 ps
CPU time 4.62 seconds
Started Jul 11 06:59:16 PM PDT 24
Finished Jul 11 06:59:22 PM PDT 24
Peak memory 242348 kb
Host smart-b7c0bde7-6188-48af-ad59-0371ffcd7936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037256512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2037256512
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.901041116
Short name T737
Test name
Test status
Simulation time 579513456 ps
CPU time 17.87 seconds
Started Jul 11 06:59:14 PM PDT 24
Finished Jul 11 06:59:33 PM PDT 24
Peak memory 241920 kb
Host smart-7b63cbba-5b74-430e-b2d2-f89d3bd5cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901041116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.901041116
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.640603104
Short name T853
Test name
Test status
Simulation time 214524218 ps
CPU time 4.18 seconds
Started Jul 11 06:59:21 PM PDT 24
Finished Jul 11 06:59:27 PM PDT 24
Peak memory 241988 kb
Host smart-5165d837-c007-4c05-a6d9-f4c67206833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640603104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.640603104
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.117440390
Short name T1149
Test name
Test status
Simulation time 113373205 ps
CPU time 4.5 seconds
Started Jul 11 06:59:20 PM PDT 24
Finished Jul 11 06:59:27 PM PDT 24
Peak memory 241808 kb
Host smart-f8171756-c6f4-47c7-8a45-dda3ebca91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117440390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.117440390
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.3589825888
Short name T293
Test name
Test status
Simulation time 204629705408 ps
CPU time 1995.78 seconds
Started Jul 11 06:59:16 PM PDT 24
Finished Jul 11 07:32:33 PM PDT 24
Peak memory 278276 kb
Host smart-7f7a1568-c447-4d9c-81e3-087e84d05083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589825888 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.3589825888
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1978055298
Short name T814
Test name
Test status
Simulation time 238691146 ps
CPU time 4.65 seconds
Started Jul 11 06:59:18 PM PDT 24
Finished Jul 11 06:59:24 PM PDT 24
Peak memory 242048 kb
Host smart-8b122bb7-ad6b-475f-bcc0-ae715ab7e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978055298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1978055298
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2871960847
Short name T709
Test name
Test status
Simulation time 864044331 ps
CPU time 12.17 seconds
Started Jul 11 06:59:14 PM PDT 24
Finished Jul 11 06:59:27 PM PDT 24
Peak memory 242224 kb
Host smart-c802df3d-a2ab-45ef-b326-928147eaacb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871960847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2871960847
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.302425967
Short name T19
Test name
Test status
Simulation time 415910835236 ps
CPU time 1412.92 seconds
Started Jul 11 06:59:20 PM PDT 24
Finished Jul 11 07:22:55 PM PDT 24
Peak memory 354612 kb
Host smart-994a884a-ea24-4232-bab9-4d238bcd0531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302425967 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.302425967
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1446842078
Short name T165
Test name
Test status
Simulation time 348267087 ps
CPU time 5.18 seconds
Started Jul 11 06:59:18 PM PDT 24
Finished Jul 11 06:59:24 PM PDT 24
Peak memory 241960 kb
Host smart-938cf05d-d502-440d-9a93-d10322bc69f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446842078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1446842078
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.808605382
Short name T225
Test name
Test status
Simulation time 4396756226 ps
CPU time 8.34 seconds
Started Jul 11 06:59:19 PM PDT 24
Finished Jul 11 06:59:28 PM PDT 24
Peak memory 242016 kb
Host smart-38cf313a-e031-490f-b788-3df8a929444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808605382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.808605382
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.301241622
Short name T232
Test name
Test status
Simulation time 998004127006 ps
CPU time 2179.52 seconds
Started Jul 11 06:59:18 PM PDT 24
Finished Jul 11 07:35:39 PM PDT 24
Peak memory 658156 kb
Host smart-6e3cfa71-f306-4269-96e5-52a8d8b4ba16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301241622 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.301241622
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.1864995355
Short name T52
Test name
Test status
Simulation time 250582635 ps
CPU time 5.07 seconds
Started Jul 11 06:59:19 PM PDT 24
Finished Jul 11 06:59:25 PM PDT 24
Peak memory 241876 kb
Host smart-067f995d-e912-4dad-b9f6-bb85d9a0109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864995355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1864995355
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3206151336
Short name T585
Test name
Test status
Simulation time 357052172 ps
CPU time 9.77 seconds
Started Jul 11 06:59:20 PM PDT 24
Finished Jul 11 06:59:32 PM PDT 24
Peak memory 241748 kb
Host smart-296cb1d1-579d-4f47-b9dc-7de4d1610296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206151336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3206151336
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.2830743389
Short name T6
Test name
Test status
Simulation time 31830803836 ps
CPU time 459.12 seconds
Started Jul 11 06:59:18 PM PDT 24
Finished Jul 11 07:06:59 PM PDT 24
Peak memory 257144 kb
Host smart-b32372f3-f0d7-49f8-9dff-922c07ec608d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830743389 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.2830743389
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.4146851365
Short name T1098
Test name
Test status
Simulation time 323577494 ps
CPU time 3.32 seconds
Started Jul 11 06:59:19 PM PDT 24
Finished Jul 11 06:59:24 PM PDT 24
Peak memory 241940 kb
Host smart-106fd874-cb3e-4c86-b70c-786a76abd625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146851365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.4146851365
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.488065989
Short name T224
Test name
Test status
Simulation time 65373079256 ps
CPU time 853.84 seconds
Started Jul 11 06:59:19 PM PDT 24
Finished Jul 11 07:13:34 PM PDT 24
Peak memory 280368 kb
Host smart-9f16179a-3fad-4f15-9617-1f9c10e45a19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488065989 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.488065989
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3742483927
Short name T545
Test name
Test status
Simulation time 2734961860 ps
CPU time 7.02 seconds
Started Jul 11 06:59:16 PM PDT 24
Finished Jul 11 06:59:25 PM PDT 24
Peak memory 242136 kb
Host smart-65c2cbc1-fcfb-4075-b5c4-d46ec6ec9aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742483927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3742483927
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.2088758416
Short name T967
Test name
Test status
Simulation time 303433812 ps
CPU time 17.78 seconds
Started Jul 11 06:59:23 PM PDT 24
Finished Jul 11 06:59:42 PM PDT 24
Peak memory 241956 kb
Host smart-c17e28a9-9563-4747-8381-c020f044e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088758416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.2088758416
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1986978512
Short name T1123
Test name
Test status
Simulation time 127138448638 ps
CPU time 2274.55 seconds
Started Jul 11 06:59:21 PM PDT 24
Finished Jul 11 07:37:18 PM PDT 24
Peak memory 328140 kb
Host smart-0f0bbf09-b177-4a3d-a61c-bae42bc541da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986978512 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.1986978512
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.2772481176
Short name T1167
Test name
Test status
Simulation time 638418459 ps
CPU time 5.06 seconds
Started Jul 11 06:59:22 PM PDT 24
Finished Jul 11 06:59:29 PM PDT 24
Peak memory 242076 kb
Host smart-19bf704f-7ff0-4358-ab25-81e67e7528ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772481176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2772481176
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.16045697
Short name T134
Test name
Test status
Simulation time 508177712 ps
CPU time 4.04 seconds
Started Jul 11 06:59:22 PM PDT 24
Finished Jul 11 06:59:28 PM PDT 24
Peak memory 241884 kb
Host smart-46dbc124-c6a6-422c-ae25-5927c3505c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16045697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.16045697
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3630808317
Short name T291
Test name
Test status
Simulation time 629713125997 ps
CPU time 1503.3 seconds
Started Jul 11 06:59:22 PM PDT 24
Finished Jul 11 07:24:27 PM PDT 24
Peak memory 257196 kb
Host smart-c46a5698-de37-4cb9-86e7-b7615d818639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630808317 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3630808317
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.858602866
Short name T943
Test name
Test status
Simulation time 155198281 ps
CPU time 2.41 seconds
Started Jul 11 06:53:51 PM PDT 24
Finished Jul 11 06:53:54 PM PDT 24
Peak memory 240168 kb
Host smart-3c14d47e-856a-40f6-8e17-debd29db3b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858602866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.858602866
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.1026916865
Short name T852
Test name
Test status
Simulation time 8279749077 ps
CPU time 10.61 seconds
Started Jul 11 06:53:39 PM PDT 24
Finished Jul 11 06:53:50 PM PDT 24
Peak memory 243128 kb
Host smart-204bf349-5cf4-402b-99dd-8e0201aa8b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026916865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1026916865
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.3408435751
Short name T710
Test name
Test status
Simulation time 3831597325 ps
CPU time 10.71 seconds
Started Jul 11 06:53:41 PM PDT 24
Finished Jul 11 06:53:53 PM PDT 24
Peak memory 242320 kb
Host smart-330b0188-404c-4c07-8d89-9aa025f3f679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408435751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3408435751
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2962585421
Short name T923
Test name
Test status
Simulation time 8415185739 ps
CPU time 18.64 seconds
Started Jul 11 06:53:41 PM PDT 24
Finished Jul 11 06:54:01 PM PDT 24
Peak memory 242260 kb
Host smart-c3b69e8d-30f2-4807-89fb-d46488740040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962585421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2962585421
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.2981278779
Short name T960
Test name
Test status
Simulation time 1914171793 ps
CPU time 34.42 seconds
Started Jul 11 06:53:41 PM PDT 24
Finished Jul 11 06:54:17 PM PDT 24
Peak memory 242232 kb
Host smart-1da678dd-6458-4ec3-a96e-e28194022423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981278779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2981278779
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.184213358
Short name T690
Test name
Test status
Simulation time 139808798 ps
CPU time 3.6 seconds
Started Jul 11 06:53:39 PM PDT 24
Finished Jul 11 06:53:43 PM PDT 24
Peak memory 242404 kb
Host smart-03411abf-4ce3-4af8-ae2b-0b9f324e3a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184213358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.184213358
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.823669879
Short name T812
Test name
Test status
Simulation time 1127494306 ps
CPU time 7.87 seconds
Started Jul 11 06:53:46 PM PDT 24
Finished Jul 11 06:53:55 PM PDT 24
Peak memory 248808 kb
Host smart-438000a8-ff6c-4cf3-8aa9-15173dc72d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823669879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.823669879
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3975455070
Short name T743
Test name
Test status
Simulation time 238403547 ps
CPU time 6.46 seconds
Started Jul 11 06:53:40 PM PDT 24
Finished Jul 11 06:53:47 PM PDT 24
Peak memory 241796 kb
Host smart-b2e3ce8d-51d6-4070-a613-de032ac1ebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975455070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3975455070
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.709145702
Short name T193
Test name
Test status
Simulation time 762860352 ps
CPU time 22.55 seconds
Started Jul 11 06:53:38 PM PDT 24
Finished Jul 11 06:54:01 PM PDT 24
Peak memory 248728 kb
Host smart-28cf07a6-b553-4d0c-964b-ba31612f7792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709145702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.709145702
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.3752449786
Short name T355
Test name
Test status
Simulation time 316280674 ps
CPU time 8.87 seconds
Started Jul 11 06:53:50 PM PDT 24
Finished Jul 11 06:54:00 PM PDT 24
Peak memory 242012 kb
Host smart-3c0348de-9981-4410-bf5a-a346a0e19eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752449786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3752449786
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2253153151
Short name T520
Test name
Test status
Simulation time 282519079 ps
CPU time 6.69 seconds
Started Jul 11 06:53:39 PM PDT 24
Finished Jul 11 06:53:47 PM PDT 24
Peak memory 242148 kb
Host smart-03815bf8-9c7a-4013-9b3a-60cebab5415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253153151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2253153151
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.4215812617
Short name T1092
Test name
Test status
Simulation time 2197734260 ps
CPU time 59.33 seconds
Started Jul 11 06:53:45 PM PDT 24
Finished Jul 11 06:54:45 PM PDT 24
Peak memory 244232 kb
Host smart-727eef48-86e6-4caf-ae96-7a135e689355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215812617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
4215812617
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3064880541
Short name T282
Test name
Test status
Simulation time 52601189621 ps
CPU time 1176.36 seconds
Started Jul 11 06:53:46 PM PDT 24
Finished Jul 11 07:13:23 PM PDT 24
Peak memory 262508 kb
Host smart-1c15b180-2ba9-45f0-9022-7a1e2e41f434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064880541 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3064880541
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2012274384
Short name T151
Test name
Test status
Simulation time 604573219 ps
CPU time 11.53 seconds
Started Jul 11 06:53:45 PM PDT 24
Finished Jul 11 06:53:58 PM PDT 24
Peak memory 241928 kb
Host smart-9218bc50-9335-4ada-b5cc-fbe3463f8910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012274384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2012274384
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.4243842172
Short name T516
Test name
Test status
Simulation time 197791272 ps
CPU time 3.86 seconds
Started Jul 11 06:59:28 PM PDT 24
Finished Jul 11 06:59:32 PM PDT 24
Peak memory 241928 kb
Host smart-1c59c018-4835-46c7-9e24-ec50af0d7229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243842172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.4243842172
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2718805615
Short name T108
Test name
Test status
Simulation time 7600819703 ps
CPU time 17.89 seconds
Started Jul 11 06:59:26 PM PDT 24
Finished Jul 11 06:59:44 PM PDT 24
Peak memory 242176 kb
Host smart-62bb8acb-68b9-4dfb-b31e-6aadf86b08dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718805615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2718805615
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.383082289
Short name T233
Test name
Test status
Simulation time 43670494082 ps
CPU time 584.43 seconds
Started Jul 11 07:00:34 PM PDT 24
Finished Jul 11 07:10:20 PM PDT 24
Peak memory 281296 kb
Host smart-25b4034d-378b-423d-bf32-b2cc6ff87437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383082289 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.383082289
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.3628521535
Short name T69
Test name
Test status
Simulation time 130842747 ps
CPU time 4.99 seconds
Started Jul 11 06:59:26 PM PDT 24
Finished Jul 11 06:59:32 PM PDT 24
Peak memory 241940 kb
Host smart-5b6d2d2f-36b7-43c8-b469-3e9d4afda1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628521535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3628521535
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.1800926602
Short name T88
Test name
Test status
Simulation time 329005670 ps
CPU time 2.93 seconds
Started Jul 11 06:59:25 PM PDT 24
Finished Jul 11 06:59:29 PM PDT 24
Peak memory 242360 kb
Host smart-8ab2e445-edd2-416e-b04f-385e928163b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800926602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1800926602
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3956844666
Short name T963
Test name
Test status
Simulation time 132416221 ps
CPU time 3.69 seconds
Started Jul 11 06:59:27 PM PDT 24
Finished Jul 11 06:59:31 PM PDT 24
Peak memory 241920 kb
Host smart-935daf09-3c33-47e5-838e-ac22fd429118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956844666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3956844666
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.892537176
Short name T439
Test name
Test status
Simulation time 98464553 ps
CPU time 3.5 seconds
Started Jul 11 06:59:28 PM PDT 24
Finished Jul 11 06:59:32 PM PDT 24
Peak memory 241980 kb
Host smart-206c5261-65d0-4697-9fa2-03d87083c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892537176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.892537176
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1978174994
Short name T240
Test name
Test status
Simulation time 693558328 ps
CPU time 5.21 seconds
Started Jul 11 06:59:26 PM PDT 24
Finished Jul 11 06:59:32 PM PDT 24
Peak memory 242032 kb
Host smart-2f864c09-8ed2-4bfa-b65e-35b7148758dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978174994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1978174994
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.1902447826
Short name T678
Test name
Test status
Simulation time 9368105144 ps
CPU time 22.26 seconds
Started Jul 11 06:59:31 PM PDT 24
Finished Jul 11 06:59:54 PM PDT 24
Peak memory 242244 kb
Host smart-55926933-754e-4b92-9e47-373e68217890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902447826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1902447826
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.994261027
Short name T597
Test name
Test status
Simulation time 970002008844 ps
CPU time 3181.61 seconds
Started Jul 11 06:59:30 PM PDT 24
Finished Jul 11 07:52:33 PM PDT 24
Peak memory 350852 kb
Host smart-4bab98fd-aef1-46b4-a6cd-76640ed1dd9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994261027 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.994261027
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.3785470730
Short name T206
Test name
Test status
Simulation time 203597514 ps
CPU time 4.47 seconds
Started Jul 11 06:59:31 PM PDT 24
Finished Jul 11 06:59:37 PM PDT 24
Peak memory 242064 kb
Host smart-c86f8a6b-5585-4b56-aad4-99bb5a589a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785470730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3785470730
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.2788053181
Short name T652
Test name
Test status
Simulation time 245430221 ps
CPU time 6.43 seconds
Started Jul 11 06:59:33 PM PDT 24
Finished Jul 11 06:59:40 PM PDT 24
Peak memory 241792 kb
Host smart-268caae6-5b46-44ec-bc7b-0038884c0bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788053181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2788053181
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.1799994263
Short name T167
Test name
Test status
Simulation time 174063709 ps
CPU time 4.14 seconds
Started Jul 11 06:59:31 PM PDT 24
Finished Jul 11 06:59:37 PM PDT 24
Peak memory 242004 kb
Host smart-e4b27a9a-f305-4f79-9217-4b53bef2caf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799994263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1799994263
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.3590745892
Short name T1062
Test name
Test status
Simulation time 1555272528 ps
CPU time 4.04 seconds
Started Jul 11 06:59:30 PM PDT 24
Finished Jul 11 06:59:34 PM PDT 24
Peak memory 241800 kb
Host smart-233bbdfb-8e2c-4aa9-84c5-0819dbceea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590745892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3590745892
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.713623194
Short name T24
Test name
Test status
Simulation time 265041652239 ps
CPU time 1196.38 seconds
Started Jul 11 06:59:30 PM PDT 24
Finished Jul 11 07:19:28 PM PDT 24
Peak memory 332740 kb
Host smart-d841a6cd-b88e-47a9-b50e-e2b43b2dcce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713623194 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.713623194
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.717479706
Short name T207
Test name
Test status
Simulation time 1935257764 ps
CPU time 6.08 seconds
Started Jul 11 06:59:33 PM PDT 24
Finished Jul 11 06:59:39 PM PDT 24
Peak memory 242064 kb
Host smart-1d20388e-7d19-4842-bcfa-8f7f8726b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717479706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.717479706
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.4135656872
Short name T409
Test name
Test status
Simulation time 142849191 ps
CPU time 4 seconds
Started Jul 11 06:59:31 PM PDT 24
Finished Jul 11 06:59:36 PM PDT 24
Peak memory 241976 kb
Host smart-e47d89a1-05d9-47e6-bd80-b0fc9f6b8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135656872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.4135656872
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2920930907
Short name T285
Test name
Test status
Simulation time 474906136577 ps
CPU time 2424.56 seconds
Started Jul 11 06:59:31 PM PDT 24
Finished Jul 11 07:39:57 PM PDT 24
Peak memory 332880 kb
Host smart-5de06f38-4350-4a50-816c-0eb219ba66b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920930907 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2920930907
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.4213104699
Short name T1107
Test name
Test status
Simulation time 158773749 ps
CPU time 3.3 seconds
Started Jul 11 06:59:40 PM PDT 24
Finished Jul 11 06:59:44 PM PDT 24
Peak memory 242412 kb
Host smart-f310bfd9-68fa-4f96-afc0-2b85379440b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213104699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.4213104699
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2169501768
Short name T631
Test name
Test status
Simulation time 251619286 ps
CPU time 5.03 seconds
Started Jul 11 06:59:40 PM PDT 24
Finished Jul 11 06:59:46 PM PDT 24
Peak memory 241812 kb
Host smart-283a6f12-8ba7-4c32-ad02-25142109b388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169501768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2169501768
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.3119232169
Short name T869
Test name
Test status
Simulation time 295025633 ps
CPU time 4.12 seconds
Started Jul 11 06:59:36 PM PDT 24
Finished Jul 11 06:59:41 PM PDT 24
Peak memory 242388 kb
Host smart-d574daa0-5f82-45e7-95a3-c467414065c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119232169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3119232169
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3084997973
Short name T227
Test name
Test status
Simulation time 1643655977 ps
CPU time 7.34 seconds
Started Jul 11 06:59:38 PM PDT 24
Finished Jul 11 06:59:46 PM PDT 24
Peak memory 242152 kb
Host smart-896c9c65-9156-4adc-9cc8-774375127259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084997973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3084997973
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.34178427
Short name T702
Test name
Test status
Simulation time 111943736041 ps
CPU time 1964.3 seconds
Started Jul 11 06:59:40 PM PDT 24
Finished Jul 11 07:32:25 PM PDT 24
Peak memory 299448 kb
Host smart-4a88258f-a10c-47e4-8c51-74f19e5b5f3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34178427 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.34178427
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.1160947580
Short name T692
Test name
Test status
Simulation time 434489675 ps
CPU time 3.69 seconds
Started Jul 11 06:59:39 PM PDT 24
Finished Jul 11 06:59:44 PM PDT 24
Peak memory 242296 kb
Host smart-bf31cefa-002f-4cff-bdc1-67bfeef2a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160947580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1160947580
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.4084630899
Short name T277
Test name
Test status
Simulation time 47923240210 ps
CPU time 281.76 seconds
Started Jul 11 06:59:39 PM PDT 24
Finished Jul 11 07:04:22 PM PDT 24
Peak memory 257040 kb
Host smart-167dfe92-52db-4d4e-ad4c-954908484429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084630899 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.4084630899
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.475604034
Short name T831
Test name
Test status
Simulation time 94534031 ps
CPU time 1.7 seconds
Started Jul 11 06:53:59 PM PDT 24
Finished Jul 11 06:54:02 PM PDT 24
Peak memory 240096 kb
Host smart-bef98f0d-251a-42fc-901f-cc720ff57542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475604034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.475604034
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1113881932
Short name T639
Test name
Test status
Simulation time 2095640951 ps
CPU time 38.15 seconds
Started Jul 11 06:53:57 PM PDT 24
Finished Jul 11 06:54:36 PM PDT 24
Peak memory 242468 kb
Host smart-6f3ef328-eb5a-46ee-b4b9-87c894312cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113881932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1113881932
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2394805588
Short name T43
Test name
Test status
Simulation time 1895370886 ps
CPU time 24.14 seconds
Started Jul 11 06:53:54 PM PDT 24
Finished Jul 11 06:54:19 PM PDT 24
Peak memory 242248 kb
Host smart-d1a7f0c7-6c77-46ed-b03e-0bcb235af44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394805588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2394805588
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1558066623
Short name T1054
Test name
Test status
Simulation time 16491953328 ps
CPU time 35.13 seconds
Started Jul 11 06:53:54 PM PDT 24
Finished Jul 11 06:54:30 PM PDT 24
Peak memory 246288 kb
Host smart-7f4406d1-cee9-43f2-a38a-cd2f37714f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558066623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1558066623
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2925587023
Short name T846
Test name
Test status
Simulation time 1431675877 ps
CPU time 27.33 seconds
Started Jul 11 06:53:52 PM PDT 24
Finished Jul 11 06:54:20 PM PDT 24
Peak memory 242624 kb
Host smart-fac5d9aa-18a6-4480-bf2d-e9e531bb11a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925587023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2925587023
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.806282168
Short name T761
Test name
Test status
Simulation time 410446642 ps
CPU time 4.51 seconds
Started Jul 11 06:53:56 PM PDT 24
Finished Jul 11 06:54:01 PM PDT 24
Peak memory 241996 kb
Host smart-fda68007-f5c9-4917-8b74-9961a72a60b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806282168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.806282168
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1551921060
Short name T105
Test name
Test status
Simulation time 983181960 ps
CPU time 26.5 seconds
Started Jul 11 06:53:55 PM PDT 24
Finished Jul 11 06:54:22 PM PDT 24
Peak memory 243308 kb
Host smart-0b929841-3318-45cc-b195-43f8c89bd946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551921060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1551921060
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2787578103
Short name T537
Test name
Test status
Simulation time 695640237 ps
CPU time 6.16 seconds
Started Jul 11 06:54:00 PM PDT 24
Finished Jul 11 06:54:07 PM PDT 24
Peak memory 242440 kb
Host smart-6edd1552-c1fe-4061-a8fa-5a3b1aca4403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787578103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2787578103
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.750541816
Short name T1011
Test name
Test status
Simulation time 872713581 ps
CPU time 20.66 seconds
Started Jul 11 06:53:50 PM PDT 24
Finished Jul 11 06:54:11 PM PDT 24
Peak memory 242380 kb
Host smart-257ab6f7-9f2b-43ce-a189-04c30787e4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750541816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.750541816
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.209355853
Short name T109
Test name
Test status
Simulation time 489880535 ps
CPU time 14.36 seconds
Started Jul 11 06:53:50 PM PDT 24
Finished Jul 11 06:54:05 PM PDT 24
Peak memory 242128 kb
Host smart-0113c56e-2058-4745-8396-5cb6cd5bb384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209355853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.209355853
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.2853318231
Short name T583
Test name
Test status
Simulation time 318999786 ps
CPU time 10.19 seconds
Started Jul 11 06:54:00 PM PDT 24
Finished Jul 11 06:54:11 PM PDT 24
Peak memory 242116 kb
Host smart-f10b9b2a-ed00-41e3-8f4a-4e852fab7584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853318231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2853318231
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.3490448273
Short name T406
Test name
Test status
Simulation time 3974468624 ps
CPU time 9.72 seconds
Started Jul 11 06:53:51 PM PDT 24
Finished Jul 11 06:54:02 PM PDT 24
Peak memory 242164 kb
Host smart-21f532ff-528a-4118-bcb0-b0c16cbdcf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490448273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3490448273
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.1576350408
Short name T789
Test name
Test status
Simulation time 18449467917 ps
CPU time 201.24 seconds
Started Jul 11 06:53:58 PM PDT 24
Finished Jul 11 06:57:19 PM PDT 24
Peak memory 249364 kb
Host smart-5008aac8-1d19-4ee5-a06e-ac8b88777611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576350408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
1576350408
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.2555428502
Short name T404
Test name
Test status
Simulation time 33362833963 ps
CPU time 624.62 seconds
Started Jul 11 06:54:02 PM PDT 24
Finished Jul 11 07:04:27 PM PDT 24
Peak memory 261740 kb
Host smart-21f78bcc-48f6-41a7-a1cd-57bbe5bd35ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555428502 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.2555428502
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.76642643
Short name T1003
Test name
Test status
Simulation time 8860535599 ps
CPU time 25.04 seconds
Started Jul 11 06:53:59 PM PDT 24
Finished Jul 11 06:54:25 PM PDT 24
Peak memory 243432 kb
Host smart-2e2b614b-8835-461c-98b5-a229742d7f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76642643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.76642643
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1687750640
Short name T927
Test name
Test status
Simulation time 173423746 ps
CPU time 5.17 seconds
Started Jul 11 06:59:38 PM PDT 24
Finished Jul 11 06:59:44 PM PDT 24
Peak memory 242664 kb
Host smart-e27ecb1b-9203-49ee-8962-70ee58a9a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687750640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1687750640
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2943240123
Short name T1153
Test name
Test status
Simulation time 2620683220 ps
CPU time 27.22 seconds
Started Jul 11 06:59:36 PM PDT 24
Finished Jul 11 07:00:04 PM PDT 24
Peak memory 242356 kb
Host smart-603fe6eb-687d-4e26-90fb-911a3186dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943240123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2943240123
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1802571290
Short name T59
Test name
Test status
Simulation time 313606998 ps
CPU time 5.05 seconds
Started Jul 11 06:59:41 PM PDT 24
Finished Jul 11 06:59:47 PM PDT 24
Peak memory 241868 kb
Host smart-973b71dd-0668-4840-9f3e-e86ddf01c20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802571290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1802571290
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3947386471
Short name T1181
Test name
Test status
Simulation time 399405060 ps
CPU time 12.13 seconds
Started Jul 11 06:59:36 PM PDT 24
Finished Jul 11 06:59:49 PM PDT 24
Peak memory 241900 kb
Host smart-5220aa8a-a9fa-4807-bb24-9c02942b7bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947386471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3947386471
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.207177415
Short name T401
Test name
Test status
Simulation time 588760623467 ps
CPU time 1235.11 seconds
Started Jul 11 06:59:49 PM PDT 24
Finished Jul 11 07:20:26 PM PDT 24
Peak memory 412564 kb
Host smart-10f3bc59-8bd6-4d6f-9a48-5fa5593b48ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207177415 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.207177415
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.163946765
Short name T501
Test name
Test status
Simulation time 106311225 ps
CPU time 3.81 seconds
Started Jul 11 06:59:48 PM PDT 24
Finished Jul 11 06:59:54 PM PDT 24
Peak memory 241928 kb
Host smart-9b9896a3-3613-4646-a0d2-7e9d0571e07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163946765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.163946765
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.959771665
Short name T482
Test name
Test status
Simulation time 352772315 ps
CPU time 8.31 seconds
Started Jul 11 06:59:41 PM PDT 24
Finished Jul 11 06:59:50 PM PDT 24
Peak memory 242152 kb
Host smart-7580dd99-fb6f-483d-ba48-fbd9aaabd206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959771665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.959771665
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.2886618671
Short name T854
Test name
Test status
Simulation time 19789752659 ps
CPU time 145.11 seconds
Started Jul 11 06:59:40 PM PDT 24
Finished Jul 11 07:02:06 PM PDT 24
Peak memory 248844 kb
Host smart-bdb7794e-4960-470d-af13-4a1cca719214
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886618671 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.2886618671
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.2061762065
Short name T518
Test name
Test status
Simulation time 545880026 ps
CPU time 4.07 seconds
Started Jul 11 06:59:49 PM PDT 24
Finished Jul 11 06:59:54 PM PDT 24
Peak memory 242500 kb
Host smart-94619a39-803a-4dbe-911b-e1bf1176d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061762065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2061762065
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.967532749
Short name T714
Test name
Test status
Simulation time 1001536206 ps
CPU time 8.14 seconds
Started Jul 11 06:59:39 PM PDT 24
Finished Jul 11 06:59:48 PM PDT 24
Peak memory 241840 kb
Host smart-39e01223-265b-4f64-87cb-250e4e593522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967532749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.967532749
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3910795405
Short name T832
Test name
Test status
Simulation time 276837297 ps
CPU time 3.63 seconds
Started Jul 11 06:59:39 PM PDT 24
Finished Jul 11 06:59:44 PM PDT 24
Peak memory 241928 kb
Host smart-8db8918e-e7cb-445d-ac87-506239620006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910795405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3910795405
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.2542848880
Short name T77
Test name
Test status
Simulation time 176663067 ps
CPU time 10.8 seconds
Started Jul 11 06:59:40 PM PDT 24
Finished Jul 11 06:59:52 PM PDT 24
Peak memory 241760 kb
Host smart-64bb10a2-b9ac-4225-9f10-2b6248aae215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542848880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2542848880
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3382737296
Short name T190
Test name
Test status
Simulation time 172153430742 ps
CPU time 2483.08 seconds
Started Jul 11 06:59:49 PM PDT 24
Finished Jul 11 07:41:13 PM PDT 24
Peak memory 740404 kb
Host smart-caa3f405-2b4a-4766-8e64-f08167fc2b35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382737296 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3382737296
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.83623339
Short name T1076
Test name
Test status
Simulation time 364748168 ps
CPU time 3.39 seconds
Started Jul 11 06:59:39 PM PDT 24
Finished Jul 11 06:59:43 PM PDT 24
Peak memory 241880 kb
Host smart-18790e64-45e0-4443-8cb3-af725e46a74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83623339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.83623339
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.275917000
Short name T952
Test name
Test status
Simulation time 228423539 ps
CPU time 7.02 seconds
Started Jul 11 06:59:40 PM PDT 24
Finished Jul 11 06:59:48 PM PDT 24
Peak memory 242128 kb
Host smart-a0f613b5-d391-4c18-838b-6516076ea6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275917000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.275917000
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.199232172
Short name T591
Test name
Test status
Simulation time 465440315 ps
CPU time 3.86 seconds
Started Jul 11 06:59:38 PM PDT 24
Finished Jul 11 06:59:42 PM PDT 24
Peak memory 242092 kb
Host smart-366fe9b8-abbf-4159-90fd-3a0c6054ec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199232172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.199232172
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2131056977
Short name T458
Test name
Test status
Simulation time 479776715 ps
CPU time 6.61 seconds
Started Jul 11 06:59:48 PM PDT 24
Finished Jul 11 06:59:56 PM PDT 24
Peak memory 242224 kb
Host smart-a58c0ee8-102a-4270-9965-afc95e85f15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131056977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2131056977
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1210290661
Short name T546
Test name
Test status
Simulation time 687405470470 ps
CPU time 1421.52 seconds
Started Jul 11 06:59:49 PM PDT 24
Finished Jul 11 07:23:32 PM PDT 24
Peak memory 293732 kb
Host smart-bea02ccd-9f62-44ec-91b6-0bb4fd6e664b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210290661 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1210290661
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2773290691
Short name T1000
Test name
Test status
Simulation time 149978619 ps
CPU time 3.65 seconds
Started Jul 11 06:59:44 PM PDT 24
Finished Jul 11 06:59:49 PM PDT 24
Peak memory 241888 kb
Host smart-981f7d44-ea0e-44ae-9e1c-abc05e6ed3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773290691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2773290691
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.454669701
Short name T840
Test name
Test status
Simulation time 4075659215 ps
CPU time 9.8 seconds
Started Jul 11 06:59:43 PM PDT 24
Finished Jul 11 06:59:53 PM PDT 24
Peak memory 241920 kb
Host smart-39db0099-cdd1-4b00-8df0-b82318ea2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454669701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.454669701
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.560082010
Short name T278
Test name
Test status
Simulation time 19852221185 ps
CPU time 424.18 seconds
Started Jul 11 06:59:44 PM PDT 24
Finished Jul 11 07:06:49 PM PDT 24
Peak memory 257080 kb
Host smart-e6623e26-fe30-4854-860a-6a5a8eb2f856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560082010 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.560082010
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.3141944108
Short name T1064
Test name
Test status
Simulation time 192728452 ps
CPU time 3.92 seconds
Started Jul 11 06:59:45 PM PDT 24
Finished Jul 11 06:59:50 PM PDT 24
Peak memory 241920 kb
Host smart-7270eb8a-b253-436f-a3de-6aaf042f08d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141944108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3141944108
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3165353253
Short name T422
Test name
Test status
Simulation time 3311008784 ps
CPU time 11.14 seconds
Started Jul 11 06:59:44 PM PDT 24
Finished Jul 11 06:59:56 PM PDT 24
Peak memory 241848 kb
Host smart-2746ecdd-90be-4f3a-8bbc-621b0fcdfca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165353253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3165353253
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.52386457
Short name T157
Test name
Test status
Simulation time 71772605860 ps
CPU time 1380.29 seconds
Started Jul 11 06:59:43 PM PDT 24
Finished Jul 11 07:22:45 PM PDT 24
Peak memory 291484 kb
Host smart-4bbb64d0-b7d6-44bb-985d-03452287b3db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52386457 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.52386457
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.894546292
Short name T926
Test name
Test status
Simulation time 140681425 ps
CPU time 4.56 seconds
Started Jul 11 06:59:45 PM PDT 24
Finished Jul 11 06:59:50 PM PDT 24
Peak memory 242020 kb
Host smart-592ae772-7d13-48de-90dc-ffb93767421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894546292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.894546292
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.4284935799
Short name T913
Test name
Test status
Simulation time 435164127 ps
CPU time 5.88 seconds
Started Jul 11 06:59:45 PM PDT 24
Finished Jul 11 06:59:52 PM PDT 24
Peak memory 242136 kb
Host smart-a5544ef8-284c-499d-b62e-185ceb7311fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284935799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.4284935799
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3337191617
Short name T290
Test name
Test status
Simulation time 1531399876672 ps
CPU time 3185.05 seconds
Started Jul 11 06:59:45 PM PDT 24
Finished Jul 11 07:52:51 PM PDT 24
Peak memory 554848 kb
Host smart-1744769f-81a9-48b6-8bf5-8711e7b2248c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337191617 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3337191617
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.951290738
Short name T486
Test name
Test status
Simulation time 65272958 ps
CPU time 1.8 seconds
Started Jul 11 06:54:10 PM PDT 24
Finished Jul 11 06:54:13 PM PDT 24
Peak memory 240096 kb
Host smart-f5fe0473-ba6c-490b-8ccf-451287d2cb80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951290738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.951290738
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1040886190
Short name T1031
Test name
Test status
Simulation time 309232771 ps
CPU time 6.47 seconds
Started Jul 11 06:54:03 PM PDT 24
Finished Jul 11 06:54:10 PM PDT 24
Peak memory 248772 kb
Host smart-8ee3004b-d6d0-4ceb-ae60-3313d717806a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040886190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1040886190
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2911607799
Short name T747
Test name
Test status
Simulation time 2604888734 ps
CPU time 7.33 seconds
Started Jul 11 06:54:11 PM PDT 24
Finished Jul 11 06:54:19 PM PDT 24
Peak memory 242332 kb
Host smart-26513bc5-cb7c-4a15-9a34-148951136228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911607799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2911607799
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.829051370
Short name T1125
Test name
Test status
Simulation time 4395386864 ps
CPU time 30.67 seconds
Started Jul 11 06:54:06 PM PDT 24
Finished Jul 11 06:54:37 PM PDT 24
Peak memory 246400 kb
Host smart-a32425b9-c2d5-42a0-a3e3-e651e53418a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829051370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.829051370
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2911028530
Short name T541
Test name
Test status
Simulation time 1165145316 ps
CPU time 27.17 seconds
Started Jul 11 06:54:06 PM PDT 24
Finished Jul 11 06:54:34 PM PDT 24
Peak memory 242452 kb
Host smart-9e524f0a-cefa-4416-afa8-9ee39de4c578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911028530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2911028530
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.4128234700
Short name T54
Test name
Test status
Simulation time 160665544 ps
CPU time 4.04 seconds
Started Jul 11 06:54:05 PM PDT 24
Finished Jul 11 06:54:10 PM PDT 24
Peak memory 241888 kb
Host smart-096273dd-ffcd-44e9-8248-941d4b7f11b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128234700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.4128234700
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3862554810
Short name T603
Test name
Test status
Simulation time 2159710830 ps
CPU time 23.22 seconds
Started Jul 11 06:54:09 PM PDT 24
Finished Jul 11 06:54:33 PM PDT 24
Peak memory 242580 kb
Host smart-595e4e40-c03e-4d3d-bc9b-61c7b6801d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862554810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3862554810
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2040435771
Short name T824
Test name
Test status
Simulation time 1622405691 ps
CPU time 38.41 seconds
Started Jul 11 06:54:07 PM PDT 24
Finished Jul 11 06:54:46 PM PDT 24
Peak memory 242812 kb
Host smart-15205a66-c047-4ee7-a90a-99130c32285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040435771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2040435771
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.2098413296
Short name T577
Test name
Test status
Simulation time 165159959 ps
CPU time 6.23 seconds
Started Jul 11 06:54:06 PM PDT 24
Finished Jul 11 06:54:13 PM PDT 24
Peak memory 241740 kb
Host smart-238262c0-4725-43dd-bad2-1ee8e8b2bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098413296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2098413296
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2916088756
Short name T497
Test name
Test status
Simulation time 3827272414 ps
CPU time 6.76 seconds
Started Jul 11 06:54:03 PM PDT 24
Finished Jul 11 06:54:10 PM PDT 24
Peak memory 248780 kb
Host smart-b826ea4f-053d-48b4-991a-4e3945ba85b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916088756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2916088756
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.898091419
Short name T765
Test name
Test status
Simulation time 340065629 ps
CPU time 6.38 seconds
Started Jul 11 06:54:06 PM PDT 24
Finished Jul 11 06:54:13 PM PDT 24
Peak memory 242036 kb
Host smart-c63245c7-696a-44ff-bde8-e28445e2df19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898091419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.898091419
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.1767974815
Short name T1036
Test name
Test status
Simulation time 275683730 ps
CPU time 8.66 seconds
Started Jul 11 06:54:01 PM PDT 24
Finished Jul 11 06:54:10 PM PDT 24
Peak memory 242328 kb
Host smart-53a4e087-beba-41d2-bf01-d9583c418e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767974815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1767974815
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.21275750
Short name T827
Test name
Test status
Simulation time 83975009951 ps
CPU time 524.24 seconds
Started Jul 11 06:54:10 PM PDT 24
Finished Jul 11 07:02:55 PM PDT 24
Peak memory 257072 kb
Host smart-98a2c804-939c-41f7-a627-5ec2b2fed688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275750 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.21275750
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.837095647
Short name T762
Test name
Test status
Simulation time 2358439156 ps
CPU time 14.74 seconds
Started Jul 11 06:54:10 PM PDT 24
Finished Jul 11 06:54:26 PM PDT 24
Peak memory 242876 kb
Host smart-9bec0610-1369-4897-afc6-7bb29da0b4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837095647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.837095647
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.3750283045
Short name T677
Test name
Test status
Simulation time 360948461 ps
CPU time 4.72 seconds
Started Jul 11 06:59:43 PM PDT 24
Finished Jul 11 06:59:49 PM PDT 24
Peak memory 241912 kb
Host smart-40095d2a-1fea-4774-947a-4978870eb4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750283045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3750283045
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.2341493914
Short name T1057
Test name
Test status
Simulation time 814697152 ps
CPU time 6.32 seconds
Started Jul 11 06:59:48 PM PDT 24
Finished Jul 11 06:59:55 PM PDT 24
Peak memory 246792 kb
Host smart-d9e0cde2-0596-4a18-9a69-f0dbf7d553a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341493914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2341493914
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.28953050
Short name T300
Test name
Test status
Simulation time 620621951507 ps
CPU time 1562.46 seconds
Started Jul 11 06:59:47 PM PDT 24
Finished Jul 11 07:25:50 PM PDT 24
Peak memory 281668 kb
Host smart-abe8e712-f96e-4d52-ac21-2cfe563a06d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953050 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.28953050
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.522715246
Short name T515
Test name
Test status
Simulation time 233733828 ps
CPU time 3.34 seconds
Started Jul 11 06:59:48 PM PDT 24
Finished Jul 11 06:59:52 PM PDT 24
Peak memory 242068 kb
Host smart-bf7608ab-07dc-454d-9751-d149bb313a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522715246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.522715246
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3492171368
Short name T1122
Test name
Test status
Simulation time 1387560135 ps
CPU time 16.24 seconds
Started Jul 11 06:59:47 PM PDT 24
Finished Jul 11 07:00:04 PM PDT 24
Peak memory 242132 kb
Host smart-da6047d3-693e-4316-b0cb-55963819d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492171368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3492171368
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2843809864
Short name T780
Test name
Test status
Simulation time 80880233675 ps
CPU time 2091.79 seconds
Started Jul 11 06:59:46 PM PDT 24
Finished Jul 11 07:34:39 PM PDT 24
Peak memory 420784 kb
Host smart-d287076b-bb5f-4e89-ba50-982ac7ca8719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843809864 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2843809864
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2430029687
Short name T937
Test name
Test status
Simulation time 1896169962 ps
CPU time 5.46 seconds
Started Jul 11 06:59:49 PM PDT 24
Finished Jul 11 06:59:56 PM PDT 24
Peak memory 242116 kb
Host smart-983ef5e5-d70f-4bb6-bc5c-52e4f63a5d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430029687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2430029687
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2962647653
Short name T248
Test name
Test status
Simulation time 1642125593 ps
CPU time 5.23 seconds
Started Jul 11 06:59:48 PM PDT 24
Finished Jul 11 06:59:55 PM PDT 24
Peak memory 242228 kb
Host smart-30093e96-a129-4b2f-80a6-c051f74e5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962647653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2962647653
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1919406661
Short name T657
Test name
Test status
Simulation time 44243064035 ps
CPU time 374.17 seconds
Started Jul 11 06:59:49 PM PDT 24
Finished Jul 11 07:06:05 PM PDT 24
Peak memory 290916 kb
Host smart-8a7b7dcf-2103-4861-aa36-242ef020a388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919406661 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1919406661
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3033841915
Short name T800
Test name
Test status
Simulation time 403911297 ps
CPU time 4.72 seconds
Started Jul 11 06:59:53 PM PDT 24
Finished Jul 11 06:59:59 PM PDT 24
Peak memory 242180 kb
Host smart-805f0d90-2c56-4745-9f23-153c88f61e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033841915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3033841915
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.3393615671
Short name T983
Test name
Test status
Simulation time 684193254 ps
CPU time 9.43 seconds
Started Jul 11 06:59:54 PM PDT 24
Finished Jul 11 07:00:04 PM PDT 24
Peak memory 242244 kb
Host smart-34422b64-31b0-4790-9cbd-895e429096f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393615671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3393615671
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.771085906
Short name T1051
Test name
Test status
Simulation time 233782430910 ps
CPU time 460.8 seconds
Started Jul 11 06:59:52 PM PDT 24
Finished Jul 11 07:07:33 PM PDT 24
Peak memory 260904 kb
Host smart-bed94e46-67d2-45f5-a31e-676edd09aa13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771085906 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.771085906
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.652857051
Short name T1037
Test name
Test status
Simulation time 216076277 ps
CPU time 3.02 seconds
Started Jul 11 06:59:53 PM PDT 24
Finished Jul 11 06:59:57 PM PDT 24
Peak memory 242008 kb
Host smart-e20ee93a-97c2-4bbf-897c-726985c81ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652857051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.652857051
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.130349767
Short name T536
Test name
Test status
Simulation time 258474592 ps
CPU time 7.85 seconds
Started Jul 11 06:59:52 PM PDT 24
Finished Jul 11 07:00:01 PM PDT 24
Peak memory 242292 kb
Host smart-e3129ad2-8b36-4818-a7ce-4e39e7143e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130349767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.130349767
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3737619983
Short name T574
Test name
Test status
Simulation time 278268354 ps
CPU time 3.76 seconds
Started Jul 11 06:59:55 PM PDT 24
Finished Jul 11 06:59:59 PM PDT 24
Peak memory 241940 kb
Host smart-e4ad531b-f47c-495c-923e-bbab38f02498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737619983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3737619983
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3393574887
Short name T226
Test name
Test status
Simulation time 311619471 ps
CPU time 6.97 seconds
Started Jul 11 06:59:52 PM PDT 24
Finished Jul 11 07:00:00 PM PDT 24
Peak memory 241976 kb
Host smart-e6811940-f29f-4ba4-bb32-a78c4f82a88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393574887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3393574887
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2209637170
Short name T887
Test name
Test status
Simulation time 419052997 ps
CPU time 4.48 seconds
Started Jul 11 06:59:56 PM PDT 24
Finished Jul 11 07:00:01 PM PDT 24
Peak memory 242080 kb
Host smart-505d9501-47d7-4bd0-988b-455a6750580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209637170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2209637170
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3671355896
Short name T434
Test name
Test status
Simulation time 250487459 ps
CPU time 6.84 seconds
Started Jul 11 06:59:57 PM PDT 24
Finished Jul 11 07:00:05 PM PDT 24
Peak memory 241864 kb
Host smart-0f1b2c9e-1405-471a-b837-668cc76c67d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671355896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3671355896
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2954572614
Short name T876
Test name
Test status
Simulation time 385371348 ps
CPU time 3.83 seconds
Started Jul 11 06:59:56 PM PDT 24
Finished Jul 11 07:00:01 PM PDT 24
Peak memory 242036 kb
Host smart-b3eca28f-38b9-4e8b-b147-cad4d5969814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954572614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2954572614
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1296057036
Short name T1151
Test name
Test status
Simulation time 2078240794 ps
CPU time 17.64 seconds
Started Jul 11 06:59:58 PM PDT 24
Finished Jul 11 07:00:17 PM PDT 24
Peak memory 242388 kb
Host smart-07766a14-b2c0-4575-b8ed-f41cd0edbdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296057036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1296057036
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3500275261
Short name T283
Test name
Test status
Simulation time 290611638035 ps
CPU time 2737.83 seconds
Started Jul 11 06:59:56 PM PDT 24
Finished Jul 11 07:45:35 PM PDT 24
Peak memory 306908 kb
Host smart-6bf92349-2701-4344-802c-409bfedeb85f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500275261 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3500275261
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2752417920
Short name T251
Test name
Test status
Simulation time 3022401074 ps
CPU time 21.11 seconds
Started Jul 11 06:59:57 PM PDT 24
Finished Jul 11 07:00:19 PM PDT 24
Peak memory 241892 kb
Host smart-05914ba2-8118-4c38-972a-bafc2bc6cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752417920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2752417920
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.3886309306
Short name T281
Test name
Test status
Simulation time 63260159985 ps
CPU time 423.51 seconds
Started Jul 11 06:59:56 PM PDT 24
Finished Jul 11 07:07:00 PM PDT 24
Peak memory 343144 kb
Host smart-31abfa5a-1141-412b-adc0-6ae2a39998e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886309306 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.3886309306
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.3408886122
Short name T115
Test name
Test status
Simulation time 451080754 ps
CPU time 5.15 seconds
Started Jul 11 06:59:56 PM PDT 24
Finished Jul 11 07:00:02 PM PDT 24
Peak memory 241924 kb
Host smart-4105399d-9b59-4629-9934-9951009f2647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408886122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3408886122
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3060482999
Short name T584
Test name
Test status
Simulation time 413209012 ps
CPU time 8.79 seconds
Started Jul 11 06:59:57 PM PDT 24
Finished Jul 11 07:00:07 PM PDT 24
Peak memory 241968 kb
Host smart-ffc88485-6953-478b-b1c1-ada94945dbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060482999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3060482999
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.4244679073
Short name T20
Test name
Test status
Simulation time 173051910194 ps
CPU time 2044.15 seconds
Started Jul 11 06:59:59 PM PDT 24
Finished Jul 11 07:34:04 PM PDT 24
Peak memory 430400 kb
Host smart-4d905bab-8adf-4dd3-8274-5f62d7f3b23a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244679073 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.4244679073
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%