SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 50624 | 1 | T1 | 76 | T5 | 53 | T9 | 439 | ||||
access_err | 67407 | 1 | T1 | 2 | T2 | 24 | T4 | 398 | ||||
write_blank_err | 421 | 1 | T6 | 3 | T14 | 1 | T17 | 1 | ||||
ecc_uncorr_err | 67286 | 1 | T10 | 10 | T6 | 865 | T14 | 636 | ||||
ecc_corr_err | 1250 | 1 | T10 | 3 | T6 | 2 | T65 | 4 | ||||
no_err | 97547 | 1 | T1 | 11 | T2 | 74 | T4 | 298 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 720 | 1 | T6 | 9 | T14 | 10 | T15 | 5 | ||||
secret2 | 26659 | 1 | T2 | 4 | T4 | 86 | T5 | 2 | ||||
secret1 | 29341 | 1 | T2 | 11 | T4 | 67 | T13 | 64 | ||||
secret0 | 36853 | 1 | T2 | 10 | T4 | 72 | T10 | 11 | ||||
hw_cfg1 | 40663 | 1 | T1 | 2 | T2 | 6 | T4 | 59 | ||||
hw_cfg0 | 24740 | 1 | T1 | 77 | T2 | 14 | T4 | 74 | ||||
rot_creator_auth_state | 21357 | 1 | T1 | 2 | T2 | 3 | T4 | 70 | ||||
rot_creator_auth_codesign | 22699 | 1 | T1 | 3 | T2 | 14 | T4 | 73 | ||||
owner_sw_cfg | 25295 | 1 | T1 | 2 | T2 | 9 | T4 | 58 | ||||
creator_sw_cfg | 20770 | 1 | T1 | 2 | T2 | 19 | T4 | 83 | ||||
vendor_test | 35438 | 1 | T1 | 1 | T2 | 8 | T4 | 54 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 3118 | 1 | T8 | 50 | T232 | 425 | T220 | 176 | ||||
fsm_err | secret1 | 4801 | 1 | T174 | 17 | T105 | 397 | T325 | 68 | ||||
fsm_err | secret0 | 4752 | 1 | T8 | 28 | T40 | 233 | T181 | 99 | ||||
fsm_err | hw_cfg1 | 3200 | 1 | T108 | 2 | T326 | 336 | T218 | 132 | ||||
fsm_err | hw_cfg0 | 4745 | 1 | T1 | 76 | T219 | 33 | T222 | 90 | ||||
fsm_err | rot_creator_auth_state | 1923 | 1 | T313 | 45 | T201 | 51 | T173 | 80 | ||||
fsm_err | rot_creator_auth_codesign | 3472 | 1 | T9 | 439 | T210 | 76 | T256 | 26 | ||||
fsm_err | owner_sw_cfg | 5246 | 1 | T5 | 53 | T6 | 397 | T7 | 427 | ||||
fsm_err | creator_sw_cfg | 2878 | 1 | T209 | 94 | T124 | 166 | T199 | 89 | ||||
fsm_err | vendor_test | 16489 | 1 | T7 | 419 | T8 | 105 | T65 | 26 | ||||
access_err | life_cycle | 720 | 1 | T6 | 9 | T14 | 10 | T15 | 5 | ||||
access_err | secret2 | 11707 | 1 | T2 | 1 | T4 | 51 | T5 | 2 | ||||
access_err | secret1 | 6157 | 1 | T2 | 1 | T4 | 56 | T13 | 40 | ||||
access_err | secret0 | 5052 | 1 | T4 | 51 | T10 | 4 | T13 | 40 | ||||
access_err | hw_cfg1 | 1397 | 1 | T1 | 2 | T2 | 1 | T4 | 6 | ||||
access_err | hw_cfg0 | 2351 | 1 | T4 | 6 | T13 | 16 | T16 | 1 | ||||
access_err | rot_creator_auth_state | 6415 | 1 | T2 | 2 | T4 | 40 | T13 | 41 | ||||
access_err | rot_creator_auth_codesign | 8729 | 1 | T2 | 9 | T4 | 48 | T11 | 1 | ||||
access_err | owner_sw_cfg | 8196 | 1 | T2 | 4 | T4 | 31 | T13 | 44 | ||||
access_err | creator_sw_cfg | 8311 | 1 | T2 | 2 | T4 | 69 | T13 | 48 | ||||
access_err | vendor_test | 8372 | 1 | T2 | 4 | T4 | 40 | T13 | 35 | ||||
write_blank_err | secret2 | 14 | 1 | T327 | 1 | T254 | 1 | T224 | 1 | ||||
write_blank_err | secret1 | 22 | 1 | T6 | 1 | T14 | 1 | T96 | 1 | ||||
write_blank_err | secret0 | 44 | 1 | T15 | 1 | T76 | 1 | T238 | 1 | ||||
write_blank_err | hw_cfg1 | 71 | 1 | T6 | 2 | T17 | 1 | T15 | 1 | ||||
write_blank_err | hw_cfg0 | 11 | 1 | T328 | 1 | T212 | 2 | T329 | 1 | ||||
write_blank_err | rot_creator_auth_state | 123 | 1 | T15 | 1 | T110 | 1 | T238 | 2 | ||||
write_blank_err | rot_creator_auth_codesign | 47 | 1 | T268 | 2 | T330 | 3 | T183 | 2 | ||||
write_blank_err | owner_sw_cfg | 35 | 1 | T331 | 1 | T328 | 2 | T183 | 1 | ||||
write_blank_err | creator_sw_cfg | 16 | 1 | T238 | 1 | T330 | 1 | T332 | 1 | ||||
write_blank_err | vendor_test | 38 | 1 | T96 | 1 | T15 | 1 | T238 | 8 | ||||
ecc_uncorr_err | secret2 | 6186 | 1 | T189 | 63 | T327 | 154 | T254 | 715 | ||||
ecc_uncorr_err | secret1 | 8506 | 1 | T6 | 460 | T14 | 636 | T96 | 343 | ||||
ecc_uncorr_err | secret0 | 17637 | 1 | T15 | 273 | T76 | 445 | T238 | 444 | ||||
ecc_uncorr_err | hw_cfg1 | 23950 | 1 | T10 | 10 | T6 | 405 | T17 | 122 | ||||
ecc_uncorr_err | hw_cfg0 | 4164 | 1 | T164 | 59 | T328 | 662 | T333 | 55 | ||||
ecc_uncorr_err | rot_creator_auth_state | 3806 | 1 | T189 | 61 | T141 | 49 | T139 | 32 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 820 | 1 | T234 | 42 | T141 | 62 | T188 | 11 | ||||
ecc_uncorr_err | owner_sw_cfg | 1635 | 1 | T141 | 64 | T139 | 74 | T169 | 28 | ||||
ecc_uncorr_err | creator_sw_cfg | 582 | 1 | T141 | 64 | T164 | 56 | T334 | 48 | ||||
ecc_corr_err | secret2 | 54 | 1 | T74 | 1 | T104 | 3 | T56 | 1 | ||||
ecc_corr_err | secret1 | 88 | 1 | T74 | 1 | T104 | 1 | T128 | 2 | ||||
ecc_corr_err | secret0 | 147 | 1 | T10 | 1 | T74 | 3 | T104 | 1 | ||||
ecc_corr_err | hw_cfg1 | 236 | 1 | T6 | 2 | T65 | 1 | T15 | 2 | ||||
ecc_corr_err | hw_cfg0 | 235 | 1 | T10 | 1 | T65 | 2 | T74 | 4 | ||||
ecc_corr_err | rot_creator_auth_state | 99 | 1 | T74 | 2 | T104 | 1 | T30 | 3 | ||||
ecc_corr_err | rot_creator_auth_codesign | 154 | 1 | T10 | 1 | T74 | 8 | T128 | 2 | ||||
ecc_corr_err | owner_sw_cfg | 119 | 1 | T74 | 2 | T234 | 1 | T104 | 5 | ||||
ecc_corr_err | creator_sw_cfg | 118 | 1 | T65 | 1 | T57 | 1 | T139 | 1 | ||||
no_err | secret2 | 5580 | 1 | T2 | 3 | T4 | 35 | T10 | 1 | ||||
no_err | secret1 | 9767 | 1 | T2 | 10 | T4 | 11 | T13 | 24 | ||||
no_err | secret0 | 9221 | 1 | T2 | 10 | T4 | 21 | T10 | 6 | ||||
no_err | hw_cfg1 | 11809 | 1 | T2 | 5 | T4 | 53 | T11 | 1 | ||||
no_err | hw_cfg0 | 13234 | 1 | T1 | 1 | T2 | 14 | T4 | 68 | ||||
no_err | rot_creator_auth_state | 8991 | 1 | T1 | 2 | T2 | 1 | T4 | 30 | ||||
no_err | rot_creator_auth_codesign | 9477 | 1 | T1 | 3 | T2 | 5 | T4 | 25 | ||||
no_err | owner_sw_cfg | 10064 | 1 | T1 | 2 | T2 | 5 | T4 | 27 | ||||
no_err | creator_sw_cfg | 8865 | 1 | T1 | 2 | T2 | 17 | T4 | 14 | ||||
no_err | vendor_test | 10539 | 1 | T1 | 1 | T2 | 4 | T4 | 14 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |