Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53957	1			T3	57		T9	202		T10	42
access_err	66788	1			T3	6		T7	6		T4	109
write_blank_err	527	1			T4	1		T121	1		T12	1
ecc_uncorr_err	63220	1			T4	520		T5	35		T121	456
ecc_corr_err	1425	1			T5	1		T114	11		T44	3
no_err	96774	1			T1	7		T3	8		T7	22

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	755	1			T4	7		T12	6		T13	18
secret2	26185	1			T7	1		T4	51		T5	20
secret1	31396	1			T7	3		T4	40		T6	66
secret0	35428	1			T1	2		T3	59		T7	3
hw_cfg1	35938	1			T3	6		T4	558		T5	1
hw_cfg0	26706	1			T1	3		T3	1		T7	3
rot_creator_auth_state	23230	1			T4	37		T6	61		T121	2
rot_creator_auth_codesign	22357	1			T1	2		T7	4		T4	50
owner_sw_cfg	20950	1			T3	1		T7	5		T4	36
creator_sw_cfg	25422	1			T3	4		T7	8		T4	35
vendor_test	34324	1			T7	1		T4	43		T6	56

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4153	1			T8	62		T106	91		T317	16
fsm_err	secret1	6049	1			T17	86		T154	316		T318	211
fsm_err	secret0	5539	1			T3	57		T113	5		T105	12
fsm_err	hw_cfg1	3457	1			T9	202		T10	42		T16	11
fsm_err	hw_cfg0	5811	1			T16	385		T162	78		T226	42
fsm_err	rot_creator_auth_state	2401	1			T16	11		T114	47		T219	53
fsm_err	rot_creator_auth_codesign	2914	1			T114	42		T37	244		T164	59
fsm_err	owner_sw_cfg	2014	1			T165	34		T204	35		T266	422
fsm_err	creator_sw_cfg	5708	1			T112	174		T206	109		T17	145
fsm_err	vendor_test	15911	1			T111	431		T114	47		T72	5
access_err	life_cycle	755	1			T4	7		T12	6		T13	18
access_err	secret2	11857	1			T4	28		T6	65		T8	80
access_err	secret1	6219	1			T12	176		T27	7		T72	5
access_err	secret0	5009	1			T6	4		T12	165		T16	2
access_err	hw_cfg1	1297	1			T3	3		T4	1		T6	2
access_err	hw_cfg0	2453	1			T12	71		T27	2		T101	1
access_err	rot_creator_auth_state	6441	1			T4	22		T6	40		T8	28
access_err	rot_creator_auth_codesign	8668	1			T7	1		T4	26		T6	36
access_err	owner_sw_cfg	7516	1			T7	3		T4	3		T6	32
access_err	creator_sw_cfg	8405	1			T3	3		T7	2		T4	11
access_err	vendor_test	8168	1			T4	11		T6	36		T8	49
write_blank_err	secret2	12	1			T38	1		T319	2		T320	1
write_blank_err	secret1	28	1			T37	1		T218	1		T321	1
write_blank_err	secret0	45	1			T106	1		T316	1		T17	1
write_blank_err	hw_cfg1	73	1			T4	1		T121	1		T13	2
write_blank_err	hw_cfg0	21	1			T207	1		T211	1		T188	1
write_blank_err	rot_creator_auth_state	187	1			T12	1		T13	6		T102	2
write_blank_err	rot_creator_auth_codesign	62	1			T37	1		T207	1		T17	1
write_blank_err	owner_sw_cfg	40	1			T207	1		T316	1		T218	1
write_blank_err	creator_sw_cfg	32	1			T13	1		T322	1		T323	1
write_blank_err	vendor_test	27	1			T13	1		T316	1		T220	1
ecc_uncorr_err	secret2	4359	1			T5	19		T200	61		T319	409
ecc_uncorr_err	secret1	9249	1			T37	5		T72	9		T218	213
ecc_uncorr_err	secret0	15333	1			T106	394		T316	91		T226	112
ecc_uncorr_err	hw_cfg1	19449	1			T4	520		T121	456		T114	130
ecc_uncorr_err	hw_cfg0	4943	1			T114	52		T165	23		T211	472
ecc_uncorr_err	rot_creator_auth_state	5277	1			T12	467		T114	45		T13	144
ecc_uncorr_err	rot_creator_auth_codesign	1049	1			T168	34		T164	74		T165	38
ecc_uncorr_err	owner_sw_cfg	1330	1			T114	41		T44	5		T168	61
ecc_uncorr_err	creator_sw_cfg	2231	1			T5	16		T164	74		T324	8
ecc_corr_err	secret2	87	1			T114	1		T80	3		T137	1
ecc_corr_err	secret1	110	1			T114	1		T72	2		T76	1
ecc_corr_err	secret0	177	1			T114	1		T72	1		T76	2
ecc_corr_err	hw_cfg1	277	1			T5	1		T114	3		T13	4
ecc_corr_err	hw_cfg0	278	1			T207	1		T164	2		T80	16
ecc_corr_err	rot_creator_auth_state	132	1			T114	1		T44	2		T164	1
ecc_corr_err	rot_creator_auth_codesign	134	1			T114	1		T168	3		T76	2
ecc_corr_err	owner_sw_cfg	111	1			T114	2		T44	1		T76	1
ecc_corr_err	creator_sw_cfg	119	1			T114	1		T72	2		T80	5
no_err	secret2	5717	1			T7	1		T4	23		T5	1
no_err	secret1	9741	1			T7	3		T4	40		T6	66
no_err	secret0	9325	1			T1	2		T3	2		T7	3
no_err	hw_cfg1	11385	1			T3	3		T4	36		T6	48
no_err	hw_cfg0	13200	1			T1	3		T3	1		T7	3
no_err	rot_creator_auth_state	8792	1			T4	15		T6	21		T121	2
no_err	rot_creator_auth_codesign	9530	1			T1	2		T7	3		T4	24
no_err	owner_sw_cfg	9939	1			T3	1		T7	2		T4	33
no_err	creator_sw_cfg	8927	1			T3	1		T7	6		T4	24
no_err	vendor_test	10218	1			T7	1		T4	32		T6	20

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded