SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 45358 | 1 | T8 | 96 | T5 | 245 | T6 | 43 | ||||
access_err | 65377 | 1 | T1 | 5 | T2 | 15 | T4 | 1 | ||||
write_blank_err | 485 | 1 | T5 | 2 | T6 | 4 | T7 | 5 | ||||
ecc_uncorr_err | 60015 | 1 | T2 | 58 | T5 | 776 | T6 | 917 | ||||
ecc_corr_err | 1275 | 1 | T6 | 3 | T7 | 3 | T28 | 36 | ||||
no_err | 94253 | 1 | T1 | 17 | T2 | 22 | T4 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 680 | 1 | T5 | 2 | T7 | 7 | T13 | 3 | ||||
secret2 | 27551 | 1 | T2 | 7 | T4 | 1 | T5 | 370 | ||||
secret1 | 28869 | 1 | T5 | 120 | T6 | 678 | T10 | 10 | ||||
secret0 | 31189 | 1 | T1 | 3 | T2 | 49 | T5 | 549 | ||||
hw_cfg1 | 36624 | 1 | T1 | 6 | T4 | 3 | T5 | 416 | ||||
hw_cfg0 | 24702 | 1 | T2 | 16 | T4 | 2 | T5 | 120 | ||||
rot_creator_auth_state | 23563 | 1 | T1 | 1 | T2 | 3 | T5 | 116 | ||||
rot_creator_auth_codesign | 20691 | 1 | T1 | 1 | T2 | 2 | T5 | 118 | ||||
owner_sw_cfg | 20869 | 1 | T1 | 2 | T2 | 2 | T5 | 117 | ||||
creator_sw_cfg | 20651 | 1 | T1 | 3 | T2 | 7 | T5 | 117 | ||||
vendor_test | 31374 | 1 | T1 | 6 | T2 | 9 | T8 | 96 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 3583 | 1 | T5 | 245 | T212 | 306 | T336 | 159 | ||||
fsm_err | secret1 | 5398 | 1 | T10 | 10 | T123 | 38 | T139 | 92 | ||||
fsm_err | secret0 | 3808 | 1 | T337 | 197 | T196 | 16 | T247 | 211 | ||||
fsm_err | hw_cfg1 | 3524 | 1 | T12 | 81 | T324 | 177 | T142 | 345 | ||||
fsm_err | hw_cfg0 | 4900 | 1 | T211 | 204 | T138 | 75 | T255 | 13 | ||||
fsm_err | rot_creator_auth_state | 2973 | 1 | T338 | 229 | T166 | 47 | T339 | 150 | ||||
fsm_err | rot_creator_auth_codesign | 1759 | 1 | T340 | 29 | T192 | 53 | T251 | 43 | ||||
fsm_err | owner_sw_cfg | 2958 | 1 | T6 | 43 | T26 | 83 | T157 | 62 | ||||
fsm_err | creator_sw_cfg | 2850 | 1 | T213 | 309 | T157 | 71 | T276 | 569 | ||||
fsm_err | vendor_test | 13605 | 1 | T8 | 96 | T110 | 180 | T28 | 82 | ||||
access_err | life_cycle | 680 | 1 | T5 | 2 | T7 | 7 | T13 | 3 | ||||
access_err | secret2 | 11515 | 1 | T2 | 7 | T4 | 1 | T5 | 91 | ||||
access_err | secret1 | 6108 | 1 | T5 | 58 | T27 | 19 | T28 | 12 | ||||
access_err | secret0 | 4859 | 1 | T5 | 48 | T6 | 3 | T27 | 5 | ||||
access_err | hw_cfg1 | 1348 | 1 | T1 | 4 | T5 | 20 | T6 | 2 | ||||
access_err | hw_cfg0 | 2323 | 1 | T5 | 26 | T27 | 7 | T28 | 3 | ||||
access_err | rot_creator_auth_state | 6548 | 1 | T2 | 1 | T5 | 43 | T6 | 93 | ||||
access_err | rot_creator_auth_codesign | 8410 | 1 | T2 | 2 | T5 | 43 | T6 | 133 | ||||
access_err | owner_sw_cfg | 7474 | 1 | T1 | 1 | T2 | 1 | T5 | 31 | ||||
access_err | creator_sw_cfg | 8402 | 1 | T2 | 1 | T5 | 65 | T6 | 122 | ||||
access_err | vendor_test | 7710 | 1 | T2 | 3 | T5 | 37 | T6 | 102 | ||||
write_blank_err | secret2 | 15 | 1 | T107 | 1 | T122 | 1 | T244 | 2 | ||||
write_blank_err | secret1 | 21 | 1 | T6 | 1 | T122 | 1 | T299 | 1 | ||||
write_blank_err | secret0 | 45 | 1 | T5 | 1 | T7 | 1 | T13 | 3 | ||||
write_blank_err | hw_cfg1 | 77 | 1 | T5 | 1 | T7 | 2 | T153 | 1 | ||||
write_blank_err | hw_cfg0 | 12 | 1 | T154 | 1 | T283 | 1 | T341 | 1 | ||||
write_blank_err | rot_creator_auth_state | 173 | 1 | T6 | 3 | T7 | 1 | T107 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 68 | 1 | T342 | 1 | T244 | 1 | T245 | 6 | ||||
write_blank_err | owner_sw_cfg | 29 | 1 | T155 | 2 | T123 | 1 | T342 | 2 | ||||
write_blank_err | creator_sw_cfg | 18 | 1 | T343 | 2 | T244 | 3 | T245 | 3 | ||||
write_blank_err | vendor_test | 27 | 1 | T7 | 1 | T154 | 1 | T122 | 1 | ||||
ecc_uncorr_err | secret2 | 6624 | 1 | T107 | 148 | T122 | 558 | T221 | 2 | ||||
ecc_uncorr_err | secret1 | 7823 | 1 | T6 | 544 | T157 | 68 | T122 | 708 | ||||
ecc_uncorr_err | secret0 | 13212 | 1 | T2 | 48 | T5 | 451 | T7 | 359 | ||||
ecc_uncorr_err | hw_cfg1 | 20205 | 1 | T5 | 325 | T153 | 254 | T155 | 596 | ||||
ecc_uncorr_err | hw_cfg0 | 4609 | 1 | T2 | 10 | T154 | 518 | T156 | 51 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4952 | 1 | T6 | 373 | T156 | 152 | T279 | 418 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 827 | 1 | T157 | 69 | T221 | 2 | T224 | 2 | ||||
ecc_uncorr_err | owner_sw_cfg | 815 | 1 | T156 | 63 | T344 | 79 | T345 | 36 | ||||
ecc_uncorr_err | creator_sw_cfg | 948 | 1 | T156 | 116 | T157 | 62 | T221 | 2 | ||||
ecc_corr_err | secret2 | 68 | 1 | T28 | 1 | T72 | 2 | T66 | 7 | ||||
ecc_corr_err | secret1 | 119 | 1 | T72 | 1 | T66 | 2 | T82 | 1 | ||||
ecc_corr_err | secret0 | 121 | 1 | T28 | 4 | T13 | 1 | T72 | 6 | ||||
ecc_corr_err | hw_cfg1 | 252 | 1 | T7 | 3 | T72 | 2 | T66 | 7 | ||||
ecc_corr_err | hw_cfg0 | 216 | 1 | T28 | 10 | T72 | 7 | T156 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 130 | 1 | T6 | 3 | T28 | 9 | T156 | 1 | ||||
ecc_corr_err | rot_creator_auth_codesign | 140 | 1 | T28 | 6 | T72 | 4 | T66 | 5 | ||||
ecc_corr_err | owner_sw_cfg | 105 | 1 | T28 | 2 | T66 | 4 | T221 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 124 | 1 | T28 | 4 | T156 | 1 | T66 | 13 | ||||
no_err | secret2 | 5746 | 1 | T5 | 34 | T6 | 6 | T10 | 1 | ||||
no_err | secret1 | 9400 | 1 | T5 | 62 | T6 | 133 | T109 | 6 | ||||
no_err | secret0 | 9144 | 1 | T1 | 3 | T2 | 1 | T5 | 49 | ||||
no_err | hw_cfg1 | 11218 | 1 | T1 | 2 | T4 | 3 | T5 | 70 | ||||
no_err | hw_cfg0 | 12642 | 1 | T2 | 6 | T4 | 2 | T5 | 94 | ||||
no_err | rot_creator_auth_state | 8787 | 1 | T1 | 1 | T2 | 2 | T5 | 73 | ||||
no_err | rot_creator_auth_codesign | 9487 | 1 | T1 | 1 | T5 | 75 | T6 | 86 | ||||
no_err | owner_sw_cfg | 9488 | 1 | T1 | 1 | T2 | 1 | T5 | 86 | ||||
no_err | creator_sw_cfg | 8309 | 1 | T1 | 3 | T2 | 6 | T5 | 52 | ||||
no_err | vendor_test | 10032 | 1 | T1 | 6 | T2 | 6 | T4 | 2 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |