SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
creator_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
owner_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_codesign_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_state_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret2_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
vendor_test_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7775 | 1 | T1 | 3 | T2 | 7 | T3 | 4 | ||||
auto[1] | 4900 | 1 | T1 | 3 | T2 | 2 | T5 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7471 | 1 | T1 | 6 | T2 | 9 | T3 | 4 | ||||
auto[1] | 5204 | 1 | T4 | 2 | T5 | 74 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7560 | 1 | T1 | 3 | T2 | 9 | T3 | 4 | ||||
auto[1] | 5115 | 1 | T1 | 3 | T4 | 2 | T5 | 77 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12639 | 1 | T1 | 5 | T2 | 9 | T3 | 4 | ||||
auto[1] | 36 | 1 | T1 | 1 | T5 | 1 | T74 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 9527 | 1 | T1 | 6 | T2 | 7 | T3 | 4 | ||||
auto[1] | 3148 | 1 | T2 | 2 | T5 | 64 | T109 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7805 | 1 | T1 | 6 | T2 | 9 | T3 | 4 | ||||
auto[1] | 4870 | 1 | T5 | 76 | T109 | 1 | T27 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 10506 | 1 | T1 | 6 | T2 | 9 | T3 | 4 | ||||
auto[1] | 2169 | 1 | T5 | 10 | T27 | 16 | T13 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7611 | 1 | T1 | 3 | T2 | 9 | T3 | 4 | ||||
auto[1] | 5064 | 1 | T1 | 3 | T5 | 69 | T27 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7584 | 1 | T1 | 6 | T2 | 9 | T3 | 4 | ||||
auto[1] | 5091 | 1 | T4 | 2 | T5 | 75 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 9065 | 1 | T1 | 6 | T2 | 9 | T3 | 4 | ||||
auto[1] | 3610 | 1 | T5 | 39 | T10 | 3 | T27 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7667 | 1 | T1 | 3 | T2 | 7 | T3 | 4 | ||||
auto[1] | 5008 | 1 | T1 | 3 | T2 | 2 | T5 | 73 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |