Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49929	1			T1	4		T9	467		T12	294
access_err	62253	1			T1	12		T4	98		T5	259
write_blank_err	454	1			T7	2		T8	6		T14	16
ecc_uncorr_err	72686	1			T1	18		T7	254		T8	86
ecc_corr_err	1400	1			T1	4		T14	1		T116	1
no_err	92877	1			T1	18		T2	5		T4	115

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	769	1			T7	4		T8	12		T14	12
secret2	24050	1			T1	2		T2	1		T4	21
secret1	31988	1			T1	5		T4	38		T11	5
secret0	34230	1			T1	7		T2	3		T4	15
hw_cfg1	33618	1			T1	6		T4	26		T11	1
hw_cfg0	30631	1			T1	1		T4	10		T11	2
rot_creator_auth_state	23887	1			T1	5		T4	16		T11	9
rot_creator_auth_codesign	22176	1			T1	8		T4	24		T11	6
owner_sw_cfg	21187	1			T1	6		T4	15		T11	4
creator_sw_cfg	21058	1			T1	10		T4	20		T11	3
vendor_test	36005	1			T1	6		T2	1		T9	467

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2838	1			T117	2		T349	65		T350	402
fsm_err	secret1	4973	1			T123	109		T114	249		T18	259
fsm_err	secret0	4246	1			T12	294		T164	24		T101	18
fsm_err	hw_cfg1	2864	1			T5	55		T163	59		T351	306
fsm_err	hw_cfg0	5440	1			T18	346		T154	15		T155	202
fsm_err	rot_creator_auth_state	2488	1			T35	33		T352	36		T353	327
fsm_err	rot_creator_auth_codesign	3545	1			T171	59		T253	72		T354	16
fsm_err	owner_sw_cfg	2175	1			T116	24		T164	34		T355	228
fsm_err	creator_sw_cfg	2954	1			T1	4		T118	393		T257	499
fsm_err	vendor_test	18406	1			T9	467		T122	86		T69	64
access_err	life_cycle	769	1			T7	4		T8	12		T14	12
access_err	secret2	11024	1			T1	2		T4	13		T5	59
access_err	secret1	6016	1			T4	23		T61	3		T37	69
access_err	secret0	4310	1			T4	3		T5	1		T16	2
access_err	hw_cfg1	1193	1			T1	5		T4	5		T7	1
access_err	hw_cfg0	2287	1			T4	3		T16	1		T36	7
access_err	rot_creator_auth_state	6128	1			T1	2		T4	4		T5	44
access_err	rot_creator_auth_codesign	7825	1			T4	8		T5	37		T16	1
access_err	owner_sw_cfg	7352	1			T4	15		T5	38		T16	2
access_err	creator_sw_cfg	7977	1			T1	3		T4	14		T5	48
access_err	vendor_test	7372	1			T4	10		T5	32		T16	1
write_blank_err	secret2	10	1			T19	2		T35	1		T288	1
write_blank_err	secret1	29	1			T19	1		T15	1		T272	1
write_blank_err	secret0	50	1			T7	1		T67	1		T15	1
write_blank_err	hw_cfg1	68	1			T8	1		T14	1		T108	1
write_blank_err	hw_cfg0	21	1			T14	1		T356	1		T271	1
write_blank_err	rot_creator_auth_state	150	1			T7	1		T14	8		T19	7
write_blank_err	rot_creator_auth_codesign	65	1			T14	6		T35	7		T357	1
write_blank_err	owner_sw_cfg	10	1			T35	1		T357	1		T180	1
write_blank_err	creator_sw_cfg	18	1			T8	5		T358	1		T180	1
write_blank_err	vendor_test	33	1			T108	1		T357	2		T359	1
ecc_uncorr_err	secret2	4684	1			T164	24		T169	39		T102	22
ecc_uncorr_err	secret1	11483	1			T116	33		T102	40		T19	638
ecc_uncorr_err	secret0	16638	1			T1	6		T7	254		T169	72
ecc_uncorr_err	hw_cfg1	18451	1			T8	86		T108	184		T164	26
ecc_uncorr_err	hw_cfg0	10225	1			T14	379		T116	32		T168	38
ecc_uncorr_err	rot_creator_auth_state	6417	1			T168	20		T169	41		T35	647
ecc_uncorr_err	rot_creator_auth_codesign	1571	1			T1	6		T116	36		T171	129
ecc_uncorr_err	owner_sw_cfg	1902	1			T1	6		T116	29		T164	30
ecc_uncorr_err	creator_sw_cfg	1315	1			T168	13		T169	35		T170	114
ecc_corr_err	secret2	89	1			T169	1		T19	2		T130	7
ecc_corr_err	secret1	153	1			T1	2		T169	7		T170	2
ecc_corr_err	secret0	146	1			T116	1		T164	1		T168	3
ecc_corr_err	hw_cfg1	286	1			T1	1		T14	1		T164	1
ecc_corr_err	hw_cfg0	206	1			T164	1		T168	1		T170	1
ecc_corr_err	rot_creator_auth_state	130	1			T170	1		T84	6		T360	1
ecc_corr_err	rot_creator_auth_codesign	122	1			T171	3		T84	5		T131	2
ecc_corr_err	owner_sw_cfg	144	1			T168	6		T169	4		T170	2
ecc_corr_err	creator_sw_cfg	124	1			T1	1		T164	1		T169	1
no_err	secret2	5405	1			T2	1		T4	8		T11	14
no_err	secret1	9334	1			T1	3		T4	15		T11	5
no_err	secret0	8840	1			T1	1		T2	3		T4	12
no_err	hw_cfg1	10756	1			T4	21		T11	1		T5	61
no_err	hw_cfg0	12452	1			T1	1		T4	7		T11	2
no_err	rot_creator_auth_state	8574	1			T1	3		T4	12		T11	9
no_err	rot_creator_auth_codesign	9048	1			T1	2		T4	16		T11	6
no_err	owner_sw_cfg	9604	1			T11	4		T5	57		T16	6
no_err	creator_sw_cfg	8670	1			T1	2		T4	6		T11	3
no_err	vendor_test	10194	1			T1	6		T2	1		T4	18

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded