Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	59269	1			T4	68		T7	119		T25	97
access_err	65545	1			T1	46		T4	313		T5	624
write_blank_err	510	1			T1	10		T4	2		T5	22
ecc_uncorr_err	67331	1			T1	215		T4	163		T5	1436
ecc_corr_err	1602	1			T1	4		T5	2		T25	14
no_err	95209	1			T1	43		T2	12		T3	13

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	832	1			T1	7		T4	14		T5	21
secret2	28362	1			T1	14		T2	1		T3	1
secret1	30024	1			T1	4		T3	5		T4	81
secret0	37357	1			T1	227		T2	1		T4	52
hw_cfg1	39916	1			T1	3		T2	3		T3	5
hw_cfg0	26996	1			T1	6		T2	1		T3	2
rot_creator_auth_state	23610	1			T1	20		T2	3		T4	78
rot_creator_auth_codesign	22248	1			T1	14		T4	186		T5	176
owner_sw_cfg	20939	1			T1	10		T2	1		T4	90
creator_sw_cfg	24288	1			T1	3		T4	101		T5	133
vendor_test	34894	1			T1	10		T2	2		T4	79

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	6222	1			T336	310		T337	356		T142	411
fsm_err	secret1	6951	1			T7	119		T338	300		T339	163
fsm_err	secret0	3696	1			T158	2		T140	125		T150	360
fsm_err	hw_cfg1	5481	1			T201	333		T155	300		T14	1
fsm_err	hw_cfg0	6070	1			T177	242		T200	129		T97	119
fsm_err	rot_creator_auth_state	2403	1			T340	194		T341	120		T342	528
fsm_err	rot_creator_auth_codesign	3440	1			T4	68		T96	123		T245	46
fsm_err	owner_sw_cfg	2433	1			T68	129		T159	18		T343	53
fsm_err	creator_sw_cfg	6082	1			T171	163		T172	417		T68	379
fsm_err	vendor_test	16491	1			T25	97		T53	14		T110	267
access_err	life_cycle	832	1			T1	7		T4	14		T5	21
access_err	secret2	11304	1			T1	14		T4	84		T5	84
access_err	secret1	6448	1			T5	89		T10	22		T25	4
access_err	secret0	4750	1			T5	55		T7	4		T10	17
access_err	hw_cfg1	1311	1			T1	1		T4	1		T5	16
access_err	hw_cfg0	2486	1			T5	27		T10	1		T25	9
access_err	rot_creator_auth_state	6257	1			T1	8		T4	42		T5	60
access_err	rot_creator_auth_codesign	8467	1			T1	5		T4	58		T5	72
access_err	owner_sw_cfg	7407	1			T1	4		T4	26		T5	59
access_err	creator_sw_cfg	8233	1			T4	50		T5	62		T7	66
access_err	vendor_test	8050	1			T1	7		T4	38		T5	79
write_blank_err	secret2	13	1			T330	1		T344	2		T345	1
write_blank_err	secret1	18	1			T13	1		T142	1		T346	1
write_blank_err	secret0	59	1			T1	2		T5	1		T11	1
write_blank_err	hw_cfg1	76	1			T5	3		T7	1		T97	1
write_blank_err	hw_cfg0	19	1			T1	1		T4	1		T226	1
write_blank_err	rot_creator_auth_state	155	1			T1	6		T5	8		T11	1
write_blank_err	rot_creator_auth_codesign	65	1			T1	1		T4	1		T5	4
write_blank_err	owner_sw_cfg	45	1			T5	1		T142	1		T347	2
write_blank_err	creator_sw_cfg	25	1			T5	5		T142	1		T348	3
write_blank_err	vendor_test	35	1			T226	1		T13	1		T123	1
ecc_uncorr_err	secret2	5044	1			T215	28		T198	18		T349	63
ecc_uncorr_err	secret1	7095	1			T164	54		T158	3		T13	523
ecc_uncorr_err	secret0	19584	1			T1	215		T5	90		T11	180
ecc_uncorr_err	hw_cfg1	21458	1			T5	1346		T7	224		T97	459
ecc_uncorr_err	hw_cfg0	5680	1			T4	163		T164	219		T226	502
ecc_uncorr_err	rot_creator_auth_state	5949	1			T164	57		T174	31		T350	587
ecc_uncorr_err	rot_creator_auth_codesign	565	1			T164	47		T174	21		T217	25
ecc_uncorr_err	owner_sw_cfg	958	1			T159	23		T333	211		T351	32
ecc_uncorr_err	creator_sw_cfg	998	1			T174	38		T215	27		T160	13
ecc_corr_err	secret2	94	1			T164	1		T74	3		T69	2
ecc_corr_err	secret1	107	1			T25	2		T69	2		T128	7
ecc_corr_err	secret0	169	1			T1	3		T25	2		T63	1
ecc_corr_err	hw_cfg1	366	1			T5	2		T25	3		T164	3
ecc_corr_err	hw_cfg0	307	1			T1	1		T25	1		T164	1
ecc_corr_err	rot_creator_auth_state	99	1			T11	1		T74	5		T63	1
ecc_corr_err	rot_creator_auth_codesign	143	1			T74	2		T63	1		T69	4
ecc_corr_err	owner_sw_cfg	156	1			T164	2		T69	4		T128	4
ecc_corr_err	creator_sw_cfg	161	1			T25	6		T164	1		T69	1
no_err	secret2	5685	1			T2	1		T3	1		T4	12
no_err	secret1	9405	1			T1	4		T3	5		T4	81
no_err	secret0	9099	1			T1	7		T2	1		T4	52
no_err	hw_cfg1	11224	1			T1	2		T2	3		T3	5
no_err	hw_cfg0	12434	1			T1	4		T2	1		T3	2
no_err	rot_creator_auth_state	8747	1			T1	6		T2	3		T4	36
no_err	rot_creator_auth_codesign	9568	1			T1	8		T4	59		T5	100
no_err	owner_sw_cfg	9940	1			T1	6		T2	1		T4	64
no_err	creator_sw_cfg	8789	1			T1	3		T4	51		T5	66
no_err	vendor_test	10318	1			T1	3		T2	2		T4	41

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded