Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
dai_access_cmd	3	0	3	100.00	100	1	1	0
lc_creator_seed_sw_rw_en	2	0	2	100.00	100	1	1	2

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_access_secret2	6	0	6	100.00	100	1	1	0

Summary for Variable dai_access_cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for dai_access_cmd

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
dai_digest	2289	1			T1	4		T3	9		T7	1
dai_wr	4272	1			T1	1		T2	4		T3	2
dai_rd	7124	1			T1	4		T2	2		T3	15

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Summary for Variable lc_creator_seed_sw_rw_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5990

1

T1

3

T2

6

T3

25

auto[1]

7695

1

T1

6

T3

1

T7

2

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Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for dai_access_secret2

Bins

lc_creator_seed_sw_rw_en	dai_access_cmd	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	dai_digest	1208	1			T1	1		T3	8		T9	1
auto[0]	dai_wr	1498	1			T2	4		T3	2		T4	1
auto[0]	dai_rd	3284	1			T1	2		T2	2		T3	15
auto[1]	dai_digest	1081	1			T1	3		T3	1		T7	1
auto[1]	dai_wr	2774	1			T1	1		T9	3		T10	5
auto[1]	dai_rd	3840	1			T1	2		T7	1		T9	3