Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47202	1			T2	214		T8	29		T101	127
access_err	61937	1			T1	33		T2	17		T3	186
write_blank_err	476	1			T5	9		T6	2		T13	2
ecc_uncorr_err	67769	1			T4	56		T5	938		T6	290
ecc_corr_err	1180	1			T4	5		T32	12		T35	38
no_err	91093	1			T1	67		T2	31		T3	280

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	697	1			T5	13		T6	7		T13	5
secret2	23399	1			T1	11		T2	9		T3	42
secret1	29384	1			T1	14		T2	4		T3	26
secret0	36719	1			T3	33		T7	2		T4	57
hw_cfg1	35628	1			T1	10		T2	6		T3	48
hw_cfg0	29222	1			T1	6		T2	214		T3	37
rot_creator_auth_state	22706	1			T1	13		T2	11		T3	38
rot_creator_auth_codesign	21760	1			T1	10		T2	11		T3	72
owner_sw_cfg	20393	1			T1	15		T2	2		T3	57
creator_sw_cfg	19116	1			T1	10		T2	3		T3	46
vendor_test	30633	1			T1	11		T2	2		T3	67

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	1428	1			T146	4		T322	98		T218	21
fsm_err	secret1	4608	1			T94	103		T208	69		T323	423
fsm_err	secret0	4637	1			T6	12		T324	46		T121	117
fsm_err	hw_cfg1	4137	1			T325	6		T326	418		T327	337
fsm_err	hw_cfg0	6329	1			T2	214		T5	138		T117	309
fsm_err	rot_creator_auth_state	3198	1			T241	216		T284	551		T286	573
fsm_err	rot_creator_auth_codesign	4082	1			T101	127		T89	547		T328	307
fsm_err	owner_sw_cfg	3238	1			T329	7		T148	54		T149	19
fsm_err	creator_sw_cfg	2302	1			T8	29		T5	511		T330	138
fsm_err	vendor_test	13243	1			T35	315		T6	19		T51	142
access_err	life_cycle	697	1			T5	13		T6	7		T13	5
access_err	secret2	10757	1			T1	7		T2	9		T3	41
access_err	secret1	5839	1			T1	1		T9	31		T35	11
access_err	secret0	4710	1			T9	11		T32	4		T35	15
access_err	hw_cfg1	1220	1			T1	1		T3	1		T9	9
access_err	hw_cfg0	2173	1			T9	8		T32	1		T35	13
access_err	rot_creator_auth_state	5990	1			T1	1		T2	7		T3	24
access_err	rot_creator_auth_codesign	8060	1			T1	6		T3	33		T9	26
access_err	owner_sw_cfg	7099	1			T1	6		T3	31		T7	1
access_err	creator_sw_cfg	7837	1			T1	6		T2	1		T3	20
access_err	vendor_test	7555	1			T1	5		T3	36		T9	40
write_blank_err	secret2	13	1			T152	1		T331	1		T332	1
write_blank_err	secret1	28	1			T5	2		T94	1		T121	2
write_blank_err	secret0	51	1			T93	1		T94	1		T333	1
write_blank_err	hw_cfg1	69	1			T5	4		T6	1		T13	1
write_blank_err	hw_cfg0	22	1			T94	1		T99	1		T69	2
write_blank_err	rot_creator_auth_state	179	1			T5	2		T6	1		T94	4
write_blank_err	rot_creator_auth_codesign	58	1			T13	1		T121	7		T334	3
write_blank_err	owner_sw_cfg	15	1			T335	2		T70	1		T138	1
write_blank_err	creator_sw_cfg	11	1			T336	1		T135	1		T337	1
write_blank_err	vendor_test	30	1			T5	1		T94	1		T152	1
ecc_uncorr_err	secret2	5597	1			T152	488		T338	63		T159	72
ecc_uncorr_err	secret1	9667	1			T5	367		T94	259		T121	440
ecc_uncorr_err	secret0	18642	1			T4	56		T93	420		T94	546
ecc_uncorr_err	hw_cfg1	19365	1			T5	571		T6	290		T13	133
ecc_uncorr_err	hw_cfg0	8164	1			T99	582		T69	657		T339	41
ecc_uncorr_err	rot_creator_auth_state	4610	1			T147	14		T340	310		T341	27
ecc_uncorr_err	rot_creator_auth_codesign	650	1			T159	128		T202	63		T203	4
ecc_uncorr_err	owner_sw_cfg	617	1			T342	12		T147	52		T159	68
ecc_uncorr_err	creator_sw_cfg	457	1			T147	4		T341	36		T202	73
ecc_corr_err	secret2	64	1			T32	2		T66	8		T80	1
ecc_corr_err	secret1	118	1			T4	2		T35	5		T51	6
ecc_corr_err	secret0	103	1			T35	2		T66	12		T80	1
ecc_corr_err	hw_cfg1	218	1			T32	5		T35	9		T5	4
ecc_corr_err	hw_cfg0	256	1			T4	2		T32	2		T35	14
ecc_corr_err	rot_creator_auth_state	117	1			T32	2		T35	2		T51	2
ecc_corr_err	rot_creator_auth_codesign	123	1			T4	1		T35	3		T13	1
ecc_corr_err	owner_sw_cfg	100	1			T32	1		T35	3		T51	2
ecc_corr_err	creator_sw_cfg	81	1			T88	2		T66	2		T80	2
no_err	secret2	5540	1			T1	4		T3	1		T7	1
no_err	secret1	9124	1			T1	13		T2	4		T3	26
no_err	secret0	8576	1			T3	33		T7	2		T4	1
no_err	hw_cfg1	10619	1			T1	9		T2	6		T3	47
no_err	hw_cfg0	12278	1			T1	6		T3	37		T7	7
no_err	rot_creator_auth_state	8612	1			T1	12		T2	4		T3	14
no_err	rot_creator_auth_codesign	8787	1			T1	4		T2	11		T3	39
no_err	owner_sw_cfg	9324	1			T1	9		T2	2		T3	26
no_err	creator_sw_cfg	8428	1			T1	4		T2	2		T3	26
no_err	vendor_test	9805	1			T1	6		T2	2		T3	31

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded