Summary for Variable flash_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for flash_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
flash_addr_key |
5734 |
1 |
|
|
T2 |
8 |
|
T3 |
53 |
|
T4 |
2 |
flash_data_key |
5760 |
1 |
|
|
T2 |
8 |
|
T3 |
54 |
|
T4 |
2 |
Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6779 |
1 |
|
|
T2 |
16 |
|
T3 |
34 |
|
T10 |
8 |
auto[1] |
4715 |
1 |
|
|
T3 |
73 |
|
T4 |
4 |
|
T11 |
8 |
Summary for Cross flash_req_lock_cross
Samples crossed: flash_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for flash_req_lock_cross
Bins
flash_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
flash_addr_key |
auto[0] |
3378 |
1 |
|
|
T2 |
8 |
|
T3 |
16 |
|
T10 |
4 |
flash_addr_key |
auto[1] |
2356 |
1 |
|
|
T3 |
37 |
|
T4 |
2 |
|
T11 |
4 |
flash_data_key |
auto[0] |
3401 |
1 |
|
|
T2 |
8 |
|
T3 |
18 |
|
T10 |
4 |
flash_data_key |
auto[1] |
2359 |
1 |
|
|
T3 |
36 |
|
T4 |
2 |
|
T11 |
4 |