Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 170819 1 T1 132 T2 75 T3 6
all_pins[1] 170819 1 T1 132 T2 75 T3 6



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 278957 1 T1 215 T2 150 T3 9
values[0x1] 62681 1 T1 49 T3 3 T5 6
transitions[0x0=>0x1] 44744 1 T1 24 T3 2 T5 6
transitions[0x1=>0x0] 44675 1 T1 24 T3 2 T5 6



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 125990 1 T1 96 T2 75 T3 5
all_pins[0] values[0x1] 44829 1 T1 36 T3 1 T5 5
all_pins[0] transitions[0x0=>0x1] 35910 1 T1 24 T5 5 T4 45
all_pins[0] transitions[0x1=>0x0] 8933 1 T1 1 T3 1 T5 1
all_pins[1] values[0x0] 152967 1 T1 119 T2 75 T3 4
all_pins[1] values[0x1] 17852 1 T1 13 T3 2 T5 1
all_pins[1] transitions[0x0=>0x1] 8834 1 T3 2 T5 1 T9 54
all_pins[1] transitions[0x1=>0x0] 35742 1 T1 23 T3 1 T5 5

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