SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 51756 | 1 | T5 | 45 | T8 | 24 | T28 | 50 | ||||
access_err | 63022 | 1 | T1 | 12 | T3 | 1 | T5 | 3 | ||||
write_blank_err | 431 | 1 | T1 | 6 | T6 | 2 | T7 | 1 | ||||
ecc_uncorr_err | 61020 | 1 | T1 | 113 | T5 | 343 | T158 | 156 | ||||
ecc_corr_err | 1275 | 1 | T5 | 3 | T12 | 45 | T28 | 4 | ||||
no_err | 91496 | 1 | T1 | 28 | T3 | 7 | T5 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 744 | 1 | T1 | 5 | T6 | 3 | T7 | 7 | ||||
secret2 | 20905 | 1 | T1 | 4 | T3 | 1 | T5 | 48 | ||||
secret1 | 29196 | 1 | T1 | 7 | T3 | 1 | T5 | 82 | ||||
secret0 | 36224 | 1 | T1 | 116 | T4 | 9 | T9 | 51 | ||||
hw_cfg1 | 34161 | 1 | T1 | 6 | T3 | 3 | T5 | 89 | ||||
hw_cfg0 | 25469 | 1 | T1 | 2 | T5 | 44 | T4 | 7 | ||||
rot_creator_auth_state | 21756 | 1 | T1 | 2 | T5 | 52 | T4 | 3 | ||||
rot_creator_auth_codesign | 23357 | 1 | T1 | 5 | T5 | 53 | T4 | 6 | ||||
owner_sw_cfg | 20104 | 1 | T3 | 3 | T5 | 40 | T4 | 4 | ||||
creator_sw_cfg | 23010 | 1 | T1 | 3 | T4 | 10 | T9 | 53 | ||||
vendor_test | 34074 | 1 | T1 | 9 | T5 | 10 | T4 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 1917 | 1 | T375 | 108 | T246 | 327 | T231 | 29 | ||||
fsm_err | secret1 | 6143 | 1 | T142 | 296 | T189 | 136 | T376 | 28 | ||||
fsm_err | secret0 | 3940 | 1 | T254 | 346 | T59 | 121 | T372 | 231 | ||||
fsm_err | hw_cfg1 | 3605 | 1 | T59 | 504 | T27 | 151 | T141 | 245 | ||||
fsm_err | hw_cfg0 | 4778 | 1 | T8 | 24 | T169 | 1 | T377 | 21 | ||||
fsm_err | rot_creator_auth_state | 2345 | 1 | T5 | 45 | T265 | 28 | T378 | 21 | ||||
fsm_err | rot_creator_auth_codesign | 4365 | 1 | T255 | 278 | T141 | 90 | T180 | 58 | ||||
fsm_err | owner_sw_cfg | 3048 | 1 | T161 | 656 | T162 | 42 | T214 | 50 | ||||
fsm_err | creator_sw_cfg | 5088 | 1 | T191 | 447 | T379 | 21 | T380 | 205 | ||||
fsm_err | vendor_test | 16527 | 1 | T28 | 50 | T131 | 28 | T63 | 509 | ||||
access_err | life_cycle | 744 | 1 | T1 | 5 | T6 | 3 | T7 | 7 | ||||
access_err | secret2 | 11159 | 1 | T1 | 4 | T3 | 1 | T5 | 2 | ||||
access_err | secret1 | 6229 | 1 | T9 | 48 | T11 | 30 | T12 | 8 | ||||
access_err | secret0 | 5041 | 1 | T9 | 45 | T11 | 34 | T35 | 4 | ||||
access_err | hw_cfg1 | 1206 | 1 | T5 | 1 | T9 | 3 | T12 | 4 | ||||
access_err | hw_cfg0 | 2131 | 1 | T9 | 19 | T11 | 13 | T97 | 8 | ||||
access_err | rot_creator_auth_state | 6058 | 1 | T9 | 35 | T11 | 20 | T150 | 1 | ||||
access_err | rot_creator_auth_codesign | 7974 | 1 | T1 | 3 | T9 | 38 | T11 | 43 | ||||
access_err | owner_sw_cfg | 6964 | 1 | T9 | 2 | T11 | 22 | T12 | 8 | ||||
access_err | creator_sw_cfg | 7838 | 1 | T9 | 34 | T11 | 32 | T63 | 4 | ||||
access_err | vendor_test | 7678 | 1 | T9 | 32 | T11 | 32 | T12 | 1 | ||||
write_blank_err | secret2 | 6 | 1 | T381 | 1 | T382 | 1 | T317 | 1 | ||||
write_blank_err | secret1 | 25 | 1 | T383 | 1 | T384 | 1 | T385 | 1 | ||||
write_blank_err | secret0 | 51 | 1 | T1 | 1 | T6 | 1 | T13 | 1 | ||||
write_blank_err | hw_cfg1 | 70 | 1 | T7 | 1 | T169 | 1 | T371 | 1 | ||||
write_blank_err | hw_cfg0 | 19 | 1 | T34 | 1 | T195 | 1 | T208 | 1 | ||||
write_blank_err | rot_creator_auth_state | 98 | 1 | T6 | 1 | T168 | 1 | T59 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 77 | 1 | T169 | 1 | T191 | 3 | T195 | 6 | ||||
write_blank_err | owner_sw_cfg | 12 | 1 | T314 | 2 | T386 | 4 | T355 | 1 | ||||
write_blank_err | creator_sw_cfg | 35 | 1 | T235 | 1 | T387 | 2 | T287 | 1 | ||||
write_blank_err | vendor_test | 38 | 1 | T1 | 5 | T388 | 1 | T383 | 1 | ||||
ecc_uncorr_err | secret2 | 2481 | 1 | T5 | 45 | T216 | 13 | T381 | 554 | ||||
ecc_uncorr_err | secret1 | 7817 | 1 | T5 | 81 | T158 | 50 | T286 | 56 | ||||
ecc_uncorr_err | secret0 | 18687 | 1 | T1 | 113 | T6 | 133 | T167 | 79 | ||||
ecc_uncorr_err | hw_cfg1 | 18023 | 1 | T5 | 86 | T7 | 618 | T169 | 110 | ||||
ecc_uncorr_err | hw_cfg0 | 5901 | 1 | T5 | 43 | T167 | 151 | T34 | 694 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4633 | 1 | T167 | 147 | T168 | 423 | T59 | 230 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1481 | 1 | T5 | 50 | T179 | 61 | T286 | 48 | ||||
ecc_uncorr_err | owner_sw_cfg | 600 | 1 | T5 | 38 | T158 | 56 | T167 | 73 | ||||
ecc_uncorr_err | creator_sw_cfg | 1397 | 1 | T158 | 50 | T167 | 78 | T206 | 9 | ||||
ecc_corr_err | secret2 | 88 | 1 | T12 | 7 | T74 | 1 | T286 | 1 | ||||
ecc_corr_err | secret1 | 119 | 1 | T69 | 6 | T92 | 1 | T74 | 6 | ||||
ecc_corr_err | secret0 | 123 | 1 | T12 | 7 | T69 | 4 | T179 | 4 | ||||
ecc_corr_err | hw_cfg1 | 231 | 1 | T12 | 1 | T28 | 1 | T69 | 3 | ||||
ecc_corr_err | hw_cfg0 | 216 | 1 | T5 | 1 | T12 | 5 | T69 | 4 | ||||
ecc_corr_err | rot_creator_auth_state | 144 | 1 | T5 | 1 | T12 | 3 | T69 | 3 | ||||
ecc_corr_err | rot_creator_auth_codesign | 150 | 1 | T5 | 1 | T12 | 11 | T28 | 2 | ||||
ecc_corr_err | owner_sw_cfg | 100 | 1 | T12 | 10 | T28 | 1 | T69 | 5 | ||||
ecc_corr_err | creator_sw_cfg | 104 | 1 | T12 | 1 | T35 | 2 | T92 | 4 | ||||
no_err | secret2 | 5254 | 1 | T5 | 1 | T4 | 4 | T9 | 7 | ||||
no_err | secret1 | 8863 | 1 | T1 | 7 | T3 | 1 | T5 | 1 | ||||
no_err | secret0 | 8382 | 1 | T1 | 2 | T4 | 9 | T9 | 6 | ||||
no_err | hw_cfg1 | 11026 | 1 | T1 | 6 | T3 | 3 | T5 | 2 | ||||
no_err | hw_cfg0 | 12424 | 1 | T1 | 2 | T4 | 7 | T9 | 32 | ||||
no_err | rot_creator_auth_state | 8478 | 1 | T1 | 2 | T5 | 6 | T4 | 3 | ||||
no_err | rot_creator_auth_codesign | 9310 | 1 | T1 | 2 | T5 | 2 | T4 | 6 | ||||
no_err | owner_sw_cfg | 9380 | 1 | T3 | 3 | T5 | 2 | T4 | 4 | ||||
no_err | creator_sw_cfg | 8548 | 1 | T1 | 3 | T4 | 10 | T9 | 19 | ||||
no_err | vendor_test | 9831 | 1 | T1 | 4 | T5 | 10 | T4 | 6 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |