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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10204 1 T1 3 T2 2 T3 1
true 16659 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11149 1 T1 3 T2 2 T3 2
true 16717 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T123 2 T107 2 T186 2
others[1] 120 1 T50 4 T98 4 T102 6
others[2] 72 1 T50 2 T98 2 T100 2
others[3] 96 1 T6 2 T50 2 T100 2
others[4] 102 1 T50 4 T51 2 T97 2
others[5] 82 1 T30 2 T50 2 T99 2
others[6] 82 1 T50 2 T99 4 T108 2
others[7] 98 1 T30 2 T50 4 T99 4
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T99 2 T102 2 T226 2
others[1] 76 1 T102 2 T186 6 T131 6
others[2] 94 1 T50 2 T99 2 T103 2
others[3] 82 1 T99 2 T103 6 T186 6
others[4] 88 1 T103 4 T107 2 T186 2
others[5] 110 1 T50 2 T98 2 T99 4
others[6] 98 1 T50 2 T101 2 T102 2
others[7] 104 1 T50 6 T99 2 T100 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T50 4 T99 2 T102 4
others[1] 92 1 T50 4 T103 4 T107 2
others[2] 72 1 T50 4 T107 2 T186 2
others[3] 76 1 T50 4 T100 2 T107 2
others[4] 96 1 T50 2 T98 2 T102 4
others[5] 80 1 T50 2 T98 2 T123 4
others[6] 86 1 T97 2 T99 4 T103 2
others[7] 106 1 T50 2 T98 4 T99 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T50 4 T99 4 T102 2
others[1] 60 1 T50 2 T98 2 T99 2
others[2] 62 1 T6 2 T30 2 T107 2
others[3] 60 1 T98 2 T136 2 T107 2
others[4] 68 1 T50 2 T101 2 T103 2
others[5] 46 1 T50 4 T99 4 T332 2
others[6] 58 1 T50 2 T99 4 T101 2
others[7] 54 1 T30 2 T98 2 T99 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T50 4 T98 2 T99 2
others[1] 74 1 T50 2 T101 2 T370 2
others[2] 64 1 T50 2 T99 2 T101 2
others[3] 112 1 T6 2 T50 4 T51 2
others[4] 98 1 T29 2 T50 2 T99 2
others[5] 90 1 T30 2 T50 2 T52 2
others[6] 84 1 T6 2 T50 2 T98 2
others[7] 106 1 T6 4 T50 4 T102 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 46 1 T100 2 T102 6 T103 2
others[1] 26 1 T99 2 T104 2 T188 2
others[2] 24 1 T103 2 T104 2 T107 2
others[3] 30 1 T100 2 T187 2 T188 2
others[4] 24 1 T264 2 T371 2 T372 2
others[5] 50 1 T102 2 T186 4 T261 4
others[6] 36 1 T102 2 T104 2 T186 2
others[7] 54 1 T103 6 T186 2 T188 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T6 2 T50 2 T51 2
others[1] 92 1 T50 8 T99 4 T100 2
others[2] 94 1 T50 4 T99 4 T107 8
others[3] 92 1 T50 2 T99 2 T101 2
others[4] 72 1 T50 4 T102 2 T103 2
others[5] 108 1 T6 2 T99 2 T100 2
others[6] 80 1 T50 2 T99 2 T102 2
others[7] 90 1 T50 2 T98 2 T100 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T99 2 T102 2 T103 2
others[1] 82 1 T50 4 T98 2 T104 2
others[2] 86 1 T50 4 T107 4 T247 4
others[3] 86 1 T50 2 T52 2 T99 2
others[4] 90 1 T99 2 T100 2 T103 2
others[5] 104 1 T6 2 T50 6 T99 2
others[6] 70 1 T50 2 T99 2 T102 4
others[7] 104 1 T50 4 T97 4 T99 4
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T50 4 T99 4 T102 4
others[1] 112 1 T50 4 T98 2 T101 2
others[2] 116 1 T6 2 T30 2 T51 2
others[3] 96 1 T50 4 T102 2 T107 2
others[4] 94 1 T99 2 T100 2 T107 4
others[5] 108 1 T50 4 T102 2 T123 2
others[6] 106 1 T50 2 T98 2 T99 2
others[7] 82 1 T50 2 T97 2 T98 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T99 6 T103 6 T186 2
others[1] 82 1 T100 2 T102 2 T107 2
others[2] 70 1 T50 4 T51 2 T102 2
others[3] 92 1 T50 2 T102 2 T107 2
others[4] 98 1 T50 2 T52 2 T136 2
others[5] 86 1 T30 2 T100 2 T101 2
others[6] 102 1 T99 2 T123 2 T186 2
others[7] 122 1 T30 2 T99 4 T100 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T50 4 T103 4 T107 4
others[1] 112 1 T50 2 T51 2 T98 2
others[2] 68 1 T6 2 T123 2 T329 2
others[3] 78 1 T50 2 T100 2 T101 2
others[4] 92 1 T50 2 T102 2 T104 2
others[5] 76 1 T99 2 T102 2 T235 2
others[6] 110 1 T98 2 T102 4 T136 2
others[7] 88 1 T30 2 T99 2 T101 2
false 14256 1 T1 4 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T14 1 T18 1 T326 1
others[1] 39 1 T7 1 T38 1 T18 1
others[2] 28 1 T50 2 T38 1 T261 2
others[3] 35 1 T38 1 T326 1 T261 2
others[4] 30 1 T38 1 T18 1 T214 1
others[5] 28 1 T38 1 T337 1 T333 1
others[6] 29 1 T14 2 T18 1 T326 1
others[7] 35 1 T7 1 T14 1 T38 1
false 14256 1 T1 4 T2 4 T3 3
true 2249 1 T1 1 T11 1 T6 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 41 1 T50 2 T38 1 T18 1
others[1] 29 1 T38 2 T326 1 T337 2
others[2] 33 1 T38 1 T332 2 T329 2
others[3] 22 1 T38 1 T18 1 T337 1
others[4] 29 1 T7 2 T14 1 T38 1
others[5] 35 1 T14 1 T243 1 T18 1
others[6] 22 1 T14 1 T18 1 T333 1
others[7] 40 1 T14 1 T326 1 T261 4
false 11637 1 T1 3 T2 2 T3 2
true 18912 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T50 2 T51 2 T102 4
others[1] 82 1 T50 2 T97 2 T98 4
others[2] 86 1 T100 2 T102 2 T103 2
others[3] 106 1 T6 2 T30 2 T99 2
others[4] 96 1 T50 2 T98 2 T107 2
others[5] 64 1 T50 4 T99 2 T103 2
others[6] 104 1 T30 2 T50 4 T99 6
others[7] 124 1 T50 6 T99 2 T100 2
false 7858 1 T1 3 T2 2 T3 2
true 16756 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T99 2 T186 4 T210 2
others[1] 78 1 T50 2 T99 6 T102 2
others[2] 104 1 T99 2 T102 4 T103 6
others[3] 86 1 T104 2 T108 2 T186 2
others[4] 104 1 T50 2 T100 2 T101 4
others[5] 74 1 T98 2 T103 2 T107 2
others[6] 86 1 T50 4 T99 2 T100 2
others[7] 110 1 T50 4 T103 6 T186 4
false 6833 1 T1 3 T2 2 T3 1
true 16520 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T50 4 T98 2 T102 2
others[1] 78 1 T50 2 T103 2 T107 2
others[2] 92 1 T98 4 T99 2 T102 2
others[3] 84 1 T50 4 T99 2 T100 2
others[4] 106 1 T50 2 T107 2 T108 2
others[5] 64 1 T50 2 T99 2 T123 2
others[6] 82 1 T50 2 T97 2 T98 2
others[7] 106 1 T50 6 T99 2 T102 4
false 7283 1 T1 3 T2 2 T3 1
true 16547 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 25 1 T50 2 T99 2 T18 1
others[1] 25 1 T38 1 T326 3 T261 2
others[2] 24 1 T14 2 T333 2 T328 1
others[3] 32 1 T14 1 T38 1 T107 2
others[4] 38 1 T7 1 T38 1 T326 1
others[5] 35 1 T102 2 T18 1 T131 2
others[6] 35 1 T7 1 T50 4 T38 1
others[7] 23 1 T14 1 T38 1 T131 2
false 11579 1 T1 3 T2 2 T3 2
true 18845 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 56 1 T99 2 T103 2 T123 2
others[1] 48 1 T108 2 T186 2 T329 2
others[2] 70 1 T6 2 T50 6 T186 4
others[3] 42 1 T98 2 T101 2 T107 2
others[4] 54 1 T30 4 T98 2 T99 2
others[5] 56 1 T50 2 T99 4 T370 2
others[6] 78 1 T99 6 T102 2 T186 2
others[7] 70 1 T50 6 T98 2 T99 2
false 9104 1 T1 3 T2 2 T3 2
true 16752 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 43 1 T38 1 T243 1 T18 1
others[1] 38 1 T6 2 T14 1 T38 2
others[2] 33 1 T110 1 T38 2 T102 2
others[3] 34 1 T38 1 T243 1 T328 1
others[4] 32 1 T7 1 T30 2 T14 1
others[5] 28 1 T14 1 T38 1 T18 1
others[6] 15 1 T337 1 T19 1 T277 1
others[7] 33 1 T50 2 T28 1 T261 4
false 11531 1 T1 3 T2 2 T3 2
true 18842 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T50 6 T51 2 T103 4
others[1] 82 1 T6 2 T50 4 T102 2
others[2] 82 1 T101 2 T103 2 T136 2
others[3] 102 1 T50 8 T100 2 T104 2
others[4] 86 1 T50 2 T99 2 T102 4
others[5] 90 1 T29 2 T52 2 T98 2
others[6] 82 1 T6 2 T50 2 T102 2
others[7] 104 1 T6 4 T30 2 T98 2
false 7783 1 T1 3 T2 2 T3 2
true 16675 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 20 1 T14 2 T99 2 T329 2
others[1] 34 1 T7 1 T18 2 T326 1
others[2] 39 1 T14 2 T333 1 T275 1
others[3] 33 1 T38 2 T18 1 T333 2
others[4] 32 1 T38 1 T186 2 T19 1
others[5] 30 1 T337 2 T19 1 T334 2
others[6] 31 1 T373 2 T18 2 T19 2
others[7] 32 1 T97 2 T247 2 T329 2
false 11481 1 T1 3 T2 2 T3 2
true 18817 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 40 1 T100 2 T102 4 T107 2
others[1] 42 1 T100 2 T103 2 T104 4
others[2] 26 1 T88 2 T374 2 T375 2
others[3] 26 1 T186 2 T187 2 T131 2
others[4] 32 1 T102 2 T186 4 T264 2
others[5] 48 1 T102 2 T103 4 T186 4
others[6] 36 1 T102 2 T103 2 T188 2
others[7] 40 1 T99 2 T103 2 T104 2
false 9996 1 T1 3 T2 2 T3 2
true 16734 1 T1 5 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T6 2 T98 2 T99 4
others[1] 82 1 T6 2 T50 6 T99 4
others[2] 82 1 T50 2 T99 2 T108 2
others[3] 110 1 T50 6 T99 2 T100 2
others[4] 70 1 T50 2 T99 2 T107 4
others[5] 90 1 T100 2 T102 2 T103 2
others[6] 78 1 T50 4 T99 2 T100 2
others[7] 124 1 T50 4 T51 2 T103 4
false 7002 1 T1 3 T2 2 T3 1
true 16525 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T50 4 T99 2 T103 2
others[1] 96 1 T50 2 T97 2 T99 4
others[2] 88 1 T50 4 T102 4 T123 2
others[3] 76 1 T99 2 T102 2 T107 2
others[4] 76 1 T52 2 T98 2 T103 2
others[5] 68 1 T50 4 T99 2 T102 2
others[6] 98 1 T6 2 T50 2 T97 2
others[7] 112 1 T50 6 T99 4 T103 2
false 7002 1 T1 3 T2 2 T3 1
true 16525 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T50 2 T98 2 T226 2
others[1] 98 1 T30 2 T50 4 T98 2
others[2] 102 1 T6 2 T50 2 T97 2
others[3] 120 1 T52 2 T98 2 T102 4
others[4] 96 1 T50 4 T102 6 T103 4
others[5] 88 1 T50 2 T51 2 T99 2
others[6] 100 1 T50 2 T99 4 T102 2
others[7] 114 1 T50 4 T99 2 T102 2
false 6352 1 T1 2 T2 2 T3 1
true 16510 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T50 2 T100 2 T102 6
others[1] 86 1 T101 2 T102 2 T103 2
others[2] 82 1 T30 2 T108 2 T186 2
others[3] 86 1 T30 2 T50 6 T103 2
others[4] 112 1 T99 2 T100 2 T107 2
others[5] 86 1 T99 4 T100 2 T102 2
others[6] 86 1 T99 4 T103 2 T136 2
others[7] 102 1 T51 2 T52 2 T99 2
false 6352 1 T1 2 T2 2 T3 1
true 16510 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 52 1 T247 2 T332 2 T263 2
others[1] 42 1 T99 2 T102 4 T261 2
others[2] 46 1 T39 2 T99 6 T186 4
others[3] 44 1 T261 2 T376 2 T377 2
others[4] 54 1 T108 2 T226 2 T261 2
others[5] 64 1 T6 2 T102 2 T104 2
others[6] 58 1 T50 2 T99 4 T108 2
others[7] 78 1 T99 4 T102 2 T103 6
false 6935 1 T1 2 T2 1 T3 1
true 17895 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T50 2 T136 2 T370 4
others[1] 56 1 T50 2 T99 2 T102 2
others[2] 58 1 T99 2 T103 2 T247 2
others[3] 70 1 T50 4 T98 2 T99 2
others[4] 50 1 T50 4 T99 4 T103 2
others[5] 70 1 T50 2 T52 2 T186 2
others[6] 66 1 T6 2 T103 2 T186 2
others[7] 70 1 T6 2 T99 4 T102 2
false 6935 1 T1 2 T2 1 T3 1
true 17895 1 T1 5 T2 4 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 24 1 T14 2 T243 1 T131 2
others[1] 29 1 T50 2 T38 1 T243 2
others[2] 46 1 T7 1 T50 2 T326 1
others[3] 42 1 T38 1 T326 1 T261 2
others[4] 30 1 T7 1 T14 1 T18 2
others[5] 17 1 T7 1 T14 1 T28 1
others[6] 36 1 T50 4 T110 1 T38 2
others[7] 26 1 T7 1 T14 1 T17 1
false 11710 1 T1 3 T2 3 T3 2
true 18957 1 T1 5 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 106 1 T98 2 T100 2 T103 4
others[1] 92 1 T50 2 T99 2 T102 4
others[2] 90 1 T30 2 T101 2 T123 2
others[3] 62 1 T50 2 T98 2 T101 2
others[4] 80 1 T50 2 T102 2 T123 2
others[5] 84 1 T6 2 T103 4 T136 2
others[6] 88 1 T50 2 T51 2 T99 4
others[7] 112 1 T50 2 T99 2 T102 2
false 7877 1 T1 3 T2 3 T3 2
true 16726 1 T1 5 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 39 1 T99 2 T378 2 T333 2
others[1] 34 1 T14 2 T50 2 T326 2
others[2] 19 1 T14 1 T38 1 T131 2
others[3] 29 1 T14 1 T50 2 T38 1
others[4] 37 1 T38 1 T243 1 T18 1
others[5] 27 1 T7 2 T38 1 T326 1
others[6] 25 1 T107 2 T18 1 T333 2
others[7] 27 1 T50 2 T38 1 T326 1
false 14256 1 T1 4 T2 4 T3 3
true 2219 1 T1 1 T11 1 T6 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%