SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 46465 | 1 | T1 | 21 | T106 | 254 | T146 | 376 | ||||
access_err | 58001 | 1 | T1 | 6 | T11 | 22 | T6 | 283 | ||||
write_blank_err | 420 | 1 | T7 | 2 | T9 | 1 | T10 | 1 | ||||
ecc_uncorr_err | 69160 | 1 | T7 | 21 | T29 | 17 | T9 | 509 | ||||
ecc_corr_err | 1393 | 1 | T11 | 9 | T29 | 13 | T15 | 1 | ||||
no_err | 86324 | 1 | T1 | 11 | T11 | 35 | T6 | 189 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 615 | 1 | T7 | 4 | T10 | 4 | T15 | 11 | ||||
secret2 | 23162 | 1 | T1 | 3 | T11 | 16 | T6 | 44 | ||||
secret1 | 27544 | 1 | T1 | 21 | T11 | 6 | T6 | 31 | ||||
secret0 | 42601 | 1 | T1 | 1 | T11 | 5 | T6 | 35 | ||||
hw_cfg1 | 35336 | 1 | T1 | 2 | T11 | 3 | T6 | 25 | ||||
hw_cfg0 | 22118 | 1 | T1 | 2 | T6 | 72 | T7 | 8 | ||||
rot_creator_auth_state | 20416 | 1 | T11 | 9 | T6 | 50 | T7 | 34 | ||||
rot_creator_auth_codesign | 20321 | 1 | T11 | 11 | T6 | 71 | T7 | 22 | ||||
owner_sw_cfg | 19285 | 1 | T11 | 3 | T6 | 49 | T7 | 19 | ||||
creator_sw_cfg | 18902 | 1 | T1 | 4 | T11 | 4 | T6 | 44 | ||||
vendor_test | 31463 | 1 | T1 | 5 | T11 | 9 | T6 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 2402 | 1 | T50 | 269 | T99 | 34 | T330 | 26 | ||||
fsm_err | secret1 | 4448 | 1 | T1 | 21 | T213 | 146 | T131 | 458 | ||||
fsm_err | secret0 | 6416 | 1 | T14 | 74 | T229 | 44 | T182 | 247 | ||||
fsm_err | hw_cfg1 | 4034 | 1 | T331 | 78 | T332 | 185 | T333 | 2 | ||||
fsm_err | hw_cfg0 | 4256 | 1 | T191 | 59 | T185 | 27 | T254 | 105 | ||||
fsm_err | rot_creator_auth_state | 2678 | 1 | T106 | 254 | T149 | 65 | T334 | 30 | ||||
fsm_err | rot_creator_auth_codesign | 3018 | 1 | T14 | 139 | T335 | 37 | T336 | 4 | ||||
fsm_err | owner_sw_cfg | 2511 | 1 | T146 | 376 | T99 | 52 | T337 | 407 | ||||
fsm_err | creator_sw_cfg | 1902 | 1 | T338 | 72 | T147 | 40 | T275 | 40 | ||||
fsm_err | vendor_test | 14800 | 1 | T50 | 6 | T111 | 46 | T140 | 164 | ||||
access_err | life_cycle | 615 | 1 | T7 | 4 | T10 | 4 | T15 | 11 | ||||
access_err | secret2 | 10247 | 1 | T1 | 3 | T11 | 16 | T6 | 31 | ||||
access_err | secret1 | 5411 | 1 | T6 | 21 | T30 | 30 | T50 | 137 | ||||
access_err | secret0 | 4605 | 1 | T11 | 1 | T6 | 22 | T8 | 2 | ||||
access_err | hw_cfg1 | 1149 | 1 | T6 | 3 | T7 | 1 | T29 | 2 | ||||
access_err | hw_cfg0 | 2071 | 1 | T6 | 23 | T30 | 1 | T50 | 70 | ||||
access_err | rot_creator_auth_state | 5380 | 1 | T6 | 28 | T7 | 2 | T39 | 2 | ||||
access_err | rot_creator_auth_codesign | 7412 | 1 | T11 | 1 | T6 | 54 | T7 | 2 | ||||
access_err | owner_sw_cfg | 6706 | 1 | T6 | 32 | T7 | 1 | T39 | 3 | ||||
access_err | creator_sw_cfg | 7509 | 1 | T1 | 3 | T11 | 2 | T6 | 32 | ||||
access_err | vendor_test | 6896 | 1 | T11 | 2 | T6 | 37 | T39 | 4 | ||||
write_blank_err | secret2 | 12 | 1 | T9 | 1 | T189 | 1 | T131 | 1 | ||||
write_blank_err | secret1 | 23 | 1 | T243 | 1 | T186 | 1 | T131 | 3 | ||||
write_blank_err | secret0 | 54 | 1 | T50 | 1 | T99 | 2 | T190 | 1 | ||||
write_blank_err | hw_cfg1 | 69 | 1 | T10 | 1 | T15 | 1 | T98 | 2 | ||||
write_blank_err | hw_cfg0 | 9 | 1 | T103 | 1 | T275 | 1 | T339 | 1 | ||||
write_blank_err | rot_creator_auth_state | 117 | 1 | T7 | 1 | T15 | 1 | T99 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 58 | 1 | T7 | 1 | T99 | 1 | T28 | 2 | ||||
write_blank_err | owner_sw_cfg | 19 | 1 | T38 | 5 | T340 | 2 | T333 | 3 | ||||
write_blank_err | creator_sw_cfg | 17 | 1 | T340 | 1 | T339 | 2 | T341 | 2 | ||||
write_blank_err | vendor_test | 42 | 1 | T98 | 1 | T189 | 1 | T103 | 1 | ||||
ecc_uncorr_err | secret2 | 5138 | 1 | T9 | 509 | T189 | 191 | T147 | 31 | ||||
ecc_uncorr_err | secret1 | 9168 | 1 | T137 | 67 | T147 | 36 | T243 | 477 | ||||
ecc_uncorr_err | secret0 | 23284 | 1 | T29 | 2 | T50 | 599 | T99 | 1029 | ||||
ecc_uncorr_err | hw_cfg1 | 19724 | 1 | T10 | 550 | T15 | 87 | T98 | 401 | ||||
ecc_uncorr_err | hw_cfg0 | 4082 | 1 | T137 | 63 | T103 | 522 | T342 | 11 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4029 | 1 | T7 | 21 | T29 | 4 | T99 | 148 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1180 | 1 | T137 | 61 | T343 | 115 | T344 | 38 | ||||
ecc_uncorr_err | owner_sw_cfg | 978 | 1 | T29 | 8 | T342 | 18 | T343 | 55 | ||||
ecc_uncorr_err | creator_sw_cfg | 1577 | 1 | T29 | 3 | T342 | 25 | T343 | 113 | ||||
ecc_corr_err | secret2 | 82 | 1 | T29 | 5 | T78 | 7 | T46 | 1 | ||||
ecc_corr_err | secret1 | 152 | 1 | T11 | 1 | T75 | 5 | T77 | 1 | ||||
ecc_corr_err | secret0 | 143 | 1 | T11 | 2 | T52 | 4 | T75 | 1 | ||||
ecc_corr_err | hw_cfg1 | 233 | 1 | T11 | 2 | T52 | 2 | T98 | 1 | ||||
ecc_corr_err | hw_cfg0 | 240 | 1 | T29 | 4 | T52 | 5 | T147 | 2 | ||||
ecc_corr_err | rot_creator_auth_state | 135 | 1 | T11 | 2 | T29 | 2 | T15 | 1 | ||||
ecc_corr_err | rot_creator_auth_codesign | 149 | 1 | T11 | 1 | T29 | 1 | T52 | 7 | ||||
ecc_corr_err | owner_sw_cfg | 128 | 1 | T11 | 1 | T52 | 7 | T77 | 2 | ||||
ecc_corr_err | creator_sw_cfg | 131 | 1 | T29 | 1 | T52 | 1 | T75 | 3 | ||||
no_err | secret2 | 5281 | 1 | T6 | 13 | T7 | 2 | T105 | 1 | ||||
no_err | secret1 | 8342 | 1 | T11 | 5 | T6 | 10 | T7 | 13 | ||||
no_err | secret0 | 8099 | 1 | T1 | 1 | T11 | 2 | T6 | 13 | ||||
no_err | hw_cfg1 | 10127 | 1 | T1 | 2 | T11 | 1 | T6 | 22 | ||||
no_err | hw_cfg0 | 11460 | 1 | T1 | 2 | T6 | 49 | T7 | 8 | ||||
no_err | rot_creator_auth_state | 8077 | 1 | T11 | 7 | T6 | 22 | T7 | 10 | ||||
no_err | rot_creator_auth_codesign | 8504 | 1 | T11 | 9 | T6 | 17 | T7 | 19 | ||||
no_err | owner_sw_cfg | 8943 | 1 | T11 | 2 | T6 | 17 | T7 | 18 | ||||
no_err | creator_sw_cfg | 7766 | 1 | T1 | 1 | T11 | 2 | T6 | 12 | ||||
no_err | vendor_test | 9725 | 1 | T1 | 5 | T11 | 7 | T6 | 14 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |