Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.88 93.76 96.20 95.63 91.89 97.05 96.34 93.28


Total test records in report: 1320
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T1265 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.747570286 Jul 21 07:00:56 PM PDT 24 Jul 21 07:01:06 PM PDT 24 87378145 ps
T1266 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3853244683 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:09 PM PDT 24 71553274 ps
T1267 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.541734165 Jul 21 07:00:57 PM PDT 24 Jul 21 07:01:04 PM PDT 24 282048328 ps
T274 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1630532900 Jul 21 07:00:53 PM PDT 24 Jul 21 07:01:14 PM PDT 24 10347317042 ps
T1268 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3551774245 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:10 PM PDT 24 1119535974 ps
T1269 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1263871470 Jul 21 07:00:55 PM PDT 24 Jul 21 07:01:01 PM PDT 24 40165649 ps
T346 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.589134695 Jul 21 07:00:57 PM PDT 24 Jul 21 07:01:23 PM PDT 24 3151226841 ps
T1270 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3122193412 Jul 21 07:01:02 PM PDT 24 Jul 21 07:01:18 PM PDT 24 609555799 ps
T1271 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1921640473 Jul 21 07:01:01 PM PDT 24 Jul 21 07:01:08 PM PDT 24 441219913 ps
T304 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2995782746 Jul 21 07:00:48 PM PDT 24 Jul 21 07:00:51 PM PDT 24 142318075 ps
T1272 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1554655220 Jul 21 07:00:59 PM PDT 24 Jul 21 07:01:04 PM PDT 24 41513532 ps
T1273 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2082089061 Jul 21 07:00:56 PM PDT 24 Jul 21 07:01:02 PM PDT 24 97279818 ps
T1274 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.809895775 Jul 21 07:00:57 PM PDT 24 Jul 21 07:01:04 PM PDT 24 89483374 ps
T1275 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2497359055 Jul 21 07:00:59 PM PDT 24 Jul 21 07:01:04 PM PDT 24 141367853 ps
T347 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1811907875 Jul 21 07:00:55 PM PDT 24 Jul 21 07:01:18 PM PDT 24 5013536431 ps
T1276 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2597291916 Jul 21 07:00:55 PM PDT 24 Jul 21 07:01:02 PM PDT 24 75845162 ps
T1277 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3565675942 Jul 21 07:00:52 PM PDT 24 Jul 21 07:00:58 PM PDT 24 112998225 ps
T1278 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3174642111 Jul 21 07:00:52 PM PDT 24 Jul 21 07:00:57 PM PDT 24 67179162 ps
T1279 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4258023573 Jul 21 07:00:54 PM PDT 24 Jul 21 07:01:01 PM PDT 24 197620655 ps
T305 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2136900107 Jul 21 07:00:48 PM PDT 24 Jul 21 07:00:51 PM PDT 24 177521282 ps
T1280 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2177950204 Jul 21 07:00:53 PM PDT 24 Jul 21 07:00:59 PM PDT 24 829008220 ps
T1281 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.236210144 Jul 21 07:01:08 PM PDT 24 Jul 21 07:01:28 PM PDT 24 2187540297 ps
T1282 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2472700276 Jul 21 07:00:36 PM PDT 24 Jul 21 07:00:43 PM PDT 24 3117333553 ps
T306 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3030657388 Jul 21 07:00:53 PM PDT 24 Jul 21 07:00:58 PM PDT 24 64874161 ps
T1283 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2312223378 Jul 21 07:01:02 PM PDT 24 Jul 21 07:01:07 PM PDT 24 37087379 ps
T1284 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1759395939 Jul 21 07:01:12 PM PDT 24 Jul 21 07:01:14 PM PDT 24 73487704 ps
T1285 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3285717640 Jul 21 07:00:52 PM PDT 24 Jul 21 07:00:58 PM PDT 24 1441282504 ps
T1286 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.881747561 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:19 PM PDT 24 1327046958 ps
T1287 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1194939688 Jul 21 07:01:03 PM PDT 24 Jul 21 07:01:07 PM PDT 24 44231303 ps
T1288 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.901552569 Jul 21 07:00:59 PM PDT 24 Jul 21 07:01:04 PM PDT 24 572127480 ps
T352 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2255667011 Jul 21 07:00:47 PM PDT 24 Jul 21 07:01:32 PM PDT 24 19683165638 ps
T1289 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3407296496 Jul 21 07:00:54 PM PDT 24 Jul 21 07:01:00 PM PDT 24 574436432 ps
T1290 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3527590985 Jul 21 07:00:47 PM PDT 24 Jul 21 07:00:50 PM PDT 24 38279675 ps
T1291 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2655035652 Jul 21 07:01:05 PM PDT 24 Jul 21 07:01:09 PM PDT 24 69245829 ps
T1292 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.439672502 Jul 21 07:00:49 PM PDT 24 Jul 21 07:00:53 PM PDT 24 199068863 ps
T1293 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3498210774 Jul 21 07:01:00 PM PDT 24 Jul 21 07:01:06 PM PDT 24 186629838 ps
T1294 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2530139254 Jul 21 07:01:03 PM PDT 24 Jul 21 07:01:08 PM PDT 24 105794074 ps
T1295 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2212402299 Jul 21 07:00:53 PM PDT 24 Jul 21 07:01:09 PM PDT 24 2551302025 ps
T1296 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2783681039 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:08 PM PDT 24 76612080 ps
T1297 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3974967663 Jul 21 07:00:51 PM PDT 24 Jul 21 07:00:58 PM PDT 24 193062640 ps
T1298 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1821412818 Jul 21 07:00:56 PM PDT 24 Jul 21 07:01:02 PM PDT 24 37793636 ps
T1299 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2035014667 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:08 PM PDT 24 86504583 ps
T1300 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.308379047 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:08 PM PDT 24 141366548 ps
T1301 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1552775859 Jul 21 07:01:00 PM PDT 24 Jul 21 07:01:11 PM PDT 24 906958188 ps
T1302 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3602439317 Jul 21 07:01:07 PM PDT 24 Jul 21 07:01:11 PM PDT 24 50518910 ps
T309 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2676077223 Jul 21 07:00:54 PM PDT 24 Jul 21 07:01:01 PM PDT 24 140465164 ps
T1303 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.814884568 Jul 21 07:01:03 PM PDT 24 Jul 21 07:01:07 PM PDT 24 538111835 ps
T1304 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2484898610 Jul 21 07:00:47 PM PDT 24 Jul 21 07:00:51 PM PDT 24 183826535 ps
T349 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2634823495 Jul 21 07:00:54 PM PDT 24 Jul 21 07:01:19 PM PDT 24 5126782446 ps
T1305 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1061157838 Jul 21 07:00:49 PM PDT 24 Jul 21 07:00:59 PM PDT 24 454587931 ps
T1306 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1329577525 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:12 PM PDT 24 1102563499 ps
T1307 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3584594905 Jul 21 07:00:48 PM PDT 24 Jul 21 07:00:51 PM PDT 24 36299009 ps
T1308 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2432187376 Jul 21 07:00:56 PM PDT 24 Jul 21 07:01:03 PM PDT 24 567269276 ps
T1309 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.337034532 Jul 21 07:00:57 PM PDT 24 Jul 21 07:01:04 PM PDT 24 270669779 ps
T1310 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.761576728 Jul 21 07:00:56 PM PDT 24 Jul 21 07:01:02 PM PDT 24 63708914 ps
T1311 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.739186919 Jul 21 07:00:53 PM PDT 24 Jul 21 07:00:59 PM PDT 24 38555195 ps
T350 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3242898559 Jul 21 07:01:00 PM PDT 24 Jul 21 07:01:21 PM PDT 24 1247126505 ps
T1312 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.713707546 Jul 21 07:00:57 PM PDT 24 Jul 21 07:01:10 PM PDT 24 847485768 ps
T1313 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3584765566 Jul 21 07:00:47 PM PDT 24 Jul 21 07:00:50 PM PDT 24 79251836 ps
T1314 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.371916835 Jul 21 07:00:50 PM PDT 24 Jul 21 07:00:53 PM PDT 24 36730487 ps
T1315 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3580058426 Jul 21 07:01:03 PM PDT 24 Jul 21 07:01:08 PM PDT 24 524914873 ps
T310 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.907457495 Jul 21 07:00:55 PM PDT 24 Jul 21 07:01:01 PM PDT 24 172543402 ps
T1316 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.811258638 Jul 21 07:00:53 PM PDT 24 Jul 21 07:00:58 PM PDT 24 91187808 ps
T355 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.443455305 Jul 21 07:00:55 PM PDT 24 Jul 21 07:01:11 PM PDT 24 1930332704 ps
T1317 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2521740850 Jul 21 07:01:12 PM PDT 24 Jul 21 07:01:15 PM PDT 24 539046313 ps
T311 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1994417581 Jul 21 07:00:58 PM PDT 24 Jul 21 07:01:04 PM PDT 24 153471346 ps
T1318 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1264213100 Jul 21 07:00:50 PM PDT 24 Jul 21 07:00:57 PM PDT 24 111892504 ps
T307 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3275596410 Jul 21 07:01:08 PM PDT 24 Jul 21 07:01:11 PM PDT 24 74689631 ps
T1319 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2032329740 Jul 21 07:01:05 PM PDT 24 Jul 21 07:01:11 PM PDT 24 601116988 ps
T1320 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3985482169 Jul 21 07:01:11 PM PDT 24 Jul 21 07:01:14 PM PDT 24 549945579 ps

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.1626209630
Short name T7
Test name
Test status
Simulation time 107022907782 ps
CPU time 707.52 seconds
Started Jul 21 06:34:30 PM PDT 24
Finished Jul 21 06:46:20 PM PDT 24
Peak memory 345872 kb
Host smart-aa1718be-8052-4d42-ac13-2b48a2508a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626209630 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.1626209630
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2122667448
Short name T50
Test name
Test status
Simulation time 195984992165 ps
CPU time 285.43 seconds
Started Jul 21 06:36:01 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 280712 kb
Host smart-a8ba3266-b100-46d0-a9db-062914e7128f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122667448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2122667448
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.471022129
Short name T186
Test name
Test status
Simulation time 37901855467 ps
CPU time 451.15 seconds
Started Jul 21 06:34:44 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 257152 kb
Host smart-551fdfce-caca-4e68-a6bd-c1c4a0e604af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471022129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.
471022129
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.2161070885
Short name T29
Test name
Test status
Simulation time 990949034 ps
CPU time 24.89 seconds
Started Jul 21 06:35:49 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241844 kb
Host smart-ab9d78a7-9257-4e74-a79f-ab8ab9a24207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161070885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2161070885
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.2749012863
Short name T22
Test name
Test status
Simulation time 10757538268 ps
CPU time 198.5 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:37:32 PM PDT 24
Peak memory 269852 kb
Host smart-6ce84585-d792-4777-a4c4-49a331f7da6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749012863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2749012863
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.959698616
Short name T143
Test name
Test status
Simulation time 148714857 ps
CPU time 4.11 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:28 PM PDT 24
Peak memory 241216 kb
Host smart-f3bf1f3e-38cf-4c56-be0e-c240a46e07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959698616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.959698616
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.3951775292
Short name T99
Test name
Test status
Simulation time 66235205512 ps
CPU time 546.34 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:44:25 PM PDT 24
Peak memory 280312 kb
Host smart-2038d80a-72ba-4bbb-85a1-b6255e641985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951775292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.3951775292
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1659040483
Short name T2
Test name
Test status
Simulation time 136953010 ps
CPU time 3.47 seconds
Started Jul 21 06:35:01 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 241240 kb
Host smart-1c0208fc-a73d-4124-b423-9a4e95efc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659040483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1659040483
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.50716681
Short name T27
Test name
Test status
Simulation time 2401999245 ps
CPU time 7.74 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 241816 kb
Host smart-d9946cd6-31ad-47a7-a5c2-8d7c3a02e3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50716681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.50716681
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2283785424
Short name T19
Test name
Test status
Simulation time 225626689896 ps
CPU time 2173.14 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 07:11:20 PM PDT 24
Peak memory 350800 kb
Host smart-87a256a9-3ba0-4e7b-8307-f6ebafb4a12c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283785424 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2283785424
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.767582424
Short name T270
Test name
Test status
Simulation time 1223150710 ps
CPU time 20.86 seconds
Started Jul 21 07:00:45 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 244112 kb
Host smart-212b4c6f-9bc3-4675-8397-b56209304c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767582424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_int
g_err.767582424
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.3657231146
Short name T131
Test name
Test status
Simulation time 58843715739 ps
CPU time 257.41 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:40:33 PM PDT 24
Peak memory 257092 kb
Host smart-09a48fcb-5ed7-456a-b164-fbc81a1f313b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657231146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.3657231146
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.257437636
Short name T59
Test name
Test status
Simulation time 1763123372 ps
CPU time 3.74 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:20 PM PDT 24
Peak memory 241352 kb
Host smart-6b14ec9e-3cb6-4258-b63f-d1116d4de66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257437636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.257437636
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.2497807698
Short name T18
Test name
Test status
Simulation time 827533308178 ps
CPU time 2178.2 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 07:11:56 PM PDT 24
Peak memory 308108 kb
Host smart-d70966ac-0380-491e-87cf-20590b535f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497807698 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.2497807698
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.397717562
Short name T183
Test name
Test status
Simulation time 1959643607 ps
CPU time 8.86 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:07 PM PDT 24
Peak memory 241156 kb
Host smart-7246d891-e7c6-436c-b6ec-768f13944d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397717562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.397717562
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2465542009
Short name T57
Test name
Test status
Simulation time 208766342 ps
CPU time 4.23 seconds
Started Jul 21 06:36:09 PM PDT 24
Finished Jul 21 06:36:17 PM PDT 24
Peak memory 241120 kb
Host smart-c871ca43-39ac-4799-bfe4-5d0ad0d0f26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465542009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2465542009
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.980438433
Short name T195
Test name
Test status
Simulation time 806925214 ps
CPU time 25.1 seconds
Started Jul 21 06:35:27 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 241748 kb
Host smart-9f6bdf1b-2798-44c6-bc01-b99289cc049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980438433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.980438433
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3475263490
Short name T127
Test name
Test status
Simulation time 693442217501 ps
CPU time 1399.69 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 481440 kb
Host smart-43e8b813-77e0-4e14-9094-71dd676daba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475263490 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.3475263490
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3061708705
Short name T49
Test name
Test status
Simulation time 410960355 ps
CPU time 4.54 seconds
Started Jul 21 06:36:48 PM PDT 24
Finished Jul 21 06:36:53 PM PDT 24
Peak memory 241240 kb
Host smart-206523ea-e2af-4e2e-9905-9f7418b795e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061708705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3061708705
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1423389337
Short name T79
Test name
Test status
Simulation time 10217997696 ps
CPU time 15.35 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:25 PM PDT 24
Peak memory 248080 kb
Host smart-e49ab5c3-5081-40eb-9e6d-eb5d0d304014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423389337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1423389337
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1533284350
Short name T275
Test name
Test status
Simulation time 1362080348725 ps
CPU time 2373.21 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 07:13:49 PM PDT 24
Peak memory 371616 kb
Host smart-23f7ce40-d223-4546-92f1-4b42a0f400a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533284350 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1533284350
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3349105183
Short name T64
Test name
Test status
Simulation time 176368973 ps
CPU time 4.51 seconds
Started Jul 21 06:34:26 PM PDT 24
Finished Jul 21 06:34:33 PM PDT 24
Peak memory 241224 kb
Host smart-193e06c6-48b7-456f-ae85-2b63bd3b9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349105183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3349105183
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1354635139
Short name T329
Test name
Test status
Simulation time 37865073614 ps
CPU time 272.1 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:40:00 PM PDT 24
Peak memory 259428 kb
Host smart-f7fda195-fc05-46e1-acd4-f1db0d67756e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354635139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1354635139
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.656157548
Short name T75
Test name
Test status
Simulation time 584372123 ps
CPU time 12.21 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:52 PM PDT 24
Peak memory 247988 kb
Host smart-8c659bb9-9118-49b6-b628-655fad15fa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656157548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.656157548
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.2857022773
Short name T44
Test name
Test status
Simulation time 519638438 ps
CPU time 3.42 seconds
Started Jul 21 06:37:05 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241232 kb
Host smart-3d4d2e99-dd7e-47f4-b151-36ed1b2d257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857022773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2857022773
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.4075229445
Short name T73
Test name
Test status
Simulation time 549853452 ps
CPU time 4.17 seconds
Started Jul 21 06:37:26 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241448 kb
Host smart-586c3696-1b48-42d8-af04-c106dafde507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075229445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.4075229445
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.303949822
Short name T3
Test name
Test status
Simulation time 349615341 ps
CPU time 4.67 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:36:37 PM PDT 24
Peak memory 241388 kb
Host smart-6937ef7c-e414-4efd-9a58-f27877a32836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303949822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.303949822
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.3623112130
Short name T736
Test name
Test status
Simulation time 3212148299 ps
CPU time 63.75 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:36:42 PM PDT 24
Peak memory 260568 kb
Host smart-ee49d0e8-a5ff-4277-962a-ae3ff8319aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623112130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3623112130
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.819937146
Short name T43
Test name
Test status
Simulation time 297235996 ps
CPU time 4.08 seconds
Started Jul 21 06:37:16 PM PDT 24
Finished Jul 21 06:37:20 PM PDT 24
Peak memory 241432 kb
Host smart-1d7697c9-b028-4616-876b-e1ec0f03ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819937146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.819937146
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.264554253
Short name T12
Test name
Test status
Simulation time 254826370 ps
CPU time 5.27 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:38 PM PDT 24
Peak memory 241224 kb
Host smart-38facb8f-7935-485a-ac15-75ae7bfd7238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264554253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.264554253
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2533263903
Short name T46
Test name
Test status
Simulation time 6514479614 ps
CPU time 37.75 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:55 PM PDT 24
Peak memory 248084 kb
Host smart-f86172a4-1dcc-4c72-8c97-e84d2db9800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533263903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2533263903
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.304824820
Short name T203
Test name
Test status
Simulation time 2052657150 ps
CPU time 5.05 seconds
Started Jul 21 06:36:42 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241300 kb
Host smart-8f6ae2be-4719-4c8c-a8c0-ed5f103d2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304824820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.304824820
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.3340043105
Short name T67
Test name
Test status
Simulation time 269096269 ps
CPU time 4.2 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:50 PM PDT 24
Peak memory 241720 kb
Host smart-15a3c71a-c73c-4361-8fce-1254fe4bb6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340043105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3340043105
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.1603998546
Short name T246
Test name
Test status
Simulation time 835016818 ps
CPU time 2.02 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 239624 kb
Host smart-19ba7d50-9750-4538-b186-14f7fde2d1ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603998546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.1603998546
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.1696379396
Short name T324
Test name
Test status
Simulation time 727379975 ps
CPU time 7.65 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241144 kb
Host smart-40e3f71a-fcf6-4fc8-ba74-cea74b181b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696379396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1696379396
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3189237448
Short name T229
Test name
Test status
Simulation time 718322004 ps
CPU time 5.54 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241824 kb
Host smart-2c7ac772-dd6f-408a-9e21-ec3b82e08bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189237448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3189237448
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.1233691952
Short name T333
Test name
Test status
Simulation time 105413795954 ps
CPU time 1512.4 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 07:01:36 PM PDT 24
Peak memory 355280 kb
Host smart-1cd535d6-342f-4d6d-b157-96a9e99ca106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233691952 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.1233691952
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.1371358752
Short name T84
Test name
Test status
Simulation time 118492649 ps
CPU time 3.74 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 241236 kb
Host smart-3fbfb4c6-9404-48eb-9443-a6d164b1fdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371358752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1371358752
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.798391855
Short name T360
Test name
Test status
Simulation time 488588499 ps
CPU time 12.49 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:08 PM PDT 24
Peak memory 241184 kb
Host smart-0df897bf-67ad-4620-b288-7ec029754bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798391855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.798391855
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.589134695
Short name T346
Test name
Test status
Simulation time 3151226841 ps
CPU time 20.72 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 244784 kb
Host smart-6568fe13-c8ad-45c4-9c4f-051a0771ff61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589134695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in
tg_err.589134695
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3244245588
Short name T301
Test name
Test status
Simulation time 151091731 ps
CPU time 1.56 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 238876 kb
Host smart-cb314a27-019e-4009-91aa-cbc00371e64e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244245588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3244245588
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.2111202683
Short name T508
Test name
Test status
Simulation time 130644310 ps
CPU time 3.79 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241152 kb
Host smart-8f1f3f48-e9e1-4006-9aea-cef8b092992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111202683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2111202683
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.1690068254
Short name T692
Test name
Test status
Simulation time 46967266625 ps
CPU time 221.23 seconds
Started Jul 21 06:34:13 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 281024 kb
Host smart-ae1dfab4-e911-436d-8130-7b4c1c31245e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690068254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
1690068254
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.2532004551
Short name T241
Test name
Test status
Simulation time 448885742856 ps
CPU time 1151 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:53:25 PM PDT 24
Peak memory 258540 kb
Host smart-6061e260-eeb4-4cc8-ad2a-8deac5d3918e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532004551 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.2532004551
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1176665449
Short name T1003
Test name
Test status
Simulation time 234222782 ps
CPU time 6.83 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:23 PM PDT 24
Peak memory 247908 kb
Host smart-00a8db2c-429c-4108-ba08-ccf6e992c726
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176665449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1176665449
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1579722423
Short name T126
Test name
Test status
Simulation time 15856242384 ps
CPU time 426.19 seconds
Started Jul 21 06:36:17 PM PDT 24
Finished Jul 21 06:43:27 PM PDT 24
Peak memory 256396 kb
Host smart-e671f182-2458-4364-8757-d480978717d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579722423 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.1579722423
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.3302534903
Short name T63
Test name
Test status
Simulation time 1009985490 ps
CPU time 18.09 seconds
Started Jul 21 06:34:49 PM PDT 24
Finished Jul 21 06:35:10 PM PDT 24
Peak memory 241680 kb
Host smart-cd6c8243-486c-4fea-a283-af362fcf6a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302534903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3302534903
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2703040929
Short name T192
Test name
Test status
Simulation time 208635955 ps
CPU time 5.41 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241144 kb
Host smart-657bdf71-e093-48e6-bc2b-5c47408cfba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703040929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2703040929
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.3714936384
Short name T125
Test name
Test status
Simulation time 676999239 ps
CPU time 19.82 seconds
Started Jul 21 06:36:59 PM PDT 24
Finished Jul 21 06:37:20 PM PDT 24
Peak memory 241504 kb
Host smart-938bdcc1-05a1-499b-bb76-b13ef3d12252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714936384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3714936384
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.624760889
Short name T233
Test name
Test status
Simulation time 857879865 ps
CPU time 14.36 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:19 PM PDT 24
Peak memory 241012 kb
Host smart-b95b478d-dabf-40ce-b3c0-2a72a647564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624760889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.624760889
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1480490492
Short name T68
Test name
Test status
Simulation time 1973099093 ps
CPU time 6.68 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241188 kb
Host smart-708292b7-829c-4d83-a37a-2ee5cb786ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480490492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1480490492
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1171086054
Short name T74
Test name
Test status
Simulation time 267268708 ps
CPU time 4.32 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241532 kb
Host smart-0c2de598-bb6a-4bd3-9847-6a6872b30603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171086054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1171086054
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.994067630
Short name T240
Test name
Test status
Simulation time 356779985 ps
CPU time 5.1 seconds
Started Jul 21 06:36:25 PM PDT 24
Finished Jul 21 06:36:31 PM PDT 24
Peak memory 241188 kb
Host smart-69530383-11dd-4fea-bb74-f0aa177dcd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994067630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.994067630
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.591503883
Short name T98
Test name
Test status
Simulation time 8465763110 ps
CPU time 65.71 seconds
Started Jul 21 06:34:30 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 256324 kb
Host smart-82dd3673-e3db-4228-bc13-d983384377ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591503883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
591503883
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.3299410173
Short name T40
Test name
Test status
Simulation time 1184995098 ps
CPU time 14.39 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:29 PM PDT 24
Peak memory 241844 kb
Host smart-9db0ca0f-2a4f-4860-a91b-ef6f3b60b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299410173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3299410173
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3505775253
Short name T603
Test name
Test status
Simulation time 37744176710 ps
CPU time 260.02 seconds
Started Jul 21 06:34:23 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 280864 kb
Host smart-aa65e190-8b3f-418f-b136-8807d4414a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505775253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3505775253
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.1605663907
Short name T144
Test name
Test status
Simulation time 1661654327 ps
CPU time 5.69 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241440 kb
Host smart-d8dea8f2-ab12-497d-b90b-1190b1117452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605663907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1605663907
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.2868626841
Short name T220
Test name
Test status
Simulation time 167594349 ps
CPU time 4.54 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241128 kb
Host smart-f7c6c3da-c74d-4e12-b342-b48eb5f81fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868626841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.2868626841
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2837672152
Short name T273
Test name
Test status
Simulation time 1619417887 ps
CPU time 16.71 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:22 PM PDT 24
Peak memory 238964 kb
Host smart-8f208408-f8cd-4f63-96c1-4e58741ae505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837672152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2837672152
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.3913780405
Short name T54
Test name
Test status
Simulation time 1605504023 ps
CPU time 16.83 seconds
Started Jul 21 06:34:36 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 241480 kb
Host smart-b94d6677-a843-4a37-b194-847c6330921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913780405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3913780405
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.2817064233
Short name T33
Test name
Test status
Simulation time 9898725670 ps
CPU time 24.46 seconds
Started Jul 21 06:35:16 PM PDT 24
Finished Jul 21 06:35:42 PM PDT 24
Peak memory 248040 kb
Host smart-f61c2baa-7020-4218-bb18-bf7d0500ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817064233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2817064233
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.1852374332
Short name T374
Test name
Test status
Simulation time 23781708977 ps
CPU time 177.33 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:39:02 PM PDT 24
Peak memory 275672 kb
Host smart-57c92a40-94ab-46b0-9509-25745aaaddaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852374332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.1852374332
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.1627002936
Short name T292
Test name
Test status
Simulation time 347442637 ps
CPU time 7.9 seconds
Started Jul 21 06:35:44 PM PDT 24
Finished Jul 21 06:35:53 PM PDT 24
Peak memory 241480 kb
Host smart-b62e174d-cf86-42b1-b963-e01124f21fc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627002936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1627002936
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.4041737217
Short name T367
Test name
Test status
Simulation time 2136720025 ps
CPU time 15.98 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 06:36:39 PM PDT 24
Peak memory 241416 kb
Host smart-eb9ed499-f4bb-441b-9ad1-92408fff986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041737217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.4041737217
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.441379814
Short name T78
Test name
Test status
Simulation time 2545536004 ps
CPU time 37.08 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 247992 kb
Host smart-b8d53d88-ee2d-460f-8303-4f33fbf6675b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441379814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.441379814
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1630532900
Short name T274
Test name
Test status
Simulation time 10347317042 ps
CPU time 17.41 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 238952 kb
Host smart-8616448b-6cb1-464a-b889-93da0d08490f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630532900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.1630532900
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.1919598092
Short name T371
Test name
Test status
Simulation time 5185935498 ps
CPU time 31.36 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:44 PM PDT 24
Peak memory 241496 kb
Host smart-34b29665-2192-4e36-978c-531427825e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919598092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1919598092
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.4018768656
Short name T146
Test name
Test status
Simulation time 1600996659 ps
CPU time 18.64 seconds
Started Jul 21 06:36:38 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241260 kb
Host smart-b2967c33-aae5-4b2a-aef8-8b717e3ff98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018768656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.4018768656
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2886583592
Short name T188
Test name
Test status
Simulation time 1488833614 ps
CPU time 26.03 seconds
Started Jul 21 06:34:23 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241404 kb
Host smart-be167cf5-4af4-44aa-9791-7fca22f09bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886583592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2886583592
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1811907875
Short name T347
Test name
Test status
Simulation time 5013536431 ps
CPU time 18.61 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:18 PM PDT 24
Peak memory 239040 kb
Host smart-d852e2d0-e525-472c-a1e2-d29e9c1198f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811907875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.1811907875
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3001519971
Short name T247
Test name
Test status
Simulation time 6420115488 ps
CPU time 78.39 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:35:27 PM PDT 24
Peak memory 267052 kb
Host smart-357cb5a0-8a5a-4800-b019-e6fa79c72ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001519971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3001519971
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.3266493653
Short name T453
Test name
Test status
Simulation time 414528233 ps
CPU time 9.2 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 241860 kb
Host smart-5518891e-4de1-4b22-9311-4c89863150db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266493653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3266493653
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3342007154
Short name T359
Test name
Test status
Simulation time 328100870 ps
CPU time 10.85 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:05 PM PDT 24
Peak memory 241272 kb
Host smart-ef300f46-93e6-4170-95df-7c7e39c0df0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342007154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3342007154
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3030657388
Short name T306
Test name
Test status
Simulation time 64874161 ps
CPU time 1.86 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 240840 kb
Host smart-472f814d-ec82-4ad4-a4d7-7b21e3b23ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030657388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3030657388
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.2523379875
Short name T244
Test name
Test status
Simulation time 200085534 ps
CPU time 1.92 seconds
Started Jul 21 06:34:09 PM PDT 24
Finished Jul 21 06:34:15 PM PDT 24
Peak memory 239608 kb
Host smart-6531295c-dd01-4a17-a4db-691ddfbfd186
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2523379875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2523379875
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.2833829177
Short name T85
Test name
Test status
Simulation time 133585334 ps
CPU time 3.64 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:08 PM PDT 24
Peak memory 241140 kb
Host smart-c72582dd-21f8-4335-8fa7-43456439dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833829177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2833829177
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.4023148458
Short name T82
Test name
Test status
Simulation time 1861552963 ps
CPU time 3.33 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241696 kb
Host smart-34110cb1-ab95-4f4a-8f0b-0e289a5b5b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023148458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.4023148458
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.4199385886
Short name T81
Test name
Test status
Simulation time 2334300757 ps
CPU time 5.66 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:34 PM PDT 24
Peak memory 241208 kb
Host smart-1b352327-1d8d-4692-b28d-fef630910c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199385886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.4199385886
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.1207855965
Short name T139
Test name
Test status
Simulation time 2481847982 ps
CPU time 6.83 seconds
Started Jul 21 06:36:46 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241412 kb
Host smart-76886b81-5a05-4a7f-91ad-4995c1946b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207855965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.1207855965
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.2087950550
Short name T228
Test name
Test status
Simulation time 2330918671 ps
CPU time 20.03 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:57 PM PDT 24
Peak memory 241404 kb
Host smart-73f2fb7a-bf33-46a1-aae2-041bd434d84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087950550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.2087950550
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.72373890
Short name T259
Test name
Test status
Simulation time 499085781 ps
CPU time 15.78 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:35:23 PM PDT 24
Peak memory 241616 kb
Host smart-843efbca-f1f6-4f0a-ab85-b2a27991ee4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72373890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.72373890
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1913108403
Short name T86
Test name
Test status
Simulation time 155177376 ps
CPU time 4.4 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241400 kb
Host smart-6f222fe2-b4da-4b1e-b234-41f3a1a46dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913108403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1913108403
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.1811725994
Short name T102
Test name
Test status
Simulation time 23469273976 ps
CPU time 194.27 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:38:27 PM PDT 24
Peak memory 245772 kb
Host smart-a0715d28-bfb8-44af-8888-1e091354d5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811725994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.1811725994
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.298308206
Short name T538
Test name
Test status
Simulation time 321906125 ps
CPU time 7.09 seconds
Started Jul 21 06:37:15 PM PDT 24
Finished Jul 21 06:37:22 PM PDT 24
Peak memory 241288 kb
Host smart-5330beb0-7e58-4e26-a93a-1fd74507de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298308206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.298308206
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2472700276
Short name T1282
Test name
Test status
Simulation time 3117333553 ps
CPU time 7.09 seconds
Started Jul 21 07:00:36 PM PDT 24
Finished Jul 21 07:00:43 PM PDT 24
Peak memory 238960 kb
Host smart-e757cd92-5440-442a-b8cc-4fc56a5a1675
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472700276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.2472700276
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1061157838
Short name T1305
Test name
Test status
Simulation time 454587931 ps
CPU time 8.68 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 240556 kb
Host smart-7ec0bed2-a60d-405e-8e64-50947e9961e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061157838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1061157838
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2484898610
Short name T1304
Test name
Test status
Simulation time 183826535 ps
CPU time 2.26 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 238812 kb
Host smart-f94030cd-0743-4c51-95f0-a535e623cd9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484898610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2484898610
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2569293573
Short name T1224
Test name
Test status
Simulation time 1094480477 ps
CPU time 3.37 seconds
Started Jul 21 07:00:40 PM PDT 24
Finished Jul 21 07:00:44 PM PDT 24
Peak memory 244488 kb
Host smart-d345fac7-c06e-4945-9cb8-8c8cb2e2d16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569293573 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2569293573
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.907457495
Short name T310
Test name
Test status
Simulation time 172543402 ps
CPU time 1.75 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 238924 kb
Host smart-7ac9f09d-5b22-4456-9edc-85dc17f053a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907457495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.907457495
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.775024130
Short name T1203
Test name
Test status
Simulation time 48267466 ps
CPU time 1.46 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:55 PM PDT 24
Peak memory 229900 kb
Host smart-22f0a1b9-5c13-4be7-84b9-79a19ab8f614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775024130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.775024130
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.739186919
Short name T1311
Test name
Test status
Simulation time 38555195 ps
CPU time 1.35 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 230400 kb
Host smart-baf90e0c-16e9-4608-8b09-4aebf04c9c3e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739186919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.739186919
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.172274910
Short name T1258
Test name
Test status
Simulation time 538980752 ps
CPU time 1.87 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 229700 kb
Host smart-5c56fb6f-9b38-4c83-bf63-ab3f167d54e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172274910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
172274910
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.876813331
Short name T315
Test name
Test status
Simulation time 111022868 ps
CPU time 1.81 seconds
Started Jul 21 07:00:46 PM PDT 24
Finished Jul 21 07:00:48 PM PDT 24
Peak memory 238880 kb
Host smart-6c77d467-3f42-4987-957b-1cb7d7452441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876813331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct
rl_same_csr_outstanding.876813331
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4249441694
Short name T1234
Test name
Test status
Simulation time 142157757 ps
CPU time 5.43 seconds
Started Jul 21 07:00:40 PM PDT 24
Finished Jul 21 07:00:46 PM PDT 24
Peak memory 246764 kb
Host smart-a53a855d-40cf-4ac8-96dc-e69cccfeb1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249441694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.4249441694
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.443455305
Short name T355
Test name
Test status
Simulation time 1930332704 ps
CPU time 11.5 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 238964 kb
Host smart-65a234f9-2f8f-41ad-b54a-6cd17c410c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443455305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int
g_err.443455305
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1669528126
Short name T323
Test name
Test status
Simulation time 2542830061 ps
CPU time 5.3 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 241908 kb
Host smart-eafb6308-3420-4d39-a93c-898dcc943750
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669528126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.1669528126
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3123869020
Short name T1249
Test name
Test status
Simulation time 429124672 ps
CPU time 9.04 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 238948 kb
Host smart-5f8f0564-f2b1-4bff-be64-d9d1987a3b23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123869020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.3123869020
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3174642111
Short name T1278
Test name
Test status
Simulation time 67179162 ps
CPU time 2.01 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:57 PM PDT 24
Peak memory 241056 kb
Host smart-e2e40512-7ede-4912-b65f-b108fc5bdc51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174642111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3174642111
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1914549852
Short name T1201
Test name
Test status
Simulation time 1068966164 ps
CPU time 2.18 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:55 PM PDT 24
Peak memory 245252 kb
Host smart-fc482c7b-3526-4b58-bb2b-f73ee71b675f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914549852 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1914549852
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3584765566
Short name T1313
Test name
Test status
Simulation time 79251836 ps
CPU time 1.55 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:50 PM PDT 24
Peak memory 240440 kb
Host smart-0691726c-f14c-49ae-84fd-278d20faf97c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584765566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3584765566
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.786746595
Short name T1245
Test name
Test status
Simulation time 122592819 ps
CPU time 1.48 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:52 PM PDT 24
Peak memory 230248 kb
Host smart-5743194f-519b-4d88-a175-34029df51d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786746595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.786746595
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.675748432
Short name T1189
Test name
Test status
Simulation time 39401370 ps
CPU time 1.36 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 229496 kb
Host smart-3d946963-ba46-48eb-8962-99ae38128202
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675748432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl
_mem_partial_access.675748432
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.813728237
Short name T1262
Test name
Test status
Simulation time 535790118 ps
CPU time 2.12 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:50 PM PDT 24
Peak memory 230724 kb
Host smart-59dc1e56-aaf9-4636-bc06-813478e1ee31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813728237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.
813728237
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3471583338
Short name T316
Test name
Test status
Simulation time 960096145 ps
CPU time 2.67 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:57 PM PDT 24
Peak memory 238976 kb
Host smart-96847cd3-f8b5-4174-9af9-860816eee1fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471583338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.3471583338
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1264213100
Short name T1318
Test name
Test status
Simulation time 111892504 ps
CPU time 4.28 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:57 PM PDT 24
Peak memory 246096 kb
Host smart-7dee6d6d-7843-4aff-b487-d375c3fc1158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264213100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1264213100
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3856081618
Short name T1251
Test name
Test status
Simulation time 81738515 ps
CPU time 2.35 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 246412 kb
Host smart-6c379bde-4b49-4ba4-8167-6ef400af7049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856081618 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.3856081618
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1632031514
Short name T302
Test name
Test status
Simulation time 83329948 ps
CPU time 1.65 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:00 PM PDT 24
Peak memory 241340 kb
Host smart-66f25c3f-0605-419b-9b0c-4f601114606f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632031514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1632031514
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.115198289
Short name T1243
Test name
Test status
Simulation time 98211137 ps
CPU time 1.6 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:55 PM PDT 24
Peak memory 230344 kb
Host smart-3bfbc3c0-eb50-488e-a48c-4ae77d7abd7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115198289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.115198289
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.965606880
Short name T272
Test name
Test status
Simulation time 132737236 ps
CPU time 3.36 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:01:00 PM PDT 24
Peak memory 238940 kb
Host smart-4a4ae28f-62f8-45b4-b585-95ca4f1eef91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965606880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_c
trl_same_csr_outstanding.965606880
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3147398160
Short name T1191
Test name
Test status
Simulation time 847633679 ps
CPU time 7.31 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 246352 kb
Host smart-64a4bc15-a09a-432c-9720-7a93d3c9e50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147398160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3147398160
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.9164918
Short name T351
Test name
Test status
Simulation time 2589238296 ps
CPU time 11.79 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 244128 kb
Host smart-8af64995-0696-4e57-acce-6814f5286287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9164918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg
_err.9164918
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.541734165
Short name T1267
Test name
Test status
Simulation time 282048328 ps
CPU time 2.35 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 239012 kb
Host smart-d285dbb8-5db2-4237-9c84-3311db1dc884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541734165 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.541734165
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.4242012859
Short name T300
Test name
Test status
Simulation time 92537673 ps
CPU time 1.7 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 241320 kb
Host smart-cc43d7ab-a60c-4a9f-9a0e-22635b50ad69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242012859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.4242012859
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2783681039
Short name T1296
Test name
Test status
Simulation time 76612080 ps
CPU time 1.38 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 230228 kb
Host smart-efdf9152-3159-4b04-8f83-1ab5e27899ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783681039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2783681039
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3022842306
Short name T314
Test name
Test status
Simulation time 111431316 ps
CPU time 2.59 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 242132 kb
Host smart-b0834606-eb46-47e7-8f3f-27d4e6bfbcbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022842306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3022842306
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.318432266
Short name T1237
Test name
Test status
Simulation time 187431662 ps
CPU time 7.12 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 239040 kb
Host smart-3666bded-24fa-4017-8c39-5706d64955af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318432266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.318432266
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.881747561
Short name T1286
Test name
Test status
Simulation time 1327046958 ps
CPU time 10.65 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 243648 kb
Host smart-cb8d6674-a0d4-4292-9a0d-fbb45b573e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881747561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_in
tg_err.881747561
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.531058817
Short name T1223
Test name
Test status
Simulation time 123795190 ps
CPU time 2.78 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 247124 kb
Host smart-66a4a08c-69dc-43d5-a751-631565495c31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531058817 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.531058817
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3133425899
Short name T1260
Test name
Test status
Simulation time 39058312 ps
CPU time 1.52 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 238860 kb
Host smart-1b836462-2c5f-49c9-801c-22f71de95b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133425899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3133425899
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2597291916
Short name T1276
Test name
Test status
Simulation time 75845162 ps
CPU time 1.36 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 230664 kb
Host smart-d9daf8d2-e53f-47c3-b8f9-80669fbc70fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597291916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2597291916
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1287253286
Short name T1229
Test name
Test status
Simulation time 98725219 ps
CPU time 1.86 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 238864 kb
Host smart-f5e39c81-3e81-45b8-908a-d2585738cdff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287253286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1287253286
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3228756677
Short name T1185
Test name
Test status
Simulation time 47818458 ps
CPU time 2.54 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 238956 kb
Host smart-ced68521-05b3-4a3a-9791-5e44e999bcd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228756677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3228756677
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1037658637
Short name T1241
Test name
Test status
Simulation time 66549844 ps
CPU time 2.15 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 246084 kb
Host smart-5f492dbb-418f-4ee9-9af6-c3582c87ffab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037658637 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1037658637
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2876589657
Short name T1239
Test name
Test status
Simulation time 49677353 ps
CPU time 1.52 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 229892 kb
Host smart-b85a1095-7e07-475d-8d25-b66c3fa7085e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876589657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2876589657
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.4200912219
Short name T313
Test name
Test status
Simulation time 254539343 ps
CPU time 2.15 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 238904 kb
Host smart-b4300d00-38c1-43bd-a014-330f421d8f79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200912219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.4200912219
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1215776481
Short name T1184
Test name
Test status
Simulation time 234321727 ps
CPU time 4.4 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 246152 kb
Host smart-87033a9a-6f25-4070-99d6-2ad25fe7386d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215776481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1215776481
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2634823495
Short name T349
Test name
Test status
Simulation time 5126782446 ps
CPU time 20.36 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 244800 kb
Host smart-45eab55c-1de6-4321-9b3a-efa12f09ba3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634823495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.2634823495
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3853244683
Short name T1266
Test name
Test status
Simulation time 71553274 ps
CPU time 1.98 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 243684 kb
Host smart-76826e7b-5cee-4a20-b2d0-a21c79ed8540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853244683 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.3853244683
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2312223378
Short name T1283
Test name
Test status
Simulation time 37087379 ps
CPU time 1.41 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 229960 kb
Host smart-56f464a5-51a0-4d06-840b-221d6bc018a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312223378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2312223378
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2177950204
Short name T1280
Test name
Test status
Simulation time 829008220 ps
CPU time 2.54 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 238896 kb
Host smart-9f128bad-1e9b-47eb-8571-580835308adb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177950204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.2177950204
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.967903664
Short name T1196
Test name
Test status
Simulation time 85095715 ps
CPU time 3.09 seconds
Started Jul 21 07:00:59 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 246164 kb
Host smart-0b156dbc-03ec-42a1-9bc4-da00caad496c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967903664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.967903664
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.236210144
Short name T1281
Test name
Test status
Simulation time 2187540297 ps
CPU time 18.03 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:28 PM PDT 24
Peak memory 245248 kb
Host smart-1e8c7d50-ef0f-4dd8-8fbe-a90569a2aa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236210144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.236210144
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.337034532
Short name T1309
Test name
Test status
Simulation time 270669779 ps
CPU time 2.14 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 245240 kb
Host smart-99e31c05-89ab-4419-8539-f26f7213d0ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337034532 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.337034532
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2530139254
Short name T1294
Test name
Test status
Simulation time 105794074 ps
CPU time 1.6 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 241364 kb
Host smart-503c2310-7d6f-4c03-b1eb-247039780b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530139254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2530139254
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2082089061
Short name T1273
Test name
Test status
Simulation time 97279818 ps
CPU time 1.3 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 230672 kb
Host smart-1bc148f4-3781-4456-9606-88a785c0005f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082089061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2082089061
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.809895775
Short name T1274
Test name
Test status
Simulation time 89483374 ps
CPU time 1.88 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 238936 kb
Host smart-3c87e884-2946-4363-95c0-91512aefdcf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809895775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.809895775
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2386219058
Short name T1244
Test name
Test status
Simulation time 1443610423 ps
CPU time 5.5 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 246380 kb
Host smart-95851baa-11d8-4965-bd81-e216cce90104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386219058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2386219058
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2212402299
Short name T1295
Test name
Test status
Simulation time 2551302025 ps
CPU time 12.36 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 244224 kb
Host smart-d21f824f-02a5-4817-b189-543cc3d7d80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212402299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2212402299
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.523272957
Short name T1216
Test name
Test status
Simulation time 72296638 ps
CPU time 2.49 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:57 PM PDT 24
Peak memory 246212 kb
Host smart-32866692-3878-43e3-aa4e-b5cc2d854eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523272957 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.523272957
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1994417581
Short name T311
Test name
Test status
Simulation time 153471346 ps
CPU time 1.64 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 238948 kb
Host smart-809c9d30-12ff-4aab-96a4-4bcc5452bb47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994417581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1994417581
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.761576728
Short name T1310
Test name
Test status
Simulation time 63708914 ps
CPU time 1.44 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 230728 kb
Host smart-40f27efa-ffd3-4b3e-987e-9f857d5e2a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761576728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.761576728
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2460164956
Short name T1233
Test name
Test status
Simulation time 106621629 ps
CPU time 2.38 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 238872 kb
Host smart-b9dbf344-d1be-43bc-a3ae-87a6e2055b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460164956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2460164956
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1749384417
Short name T1207
Test name
Test status
Simulation time 731989152 ps
CPU time 7.21 seconds
Started Jul 21 07:00:59 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 246004 kb
Host smart-26179466-5aed-4762-82a1-f8006774a83d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749384417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1749384417
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2623928832
Short name T354
Test name
Test status
Simulation time 20234237115 ps
CPU time 30.57 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 245788 kb
Host smart-c58cc490-a1e4-41ec-9aec-cf30641dc3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623928832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.2623928832
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2891146881
Short name T1208
Test name
Test status
Simulation time 421020701 ps
CPU time 3.28 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:13 PM PDT 24
Peak memory 247236 kb
Host smart-9050b03f-7e4a-475b-a500-350ca666f642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891146881 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.2891146881
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3089882634
Short name T1213
Test name
Test status
Simulation time 83072856 ps
CPU time 1.65 seconds
Started Jul 21 07:00:59 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 240564 kb
Host smart-feaa42ab-3d76-449b-bf32-d06d87fdf5ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089882634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3089882634
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2497359055
Short name T1275
Test name
Test status
Simulation time 141367853 ps
CPU time 1.46 seconds
Started Jul 21 07:00:59 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 229932 kb
Host smart-2594bc2f-1b12-40aa-97c8-64bdf176765f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497359055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2497359055
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1260566554
Short name T1264
Test name
Test status
Simulation time 168478736 ps
CPU time 2.08 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 238968 kb
Host smart-2a582e03-bf96-4a2e-a91b-259e80ca232f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260566554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1260566554
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1329577525
Short name T1306
Test name
Test status
Simulation time 1102563499 ps
CPU time 5.36 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:12 PM PDT 24
Peak memory 246140 kb
Host smart-1390a7a8-7106-4033-a7bc-70eafe80a5e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329577525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1329577525
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3646659944
Short name T1255
Test name
Test status
Simulation time 412828315 ps
CPU time 4.94 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 247132 kb
Host smart-b4cd0258-c247-4088-8402-e8ff709b854e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646659944 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3646659944
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.530378633
Short name T1231
Test name
Test status
Simulation time 46079236 ps
CPU time 1.69 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 241136 kb
Host smart-9aa95728-8357-4906-bcdc-f725a3b5caf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530378633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.530378633
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1328251333
Short name T1211
Test name
Test status
Simulation time 528375469 ps
CPU time 1.97 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 229900 kb
Host smart-4295dff3-de24-457a-b25a-38632ba5dfa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328251333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1328251333
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3602439317
Short name T1302
Test name
Test status
Simulation time 50518910 ps
CPU time 1.93 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 241836 kb
Host smart-4865dce1-a36c-4673-b317-d2dfcb03f020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602439317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3602439317
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1552775859
Short name T1301
Test name
Test status
Simulation time 906958188 ps
CPU time 7.97 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 246352 kb
Host smart-fbac8e32-a4d9-4d31-8c09-66908cf070fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552775859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1552775859
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.864197466
Short name T353
Test name
Test status
Simulation time 1227147371 ps
CPU time 9.87 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 243624 kb
Host smart-b1d818aa-1f26-44c1-b976-80cd923801e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864197466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in
tg_err.864197466
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2303223672
Short name T1221
Test name
Test status
Simulation time 110925831 ps
CPU time 2.89 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 239060 kb
Host smart-da52271e-fbb9-4c69-949e-4aeb3be33f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303223672 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2303223672
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1554655220
Short name T1272
Test name
Test status
Simulation time 41513532 ps
CPU time 1.58 seconds
Started Jul 21 07:00:59 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 241300 kb
Host smart-8e91f09d-0306-45f2-8a3c-a347e7556f49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554655220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1554655220
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1821412818
Short name T1298
Test name
Test status
Simulation time 37793636 ps
CPU time 1.45 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 229952 kb
Host smart-cecf14cd-f146-4624-84e0-47c811652c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821412818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1821412818
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2655035652
Short name T1291
Test name
Test status
Simulation time 69245829 ps
CPU time 1.98 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 238852 kb
Host smart-565f1b20-abc2-44c6-832a-a3ad32f0e4bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655035652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2655035652
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3254520663
Short name T1247
Test name
Test status
Simulation time 297116406 ps
CPU time 5.18 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 246296 kb
Host smart-07ea7a7a-d4fc-4bbc-ae1f-26827a87f015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254520663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3254520663
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2917370679
Short name T1209
Test name
Test status
Simulation time 206277173 ps
CPU time 3.18 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:55 PM PDT 24
Peak memory 238912 kb
Host smart-c3eb8e04-8e1b-4230-b82a-fe2807ebb6f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917370679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.2917370679
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3812486730
Short name T308
Test name
Test status
Simulation time 1600818772 ps
CPU time 9.05 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:15 PM PDT 24
Peak memory 238820 kb
Host smart-77c9a02e-566b-4c06-8e2e-36691972a8de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812486730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3812486730
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.384752854
Short name T1218
Test name
Test status
Simulation time 74747375 ps
CPU time 2.06 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 240576 kb
Host smart-4e303a5a-cc76-4cdc-96f3-a37e81ebb0bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384752854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.384752854
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1921640473
Short name T1271
Test name
Test status
Simulation time 441219913 ps
CPU time 3.12 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 247160 kb
Host smart-28b07d29-72bc-4830-a48d-57095acd00a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921640473 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1921640473
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2995782746
Short name T304
Test name
Test status
Simulation time 142318075 ps
CPU time 1.64 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 241008 kb
Host smart-38e2d637-1b58-4f89-b309-7cce448b4e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995782746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2995782746
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.811258638
Short name T1316
Test name
Test status
Simulation time 91187808 ps
CPU time 1.51 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 230600 kb
Host smart-c9c2ca1d-7b02-4c9d-8731-2212c4891e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811258638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.811258638
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3678082489
Short name T1198
Test name
Test status
Simulation time 125742187 ps
CPU time 1.36 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 229568 kb
Host smart-707b0e67-439c-4426-b310-bf92e313977c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678082489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3678082489
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3527590985
Short name T1290
Test name
Test status
Simulation time 38279675 ps
CPU time 1.32 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:50 PM PDT 24
Peak memory 229660 kb
Host smart-2cf42898-76ff-4d8f-92bf-103d1f9dbf7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527590985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3527590985
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3285717640
Short name T1285
Test name
Test status
Simulation time 1441282504 ps
CPU time 3.41 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 242188 kb
Host smart-c04591a7-d8ab-4616-8878-f6da32489bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285717640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3285717640
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2767924978
Short name T1195
Test name
Test status
Simulation time 1614063433 ps
CPU time 4.67 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 245492 kb
Host smart-6a0c66db-8673-4903-a240-6a6e5194eb8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767924978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2767924978
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3242898559
Short name T350
Test name
Test status
Simulation time 1247126505 ps
CPU time 17.25 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:21 PM PDT 24
Peak memory 244148 kb
Host smart-8358e0ea-ed15-4f81-a78d-3831cdee4a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242898559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.3242898559
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1595013530
Short name T1225
Test name
Test status
Simulation time 142141382 ps
CPU time 1.48 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 230312 kb
Host smart-7dc1774d-720b-4a82-a97b-6407489fed29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595013530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1595013530
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2582085885
Short name T1200
Test name
Test status
Simulation time 72723453 ps
CPU time 1.44 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 229856 kb
Host smart-29675cff-626b-450d-ac7f-d3b9d2ac9fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582085885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2582085885
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3407296496
Short name T1289
Test name
Test status
Simulation time 574436432 ps
CPU time 1.54 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:00 PM PDT 24
Peak memory 230620 kb
Host smart-a0e2b447-00d8-4023-8ed6-5a0e2a6f27d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407296496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3407296496
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1651556636
Short name T1253
Test name
Test status
Simulation time 78264379 ps
CPU time 1.41 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 230676 kb
Host smart-31191bd8-6c3a-4644-b6c1-4a0c3f4e0c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651556636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1651556636
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3580058426
Short name T1315
Test name
Test status
Simulation time 524914873 ps
CPU time 1.52 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 229920 kb
Host smart-e233875f-a612-4204-a659-b475cba1cfed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580058426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3580058426
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.814884568
Short name T1303
Test name
Test status
Simulation time 538111835 ps
CPU time 1.41 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 230332 kb
Host smart-6ccac95e-48fd-48b3-83e5-3b5f3e9e3725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814884568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.814884568
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.509379048
Short name T1222
Test name
Test status
Simulation time 38607911 ps
CPU time 1.39 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 230644 kb
Host smart-4d0dee17-d3e3-4d44-9f86-102b7059b018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509379048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.509379048
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.172500355
Short name T1261
Test name
Test status
Simulation time 68633839 ps
CPU time 1.31 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 230156 kb
Host smart-2409b967-99af-4cdf-96b2-f6c63b357918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172500355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.172500355
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1741713127
Short name T1210
Test name
Test status
Simulation time 45898419 ps
CPU time 1.42 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 230656 kb
Host smart-e5b1817f-ac66-4988-8027-3fafca2943af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741713127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1741713127
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1033472747
Short name T1250
Test name
Test status
Simulation time 62835514 ps
CPU time 1.47 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 229916 kb
Host smart-2304425a-7d08-4f6a-953c-9b1fd4afa769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033472747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1033472747
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2519857959
Short name T322
Test name
Test status
Simulation time 1757535166 ps
CPU time 4.29 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 238920 kb
Host smart-8053c52f-ef02-4ec6-b0c8-e6b4e94db7be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519857959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2519857959
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3974967663
Short name T1297
Test name
Test status
Simulation time 193062640 ps
CPU time 4.77 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 238916 kb
Host smart-e5f83dc4-adea-4d4d-b1c6-6aaa8a2c9d49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974967663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3974967663
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.439672502
Short name T1292
Test name
Test status
Simulation time 199068863 ps
CPU time 2.44 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 240716 kb
Host smart-66d65ea9-607d-472b-a0fe-8bd4d177a638
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439672502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.439672502
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3162703355
Short name T1215
Test name
Test status
Simulation time 171398498 ps
CPU time 2.84 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 246600 kb
Host smart-f5babde1-06e7-4a48-98c5-f60c9188b76e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162703355 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3162703355
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1570809207
Short name T312
Test name
Test status
Simulation time 73106080 ps
CPU time 1.53 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:55 PM PDT 24
Peak memory 241108 kb
Host smart-66fb4ace-c25b-42c6-9b4e-ad195fe7e5da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570809207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1570809207
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3888625024
Short name T1197
Test name
Test status
Simulation time 126687741 ps
CPU time 1.41 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 229944 kb
Host smart-9f67f8f7-a9cb-44e5-8c34-3dde3ddc53dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888625024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3888625024
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1086965415
Short name T1240
Test name
Test status
Simulation time 126380158 ps
CPU time 1.33 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 229484 kb
Host smart-470cc73f-062f-4a61-939a-14c34a986c81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086965415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1086965415
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.678532973
Short name T1235
Test name
Test status
Simulation time 78044157 ps
CPU time 1.33 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 229804 kb
Host smart-2c3f0c71-053d-4a64-9fd5-0d4206bc02f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678532973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.
678532973
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4258023573
Short name T1279
Test name
Test status
Simulation time 197620655 ps
CPU time 2.32 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 241876 kb
Host smart-f4076999-216e-45f6-ae9b-27ca033c0ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258023573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.4258023573
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.740976867
Short name T1190
Test name
Test status
Simulation time 1572974036 ps
CPU time 5.95 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 239008 kb
Host smart-8c6e3fbd-8950-4080-8d3d-52c0c5df2e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740976867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.740976867
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1921295733
Short name T348
Test name
Test status
Simulation time 2224834936 ps
CPU time 10.39 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 243932 kb
Host smart-8e01220a-81b9-42ab-8c2f-18ccca9fd2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921295733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.1921295733
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1773184817
Short name T1188
Test name
Test status
Simulation time 75960579 ps
CPU time 1.45 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 230292 kb
Host smart-7c8ff090-056d-4429-8a17-5932f833d7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773184817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1773184817
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1091928668
Short name T1186
Test name
Test status
Simulation time 43080955 ps
CPU time 1.46 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 229968 kb
Host smart-70ee1acb-a1a9-4eed-92f9-0c26702cd3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091928668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1091928668
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.4146913279
Short name T1232
Test name
Test status
Simulation time 563294602 ps
CPU time 1.43 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 229944 kb
Host smart-e54ff77e-fad4-4d7c-9000-149f26daca4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146913279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.4146913279
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2369651371
Short name T1187
Test name
Test status
Simulation time 554045349 ps
CPU time 1.61 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 229948 kb
Host smart-1169a510-bda7-4afd-923d-de7738eb25ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369651371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2369651371
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3100929034
Short name T1194
Test name
Test status
Simulation time 69943458 ps
CPU time 1.4 seconds
Started Jul 21 07:01:09 PM PDT 24
Finished Jul 21 07:01:12 PM PDT 24
Peak memory 229928 kb
Host smart-70c099b2-fc3e-4499-a43f-204112833993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100929034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3100929034
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.4283625172
Short name T1246
Test name
Test status
Simulation time 68772793 ps
CPU time 1.37 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 229768 kb
Host smart-7fd878e6-afa1-45a2-a84d-7c03e5e1ffaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283625172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.4283625172
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1194939688
Short name T1287
Test name
Test status
Simulation time 44231303 ps
CPU time 1.45 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 230024 kb
Host smart-146f88c0-f3e1-4e92-b51e-89cd02eedc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194939688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1194939688
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.651926082
Short name T1230
Test name
Test status
Simulation time 42177254 ps
CPU time 1.51 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 230208 kb
Host smart-c9ca21ef-7a15-4fb6-8f6e-78cdf752c47f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651926082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.651926082
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2032329740
Short name T1319
Test name
Test status
Simulation time 601116988 ps
CPU time 2.08 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 230016 kb
Host smart-d93de28d-19ee-4399-8e8a-61c8463a9d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032329740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2032329740
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.129793233
Short name T1248
Test name
Test status
Simulation time 136877448 ps
CPU time 1.42 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 229964 kb
Host smart-996bf688-5cf9-4964-9741-dcc004c099fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129793233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.129793233
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.713707546
Short name T1312
Test name
Test status
Simulation time 847485768 ps
CPU time 3.29 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 238884 kb
Host smart-8370a109-9704-477b-a355-7859f42ec385
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713707546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias
ing.713707546
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2124194628
Short name T1257
Test name
Test status
Simulation time 1257642897 ps
CPU time 4.67 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 238952 kb
Host smart-10235ae1-fc20-4a44-9bc1-4c1f71981918
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124194628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2124194628
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2676077223
Short name T309
Test name
Test status
Simulation time 140465164 ps
CPU time 2.53 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 238932 kb
Host smart-294a5871-38b4-4f11-963a-06476e2744e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676077223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.2676077223
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2945118047
Short name T1219
Test name
Test status
Simulation time 127637698 ps
CPU time 1.95 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 244484 kb
Host smart-20d58c66-17d8-45c4-9e7f-56b5d5fbb633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945118047 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.2945118047
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2833905979
Short name T1238
Test name
Test status
Simulation time 116996527 ps
CPU time 1.86 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 240648 kb
Host smart-77b72f4e-f069-4545-8d8f-9d40bf263a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833905979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2833905979
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1166246801
Short name T1202
Test name
Test status
Simulation time 541848127 ps
CPU time 2 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 230632 kb
Host smart-b5074d4c-92b6-496e-baa3-a9ecf4284587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166246801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1166246801
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.371916835
Short name T1314
Test name
Test status
Simulation time 36730487 ps
CPU time 1.35 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 229484 kb
Host smart-606566c8-28dd-477e-a1ee-e16997ba500b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371916835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.371916835
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3660248088
Short name T1204
Test name
Test status
Simulation time 71206825 ps
CPU time 1.38 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 229984 kb
Host smart-82a0f07e-2660-404d-83a0-13ff6cfac347
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660248088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.3660248088
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.4186978232
Short name T1217
Test name
Test status
Simulation time 109466959 ps
CPU time 2.32 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 238960 kb
Host smart-e5393d9a-2263-4df0-9027-0f8f0029c5f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186978232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.4186978232
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1443717571
Short name T1227
Test name
Test status
Simulation time 364650436 ps
CPU time 3.85 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 245804 kb
Host smart-7c483d9d-ce9d-4a1c-a3af-4550f123e6db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443717571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1443717571
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3326358704
Short name T345
Test name
Test status
Simulation time 1376247214 ps
CPU time 19.17 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 244104 kb
Host smart-0c7966a3-d0f5-4e29-9ccd-b55d77c3349b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326358704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3326358704
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2649353027
Short name T1263
Test name
Test status
Simulation time 37561591 ps
CPU time 1.39 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 230692 kb
Host smart-91c67178-6819-484c-9824-6ec0844bb461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649353027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2649353027
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.610152046
Short name T1220
Test name
Test status
Simulation time 42205512 ps
CPU time 1.46 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 230668 kb
Host smart-e82d63fd-ad4f-4ffc-a1b4-6ff65db4541f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610152046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.610152046
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2035014667
Short name T1299
Test name
Test status
Simulation time 86504583 ps
CPU time 1.46 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 230684 kb
Host smart-55ea7e80-8548-4761-9b34-5ac469b6a196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035014667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2035014667
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1759395939
Short name T1284
Test name
Test status
Simulation time 73487704 ps
CPU time 1.38 seconds
Started Jul 21 07:01:12 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 229868 kb
Host smart-0db71ab0-8a7f-4a16-9e0f-29c61eb33eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759395939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1759395939
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2521740850
Short name T1317
Test name
Test status
Simulation time 539046313 ps
CPU time 1.95 seconds
Started Jul 21 07:01:12 PM PDT 24
Finished Jul 21 07:01:15 PM PDT 24
Peak memory 229904 kb
Host smart-7a3b13f2-6648-4172-9279-3ffcb9e1bf48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521740850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2521740850
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.901552569
Short name T1288
Test name
Test status
Simulation time 572127480 ps
CPU time 1.64 seconds
Started Jul 21 07:00:59 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 230004 kb
Host smart-f0b16453-2144-4d0a-9399-38ba74f9fc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901552569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.901552569
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.308379047
Short name T1300
Test name
Test status
Simulation time 141366548 ps
CPU time 1.48 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 230628 kb
Host smart-5a265e53-fab2-4d37-b58d-5d0f85bf7d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308379047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.308379047
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3985482169
Short name T1320
Test name
Test status
Simulation time 549945579 ps
CPU time 2.03 seconds
Started Jul 21 07:01:11 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 229972 kb
Host smart-a8ddf3b3-39eb-4722-b788-88c28ce2891d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985482169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3985482169
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3966119452
Short name T1256
Test name
Test status
Simulation time 74959585 ps
CPU time 1.52 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 230692 kb
Host smart-2c1d857f-e04c-4dec-aa84-0e705820530d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966119452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3966119452
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.145416693
Short name T1226
Test name
Test status
Simulation time 534610055 ps
CPU time 1.5 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 230624 kb
Host smart-55a050eb-57f6-45d6-b94b-516c73b86b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145416693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.145416693
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3551774245
Short name T1268
Test name
Test status
Simulation time 1119535974 ps
CPU time 3.43 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 245952 kb
Host smart-597d6861-cc1b-49d0-91ed-6ae1a9ff4cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551774245 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3551774245
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2988991046
Short name T303
Test name
Test status
Simulation time 38460961 ps
CPU time 1.59 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 240992 kb
Host smart-2414d846-b798-44b4-bf07-4834502d4998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988991046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2988991046
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.289179214
Short name T1214
Test name
Test status
Simulation time 77468479 ps
CPU time 1.55 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:00 PM PDT 24
Peak memory 230040 kb
Host smart-f18ce499-34ed-40e3-8b65-2c46aa5c0939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289179214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.289179214
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2449890763
Short name T317
Test name
Test status
Simulation time 91265404 ps
CPU time 2.05 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 238868 kb
Host smart-0c8df59a-f934-4b1a-b8cb-43223366ed67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449890763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.2449890763
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3358705807
Short name T1252
Test name
Test status
Simulation time 152409164 ps
CPU time 5.76 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 246340 kb
Host smart-bdf59c84-5531-4b74-bf5b-7fa70fd8858c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358705807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3358705807
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4269240430
Short name T269
Test name
Test status
Simulation time 2340663212 ps
CPU time 10.85 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 244168 kb
Host smart-2bfdcf74-0c4c-4a17-8477-12872d41ef00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269240430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.4269240430
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4222934903
Short name T1259
Test name
Test status
Simulation time 268169010 ps
CPU time 2.36 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 247148 kb
Host smart-85ba75e8-86bf-4bd9-8f06-393391e4dcdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222934903 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.4222934903
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2136900107
Short name T305
Test name
Test status
Simulation time 177521282 ps
CPU time 1.84 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 238980 kb
Host smart-f2da0d99-bab4-48da-ad5a-9055407fd262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136900107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2136900107
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2692776880
Short name T1205
Test name
Test status
Simulation time 138326451 ps
CPU time 1.42 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 229920 kb
Host smart-7e21edba-f475-43b0-bb15-e62256513fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692776880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2692776880
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.128405687
Short name T318
Test name
Test status
Simulation time 841888354 ps
CPU time 2.81 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:02 PM PDT 24
Peak memory 238900 kb
Host smart-6a59eeae-f644-4e59-acfd-0f8ba8773fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128405687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct
rl_same_csr_outstanding.128405687
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.4221249533
Short name T1206
Test name
Test status
Simulation time 634586567 ps
CPU time 5.8 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 246184 kb
Host smart-304239ff-7091-412d-8674-b2b2bac44804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221249533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.4221249533
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2419880929
Short name T1192
Test name
Test status
Simulation time 143673503 ps
CPU time 2.62 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 247256 kb
Host smart-72944676-8791-4cd0-a82d-c790c02b4034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419880929 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.2419880929
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1263871470
Short name T1269
Test name
Test status
Simulation time 40165649 ps
CPU time 1.59 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 240836 kb
Host smart-05be22f9-fcbc-486f-b118-24502ff363d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263871470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1263871470
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.155883601
Short name T1254
Test name
Test status
Simulation time 47420568 ps
CPU time 1.35 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 230668 kb
Host smart-06d76110-9b2f-4b38-be96-0304a2ec056f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155883601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.155883601
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3565675942
Short name T1277
Test name
Test status
Simulation time 112998225 ps
CPU time 2.34 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 238872 kb
Host smart-18944333-79ec-41e1-9b91-2e41eae2e31a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565675942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.3565675942
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.747570286
Short name T1265
Test name
Test status
Simulation time 87378145 ps
CPU time 5.89 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 238992 kb
Host smart-b66f6148-2c79-4312-8f42-e5cf131b541b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747570286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.747570286
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3927412335
Short name T271
Test name
Test status
Simulation time 5086810501 ps
CPU time 19.04 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:25 PM PDT 24
Peak memory 245792 kb
Host smart-a2e80eee-2d1c-451c-8e24-46879ab9fa0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927412335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3927412335
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.4068333862
Short name T1242
Test name
Test status
Simulation time 203249133 ps
CPU time 2.61 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 247140 kb
Host smart-2f44d20c-428f-4aae-905d-a0b4bfd421c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068333862 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.4068333862
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2432187376
Short name T1308
Test name
Test status
Simulation time 567269276 ps
CPU time 1.9 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 241296 kb
Host smart-ee2ade35-4085-4eb3-abc9-b07876f52c04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432187376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2432187376
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3584594905
Short name T1307
Test name
Test status
Simulation time 36299009 ps
CPU time 1.36 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 230196 kb
Host smart-54d03ec6-30d5-426d-8b9d-0f9ee0acd2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584594905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3584594905
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3498210774
Short name T1293
Test name
Test status
Simulation time 186629838 ps
CPU time 3.19 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:06 PM PDT 24
Peak memory 242024 kb
Host smart-cf01508b-5242-4f92-9ec7-a03698c934de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498210774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.3498210774
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2499441976
Short name T1199
Test name
Test status
Simulation time 200764637 ps
CPU time 4.13 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 245984 kb
Host smart-db394826-f7be-4afd-b449-181551bb707c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499441976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2499441976
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3122193412
Short name T1270
Test name
Test status
Simulation time 609555799 ps
CPU time 9.28 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:18 PM PDT 24
Peak memory 243624 kb
Host smart-4a186d27-dbd4-49ae-b063-7ace2c75ee4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122193412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3122193412
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1754903536
Short name T1212
Test name
Test status
Simulation time 422062034 ps
CPU time 3.47 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 247184 kb
Host smart-1968ed52-2b9e-4cd8-8d09-6d8ae967a042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754903536 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1754903536
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3275596410
Short name T307
Test name
Test status
Simulation time 74689631 ps
CPU time 1.6 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 241444 kb
Host smart-4675440c-676a-454b-8bf3-dba1291d0caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275596410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3275596410
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.724055058
Short name T1236
Test name
Test status
Simulation time 77791730 ps
CPU time 1.46 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 229920 kb
Host smart-91f5d4c5-3476-4560-9e63-5f9e5c4a4124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724055058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.724055058
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1480338582
Short name T1228
Test name
Test status
Simulation time 1165120456 ps
CPU time 3.91 seconds
Started Jul 21 07:01:09 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 238808 kb
Host smart-2fe9cfa8-02ec-49f5-a05e-6e7a2c73db09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480338582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.1480338582
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.29381444
Short name T1193
Test name
Test status
Simulation time 56472862 ps
CPU time 3.21 seconds
Started Jul 21 07:00:58 PM PDT 24
Finished Jul 21 07:01:05 PM PDT 24
Peak memory 245836 kb
Host smart-bc86ad18-651b-4612-b334-50177535851a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.29381444
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2255667011
Short name T352
Test name
Test status
Simulation time 19683165638 ps
CPU time 42.76 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:01:32 PM PDT 24
Peak memory 244728 kb
Host smart-815a7222-e7ae-4a5e-8cab-22c47a6325c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255667011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2255667011
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.4177554550
Short name T924
Test name
Test status
Simulation time 92564591 ps
CPU time 1.76 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:10 PM PDT 24
Peak memory 239848 kb
Host smart-eefe3eab-e608-450f-935f-65c1327dcdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177554550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.4177554550
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.4155547196
Short name T963
Test name
Test status
Simulation time 3580237735 ps
CPU time 18.08 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 241440 kb
Host smart-ed97d094-9601-4b16-bb78-4d65b3d220c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155547196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.4155547196
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3921597991
Short name T379
Test name
Test status
Simulation time 2338194173 ps
CPU time 14.77 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:30 PM PDT 24
Peak memory 248068 kb
Host smart-632b6140-44c4-44d5-a6c8-07e5e2e2ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921597991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3921597991
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.1820565020
Short name T189
Test name
Test status
Simulation time 1591053388 ps
CPU time 14.42 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:23 PM PDT 24
Peak memory 241108 kb
Host smart-27330932-e962-4f26-8a27-d3fd398e4a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820565020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1820565020
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.1718600292
Short name T882
Test name
Test status
Simulation time 4310675119 ps
CPU time 29.56 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241444 kb
Host smart-8cbe7d14-5db2-40b0-a2ff-a115c2a457ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718600292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1718600292
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3089395652
Short name T992
Test name
Test status
Simulation time 115901048 ps
CPU time 3.74 seconds
Started Jul 21 06:34:07 PM PDT 24
Finished Jul 21 06:34:14 PM PDT 24
Peak memory 241736 kb
Host smart-25398dee-720c-43a3-ac56-3b2391d12722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089395652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3089395652
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.172737866
Short name T89
Test name
Test status
Simulation time 6007863127 ps
CPU time 11.26 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:21 PM PDT 24
Peak memory 240824 kb
Host smart-15a02829-76b6-40ae-89dc-8877308023f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172737866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.172737866
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.2843486750
Short name T955
Test name
Test status
Simulation time 286477888 ps
CPU time 7.26 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 241376 kb
Host smart-1e9e5953-6ef6-41e8-8fbf-4e932eaaa3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843486750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2843486750
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.3056250423
Short name T1158
Test name
Test status
Simulation time 813169808 ps
CPU time 18.42 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 241996 kb
Host smart-9ff479e6-7cae-424e-8372-d318d5d03788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056250423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3056250423
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.1490126116
Short name T254
Test name
Test status
Simulation time 328641302 ps
CPU time 5.78 seconds
Started Jul 21 06:34:07 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 241156 kb
Host smart-b87d5c14-f976-4d8e-bf11-94a36508e4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490126116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1490126116
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.654172269
Short name T1107
Test name
Test status
Simulation time 565966051 ps
CPU time 9.87 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:20 PM PDT 24
Peak memory 241412 kb
Host smart-34d49a0c-2d94-44b0-bdf1-d9ff6fadc669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654172269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.654172269
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2386045178
Short name T421
Test name
Test status
Simulation time 611747998 ps
CPU time 19.66 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:30 PM PDT 24
Peak memory 240996 kb
Host smart-c0da630a-aa5c-48f9-8f3b-59f0b4777449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386045178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2386045178
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3314858641
Short name T917
Test name
Test status
Simulation time 647602062 ps
CPU time 10.35 seconds
Started Jul 21 06:34:08 PM PDT 24
Finished Jul 21 06:34:23 PM PDT 24
Peak memory 241328 kb
Host smart-f27d08ee-9189-4849-81ca-c375b024636f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314858641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3314858641
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.1606839388
Short name T249
Test name
Test status
Simulation time 20741671483 ps
CPU time 194.63 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 277848 kb
Host smart-3dd9dc39-b986-405a-907a-5c281697a81d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606839388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1606839388
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.3697901836
Short name T288
Test name
Test status
Simulation time 138348683 ps
CPU time 5.03 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:14 PM PDT 24
Peak memory 241256 kb
Host smart-00dd60c9-0b5a-4ba6-9bfa-843a36b2e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697901836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3697901836
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2022932757
Short name T280
Test name
Test status
Simulation time 124204840517 ps
CPU time 1562.65 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 07:00:13 PM PDT 24
Peak memory 331476 kb
Host smart-39dff127-af6c-4d60-a551-118a5769886c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022932757 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2022932757
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2691930464
Short name T614
Test name
Test status
Simulation time 1111552548 ps
CPU time 18.31 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241596 kb
Host smart-69797641-f49b-4f2f-80a3-c75f98cdbb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691930464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2691930464
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.417130972
Short name T797
Test name
Test status
Simulation time 85726835 ps
CPU time 2 seconds
Started Jul 21 06:34:08 PM PDT 24
Finished Jul 21 06:34:14 PM PDT 24
Peak memory 239632 kb
Host smart-891757b7-8b20-4a61-870d-b1eef0216440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417130972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.417130972
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.3358750318
Short name T586
Test name
Test status
Simulation time 1192439367 ps
CPU time 12.12 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:21 PM PDT 24
Peak memory 241644 kb
Host smart-74fe53ab-8536-4794-beaf-911b9e8d02c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358750318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3358750318
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2284491265
Short name T927
Test name
Test status
Simulation time 3074925833 ps
CPU time 33.1 seconds
Started Jul 21 06:34:07 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 244544 kb
Host smart-d49356b3-4734-4240-8822-8d92b4486a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284491265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2284491265
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.4059940105
Short name T636
Test name
Test status
Simulation time 564975372 ps
CPU time 6.89 seconds
Started Jul 21 06:34:07 PM PDT 24
Finished Jul 21 06:34:18 PM PDT 24
Peak memory 241612 kb
Host smart-b508edeb-ee54-4249-b48d-3b117616f3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059940105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.4059940105
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.1710957909
Short name T510
Test name
Test status
Simulation time 254425163 ps
CPU time 4.38 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:14 PM PDT 24
Peak memory 241452 kb
Host smart-d26ba1af-b5bc-4524-a7a8-6959369d06dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710957909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1710957909
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.2379302807
Short name T1134
Test name
Test status
Simulation time 1047474552 ps
CPU time 8.86 seconds
Started Jul 21 06:34:03 PM PDT 24
Finished Jul 21 06:34:16 PM PDT 24
Peak memory 241480 kb
Host smart-690b628e-2a21-472a-a878-af65a851d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379302807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2379302807
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.399772025
Short name T412
Test name
Test status
Simulation time 1396776491 ps
CPU time 4.09 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:13 PM PDT 24
Peak memory 241320 kb
Host smart-fc160d94-9ae5-440b-ae91-ce2bd12decce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399772025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.399772025
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.3425216068
Short name T377
Test name
Test status
Simulation time 677034473 ps
CPU time 18.56 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241468 kb
Host smart-47bbdf26-7808-4a86-9deb-548620176aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425216068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3425216068
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.1143307845
Short name T441
Test name
Test status
Simulation time 146728747 ps
CPU time 4.16 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:14 PM PDT 24
Peak memory 241304 kb
Host smart-69cfc37a-2186-4b9d-8bed-d4a13c3d96d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143307845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1143307845
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.2515684203
Short name T248
Test name
Test status
Simulation time 170440630726 ps
CPU time 268.81 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 278540 kb
Host smart-74ea69d0-ee5f-49a7-a748-c91e1380bbd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515684203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2515684203
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.661215292
Short name T662
Test name
Test status
Simulation time 246698476 ps
CPU time 4.75 seconds
Started Jul 21 06:34:07 PM PDT 24
Finished Jul 21 06:34:15 PM PDT 24
Peak memory 241700 kb
Host smart-533f28a9-4de8-4c74-9bf4-91f20ba276a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661215292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.661215292
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.2142137309
Short name T474
Test name
Test status
Simulation time 19807528035 ps
CPU time 65.65 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:35:16 PM PDT 24
Peak memory 244592 kb
Host smart-c6a6e003-f3d2-4c36-9247-360a33656e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142137309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
2142137309
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2429558203
Short name T214
Test name
Test status
Simulation time 633785811179 ps
CPU time 1127.12 seconds
Started Jul 21 06:34:03 PM PDT 24
Finished Jul 21 06:52:54 PM PDT 24
Peak memory 265904 kb
Host smart-a7305e8a-7b25-46da-a0cd-eec1779a5b89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429558203 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2429558203
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.1246800790
Short name T932
Test name
Test status
Simulation time 1509625411 ps
CPU time 11.93 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:22 PM PDT 24
Peak memory 247920 kb
Host smart-a702d7f2-f707-4e6f-a17b-d5e324127391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246800790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1246800790
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2503443763
Short name T1177
Test name
Test status
Simulation time 131275171 ps
CPU time 1.96 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:34 PM PDT 24
Peak memory 239880 kb
Host smart-d6f2fb08-4476-4a46-938d-57014ad123fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503443763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2503443763
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.3669272129
Short name T1150
Test name
Test status
Simulation time 11728132931 ps
CPU time 33.78 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:35:05 PM PDT 24
Peak memory 244108 kb
Host smart-53a91d31-ad8a-4478-b573-41415f5c0294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669272129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3669272129
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.2979334862
Short name T290
Test name
Test status
Simulation time 677694063 ps
CPU time 23.44 seconds
Started Jul 21 06:34:30 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 241184 kb
Host smart-898732f9-dce9-4ff5-8f3e-d46f66185685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979334862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2979334862
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2631457179
Short name T1059
Test name
Test status
Simulation time 2323551241 ps
CPU time 24.98 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 241884 kb
Host smart-be3cb5f0-edab-4239-8f49-2191c67a5927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631457179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2631457179
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3734295376
Short name T995
Test name
Test status
Simulation time 95557896 ps
CPU time 3.44 seconds
Started Jul 21 06:34:30 PM PDT 24
Finished Jul 21 06:34:36 PM PDT 24
Peak memory 241376 kb
Host smart-63ddf76c-b643-4fa6-951b-05eb2287962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734295376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3734295376
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.3748175249
Short name T225
Test name
Test status
Simulation time 10859589936 ps
CPU time 24.33 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:57 PM PDT 24
Peak memory 248068 kb
Host smart-5ac6b6cf-8a82-4658-a141-fa5c2691db1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748175249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3748175249
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.3115636541
Short name T1018
Test name
Test status
Simulation time 3956336996 ps
CPU time 12.01 seconds
Started Jul 21 06:34:32 PM PDT 24
Finished Jul 21 06:34:46 PM PDT 24
Peak memory 242268 kb
Host smart-c5bb6147-ca6e-4023-9302-0d7e0ccf7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115636541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3115636541
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.861525432
Short name T71
Test name
Test status
Simulation time 421345896 ps
CPU time 7.29 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241196 kb
Host smart-00a4b60c-ebb5-4c5d-9c1b-06a2f643d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861525432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.861525432
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2175544838
Short name T618
Test name
Test status
Simulation time 1944483791 ps
CPU time 25.69 seconds
Started Jul 21 06:34:31 PM PDT 24
Finished Jul 21 06:34:59 PM PDT 24
Peak memory 241484 kb
Host smart-d35b090d-5ac2-4e2e-919e-fc004c3b5685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175544838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2175544838
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1737128993
Short name T550
Test name
Test status
Simulation time 381335876 ps
CPU time 6.26 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241264 kb
Host smart-e5d6d34b-36c7-48fd-921c-d2b1099ce5ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737128993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1737128993
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.4182085999
Short name T429
Test name
Test status
Simulation time 990489070 ps
CPU time 8.42 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:40 PM PDT 24
Peak memory 241452 kb
Host smart-eee5d31c-7e1f-4b53-8821-e49e0d78183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182085999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.4182085999
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1815517277
Short name T28
Test name
Test status
Simulation time 281471546604 ps
CPU time 830.93 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:48:23 PM PDT 24
Peak memory 264492 kb
Host smart-94caeec3-82c9-491d-9597-eca3e6a8b297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815517277 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1815517277
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2101774685
Short name T967
Test name
Test status
Simulation time 2937798179 ps
CPU time 25.51 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 241864 kb
Host smart-dd25c004-4016-48e5-b91b-87e26911f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101774685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2101774685
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.1069542075
Short name T165
Test name
Test status
Simulation time 2644531234 ps
CPU time 7.37 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:47 PM PDT 24
Peak memory 241596 kb
Host smart-55da46ff-a604-4b35-a2f5-d1c79a000381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069542075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1069542075
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.4198735386
Short name T889
Test name
Test status
Simulation time 209163860 ps
CPU time 3.47 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:42 PM PDT 24
Peak memory 241220 kb
Host smart-bdabf6f4-5886-460e-b40e-d909472f4749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198735386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.4198735386
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.2025482173
Short name T295
Test name
Test status
Simulation time 246887517 ps
CPU time 4.4 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241448 kb
Host smart-42a5b6d9-1ff7-4f0f-9800-103192ecac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025482173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2025482173
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.56484043
Short name T330
Test name
Test status
Simulation time 1106167764 ps
CPU time 3.37 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241148 kb
Host smart-3d4e9253-ea23-44f6-9fc2-0ca5627d140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56484043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.56484043
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2306121716
Short name T726
Test name
Test status
Simulation time 201250143 ps
CPU time 4.34 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241260 kb
Host smart-a65c00f5-1352-4023-a135-8a86b1c10ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306121716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2306121716
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1500407261
Short name T179
Test name
Test status
Simulation time 111816049 ps
CPU time 4.83 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241680 kb
Host smart-1e68a35c-9ad2-4a72-9d96-cdde75921557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500407261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1500407261
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.3176987399
Short name T1
Test name
Test status
Simulation time 2096318370 ps
CPU time 3.99 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:42 PM PDT 24
Peak memory 241664 kb
Host smart-a8bfa35f-2572-4d80-8ba6-a0ebf2042fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176987399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3176987399
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1633462937
Short name T1053
Test name
Test status
Simulation time 199799256 ps
CPU time 3.35 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:42 PM PDT 24
Peak memory 241508 kb
Host smart-134fada3-c07a-4088-bd77-bcba09e57ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633462937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1633462937
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.3402711208
Short name T1151
Test name
Test status
Simulation time 337454517 ps
CPU time 8.02 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241572 kb
Host smart-6b03f935-c2e0-4977-9905-8a69bdbfa82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402711208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3402711208
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.2568949336
Short name T206
Test name
Test status
Simulation time 118742823 ps
CPU time 3.6 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241420 kb
Host smart-4fb98345-d551-4aa0-aadb-7b70bc9728c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568949336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2568949336
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3357615288
Short name T983
Test name
Test status
Simulation time 307436991 ps
CPU time 7.42 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:45 PM PDT 24
Peak memory 241536 kb
Host smart-e545efc7-cb8a-4d41-b9bc-a55ce454d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357615288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3357615288
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3268376595
Short name T616
Test name
Test status
Simulation time 292525447 ps
CPU time 4.11 seconds
Started Jul 21 06:36:42 PM PDT 24
Finished Jul 21 06:36:47 PM PDT 24
Peak memory 241404 kb
Host smart-d0f40431-c9d1-4a1b-8b83-7da348f25f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268376595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3268376595
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.4231432807
Short name T915
Test name
Test status
Simulation time 4330363209 ps
CPU time 9.03 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:47 PM PDT 24
Peak memory 241788 kb
Host smart-02e59265-cfd0-40c6-9cde-c52bb3384155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231432807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.4231432807
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.880172116
Short name T709
Test name
Test status
Simulation time 127495038 ps
CPU time 5.2 seconds
Started Jul 21 06:36:45 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241536 kb
Host smart-565efd1e-5aec-4417-b5a2-d0b2c6f2a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880172116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.880172116
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.2883516724
Short name T552
Test name
Test status
Simulation time 3261363591 ps
CPU time 6.69 seconds
Started Jul 21 06:36:43 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241300 kb
Host smart-8a8c6fcb-37a0-450d-b810-fd71e3d1f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883516724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2883516724
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.882449340
Short name T946
Test name
Test status
Simulation time 117382591 ps
CPU time 4.46 seconds
Started Jul 21 06:36:49 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241132 kb
Host smart-59bc1668-017e-468e-96cb-eee854d10e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882449340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.882449340
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.2057037499
Short name T698
Test name
Test status
Simulation time 829757954 ps
CPU time 2.4 seconds
Started Jul 21 06:34:33 PM PDT 24
Finished Jul 21 06:34:37 PM PDT 24
Peak memory 239744 kb
Host smart-2d8ac991-f390-47bf-b200-6f6390b21455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057037499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2057037499
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.3296421687
Short name T1024
Test name
Test status
Simulation time 504091354 ps
CPU time 13.97 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:53 PM PDT 24
Peak memory 241816 kb
Host smart-13128cbe-574f-439c-b0ae-ef0c80479d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296421687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3296421687
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.146456220
Short name T1076
Test name
Test status
Simulation time 3889505817 ps
CPU time 35.18 seconds
Started Jul 21 06:34:38 PM PDT 24
Finished Jul 21 06:35:15 PM PDT 24
Peak memory 241652 kb
Host smart-bfbd4b55-6394-4b34-9107-4c52ecc8413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146456220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.146456220
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.194312698
Short name T171
Test name
Test status
Simulation time 156249092 ps
CPU time 3.79 seconds
Started Jul 21 06:34:30 PM PDT 24
Finished Jul 21 06:34:36 PM PDT 24
Peak memory 241520 kb
Host smart-cdc58531-2333-4c94-a29b-7132e0840be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194312698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.194312698
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.3828488570
Short name T782
Test name
Test status
Simulation time 625591259 ps
CPU time 13.59 seconds
Started Jul 21 06:34:33 PM PDT 24
Finished Jul 21 06:34:48 PM PDT 24
Peak memory 243560 kb
Host smart-183b2b27-fac9-4a1c-9beb-6045ac8699ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828488570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3828488570
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.1671779770
Short name T471
Test name
Test status
Simulation time 2483051306 ps
CPU time 35.97 seconds
Started Jul 21 06:34:34 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 241832 kb
Host smart-043b4864-a4c1-4905-9c0c-e3411fa3ba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671779770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1671779770
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.4241947259
Short name T529
Test name
Test status
Simulation time 1240573521 ps
CPU time 7.93 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241532 kb
Host smart-6989fda6-05f2-4eb1-aa4f-5cb55054bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241947259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.4241947259
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.3143547991
Short name T700
Test name
Test status
Simulation time 603325552 ps
CPU time 7.71 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:40 PM PDT 24
Peak memory 241528 kb
Host smart-dcd03832-9dc7-49bc-b6d2-76528e4e973e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143547991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3143547991
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.4284809944
Short name T966
Test name
Test status
Simulation time 224365358 ps
CPU time 4.7 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241240 kb
Host smart-a0a98b1f-2375-49f8-b21b-d32b8f890428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284809944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.4284809944
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.3137383972
Short name T1031
Test name
Test status
Simulation time 292524638 ps
CPU time 7.33 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241608 kb
Host smart-7950a371-eea3-4fed-98d8-307c0c682737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137383972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3137383972
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3401543932
Short name T261
Test name
Test status
Simulation time 24827010965 ps
CPU time 202.5 seconds
Started Jul 21 06:34:48 PM PDT 24
Finished Jul 21 06:38:14 PM PDT 24
Peak memory 256320 kb
Host smart-171d9666-d23f-483f-8044-7d8c26fd0a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401543932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3401543932
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.884816404
Short name T110
Test name
Test status
Simulation time 21364038640 ps
CPU time 198.8 seconds
Started Jul 21 06:34:36 PM PDT 24
Finished Jul 21 06:37:57 PM PDT 24
Peak memory 248140 kb
Host smart-a81e761a-4922-41c3-8f9e-0a1c4a9ced10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884816404 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.884816404
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.3873944591
Short name T479
Test name
Test status
Simulation time 6268403327 ps
CPU time 26.74 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 241664 kb
Host smart-c315ac4e-d9b7-49de-8c20-b6c5c114ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873944591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3873944591
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2077624295
Short name T694
Test name
Test status
Simulation time 205549320 ps
CPU time 4.1 seconds
Started Jul 21 06:36:43 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241432 kb
Host smart-187e9fcb-cf34-43bd-92fb-1c6c92091a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077624295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2077624295
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3850995244
Short name T117
Test name
Test status
Simulation time 636698086 ps
CPU time 8.17 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241212 kb
Host smart-b2ab7f32-1d03-4a2c-a02f-5cfefa34e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850995244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3850995244
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.90179798
Short name T597
Test name
Test status
Simulation time 109280162 ps
CPU time 4.19 seconds
Started Jul 21 06:36:47 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241464 kb
Host smart-13c32147-fe24-4090-b8a8-921f58ef4920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90179798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.90179798
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3483326303
Short name T1145
Test name
Test status
Simulation time 762560003 ps
CPU time 8.58 seconds
Started Jul 21 06:36:43 PM PDT 24
Finished Jul 21 06:36:53 PM PDT 24
Peak memory 241608 kb
Host smart-20786cac-6df0-4ca8-bc8a-2c5113787c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483326303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3483326303
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.4280632175
Short name T500
Test name
Test status
Simulation time 342597172 ps
CPU time 4.5 seconds
Started Jul 21 06:36:46 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241416 kb
Host smart-7f873ad6-148c-454e-90e2-50bd0e4d47d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280632175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4280632175
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.4225048558
Short name T256
Test name
Test status
Simulation time 805837821 ps
CPU time 11.86 seconds
Started Jul 21 06:36:46 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241192 kb
Host smart-9d391042-475f-44f3-9f04-8e40833a63f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225048558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.4225048558
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3777618776
Short name T604
Test name
Test status
Simulation time 153199632 ps
CPU time 4.58 seconds
Started Jul 21 06:36:42 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241416 kb
Host smart-1b6729b4-56ec-4815-8c7c-ca2fc0552ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777618776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3777618776
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.3712476024
Short name T496
Test name
Test status
Simulation time 255774969 ps
CPU time 6.49 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:52 PM PDT 24
Peak memory 241272 kb
Host smart-6aa9f10f-24cb-4858-a671-7c93b1573849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712476024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3712476024
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.4242067966
Short name T464
Test name
Test status
Simulation time 780576206 ps
CPU time 5.99 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241088 kb
Host smart-a913640f-f78b-4f53-a8f7-440fb9639637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242067966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4242067966
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.1535708334
Short name T896
Test name
Test status
Simulation time 122289973 ps
CPU time 3.53 seconds
Started Jul 21 06:36:46 PM PDT 24
Finished Jul 21 06:36:50 PM PDT 24
Peak memory 241204 kb
Host smart-c114e643-20d5-4218-8143-6d5a91653064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535708334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1535708334
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.4230944160
Short name T880
Test name
Test status
Simulation time 983451927 ps
CPU time 27.87 seconds
Started Jul 21 06:36:45 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241512 kb
Host smart-115c79eb-1049-4604-ad28-9653a6a86a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230944160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.4230944160
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.3516820192
Short name T754
Test name
Test status
Simulation time 1644271761 ps
CPU time 4.94 seconds
Started Jul 21 06:36:43 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 241372 kb
Host smart-8f51f53a-125a-48ef-9951-cea39b5f73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516820192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3516820192
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2422402524
Short name T663
Test name
Test status
Simulation time 237203532 ps
CPU time 3.71 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 241144 kb
Host smart-894fd02b-a5c6-46e7-9d47-665206d4081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422402524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2422402524
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2924097128
Short name T936
Test name
Test status
Simulation time 161781715 ps
CPU time 3.88 seconds
Started Jul 21 06:36:45 PM PDT 24
Finished Jul 21 06:36:50 PM PDT 24
Peak memory 241708 kb
Host smart-9ae6309d-a6e3-4e07-a3e5-628b834a7217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924097128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2924097128
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3005898255
Short name T1160
Test name
Test status
Simulation time 85907977 ps
CPU time 3.26 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 241508 kb
Host smart-a4d4af39-191e-42b9-8e09-f6b0c5dec59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005898255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3005898255
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3386572107
Short name T695
Test name
Test status
Simulation time 153505662 ps
CPU time 3.75 seconds
Started Jul 21 06:36:43 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241240 kb
Host smart-3af7b93e-51cf-400e-b7f4-9efaa756d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386572107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3386572107
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.4021409471
Short name T87
Test name
Test status
Simulation time 342133093 ps
CPU time 3.2 seconds
Started Jul 21 06:36:46 PM PDT 24
Finished Jul 21 06:36:50 PM PDT 24
Peak memory 241656 kb
Host smart-347064e5-9f7a-4699-b6eb-e43634338dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021409471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.4021409471
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1240937034
Short name T325
Test name
Test status
Simulation time 514392587 ps
CPU time 6.85 seconds
Started Jul 21 06:36:49 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241196 kb
Host smart-39fc3784-3329-4a84-8749-6bb7f8c0f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240937034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1240937034
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1674895412
Short name T679
Test name
Test status
Simulation time 125811516 ps
CPU time 1.92 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:41 PM PDT 24
Peak memory 239656 kb
Host smart-87fa722f-8005-4daf-8282-a29d4aae5f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674895412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1674895412
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.914124616
Short name T821
Test name
Test status
Simulation time 316248237 ps
CPU time 17.91 seconds
Started Jul 21 06:34:33 PM PDT 24
Finished Jul 21 06:34:52 PM PDT 24
Peak memory 241208 kb
Host smart-69a5381f-d19b-469d-a1f5-d2390c10246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914124616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.914124616
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.1257081655
Short name T750
Test name
Test status
Simulation time 18113272921 ps
CPU time 34.37 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 242280 kb
Host smart-419d9b27-593a-447e-9b62-d8aebb1a02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257081655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.1257081655
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.2362996619
Short name T902
Test name
Test status
Simulation time 136170703 ps
CPU time 3.76 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:34:54 PM PDT 24
Peak memory 241704 kb
Host smart-908a7a7c-f1ae-45f1-8977-aedfc597d205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362996619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.2362996619
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2579846465
Short name T200
Test name
Test status
Simulation time 1534834431 ps
CPU time 31.08 seconds
Started Jul 21 06:34:36 PM PDT 24
Finished Jul 21 06:35:09 PM PDT 24
Peak memory 248356 kb
Host smart-69d35ac1-8786-418d-a88e-ce5296ad7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579846465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2579846465
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.130314862
Short name T795
Test name
Test status
Simulation time 436732730 ps
CPU time 4.56 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:34:47 PM PDT 24
Peak memory 247916 kb
Host smart-00f510f8-52e6-46ec-965e-00fc6d9ba45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130314862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.130314862
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2106083205
Short name T533
Test name
Test status
Simulation time 7878306521 ps
CPU time 19.87 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:59 PM PDT 24
Peak memory 241324 kb
Host smart-c52ce343-7280-4c61-aa61-1cc052039f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106083205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2106083205
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.4188151313
Short name T431
Test name
Test status
Simulation time 2743542353 ps
CPU time 21.71 seconds
Started Jul 21 06:34:38 PM PDT 24
Finished Jul 21 06:35:02 PM PDT 24
Peak memory 248012 kb
Host smart-8af675ef-acc4-41fd-9b18-b714b58cbac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188151313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.4188151313
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2390388550
Short name T357
Test name
Test status
Simulation time 840151707 ps
CPU time 7.22 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 241564 kb
Host smart-eba6daf6-ea12-4d2c-b624-474c646cae66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390388550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2390388550
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.813326415
Short name T558
Test name
Test status
Simulation time 197848153 ps
CPU time 4.26 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:41 PM PDT 24
Peak memory 241340 kb
Host smart-5b830650-3559-4dd8-8788-05083c1bb87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813326415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.813326415
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.863949541
Short name T478
Test name
Test status
Simulation time 53784053431 ps
CPU time 162.24 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:37:20 PM PDT 24
Peak memory 249512 kb
Host smart-654c6b3f-f497-4e59-8bd6-0a55563e0de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863949541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.
863949541
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.2720108816
Short name T1071
Test name
Test status
Simulation time 2458934983 ps
CPU time 25.44 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 241556 kb
Host smart-778cc796-ac24-46d6-a04f-79c3bae1b2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720108816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2720108816
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.1974225770
Short name T589
Test name
Test status
Simulation time 1705907048 ps
CPU time 5.81 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241228 kb
Host smart-2ee42318-f5cf-4e42-9d5a-38536a4d5875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974225770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1974225770
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3367267790
Short name T1037
Test name
Test status
Simulation time 497575303 ps
CPU time 7.36 seconds
Started Jul 21 06:36:46 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241196 kb
Host smart-2219f9e4-fdef-4364-8444-051c65198743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367267790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3367267790
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2353663827
Short name T790
Test name
Test status
Simulation time 505708963 ps
CPU time 3.95 seconds
Started Jul 21 06:36:44 PM PDT 24
Finished Jul 21 06:36:50 PM PDT 24
Peak memory 241540 kb
Host smart-d1824aa0-29f0-45c1-8d11-178017fa4143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353663827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2353663827
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.2862037381
Short name T847
Test name
Test status
Simulation time 271390979 ps
CPU time 6.73 seconds
Started Jul 21 06:36:47 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241252 kb
Host smart-5096397a-d529-4280-9bea-5644b4d1eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862037381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2862037381
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3044315750
Short name T208
Test name
Test status
Simulation time 184885314 ps
CPU time 4.42 seconds
Started Jul 21 06:36:55 PM PDT 24
Finished Jul 21 06:37:00 PM PDT 24
Peak memory 241372 kb
Host smart-188fccd4-1399-4dda-b3d9-b02460a28fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044315750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3044315750
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3921168235
Short name T908
Test name
Test status
Simulation time 4468447205 ps
CPU time 7.24 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:37:00 PM PDT 24
Peak memory 241616 kb
Host smart-07a9f06b-6561-44ad-b951-624b281bafb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921168235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3921168235
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.4126953601
Short name T798
Test name
Test status
Simulation time 142919614 ps
CPU time 3.74 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:36:55 PM PDT 24
Peak memory 241308 kb
Host smart-a0f5d422-4cc4-4103-acaa-8f1a5e4f349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126953601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.4126953601
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.208105415
Short name T258
Test name
Test status
Simulation time 186211195 ps
CPU time 8.08 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241508 kb
Host smart-f043d2af-9498-4798-8548-37f718618286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208105415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.208105415
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.605419189
Short name T501
Test name
Test status
Simulation time 225273878 ps
CPU time 4.24 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241400 kb
Host smart-0312729d-4a9d-453c-95e0-dc0914bf62ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605419189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.605419189
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.204587759
Short name T734
Test name
Test status
Simulation time 2046103872 ps
CPU time 17.45 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241328 kb
Host smart-2d88151a-693a-41fb-adb3-0756bade84a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204587759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.204587759
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3829674562
Short name T411
Test name
Test status
Simulation time 149094351 ps
CPU time 4.91 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241200 kb
Host smart-c6fb8688-431b-4850-895e-0fe7a688d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829674562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3829674562
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.3961593817
Short name T919
Test name
Test status
Simulation time 961759009 ps
CPU time 7.63 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:37:01 PM PDT 24
Peak memory 241280 kb
Host smart-23eb5a31-5ad0-4687-9a4c-f655d0a73de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961593817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.3961593817
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3050619363
Short name T155
Test name
Test status
Simulation time 428150979 ps
CPU time 3.95 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241220 kb
Host smart-4ca8b346-0f20-4736-9edd-e439ec3a9118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050619363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3050619363
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2564655055
Short name T837
Test name
Test status
Simulation time 185031056 ps
CPU time 5.19 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241248 kb
Host smart-55b719e0-1fb6-4171-abf4-06856c67d584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564655055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2564655055
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.3616665190
Short name T922
Test name
Test status
Simulation time 214844612 ps
CPU time 3.73 seconds
Started Jul 21 06:36:53 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241452 kb
Host smart-241f6102-336f-426f-814a-6662c732e8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616665190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3616665190
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.4216861461
Short name T641
Test name
Test status
Simulation time 10944495242 ps
CPU time 20.44 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:37:13 PM PDT 24
Peak memory 241340 kb
Host smart-f099e380-86e8-4872-bcb6-fbf3a29b2519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216861461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.4216861461
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.33035976
Short name T661
Test name
Test status
Simulation time 1780717232 ps
CPU time 4.83 seconds
Started Jul 21 06:36:49 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241260 kb
Host smart-712d9779-ed87-4cb7-9c84-d1873cc9ea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33035976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.33035976
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3113205261
Short name T960
Test name
Test status
Simulation time 395069400 ps
CPU time 11.51 seconds
Started Jul 21 06:36:53 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241108 kb
Host smart-5ef67cf6-46f0-43f2-885b-08d56c411463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113205261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3113205261
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.2269880720
Short name T60
Test name
Test status
Simulation time 231021369 ps
CPU time 4.33 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:36:56 PM PDT 24
Peak memory 241544 kb
Host smart-b046cb16-f4ac-4369-b9bd-c83d6c8e10ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269880720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2269880720
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3209282500
Short name T294
Test name
Test status
Simulation time 229829044 ps
CPU time 6.74 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241632 kb
Host smart-841fc92a-92d4-40d9-a3a6-b643b6ef0ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209282500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3209282500
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.2667619466
Short name T1086
Test name
Test status
Simulation time 178931165 ps
CPU time 1.94 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:39 PM PDT 24
Peak memory 239816 kb
Host smart-95fab01d-0864-4303-92b5-350c9d9c46b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667619466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2667619466
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2303308394
Short name T53
Test name
Test status
Simulation time 1391158137 ps
CPU time 27.03 seconds
Started Jul 21 06:34:38 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 242156 kb
Host smart-e4773c6a-fe66-4802-8819-cc747979d163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303308394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2303308394
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.683088857
Short name T964
Test name
Test status
Simulation time 851909650 ps
CPU time 11.92 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 241288 kb
Host smart-57e26802-f729-4663-9a18-114b2b109517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683088857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.683088857
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3924772860
Short name T395
Test name
Test status
Simulation time 1363046856 ps
CPU time 9.96 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 241408 kb
Host smart-c53dad0d-d59c-45b7-8c6e-e4c8346911ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924772860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3924772860
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.2754745588
Short name T540
Test name
Test status
Simulation time 230486786 ps
CPU time 4.74 seconds
Started Jul 21 06:34:38 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241156 kb
Host smart-f35f0e62-968b-4b13-9f90-a1b0fd4f1cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754745588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2754745588
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.882715478
Short name T525
Test name
Test status
Simulation time 1023458975 ps
CPU time 30.56 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 243548 kb
Host smart-ebd80d78-8590-4abe-9046-21ee2671609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882715478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.882715478
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1580013041
Short name T470
Test name
Test status
Simulation time 3098086540 ps
CPU time 45.3 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:35:22 PM PDT 24
Peak memory 242600 kb
Host smart-2efdc38f-5125-49ca-9b65-500dab17baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580013041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1580013041
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.155935276
Short name T892
Test name
Test status
Simulation time 138208973 ps
CPU time 3.2 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241268 kb
Host smart-a0b2ed0b-a3b4-4e81-8094-dafcadb9e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155935276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.155935276
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1417417211
Short name T933
Test name
Test status
Simulation time 349296030 ps
CPU time 10.5 seconds
Started Jul 21 06:34:34 PM PDT 24
Finished Jul 21 06:34:47 PM PDT 24
Peak memory 241604 kb
Host smart-9f3f816b-c473-4135-8c9b-462da96c0bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417417211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1417417211
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2134278165
Short name T929
Test name
Test status
Simulation time 318531184 ps
CPU time 10.29 seconds
Started Jul 21 06:34:34 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241280 kb
Host smart-04cb06b1-cc1b-442f-8e21-8ae00d5aaa7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134278165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2134278165
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.3161244238
Short name T1148
Test name
Test status
Simulation time 532361639 ps
CPU time 3.96 seconds
Started Jul 21 06:34:39 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241452 kb
Host smart-f627539d-2ccd-4216-a9fd-f232c7e32d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161244238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.3161244238
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.2694048942
Short name T833
Test name
Test status
Simulation time 71763669 ps
CPU time 2.07 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 240756 kb
Host smart-913f816b-2833-446b-95cd-a37419e965a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694048942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.2694048942
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.223558206
Short name T916
Test name
Test status
Simulation time 6238891784 ps
CPU time 38.34 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 241668 kb
Host smart-4c8896e6-20df-4ccb-8990-7183c133042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223558206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.223558206
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2172322651
Short name T390
Test name
Test status
Simulation time 217955945 ps
CPU time 4.19 seconds
Started Jul 21 06:36:50 PM PDT 24
Finished Jul 21 06:36:56 PM PDT 24
Peak memory 241244 kb
Host smart-67abd21e-00c2-46ea-977c-1030246c658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172322651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2172322651
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.484161039
Short name T1129
Test name
Test status
Simulation time 515502816 ps
CPU time 5.74 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241272 kb
Host smart-7aaebb0d-2e08-4f63-8402-a1def8cccb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484161039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.484161039
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.4006299362
Short name T890
Test name
Test status
Simulation time 538929541 ps
CPU time 8.01 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:37:01 PM PDT 24
Peak memory 241248 kb
Host smart-5411f4da-dfa0-4390-a38c-71d65ef3df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006299362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.4006299362
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.427416556
Short name T1063
Test name
Test status
Simulation time 117442709 ps
CPU time 4.21 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241328 kb
Host smart-32f7a859-2a79-4be9-90ce-9d10cd4c022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427416556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.427416556
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.3542611268
Short name T194
Test name
Test status
Simulation time 220763313 ps
CPU time 4.04 seconds
Started Jul 21 06:36:49 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 241192 kb
Host smart-90571d26-9701-4161-ac78-70a8df8bf5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542611268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3542611268
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.3675614535
Short name T585
Test name
Test status
Simulation time 225309258 ps
CPU time 4.43 seconds
Started Jul 21 06:36:53 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241464 kb
Host smart-46468c69-6041-4ed4-8475-c4d521535668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675614535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3675614535
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2619793072
Short name T404
Test name
Test status
Simulation time 269234098 ps
CPU time 7.13 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241284 kb
Host smart-996c994b-3540-4c0f-abd2-7e5e967b897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619793072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2619793072
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1357969577
Short name T1029
Test name
Test status
Simulation time 159814737 ps
CPU time 4.26 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241544 kb
Host smart-ffbf714e-7d91-4c60-a651-298272ea6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357969577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1357969577
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.1941376925
Short name T236
Test name
Test status
Simulation time 399461721 ps
CPU time 9.56 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:37:02 PM PDT 24
Peak memory 241204 kb
Host smart-ecf70044-b359-4f89-a408-fb78a4e1e9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941376925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1941376925
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2883678314
Short name T56
Test name
Test status
Simulation time 257158847 ps
CPU time 4.43 seconds
Started Jul 21 06:36:53 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241228 kb
Host smart-2d7d63bf-c5bf-43b2-bfc2-053fc515c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883678314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2883678314
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.353740258
Short name T557
Test name
Test status
Simulation time 343657027 ps
CPU time 9.4 seconds
Started Jul 21 06:36:53 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 240972 kb
Host smart-67593e55-86a0-4eb0-a0a6-b9c608c7bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353740258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.353740258
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.2387711860
Short name T1174
Test name
Test status
Simulation time 296397947 ps
CPU time 5.38 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241336 kb
Host smart-8ed9dfbc-d932-4dad-aeab-f725dbef6ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387711860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2387711860
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1211960561
Short name T1040
Test name
Test status
Simulation time 594475941 ps
CPU time 10.52 seconds
Started Jul 21 06:36:53 PM PDT 24
Finished Jul 21 06:37:05 PM PDT 24
Peak memory 241300 kb
Host smart-fabfdfeb-b0e0-4edf-abe4-d902790b24a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211960561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1211960561
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.2761752232
Short name T1138
Test name
Test status
Simulation time 125120138 ps
CPU time 3.8 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:57 PM PDT 24
Peak memory 241392 kb
Host smart-b02cae90-b057-437a-82fe-d46002a4484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761752232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2761752232
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3583261543
Short name T209
Test name
Test status
Simulation time 148650169 ps
CPU time 3.37 seconds
Started Jul 21 06:36:51 PM PDT 24
Finished Jul 21 06:36:56 PM PDT 24
Peak memory 241304 kb
Host smart-e4603f46-2568-4ff1-b17c-d48b1fdc6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583261543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3583261543
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2757697437
Short name T684
Test name
Test status
Simulation time 2811774511 ps
CPU time 7.96 seconds
Started Jul 21 06:36:55 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 241268 kb
Host smart-05432b36-f72b-42af-89d1-605520e4d400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757697437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2757697437
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1383929092
Short name T877
Test name
Test status
Simulation time 118394752 ps
CPU time 4.27 seconds
Started Jul 21 06:36:52 PM PDT 24
Finished Jul 21 06:36:58 PM PDT 24
Peak memory 241432 kb
Host smart-93b00640-df59-470e-b8e9-0394d522febe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383929092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1383929092
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.245311888
Short name T580
Test name
Test status
Simulation time 783891526 ps
CPU time 12.11 seconds
Started Jul 21 06:36:55 PM PDT 24
Finished Jul 21 06:37:08 PM PDT 24
Peak memory 241512 kb
Host smart-a707ebe1-cfac-47d5-bc2f-808bc07ecb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245311888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.245311888
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.187584650
Short name T476
Test name
Test status
Simulation time 886130282 ps
CPU time 2.36 seconds
Started Jul 21 06:34:36 PM PDT 24
Finished Jul 21 06:34:41 PM PDT 24
Peak memory 239656 kb
Host smart-a551979c-e08a-44f6-a6ae-e033482d046d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187584650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.187584650
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.3410326285
Short name T299
Test name
Test status
Simulation time 167949123 ps
CPU time 5.76 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:43 PM PDT 24
Peak memory 247980 kb
Host smart-b5418031-f4d6-4549-af4f-894d53731f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410326285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3410326285
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.1448099638
Short name T551
Test name
Test status
Simulation time 836879491 ps
CPU time 33.89 seconds
Started Jul 21 06:34:48 PM PDT 24
Finished Jul 21 06:35:25 PM PDT 24
Peak memory 241988 kb
Host smart-2d1bf0a9-9a51-4466-b1da-ff2c833f3486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448099638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1448099638
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.2742623920
Short name T873
Test name
Test status
Simulation time 2276705919 ps
CPU time 3.86 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:34:46 PM PDT 24
Peak memory 241840 kb
Host smart-1ad0120b-b1e4-47ba-b90a-661d9890f1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742623920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2742623920
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.2742771771
Short name T537
Test name
Test status
Simulation time 2147546305 ps
CPU time 33.47 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 246484 kb
Host smart-23d306eb-aba3-4f51-a5a2-0a11a4798913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742771771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2742771771
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.529192290
Short name T682
Test name
Test status
Simulation time 2372676648 ps
CPU time 17.77 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 241620 kb
Host smart-7899b3e6-f2fe-4060-ab9d-c3ba58d3ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529192290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.529192290
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2399202246
Short name T1130
Test name
Test status
Simulation time 783226547 ps
CPU time 21.62 seconds
Started Jul 21 06:34:34 PM PDT 24
Finished Jul 21 06:34:58 PM PDT 24
Peak memory 241140 kb
Host smart-fcc400de-4dcb-42d7-87a2-48352e3266f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399202246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2399202246
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1370989752
Short name T519
Test name
Test status
Simulation time 1004372688 ps
CPU time 17.66 seconds
Started Jul 21 06:34:36 PM PDT 24
Finished Jul 21 06:34:55 PM PDT 24
Peak memory 241328 kb
Host smart-0d431483-97da-40c1-96bb-67d5984dc74b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370989752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1370989752
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2935237025
Short name T366
Test name
Test status
Simulation time 4448914965 ps
CPU time 8.36 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:48 PM PDT 24
Peak memory 247996 kb
Host smart-6f43eb26-012b-4799-ab4e-077d0c31777b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935237025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2935237025
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1991389694
Short name T881
Test name
Test status
Simulation time 1136443364 ps
CPU time 8.55 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:48 PM PDT 24
Peak memory 241424 kb
Host smart-34461e5d-f1af-49cf-9e03-a7e288fa57e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991389694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1991389694
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1524068942
Short name T997
Test name
Test status
Simulation time 6458640890 ps
CPU time 91.88 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 245084 kb
Host smart-a7e32d90-8c82-4613-aa4e-90c36826b1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524068942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1524068942
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.1794513138
Short name T439
Test name
Test status
Simulation time 230961321 ps
CPU time 4.97 seconds
Started Jul 21 06:34:37 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 241840 kb
Host smart-a78555f2-53d4-4885-bd85-3e12d67b0d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794513138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1794513138
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.3658474082
Short name T219
Test name
Test status
Simulation time 418671620 ps
CPU time 4.2 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 241372 kb
Host smart-548f89a8-a64d-4e18-ac6e-b448083a137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658474082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3658474082
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.683635322
Short name T532
Test name
Test status
Simulation time 487286422 ps
CPU time 11.91 seconds
Started Jul 21 06:37:00 PM PDT 24
Finished Jul 21 06:37:13 PM PDT 24
Peak memory 241584 kb
Host smart-eb71054e-13e1-468e-bdad-c0dc6beb9ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683635322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.683635322
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.3062969414
Short name T484
Test name
Test status
Simulation time 2544862911 ps
CPU time 7.97 seconds
Started Jul 21 06:37:00 PM PDT 24
Finished Jul 21 06:37:08 PM PDT 24
Peak memory 241480 kb
Host smart-51ee8d0d-b2c1-4ad1-81b5-d69635e54f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062969414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3062969414
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.230903687
Short name T763
Test name
Test status
Simulation time 309428046 ps
CPU time 17.49 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 241168 kb
Host smart-fe4de3bd-73a8-48e4-9eac-db4b4a7593f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230903687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.230903687
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.650118256
Short name T1149
Test name
Test status
Simulation time 112250496 ps
CPU time 4.54 seconds
Started Jul 21 06:37:00 PM PDT 24
Finished Jul 21 06:37:05 PM PDT 24
Peak memory 241368 kb
Host smart-dd2a6700-8855-4bcf-9227-ca71c8bfbe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650118256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.650118256
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.749869464
Short name T1078
Test name
Test status
Simulation time 252006943 ps
CPU time 5.16 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:05 PM PDT 24
Peak memory 241324 kb
Host smart-da9e76f7-c5c9-4238-9dfe-e47797b153f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749869464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.749869464
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3440132486
Short name T34
Test name
Test status
Simulation time 619888861 ps
CPU time 5.23 seconds
Started Jul 21 06:36:56 PM PDT 24
Finished Jul 21 06:37:02 PM PDT 24
Peak memory 241156 kb
Host smart-77e00e53-6197-4531-8fe5-0404bd98f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440132486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3440132486
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.27387080
Short name T753
Test name
Test status
Simulation time 10757958507 ps
CPU time 25.65 seconds
Started Jul 21 06:36:55 PM PDT 24
Finished Jul 21 06:37:22 PM PDT 24
Peak memory 241284 kb
Host smart-515c0d88-5a59-4f60-a026-cce06188ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27387080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.27387080
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.2420330085
Short name T531
Test name
Test status
Simulation time 2277522093 ps
CPU time 6.47 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241404 kb
Host smart-5dc0c447-6e12-46ad-b1af-a992323cbb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420330085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2420330085
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.3359570871
Short name T488
Test name
Test status
Simulation time 275071645 ps
CPU time 3.79 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:03 PM PDT 24
Peak memory 241132 kb
Host smart-061c9ec8-460c-43c9-933c-7d2feab92d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359570871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3359570871
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.1212267929
Short name T335
Test name
Test status
Simulation time 365962722 ps
CPU time 4.64 seconds
Started Jul 21 06:36:59 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 241092 kb
Host smart-81233137-c7b4-4b5d-8fc9-ea3e7a5141eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212267929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1212267929
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.3975511811
Short name T221
Test name
Test status
Simulation time 146127729 ps
CPU time 3.98 seconds
Started Jul 21 06:36:56 PM PDT 24
Finished Jul 21 06:37:00 PM PDT 24
Peak memory 241244 kb
Host smart-de7522ca-6047-40ef-87f9-070ff1f797f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975511811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3975511811
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.808490521
Short name T72
Test name
Test status
Simulation time 220540376 ps
CPU time 12.98 seconds
Started Jul 21 06:36:59 PM PDT 24
Finished Jul 21 06:37:13 PM PDT 24
Peak memory 241536 kb
Host smart-0a4c50ab-8a71-4a61-8f6c-490fc46d943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808490521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.808490521
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.87174007
Short name T644
Test name
Test status
Simulation time 357897006 ps
CPU time 4.08 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:02 PM PDT 24
Peak memory 241672 kb
Host smart-7c71f77c-b127-4ecb-96eb-17c10e64e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87174007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.87174007
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3033579464
Short name T849
Test name
Test status
Simulation time 106160962 ps
CPU time 4.1 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 241244 kb
Host smart-c4d64f50-db14-4c4b-aa49-a587ebeac354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033579464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3033579464
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.3736038820
Short name T910
Test name
Test status
Simulation time 201877187 ps
CPU time 4.32 seconds
Started Jul 21 06:37:01 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241668 kb
Host smart-62925693-f045-464b-bd15-e3edadbe5d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736038820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3736038820
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.1902349098
Short name T118
Test name
Test status
Simulation time 222710812 ps
CPU time 3.52 seconds
Started Jul 21 06:36:55 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 241612 kb
Host smart-66217d91-26db-4ed1-9a88-a5b5255c34e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902349098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1902349098
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.3376216547
Short name T475
Test name
Test status
Simulation time 1607375470 ps
CPU time 4.99 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:03 PM PDT 24
Peak memory 241144 kb
Host smart-c4c9fe0e-cd5f-4b3f-b055-3f5bc5d56ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376216547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3376216547
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.3737113528
Short name T459
Test name
Test status
Simulation time 190658424 ps
CPU time 1.9 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:34:46 PM PDT 24
Peak memory 239620 kb
Host smart-873cdd22-aa66-4274-b5b5-202ac9252581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737113528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3737113528
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2991330221
Short name T384
Test name
Test status
Simulation time 171192012 ps
CPU time 4.24 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:34:46 PM PDT 24
Peak memory 241472 kb
Host smart-c4b7ac60-7d2b-41c2-9d40-e4280e6bf5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991330221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2991330221
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.3148033503
Short name T399
Test name
Test status
Simulation time 977703295 ps
CPU time 30.99 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:35:16 PM PDT 24
Peak memory 243304 kb
Host smart-7d33c0b6-a29e-49d8-9396-01b55bb3e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148033503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.3148033503
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3487654333
Short name T1002
Test name
Test status
Simulation time 837331599 ps
CPU time 12.65 seconds
Started Jul 21 06:34:45 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 241264 kb
Host smart-aebc8f7a-468b-40ea-93b7-cc3a6b36e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487654333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3487654333
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.3289405677
Short name T1060
Test name
Test status
Simulation time 180569562 ps
CPU time 4.03 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241180 kb
Host smart-199d8530-3842-4134-a7ff-14837472b228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289405677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3289405677
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3528836072
Short name T1141
Test name
Test status
Simulation time 1368022978 ps
CPU time 24.03 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 244056 kb
Host smart-4793552a-055d-4d72-a9e4-80fd8d0f1ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528836072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3528836072
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.4079840272
Short name T928
Test name
Test status
Simulation time 133938258 ps
CPU time 6.28 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241620 kb
Host smart-1ec2dbae-f404-497a-b664-d8f8fb84cb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079840272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.4079840272
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.756097396
Short name T935
Test name
Test status
Simulation time 677859152 ps
CPU time 11.04 seconds
Started Jul 21 06:34:44 PM PDT 24
Finished Jul 21 06:34:57 PM PDT 24
Peak memory 241264 kb
Host smart-58b8e9a1-9d58-4186-a212-e745e065ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756097396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.756097396
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.713143873
Short name T436
Test name
Test status
Simulation time 2423742652 ps
CPU time 22.63 seconds
Started Jul 21 06:34:44 PM PDT 24
Finished Jul 21 06:35:09 PM PDT 24
Peak memory 241260 kb
Host smart-087fbb0f-1c5b-4909-a32c-f52b6404dddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713143873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.713143873
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2184899269
Short name T853
Test name
Test status
Simulation time 296143634 ps
CPU time 7.48 seconds
Started Jul 21 06:34:48 PM PDT 24
Finished Jul 21 06:34:58 PM PDT 24
Peak memory 241524 kb
Host smart-565c6d72-0f79-4895-88e4-7ba9e9693911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184899269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2184899269
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.1538170817
Short name T486
Test name
Test status
Simulation time 621746978 ps
CPU time 4.46 seconds
Started Jul 21 06:34:35 PM PDT 24
Finished Jul 21 06:34:41 PM PDT 24
Peak memory 247364 kb
Host smart-c1513aec-1c4b-4364-b5b7-62ab7c581754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538170817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1538170817
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.516366014
Short name T520
Test name
Test status
Simulation time 1041463401 ps
CPU time 18.12 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:09 PM PDT 24
Peak memory 241308 kb
Host smart-26000325-96f3-4f00-aa65-eac6abe3e7a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516366014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.
516366014
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.487335590
Short name T1137
Test name
Test status
Simulation time 1702744091 ps
CPU time 12.91 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:34:58 PM PDT 24
Peak memory 241552 kb
Host smart-001d2b53-1366-4892-843d-b95783cc0520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487335590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.487335590
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.4260692337
Short name T635
Test name
Test status
Simulation time 1997828764 ps
CPU time 6.23 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 241432 kb
Host smart-7eaa1caa-44ee-4861-96bd-87f668873ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260692337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.4260692337
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.2465206123
Short name T814
Test name
Test status
Simulation time 2179041254 ps
CPU time 4.3 seconds
Started Jul 21 06:36:56 PM PDT 24
Finished Jul 21 06:37:01 PM PDT 24
Peak memory 241256 kb
Host smart-e8e65af2-7da1-4134-b8ff-25ff86d50042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465206123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2465206123
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.681010942
Short name T212
Test name
Test status
Simulation time 142621060 ps
CPU time 3.95 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:03 PM PDT 24
Peak memory 241616 kb
Host smart-b1853e81-b50e-4493-ba8c-9f2507bfcb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681010942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.681010942
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.1945080905
Short name T1092
Test name
Test status
Simulation time 902276689 ps
CPU time 13.61 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241532 kb
Host smart-96f03020-3ec2-4daf-8bfd-ceed6ce33dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945080905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1945080905
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.625367168
Short name T174
Test name
Test status
Simulation time 153104466 ps
CPU time 4.29 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:03 PM PDT 24
Peak memory 241120 kb
Host smart-a202e370-7d42-4a10-9160-94ba3ee96c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625367168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.625367168
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2207764892
Short name T652
Test name
Test status
Simulation time 163023850 ps
CPU time 4.05 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:03 PM PDT 24
Peak memory 241120 kb
Host smart-6aa35c89-77c8-4410-856d-c872d3835917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207764892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2207764892
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.50662865
Short name T701
Test name
Test status
Simulation time 240773509 ps
CPU time 3.67 seconds
Started Jul 21 06:37:00 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 241256 kb
Host smart-8c1b8bf5-252b-435a-befc-74a3f769cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50662865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.50662865
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.172047114
Short name T96
Test name
Test status
Simulation time 1268892650 ps
CPU time 21.55 seconds
Started Jul 21 06:36:57 PM PDT 24
Finished Jul 21 06:37:20 PM PDT 24
Peak memory 241472 kb
Host smart-b0280b1c-1760-4e26-a8e9-9b1329fd804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172047114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.172047114
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.1394339364
Short name T905
Test name
Test status
Simulation time 2295406233 ps
CPU time 6.95 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:07 PM PDT 24
Peak memory 241548 kb
Host smart-62d012cc-9c1a-41bc-ac07-4dbaa3de379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394339364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1394339364
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.3483142342
Short name T253
Test name
Test status
Simulation time 192582582 ps
CPU time 2.89 seconds
Started Jul 21 06:36:56 PM PDT 24
Finished Jul 21 06:37:00 PM PDT 24
Peak memory 241208 kb
Host smart-a14b99bc-5cb6-4a6e-8433-be76661cfe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483142342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3483142342
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.4180806930
Short name T668
Test name
Test status
Simulation time 348146358 ps
CPU time 3.72 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:03 PM PDT 24
Peak memory 241712 kb
Host smart-da12c150-70a1-4f3d-9fbf-9e15fdcb80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180806930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.4180806930
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2014138065
Short name T268
Test name
Test status
Simulation time 287100996 ps
CPU time 7.04 seconds
Started Jul 21 06:36:58 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241020 kb
Host smart-9f72d794-5079-4953-9eba-bd378a95a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014138065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2014138065
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.516049383
Short name T799
Test name
Test status
Simulation time 2117671936 ps
CPU time 6.09 seconds
Started Jul 21 06:37:07 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241444 kb
Host smart-0c4bddaa-b1bd-44f9-af06-3dff4dbe54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516049383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.516049383
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.3590357447
Short name T949
Test name
Test status
Simulation time 1716110237 ps
CPU time 6.93 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:11 PM PDT 24
Peak memory 241244 kb
Host smart-038ba76f-c227-4958-8afa-b7f5f154377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590357447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3590357447
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2054543521
Short name T755
Test name
Test status
Simulation time 5055889817 ps
CPU time 26.62 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241204 kb
Host smart-47d2b0a8-c31e-434d-8be5-64d65aad7d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054543521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2054543521
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.915020416
Short name T884
Test name
Test status
Simulation time 331388218 ps
CPU time 4.52 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241280 kb
Host smart-1d0cfadc-379d-4764-815f-b10d73a05958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915020416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.915020416
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.162098039
Short name T952
Test name
Test status
Simulation time 157403112 ps
CPU time 4.22 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 241540 kb
Host smart-24d70380-d057-4ca4-886e-6f8347fe6bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162098039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.162098039
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.3682905798
Short name T862
Test name
Test status
Simulation time 142597022 ps
CPU time 4.03 seconds
Started Jul 21 06:37:05 PM PDT 24
Finished Jul 21 06:37:10 PM PDT 24
Peak memory 241216 kb
Host smart-f70b29de-60b5-409a-a55b-818fd4e668ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682905798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3682905798
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.2023023893
Short name T251
Test name
Test status
Simulation time 917878228 ps
CPU time 12.28 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241264 kb
Host smart-35e75eec-af82-463f-bf32-488ee25d62e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023023893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2023023893
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1589789292
Short name T718
Test name
Test status
Simulation time 16822103118 ps
CPU time 90.99 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:36:13 PM PDT 24
Peak memory 242904 kb
Host smart-0dcb1fbe-b704-4f89-9d20-d8f0325fb633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589789292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1589789292
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.2364921657
Short name T10
Test name
Test status
Simulation time 733114813 ps
CPU time 21.93 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 241280 kb
Host smart-31bef29b-d971-47ac-bae5-36deeb1cca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364921657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2364921657
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2138013409
Short name T462
Test name
Test status
Simulation time 200795708 ps
CPU time 5.8 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 241232 kb
Host smart-9676e4cf-576a-4e0b-a92d-6d2e9e2efce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138013409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2138013409
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.4031503124
Short name T789
Test name
Test status
Simulation time 154987591 ps
CPU time 4.01 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241460 kb
Host smart-cd53569f-f51f-4efa-840f-48d7f6413f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031503124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.4031503124
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.1932530691
Short name T767
Test name
Test status
Simulation time 2908328819 ps
CPU time 32.48 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:35:16 PM PDT 24
Peak memory 256296 kb
Host smart-f29bdeac-82f1-499f-9d2d-ffcc61a35b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932530691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1932530691
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4010847713
Short name T934
Test name
Test status
Simulation time 407439898 ps
CPU time 5.12 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:34:55 PM PDT 24
Peak memory 241548 kb
Host smart-fc1d8686-4d84-4a6a-a989-8d5859bfc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010847713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4010847713
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3484903431
Short name T380
Test name
Test status
Simulation time 2317637454 ps
CPU time 5.52 seconds
Started Jul 21 06:34:44 PM PDT 24
Finished Jul 21 06:34:52 PM PDT 24
Peak memory 241312 kb
Host smart-c8e4d0d6-5253-4d29-8ed9-83da69f8b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484903431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3484903431
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3316467950
Short name T791
Test name
Test status
Simulation time 1239100798 ps
CPU time 9.02 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:34:52 PM PDT 24
Peak memory 241604 kb
Host smart-6de30440-b9b7-4a05-b9ea-bd842dd31d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316467950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3316467950
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.70114899
Short name T289
Test name
Test status
Simulation time 699745552 ps
CPU time 5.56 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241312 kb
Host smart-57eec376-a7a9-4296-b817-e72db335768d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70114899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.70114899
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2009951184
Short name T583
Test name
Test status
Simulation time 342596349 ps
CPU time 5.02 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:34:55 PM PDT 24
Peak memory 241288 kb
Host smart-91b3897a-fd1f-4856-93e2-44e5ca094ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009951184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2009951184
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.2909379152
Short name T1073
Test name
Test status
Simulation time 6998052086 ps
CPU time 231.15 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 260872 kb
Host smart-6e2c4af6-07e5-4892-8611-cc207bdb88fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909379152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.2909379152
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.1626719861
Short name T281
Test name
Test status
Simulation time 517906567 ps
CPU time 16.49 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:10 PM PDT 24
Peak memory 241388 kb
Host smart-b3f63098-c7cb-4a74-be26-d218dd84f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626719861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.1626719861
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.4187660123
Short name T1176
Test name
Test status
Simulation time 250832568 ps
CPU time 3.19 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241240 kb
Host smart-abe9f20a-0eec-4c8a-ba6e-182703188eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187660123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4187660123
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.1422591438
Short name T766
Test name
Test status
Simulation time 152615624 ps
CPU time 6.08 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241084 kb
Host smart-002542d5-0b9e-48d5-8ba8-8bd8b3310589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422591438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1422591438
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.1458873088
Short name T675
Test name
Test status
Simulation time 1521330635 ps
CPU time 13.49 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241072 kb
Host smart-13688534-c77e-4868-9e2c-467a296e09a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458873088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1458873088
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.247282249
Short name T222
Test name
Test status
Simulation time 220520959 ps
CPU time 4.7 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241264 kb
Host smart-ae0d8fde-749e-4b66-ad19-06a750f61119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247282249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.247282249
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.77278436
Short name T748
Test name
Test status
Simulation time 316792452 ps
CPU time 8.18 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:11 PM PDT 24
Peak memory 241304 kb
Host smart-574beb83-bde3-4626-bcf5-a873faca2928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77278436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.77278436
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3365445456
Short name T945
Test name
Test status
Simulation time 151329977 ps
CPU time 4.5 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241816 kb
Host smart-0792f4b9-75db-4020-8fbd-47b2dc8b50cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365445456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3365445456
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2898640107
Short name T231
Test name
Test status
Simulation time 1121101650 ps
CPU time 19.56 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241584 kb
Host smart-f2ebd5c9-4598-4170-a425-2291b4a3353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898640107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2898640107
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.3233928976
Short name T5
Test name
Test status
Simulation time 137960619 ps
CPU time 3.69 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:07 PM PDT 24
Peak memory 241380 kb
Host smart-eb8d5aa7-e041-4045-89bb-17847787e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233928976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3233928976
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.2436883839
Short name T811
Test name
Test status
Simulation time 1693649936 ps
CPU time 26.55 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241724 kb
Host smart-6efe9ff5-e8f3-4a79-8c1a-e697f22706b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436883839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2436883839
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2686851840
Short name T564
Test name
Test status
Simulation time 574686155 ps
CPU time 4.96 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241524 kb
Host smart-41f7886d-f8f3-4a1f-9dec-09eeaad04958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686851840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2686851840
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2042104192
Short name T105
Test name
Test status
Simulation time 290618756 ps
CPU time 3.5 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241692 kb
Host smart-ddbabc9a-529d-42c8-9701-d75e6dfc67e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042104192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2042104192
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3652685401
Short name T609
Test name
Test status
Simulation time 336050770 ps
CPU time 3.88 seconds
Started Jul 21 06:37:01 PM PDT 24
Finished Jul 21 06:37:05 PM PDT 24
Peak memory 241720 kb
Host smart-2b60b8e1-d91a-48da-9b47-a553a859802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652685401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3652685401
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.3497268754
Short name T886
Test name
Test status
Simulation time 438745165 ps
CPU time 4.98 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 241252 kb
Host smart-5d4152c8-d95d-451a-9ca7-455126b122b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497268754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3497268754
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1773477316
Short name T703
Test name
Test status
Simulation time 253321520 ps
CPU time 5.12 seconds
Started Jul 21 06:37:07 PM PDT 24
Finished Jul 21 06:37:13 PM PDT 24
Peak memory 241708 kb
Host smart-8ea22918-b624-4d69-b349-cbe40169387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773477316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1773477316
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2701951490
Short name T483
Test name
Test status
Simulation time 1352411922 ps
CPU time 4.52 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:08 PM PDT 24
Peak memory 241368 kb
Host smart-3c68f22e-9f62-47f6-8cb6-391d07b6ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701951490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2701951490
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.245988558
Short name T1087
Test name
Test status
Simulation time 695607921 ps
CPU time 5.74 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241196 kb
Host smart-ee69f02b-94aa-421c-81af-21f84196fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245988558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.245988558
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3186576020
Short name T575
Test name
Test status
Simulation time 331213144 ps
CPU time 3.75 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241736 kb
Host smart-f9e6dec7-b3bc-4c72-b6ce-1be3c5a9fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186576020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3186576020
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3778251975
Short name T1100
Test name
Test status
Simulation time 188040128 ps
CPU time 4.73 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241644 kb
Host smart-15975b67-1cdc-435c-a1d9-5320766f4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778251975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3778251975
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.43219100
Short name T443
Test name
Test status
Simulation time 145635265 ps
CPU time 1.82 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 239648 kb
Host smart-bafa6474-0f9d-4e56-8067-c2f0b92be7de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43219100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.43219100
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.2968231963
Short name T62
Test name
Test status
Simulation time 1522284319 ps
CPU time 18.19 seconds
Started Jul 21 06:34:46 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 242476 kb
Host smart-c1a60d1a-ca45-4760-a9d5-4d36d2bf7a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968231963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2968231963
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.256938099
Short name T521
Test name
Test status
Simulation time 1548953355 ps
CPU time 27.56 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 242556 kb
Host smart-d5616b2c-ac61-4712-be4f-27a260d2fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256938099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.256938099
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.782962769
Short name T1075
Test name
Test status
Simulation time 3743901067 ps
CPU time 9.01 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:34:54 PM PDT 24
Peak memory 241324 kb
Host smart-545c1793-ba17-443c-bc0d-c73ff3e52547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782962769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.782962769
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3668178557
Short name T66
Test name
Test status
Simulation time 2954947162 ps
CPU time 4.96 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:49 PM PDT 24
Peak memory 241512 kb
Host smart-0ec4833c-9b4e-498a-9b6c-3c3475266da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668178557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3668178557
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.472045405
Short name T161
Test name
Test status
Simulation time 1109907580 ps
CPU time 18.43 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:08 PM PDT 24
Peak memory 243148 kb
Host smart-f2cf53f8-289d-48aa-b679-0890ee401e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472045405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.472045405
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.1922510839
Short name T699
Test name
Test status
Simulation time 574677734 ps
CPU time 14.25 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:58 PM PDT 24
Peak memory 248020 kb
Host smart-061a006d-c40e-4399-8ebc-b19382bd0769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922510839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1922510839
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3862262507
Short name T111
Test name
Test status
Simulation time 697708875 ps
CPU time 6.5 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:52 PM PDT 24
Peak memory 241544 kb
Host smart-84340ee3-9c9a-4851-bcc6-1c935347efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862262507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3862262507
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.912683154
Short name T375
Test name
Test status
Simulation time 1944660557 ps
CPU time 24.37 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 247956 kb
Host smart-afa128d8-5b20-41fe-9413-7de90b4c1b78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912683154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.912683154
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1233282683
Short name T669
Test name
Test status
Simulation time 130489745 ps
CPU time 4.54 seconds
Started Jul 21 06:34:51 PM PDT 24
Finished Jul 21 06:34:57 PM PDT 24
Peak memory 241232 kb
Host smart-f4af95c9-fddc-4704-9a3e-491df75377c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233282683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1233282683
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3943691062
Short name T930
Test name
Test status
Simulation time 423665586 ps
CPU time 7.47 seconds
Started Jul 21 06:34:46 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 241760 kb
Host smart-68e38b41-f9d7-41b8-8efb-191c5890ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943691062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3943691062
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.202652755
Short name T646
Test name
Test status
Simulation time 14901877579 ps
CPU time 21.81 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 242152 kb
Host smart-ebf26070-f623-47c2-a26c-652dbf54b05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202652755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.
202652755
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2227496124
Short name T958
Test name
Test status
Simulation time 1264053655 ps
CPU time 8.51 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:34:54 PM PDT 24
Peak memory 241584 kb
Host smart-75825b8f-b83f-4b7f-97bb-6586f2d3469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227496124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2227496124
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.600674375
Short name T435
Test name
Test status
Simulation time 216821226 ps
CPU time 3.1 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241572 kb
Host smart-9b833602-80fa-47ec-b160-2873c63c9b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600674375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.600674375
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3524975561
Short name T559
Test name
Test status
Simulation time 716160349 ps
CPU time 5.27 seconds
Started Jul 21 06:37:05 PM PDT 24
Finished Jul 21 06:37:11 PM PDT 24
Peak memory 241508 kb
Host smart-90943094-740a-4ad3-8bba-eb1870bba953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524975561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3524975561
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2509865675
Short name T205
Test name
Test status
Simulation time 142251631 ps
CPU time 3.57 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241696 kb
Host smart-e59064ba-af73-4ab1-9eaa-786acff3d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509865675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2509865675
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3983078881
Short name T69
Test name
Test status
Simulation time 1123133636 ps
CPU time 15.79 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241072 kb
Host smart-277a76ea-624c-4e33-ad09-5e6ba23e6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983078881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3983078881
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.3022314565
Short name T1011
Test name
Test status
Simulation time 225589052 ps
CPU time 3.19 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:08 PM PDT 24
Peak memory 241300 kb
Host smart-45baed30-1dd0-4404-b600-95f95a3b2dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022314565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3022314565
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.4170012483
Short name T655
Test name
Test status
Simulation time 453472805 ps
CPU time 9.39 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241492 kb
Host smart-c6722df6-867f-4c0a-9051-690381624144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170012483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.4170012483
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.1427776108
Short name T901
Test name
Test status
Simulation time 365408247 ps
CPU time 3.14 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:10 PM PDT 24
Peak memory 241704 kb
Host smart-a019ebc6-43e1-4c8c-89d6-d1a7f2989b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427776108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1427776108
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.1521503095
Short name T503
Test name
Test status
Simulation time 1644131923 ps
CPU time 17.48 seconds
Started Jul 21 06:37:05 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241800 kb
Host smart-0b604569-ef55-4d33-acac-9af5b8838a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521503095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1521503095
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2050294217
Short name T417
Test name
Test status
Simulation time 318853909 ps
CPU time 4.37 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241360 kb
Host smart-a836d8b1-3360-4d04-ba69-24b5b0ba038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050294217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2050294217
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2529890504
Short name T592
Test name
Test status
Simulation time 213074682 ps
CPU time 3.29 seconds
Started Jul 21 06:37:07 PM PDT 24
Finished Jul 21 06:37:11 PM PDT 24
Peak memory 241056 kb
Host smart-fa0362cd-f752-4385-a2c6-a34d25fa502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529890504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2529890504
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.16621186
Short name T94
Test name
Test status
Simulation time 331874773 ps
CPU time 8.51 seconds
Started Jul 21 06:37:03 PM PDT 24
Finished Jul 21 06:37:12 PM PDT 24
Peak memory 241068 kb
Host smart-dc6f7b54-6bde-4ed5-ab51-450a39eb8542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16621186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.16621186
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.4077878708
Short name T628
Test name
Test status
Simulation time 104018755 ps
CPU time 3.72 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:06 PM PDT 24
Peak memory 241368 kb
Host smart-7cdab2ed-eb50-4b81-98ca-591ead7288d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077878708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4077878708
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.618842920
Short name T238
Test name
Test status
Simulation time 625404175 ps
CPU time 6.81 seconds
Started Jul 21 06:37:07 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241532 kb
Host smart-dbc9bbd6-13e9-4e26-a860-a278d316bdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618842920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.618842920
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.4118727829
Short name T405
Test name
Test status
Simulation time 198898104 ps
CPU time 4.35 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:10 PM PDT 24
Peak memory 241124 kb
Host smart-ad60bfbd-5ad2-4d03-b843-2b599553efd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118727829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4118727829
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3284659286
Short name T780
Test name
Test status
Simulation time 1168817736 ps
CPU time 26.43 seconds
Started Jul 21 06:37:04 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241260 kb
Host smart-850fdd30-86bf-49af-adcc-a8b05b80cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284659286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3284659286
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3106109655
Short name T1038
Test name
Test status
Simulation time 162260998 ps
CPU time 4.4 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241236 kb
Host smart-f94ec0fc-0635-458c-97a5-5d94cd496297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106109655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3106109655
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3678408837
Short name T154
Test name
Test status
Simulation time 319910185 ps
CPU time 3.68 seconds
Started Jul 21 06:37:07 PM PDT 24
Finished Jul 21 06:37:11 PM PDT 24
Peak memory 241664 kb
Host smart-c6eedb58-8ea4-4b0a-98d5-fb068b41b60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678408837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3678408837
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2690406367
Short name T252
Test name
Test status
Simulation time 267965706 ps
CPU time 6.29 seconds
Started Jul 21 06:37:02 PM PDT 24
Finished Jul 21 06:37:09 PM PDT 24
Peak memory 241256 kb
Host smart-e63e7793-d96f-4480-9b6f-3d9c670dd01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690406367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2690406367
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1252814631
Short name T731
Test name
Test status
Simulation time 837940292 ps
CPU time 2.08 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 240104 kb
Host smart-a9dc70bf-6b82-475a-839f-d41de73e513e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252814631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1252814631
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1089878818
Short name T11
Test name
Test status
Simulation time 237359728 ps
CPU time 5.08 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241504 kb
Host smart-f4c0c480-813d-4777-9179-9dba648a2b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089878818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1089878818
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.696222003
Short name T1043
Test name
Test status
Simulation time 5168052474 ps
CPU time 29.47 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 241672 kb
Host smart-b9c2686b-f5ff-408d-b29b-165156857a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696222003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.696222003
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2335207609
Short name T871
Test name
Test status
Simulation time 3119245352 ps
CPU time 28.96 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 241528 kb
Host smart-f382ec8f-486e-45f1-890c-5a4ae2371640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335207609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2335207609
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1978374140
Short name T173
Test name
Test status
Simulation time 164116633 ps
CPU time 4.06 seconds
Started Jul 21 06:34:42 PM PDT 24
Finished Jul 21 06:34:48 PM PDT 24
Peak memory 241236 kb
Host smart-44096b9b-1066-42be-8e50-fde7641e7dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978374140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1978374140
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.3571779695
Short name T944
Test name
Test status
Simulation time 617623169 ps
CPU time 11 seconds
Started Jul 21 06:34:46 PM PDT 24
Finished Jul 21 06:34:59 PM PDT 24
Peak memory 241768 kb
Host smart-521a8d55-ac9b-47b7-9e8c-137cd5a7744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571779695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3571779695
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.3263151121
Short name T413
Test name
Test status
Simulation time 832181736 ps
CPU time 9.9 seconds
Started Jul 21 06:34:46 PM PDT 24
Finished Jul 21 06:34:59 PM PDT 24
Peak memory 241608 kb
Host smart-29c3b9dd-6bf8-4f5c-95c1-e6bcd9405211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263151121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3263151121
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2097432272
Short name T968
Test name
Test status
Simulation time 1040904417 ps
CPU time 7.6 seconds
Started Jul 21 06:34:51 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 241196 kb
Host smart-d91a9ff7-e26c-4aed-b1ef-e6d165392892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097432272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2097432272
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.1565134058
Short name T88
Test name
Test status
Simulation time 2631955234 ps
CPU time 16.73 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:06 PM PDT 24
Peak memory 241332 kb
Host smart-47cbed8e-6443-4662-a9f3-93477078cb53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565134058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1565134058
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.3181088863
Short name T361
Test name
Test status
Simulation time 142072709 ps
CPU time 3.56 seconds
Started Jul 21 06:34:43 PM PDT 24
Finished Jul 21 06:34:49 PM PDT 24
Peak memory 241288 kb
Host smart-7607bb4a-275e-48e1-a7a1-e8ac7d845412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181088863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3181088863
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3594081943
Short name T426
Test name
Test status
Simulation time 454334008 ps
CPU time 6.15 seconds
Started Jul 21 06:34:41 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241616 kb
Host smart-5fc3700e-1bb3-47b0-8240-c9b3e7074399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594081943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3594081943
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.621720691
Short name T285
Test name
Test status
Simulation time 201279433387 ps
CPU time 2066.8 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 07:09:09 PM PDT 24
Peak memory 575292 kb
Host smart-c3e750d5-d2f8-4fcf-b46c-d4113371a798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621720691 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.621720691
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.701820420
Short name T803
Test name
Test status
Simulation time 3156788798 ps
CPU time 39.98 seconds
Started Jul 21 06:34:44 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241928 kb
Host smart-b54f7e62-b259-4087-a440-99685138a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701820420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.701820420
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3315443091
Short name T1180
Test name
Test status
Simulation time 1855862231 ps
CPU time 5.91 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241476 kb
Host smart-19f9e802-579c-4a64-a42f-8b1552f65a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315443091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3315443091
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2989368242
Short name T114
Test name
Test status
Simulation time 786792171 ps
CPU time 6.95 seconds
Started Jul 21 06:37:07 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 241200 kb
Host smart-e48c2059-3222-4ea4-a200-ef20889490ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989368242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2989368242
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.2590612638
Short name T649
Test name
Test status
Simulation time 363357788 ps
CPU time 3.99 seconds
Started Jul 21 06:37:06 PM PDT 24
Finished Jul 21 06:37:11 PM PDT 24
Peak memory 241568 kb
Host smart-82dd3139-5fb5-4030-8a00-d23fa99a38a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590612638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2590612638
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1313606861
Short name T185
Test name
Test status
Simulation time 100721959 ps
CPU time 3.62 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:13 PM PDT 24
Peak memory 241180 kb
Host smart-a01e2da1-5e8c-4d12-94a2-b05d2d254ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313606861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1313606861
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3458171157
Short name T223
Test name
Test status
Simulation time 96061183 ps
CPU time 3.22 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241504 kb
Host smart-3f3f2a0a-d9da-4f79-b95c-e40710f54234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458171157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3458171157
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.875995616
Short name T674
Test name
Test status
Simulation time 460201160 ps
CPU time 3.47 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 241212 kb
Host smart-f89ef116-780a-41e7-97c5-d4f91486719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875995616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.875995616
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.329704826
Short name T600
Test name
Test status
Simulation time 105442221 ps
CPU time 3.43 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241368 kb
Host smart-351e47d7-abe6-414e-a5d3-0ae5bd0dbc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329704826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.329704826
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1223826934
Short name T801
Test name
Test status
Simulation time 285827415 ps
CPU time 7.57 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:18 PM PDT 24
Peak memory 241664 kb
Host smart-77624bd0-cb4e-4105-84a3-79c12089ca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223826934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1223826934
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1060708184
Short name T832
Test name
Test status
Simulation time 132087838 ps
CPU time 3.66 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241232 kb
Host smart-9d3d0186-031f-425c-8241-4fabf9ff2bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060708184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1060708184
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1446876062
Short name T267
Test name
Test status
Simulation time 1894154211 ps
CPU time 7.51 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:19 PM PDT 24
Peak memory 241672 kb
Host smart-fb87a085-f592-4572-8ce8-a192b7c398eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446876062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1446876062
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.659671915
Short name T514
Test name
Test status
Simulation time 329728115 ps
CPU time 3.07 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 241348 kb
Host smart-22e1a6e7-294b-4876-af07-4440c79888de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659671915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.659671915
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.1328375611
Short name T1047
Test name
Test status
Simulation time 1890300695 ps
CPU time 14.57 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:27 PM PDT 24
Peak memory 241320 kb
Host smart-051882dc-fef5-4404-98f6-1c0bb6c91a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328375611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1328375611
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.2849277216
Short name T444
Test name
Test status
Simulation time 177061751 ps
CPU time 4.42 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 241524 kb
Host smart-5b00d38a-6bef-4904-8601-53b8d014211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849277216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2849277216
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3844667644
Short name T193
Test name
Test status
Simulation time 926381791 ps
CPU time 14.08 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 241200 kb
Host smart-f18a3773-062a-43ba-9cde-682529ea64b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844667644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3844667644
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1887185893
Short name T1022
Test name
Test status
Simulation time 286624329 ps
CPU time 5.89 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:18 PM PDT 24
Peak memory 241500 kb
Host smart-a7d02b16-ebd1-4763-9405-869e6fb146bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887185893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1887185893
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.280508817
Short name T831
Test name
Test status
Simulation time 1187217389 ps
CPU time 16.58 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 241676 kb
Host smart-3f46abe0-6ef4-46f8-89ff-5fb647e71221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280508817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.280508817
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.532900035
Short name T724
Test name
Test status
Simulation time 565319373 ps
CPU time 5.85 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241476 kb
Host smart-ad7aad8c-4b4e-45a5-97c2-93638e213d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532900035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.532900035
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.1979530729
Short name T546
Test name
Test status
Simulation time 954800347 ps
CPU time 8.06 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241272 kb
Host smart-cb255d8c-3a28-4f39-887f-9cc3911ed786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979530729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1979530729
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2024952520
Short name T172
Test name
Test status
Simulation time 139987347 ps
CPU time 3.35 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:14 PM PDT 24
Peak memory 241368 kb
Host smart-bd88c894-ec9c-4117-bf25-028046e6f4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024952520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2024952520
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.3026318644
Short name T591
Test name
Test status
Simulation time 2656279784 ps
CPU time 22.92 seconds
Started Jul 21 06:37:13 PM PDT 24
Finished Jul 21 06:37:36 PM PDT 24
Peak memory 241328 kb
Host smart-eff7be3c-27da-4a75-a5fd-6104a91954bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026318644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3026318644
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3087794633
Short name T440
Test name
Test status
Simulation time 700224112 ps
CPU time 2.61 seconds
Started Jul 21 06:34:49 PM PDT 24
Finished Jul 21 06:34:55 PM PDT 24
Peak memory 239516 kb
Host smart-48f822ac-7b7b-4b83-9c49-d4c887c6beb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087794633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3087794633
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.1671034838
Short name T1010
Test name
Test status
Simulation time 892092928 ps
CPU time 17.78 seconds
Started Jul 21 06:34:50 PM PDT 24
Finished Jul 21 06:35:10 PM PDT 24
Peak memory 241356 kb
Host smart-65dadd6c-83dd-42f8-88ec-e59e8c180aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671034838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1671034838
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.1897840913
Short name T539
Test name
Test status
Simulation time 8737579281 ps
CPU time 20.04 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:10 PM PDT 24
Peak memory 248084 kb
Host smart-658abb28-7a24-4372-a627-1f9ce3f82d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897840913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1897840913
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.3497755351
Short name T145
Test name
Test status
Simulation time 375069128 ps
CPU time 4.26 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:34:54 PM PDT 24
Peak memory 241724 kb
Host smart-98e011e7-7abc-4ca1-b3bb-fbf7a8950ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497755351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3497755351
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3539255744
Short name T642
Test name
Test status
Simulation time 778793901 ps
CPU time 23.47 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 241260 kb
Host smart-67c5c08d-d89e-4c75-8c20-44941fd32433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539255744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3539255744
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.863142804
Short name T1165
Test name
Test status
Simulation time 904469700 ps
CPU time 19.83 seconds
Started Jul 21 06:34:45 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 241980 kb
Host smart-6c80028e-bd36-4359-97e9-e54ce0fb5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863142804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.863142804
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2657328912
Short name T1120
Test name
Test status
Simulation time 247381221 ps
CPU time 13.92 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 241092 kb
Host smart-b7d2a24d-8e21-4eb4-98cf-a91b54271f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657328912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2657328912
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2383383505
Short name T762
Test name
Test status
Simulation time 10241537725 ps
CPU time 35.91 seconds
Started Jul 21 06:34:46 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 241244 kb
Host smart-135c70f0-c0c0-4baf-86f4-5f4b41961895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383383505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2383383505
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.2284435702
Short name T364
Test name
Test status
Simulation time 531275425 ps
CPU time 4.19 seconds
Started Jul 21 06:34:47 PM PDT 24
Finished Jul 21 06:34:54 PM PDT 24
Peak memory 241328 kb
Host smart-37c2cf8a-9d14-4365-b684-a302acfc621c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284435702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2284435702
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.4240313032
Short name T810
Test name
Test status
Simulation time 1174033858 ps
CPU time 8.75 seconds
Started Jul 21 06:34:40 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 241376 kb
Host smart-ff547508-3ed5-47d8-a0f7-b68d332730d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240313032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.4240313032
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.1277955325
Short name T332
Test name
Test status
Simulation time 93199109074 ps
CPU time 266.52 seconds
Started Jul 21 06:34:48 PM PDT 24
Finished Jul 21 06:39:17 PM PDT 24
Peak memory 256628 kb
Host smart-d7a5cfeb-5fd6-4b38-8c7a-f9496a0fd1f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277955325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.1277955325
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1744411369
Short name T9
Test name
Test status
Simulation time 110543582277 ps
CPU time 1173.21 seconds
Started Jul 21 06:34:49 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 264536 kb
Host smart-9c155cdf-01e3-449f-b1c6-d8b423a98f02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744411369 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1744411369
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1700147862
Short name T545
Test name
Test status
Simulation time 1590129678 ps
CPU time 19.46 seconds
Started Jul 21 06:34:48 PM PDT 24
Finished Jul 21 06:35:10 PM PDT 24
Peak memory 241868 kb
Host smart-b1878d5e-c970-4102-979f-9e861dfff5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700147862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1700147862
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.2014891075
Short name T473
Test name
Test status
Simulation time 1645162090 ps
CPU time 5.96 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:18 PM PDT 24
Peak memory 241204 kb
Host smart-838dc9b7-8b9c-4a35-86dc-aa1256076ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014891075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2014891075
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3018245771
Short name T1035
Test name
Test status
Simulation time 1781067369 ps
CPU time 28.22 seconds
Started Jul 21 06:37:13 PM PDT 24
Finished Jul 21 06:37:42 PM PDT 24
Peak memory 241128 kb
Host smart-94180bbd-b3e0-441a-a431-e7058b72816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018245771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3018245771
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1874759874
Short name T491
Test name
Test status
Simulation time 2011673386 ps
CPU time 5.33 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:18 PM PDT 24
Peak memory 241400 kb
Host smart-2f30e3d3-420f-435c-ba2a-bef90d0731dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874759874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1874759874
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.1231784959
Short name T1065
Test name
Test status
Simulation time 167975209 ps
CPU time 5.03 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 241184 kb
Host smart-8683fed0-5f92-4241-8b5e-9f77b7297807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231784959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1231784959
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2429287386
Short name T1025
Test name
Test status
Simulation time 150896547 ps
CPU time 3.63 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:13 PM PDT 24
Peak memory 241708 kb
Host smart-7fdd7430-b249-472d-9211-7ce87f0203a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429287386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2429287386
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.98989225
Short name T1054
Test name
Test status
Simulation time 280712590 ps
CPU time 2.95 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 241436 kb
Host smart-621f3cc8-1a08-4a3f-8363-3b63e67f647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98989225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.98989225
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.2097683841
Short name T615
Test name
Test status
Simulation time 2383256986 ps
CPU time 5.56 seconds
Started Jul 21 06:37:08 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 241328 kb
Host smart-797085ec-ff72-4afc-81ef-0bde8faf2a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097683841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2097683841
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.2234085766
Short name T485
Test name
Test status
Simulation time 682043356 ps
CPU time 5.91 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 241068 kb
Host smart-dcada51b-c598-4c55-be93-405642a3b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234085766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2234085766
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2563922633
Short name T658
Test name
Test status
Simulation time 371538845 ps
CPU time 4.17 seconds
Started Jul 21 06:37:09 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 241368 kb
Host smart-0c73d237-cec6-4175-92a6-c97947bcb036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563922633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2563922633
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.705601950
Short name T542
Test name
Test status
Simulation time 327997664 ps
CPU time 9.25 seconds
Started Jul 21 06:37:10 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241692 kb
Host smart-6ed15035-6e11-4904-9453-66dde330e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705601950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.705601950
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.2979202212
Short name T602
Test name
Test status
Simulation time 2297552351 ps
CPU time 4.23 seconds
Started Jul 21 06:37:12 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241852 kb
Host smart-9e790c8a-8de6-4bce-a4a8-76a27d93d0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979202212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2979202212
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.2693300812
Short name T454
Test name
Test status
Simulation time 1659865967 ps
CPU time 4.64 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:17 PM PDT 24
Peak memory 241428 kb
Host smart-f1310681-4b33-48ea-831b-043988cea0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693300812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2693300812
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.3612485034
Short name T860
Test name
Test status
Simulation time 138422853 ps
CPU time 6.12 seconds
Started Jul 21 06:37:11 PM PDT 24
Finished Jul 21 06:37:18 PM PDT 24
Peak memory 241420 kb
Host smart-52e6009b-09fb-437c-b610-48dd95068f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612485034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3612485034
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.855221756
Short name T1115
Test name
Test status
Simulation time 266138372 ps
CPU time 3.72 seconds
Started Jul 21 06:37:21 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 241380 kb
Host smart-93aa8f22-e814-48ce-b136-a03af9c1b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855221756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.855221756
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.3794265808
Short name T904
Test name
Test status
Simulation time 118903990 ps
CPU time 4.23 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241484 kb
Host smart-13210085-8e4f-4d63-81ef-b24c6c0ff06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794265808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3794265808
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.662166620
Short name T840
Test name
Test status
Simulation time 504110450 ps
CPU time 4.78 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241476 kb
Host smart-769f3c28-2ea3-47c7-a80e-f5d3a26c133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662166620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.662166620
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2080806260
Short name T445
Test name
Test status
Simulation time 1527031847 ps
CPU time 16.6 seconds
Started Jul 21 06:37:17 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241172 kb
Host smart-8ebcca4d-850e-4fd7-96ad-3ef51fb9ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080806260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2080806260
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.1843608422
Short name T480
Test name
Test status
Simulation time 2011249128 ps
CPU time 7.35 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241160 kb
Host smart-56a14439-6185-4af7-a9b6-ff50c7369446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843608422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1843608422
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1342612005
Short name T805
Test name
Test status
Simulation time 136213353 ps
CPU time 2.06 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 239624 kb
Host smart-2cb62ad4-a241-4990-a337-dc54d715019e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342612005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1342612005
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.1980800685
Short name T263
Test name
Test status
Simulation time 869938903 ps
CPU time 17.75 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241152 kb
Host smart-21a54612-5837-42fd-b05d-d8ac3af557d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980800685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1980800685
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.3771055994
Short name T659
Test name
Test status
Simulation time 1254309483 ps
CPU time 30.4 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241416 kb
Host smart-41965852-3189-4eb9-ab28-b3e647571553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771055994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3771055994
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.2215285079
Short name T1122
Test name
Test status
Simulation time 583958658 ps
CPU time 18.13 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 248012 kb
Host smart-b2122dcc-74d2-43d2-84d9-64cd760e0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215285079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2215285079
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.2735524719
Short name T981
Test name
Test status
Simulation time 348242022 ps
CPU time 3.02 seconds
Started Jul 21 06:34:04 PM PDT 24
Finished Jul 21 06:34:12 PM PDT 24
Peak memory 241196 kb
Host smart-62322509-35fd-45b8-b5f7-7f661a76fa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735524719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2735524719
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1605198853
Short name T1179
Test name
Test status
Simulation time 896421044 ps
CPU time 14.33 seconds
Started Jul 21 06:34:14 PM PDT 24
Finished Jul 21 06:34:32 PM PDT 24
Peak memory 241788 kb
Host smart-3998f2a2-ab4f-4c14-be67-0fcbbb678759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605198853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1605198853
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.483201931
Short name T653
Test name
Test status
Simulation time 2385964737 ps
CPU time 5.95 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:22 PM PDT 24
Peak memory 241312 kb
Host smart-ead6baba-e0a7-48d9-8055-3a021711a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483201931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.483201931
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2273664946
Short name T1121
Test name
Test status
Simulation time 251729084 ps
CPU time 6.77 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:16 PM PDT 24
Peak memory 241072 kb
Host smart-46e39d1c-065e-420d-9325-f00d0e52b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273664946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2273664946
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.896741537
Short name T1088
Test name
Test status
Simulation time 1012326377 ps
CPU time 22.48 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241348 kb
Host smart-1b294e45-fdc6-489a-bc26-d6430b37b130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896741537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.896741537
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.873444956
Short name T621
Test name
Test status
Simulation time 575780427 ps
CPU time 5.66 seconds
Started Jul 21 06:34:14 PM PDT 24
Finished Jul 21 06:34:23 PM PDT 24
Peak memory 241616 kb
Host smart-7e5df0ba-9565-4dc8-8d02-41fd45e9abed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873444956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.873444956
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.4192179967
Short name T634
Test name
Test status
Simulation time 1202040198 ps
CPU time 14.61 seconds
Started Jul 21 06:34:07 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241464 kb
Host smart-ebb6e7f9-a9d6-4fb5-9310-8c2314916e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192179967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.4192179967
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2684935451
Short name T820
Test name
Test status
Simulation time 93306765279 ps
CPU time 281.33 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:38:57 PM PDT 24
Peak memory 256220 kb
Host smart-bd57ff9a-8eaf-49fc-9be3-3e869b8c65d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684935451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2684935451
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.582495658
Short name T587
Test name
Test status
Simulation time 128586322204 ps
CPU time 1737.85 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 07:03:14 PM PDT 24
Peak memory 349004 kb
Host smart-f429267b-2709-4c61-8bcf-b82d250f4275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582495658 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.582495658
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2186855135
Short name T456
Test name
Test status
Simulation time 2936122603 ps
CPU time 20.33 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:34 PM PDT 24
Peak memory 241464 kb
Host smart-0f18d8db-0173-47bc-924e-64e153dfbfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186855135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2186855135
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.2764209411
Short name T1123
Test name
Test status
Simulation time 62287917 ps
CPU time 2.01 seconds
Started Jul 21 06:34:56 PM PDT 24
Finished Jul 21 06:34:59 PM PDT 24
Peak memory 239880 kb
Host smart-7ae0df1e-d6e4-485f-bce2-0949aa514e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764209411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2764209411
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.1701363667
Short name T135
Test name
Test status
Simulation time 2371609759 ps
CPU time 19.03 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:15 PM PDT 24
Peak memory 241552 kb
Host smart-124fc21a-378b-488d-aa22-920b5e5a2ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701363667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1701363667
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.3471425357
Short name T760
Test name
Test status
Simulation time 17272736139 ps
CPU time 37.9 seconds
Started Jul 21 06:34:58 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 248848 kb
Host smart-0c772aea-ec08-4e13-b52a-4825b88fcb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471425357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3471425357
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3134387522
Short name T1182
Test name
Test status
Simulation time 2995555419 ps
CPU time 8.19 seconds
Started Jul 21 06:34:52 PM PDT 24
Finished Jul 21 06:35:02 PM PDT 24
Peak memory 241556 kb
Host smart-994ea11b-56f4-4422-a1df-7d96e924f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134387522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3134387522
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2166536278
Short name T888
Test name
Test status
Simulation time 391423169 ps
CPU time 4.45 seconds
Started Jul 21 06:34:50 PM PDT 24
Finished Jul 21 06:34:57 PM PDT 24
Peak memory 241256 kb
Host smart-c783a53c-f9a3-4bff-8824-7d9a00e629fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166536278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2166536278
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.4269238967
Short name T708
Test name
Test status
Simulation time 662671479 ps
CPU time 9.54 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:05 PM PDT 24
Peak memory 241312 kb
Host smart-e513d3e7-b423-430b-b760-220eb949eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269238967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.4269238967
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.1468791163
Short name T770
Test name
Test status
Simulation time 10484682876 ps
CPU time 17.83 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:13 PM PDT 24
Peak memory 241564 kb
Host smart-fe685d5e-f9aa-4064-abe1-89bbf7f9dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468791163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1468791163
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1596346482
Short name T239
Test name
Test status
Simulation time 184984352 ps
CPU time 10.33 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:05 PM PDT 24
Peak memory 241524 kb
Host smart-1acad84a-66cc-40cb-821e-1231aa637967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596346482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1596346482
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2580000452
Short name T651
Test name
Test status
Simulation time 715817028 ps
CPU time 25.5 seconds
Started Jul 21 06:34:46 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 247880 kb
Host smart-19c7714f-7eef-4460-ace7-4190f3500ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580000452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2580000452
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.981960275
Short name T678
Test name
Test status
Simulation time 216594641 ps
CPU time 4.97 seconds
Started Jul 21 06:34:49 PM PDT 24
Finished Jul 21 06:34:57 PM PDT 24
Peak memory 241744 kb
Host smart-faeda78f-15a0-4d14-a22a-fef6d8110533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981960275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.981960275
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3929668556
Short name T372
Test name
Test status
Simulation time 15804520436 ps
CPU time 158.89 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 256352 kb
Host smart-c6aac709-5bd8-4778-9d73-f03766277a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929668556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3929668556
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2137246974
Short name T918
Test name
Test status
Simulation time 484360495135 ps
CPU time 1134.79 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:53:49 PM PDT 24
Peak memory 343708 kb
Host smart-91cfd835-03ec-4fd8-b685-47a0a0326ffe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137246974 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.2137246974
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.2783900804
Short name T921
Test name
Test status
Simulation time 1866070864 ps
CPU time 22.29 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:18 PM PDT 24
Peak memory 241684 kb
Host smart-456bcaea-e535-4f4c-b10d-d17f31d3f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783900804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2783900804
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3986545316
Short name T1080
Test name
Test status
Simulation time 1860298320 ps
CPU time 5.03 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 241520 kb
Host smart-99423516-d58f-418a-9a70-cd7cf09f9314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986545316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3986545316
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.553365813
Short name T120
Test name
Test status
Simulation time 209659004 ps
CPU time 3.89 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241160 kb
Host smart-6985350b-1e5c-4b73-b62c-7bbc6870e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553365813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.553365813
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.2379029494
Short name T681
Test name
Test status
Simulation time 1822881094 ps
CPU time 3.74 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241484 kb
Host smart-75416bce-72e0-4203-a29c-87440cd7c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379029494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.2379029494
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.4093610885
Short name T129
Test name
Test status
Simulation time 378061455 ps
CPU time 4.38 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241748 kb
Host smart-123de53d-55e5-49e6-962d-905318a40188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093610885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.4093610885
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2321254704
Short name T911
Test name
Test status
Simulation time 126586255 ps
CPU time 3.71 seconds
Started Jul 21 06:37:17 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241560 kb
Host smart-2635e141-a4aa-437b-ae0f-4be48e4727dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321254704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2321254704
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.555849065
Short name T676
Test name
Test status
Simulation time 188509076 ps
CPU time 4.16 seconds
Started Jul 21 06:37:17 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241096 kb
Host smart-8b9300d2-6e9b-4c14-a942-384d2f59e71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555849065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.555849065
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2914997903
Short name T988
Test name
Test status
Simulation time 260141621 ps
CPU time 4.98 seconds
Started Jul 21 06:37:16 PM PDT 24
Finished Jul 21 06:37:22 PM PDT 24
Peak memory 241368 kb
Host smart-cb7c5892-fbfb-4ddc-add6-1a79615bf4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914997903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2914997903
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.32177404
Short name T158
Test name
Test status
Simulation time 165889456 ps
CPU time 4.53 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241216 kb
Host smart-44a87904-b780-44e2-b83d-ebcfa8ac0d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32177404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.32177404
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.248530138
Short name T92
Test name
Test status
Simulation time 677482178 ps
CPU time 2.61 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:06 PM PDT 24
Peak memory 239860 kb
Host smart-1aac058b-0815-4b1b-b0c4-068c08a9317a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248530138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.248530138
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1994202113
Short name T42
Test name
Test status
Simulation time 13876187784 ps
CPU time 39.82 seconds
Started Jul 21 06:34:52 PM PDT 24
Finished Jul 21 06:35:33 PM PDT 24
Peak memory 242996 kb
Host smart-a0cf14bf-9271-47b4-b101-8851b681e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994202113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1994202113
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.1929080851
Short name T704
Test name
Test status
Simulation time 331060112 ps
CPU time 20.54 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:16 PM PDT 24
Peak memory 241220 kb
Host smart-65aa4a74-5218-4422-82f4-f15270a7fd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929080851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1929080851
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1637492915
Short name T100
Test name
Test status
Simulation time 23231103259 ps
CPU time 63.28 seconds
Started Jul 21 06:34:58 PM PDT 24
Finished Jul 21 06:36:04 PM PDT 24
Peak memory 242356 kb
Host smart-ac1078fc-5268-4873-a34a-f5295869bfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637492915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1637492915
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.4120904235
Short name T438
Test name
Test status
Simulation time 614015108 ps
CPU time 4.72 seconds
Started Jul 21 06:34:52 PM PDT 24
Finished Jul 21 06:34:58 PM PDT 24
Peak memory 241224 kb
Host smart-8f484cee-a3b8-45e0-872d-413b1b68c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120904235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.4120904235
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.3299204780
Short name T147
Test name
Test status
Simulation time 836274028 ps
CPU time 16.86 seconds
Started Jul 21 06:34:58 PM PDT 24
Finished Jul 21 06:35:17 PM PDT 24
Peak memory 241528 kb
Host smart-63eb661e-9e94-451c-b0a8-cca8f527aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299204780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3299204780
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2364839662
Short name T1111
Test name
Test status
Simulation time 374789761 ps
CPU time 11.52 seconds
Started Jul 21 06:34:57 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 241580 kb
Host smart-a06f60d3-31f5-41e9-b03f-84d719a5951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364839662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2364839662
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2095247710
Short name T140
Test name
Test status
Simulation time 3450709945 ps
CPU time 10.77 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:06 PM PDT 24
Peak memory 241284 kb
Host smart-e0e516df-20a8-481b-8478-9ddfd10148ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095247710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2095247710
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.1606992351
Short name T468
Test name
Test status
Simulation time 3900714447 ps
CPU time 32.77 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:27 PM PDT 24
Peak memory 241232 kb
Host smart-3673d97b-44ba-450c-bb06-ba828bdbc1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606992351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1606992351
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.4075750576
Short name T517
Test name
Test status
Simulation time 368206944 ps
CPU time 4.98 seconds
Started Jul 21 06:34:54 PM PDT 24
Finished Jul 21 06:35:01 PM PDT 24
Peak memory 241572 kb
Host smart-fa524b95-aed3-47d4-ae47-fa4f3f75b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075750576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.4075750576
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.1391472366
Short name T1036
Test name
Test status
Simulation time 6861943918 ps
CPU time 73.28 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:36:08 PM PDT 24
Peak memory 244864 kb
Host smart-bbcd1b84-1afa-46e4-ac1e-8685f20a079c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391472366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.1391472366
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3286758619
Short name T286
Test name
Test status
Simulation time 431085668030 ps
CPU time 853.38 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:49:08 PM PDT 24
Peak memory 274852 kb
Host smart-e048bcef-47e8-4a80-b411-d8d50972ff44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286758619 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.3286758619
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1151456686
Short name T16
Test name
Test status
Simulation time 574285064 ps
CPU time 8.17 seconds
Started Jul 21 06:34:53 PM PDT 24
Finished Jul 21 06:35:03 PM PDT 24
Peak memory 241712 kb
Host smart-f9db4d67-d172-42e8-ad1a-dff786ac8b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151456686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1151456686
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3190947612
Short name T953
Test name
Test status
Simulation time 173252345 ps
CPU time 4.65 seconds
Started Jul 21 06:37:17 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241544 kb
Host smart-331cc889-944b-41d9-92fd-9ddde3882cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190947612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3190947612
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.436539279
Short name T962
Test name
Test status
Simulation time 122386104 ps
CPU time 3.36 seconds
Started Jul 21 06:37:17 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241264 kb
Host smart-124115de-f8f4-4df4-821b-169a88dc2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436539279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.436539279
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.3431895167
Short name T764
Test name
Test status
Simulation time 342586025 ps
CPU time 4.13 seconds
Started Jul 21 06:37:16 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241068 kb
Host smart-c8e28086-738a-47a7-95a8-b4443b8921c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431895167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3431895167
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.2368631552
Short name T437
Test name
Test status
Simulation time 139761821 ps
CPU time 3.81 seconds
Started Jul 21 06:37:16 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241632 kb
Host smart-1d390dc8-079c-440c-a401-a917251c4d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368631552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2368631552
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3432403375
Short name T588
Test name
Test status
Simulation time 411695718 ps
CPU time 4.08 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241708 kb
Host smart-4b686db2-c94b-475f-9d81-b37b69b09865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432403375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3432403375
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3497288196
Short name T180
Test name
Test status
Simulation time 269597294 ps
CPU time 3.82 seconds
Started Jul 21 06:37:16 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241464 kb
Host smart-39cbb43f-9091-413c-9ec0-a598e007fcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497288196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3497288196
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.3796992792
Short name T691
Test name
Test status
Simulation time 143299871 ps
CPU time 4.36 seconds
Started Jul 21 06:37:21 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 241140 kb
Host smart-a225ce20-9e60-4950-b249-693e727fea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796992792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.3796992792
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.1096925032
Short name T460
Test name
Test status
Simulation time 432380533 ps
CPU time 4.14 seconds
Started Jul 21 06:37:17 PM PDT 24
Finished Jul 21 06:37:22 PM PDT 24
Peak memory 241504 kb
Host smart-f3a6151f-2ca9-495f-a60a-7e5347720a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096925032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1096925032
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3415181824
Short name T715
Test name
Test status
Simulation time 60089998 ps
CPU time 1.89 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 239588 kb
Host smart-909fc5f7-b589-4716-acd1-ef74af624633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415181824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3415181824
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.4249785388
Short name T843
Test name
Test status
Simulation time 1776818677 ps
CPU time 12.23 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 248036 kb
Host smart-76fa730e-b193-4365-88ce-58eaf28dad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249785388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.4249785388
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1194583097
Short name T1091
Test name
Test status
Simulation time 321743482 ps
CPU time 17.57 seconds
Started Jul 21 06:35:07 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241356 kb
Host smart-5cc582e0-4eca-4a88-beb9-ece01b4b7432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194583097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1194583097
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2488422557
Short name T1167
Test name
Test status
Simulation time 539537604 ps
CPU time 9.36 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 241900 kb
Host smart-fdaaa300-e202-475c-9423-01912d228a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488422557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2488422557
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1656559263
Short name T802
Test name
Test status
Simulation time 1585625085 ps
CPU time 32.79 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 256156 kb
Host smart-99c11ba3-7416-4c45-a01a-d9b6a665ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656559263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1656559263
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.1896751146
Short name T714
Test name
Test status
Simulation time 1993531595 ps
CPU time 17.88 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:20 PM PDT 24
Peak memory 241588 kb
Host smart-cc856333-f5c6-442a-944d-891e2e24fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896751146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1896751146
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.4262543383
Short name T385
Test name
Test status
Simulation time 209823278 ps
CPU time 11.89 seconds
Started Jul 21 06:35:08 PM PDT 24
Finished Jul 21 06:35:21 PM PDT 24
Peak memory 241624 kb
Host smart-ad5b4e96-9876-4d8b-9eaa-d1a8b36b9c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262543383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.4262543383
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.800838055
Short name T740
Test name
Test status
Simulation time 1488762503 ps
CPU time 19.9 seconds
Started Jul 21 06:35:02 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 247752 kb
Host smart-fc7841a3-3e3d-4c1d-a666-eb5261e30b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800838055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.800838055
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.555670842
Short name T1127
Test name
Test status
Simulation time 612170046 ps
CPU time 10.06 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 241360 kb
Host smart-1f8c0cb2-5628-49cc-b863-3c6873dadbd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555670842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.555670842
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.2805342537
Short name T752
Test name
Test status
Simulation time 1259649966 ps
CPU time 9.7 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 241320 kb
Host smart-8a7912ea-803c-4cb6-a7bb-85cb8e7d69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805342537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2805342537
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.85417829
Short name T262
Test name
Test status
Simulation time 56267876733 ps
CPU time 254.37 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:39:17 PM PDT 24
Peak memory 256236 kb
Host smart-733f4198-6d2a-49b9-9d33-814193c494dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85417829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.85417829
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.925088696
Short name T276
Test name
Test status
Simulation time 10370178655 ps
CPU time 331.74 seconds
Started Jul 21 06:35:01 PM PDT 24
Finished Jul 21 06:40:35 PM PDT 24
Peak memory 248188 kb
Host smart-6f888f40-7216-4438-9da7-751bc0ed0bb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925088696 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.925088696
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3397006352
Short name T376
Test name
Test status
Simulation time 7092468565 ps
CPU time 47.38 seconds
Started Jul 21 06:35:01 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 242468 kb
Host smart-d323b723-99e7-4f56-85fa-4a62e0c57def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397006352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3397006352
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1610877367
Short name T167
Test name
Test status
Simulation time 367268895 ps
CPU time 3.85 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241404 kb
Host smart-fcaa584a-d695-4853-8458-89b780534bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610877367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1610877367
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3381614231
Short name T574
Test name
Test status
Simulation time 147827365 ps
CPU time 4.06 seconds
Started Jul 21 06:37:21 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241408 kb
Host smart-22f8fc3f-cf1f-48c4-98da-6dfa8046705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381614231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3381614231
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3741654234
Short name T716
Test name
Test status
Simulation time 139466163 ps
CPU time 3.96 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241364 kb
Host smart-e38b0f57-8302-4bc3-89ed-cc01ece46333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741654234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3741654234
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.3813467274
Short name T169
Test name
Test status
Simulation time 1698272698 ps
CPU time 4.89 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241348 kb
Host smart-6c246bb8-bc6f-4d09-85e6-da8a099b7e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813467274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3813467274
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.2013893151
Short name T177
Test name
Test status
Simulation time 205534558 ps
CPU time 3.49 seconds
Started Jul 21 06:37:20 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241252 kb
Host smart-0396394e-14f2-450e-ad80-0b80cc7940d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013893151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2013893151
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.3797463698
Short name T842
Test name
Test status
Simulation time 107216793 ps
CPU time 3.83 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241448 kb
Host smart-85aff144-4d26-4b2e-abcf-5968cac03d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797463698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3797463698
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2985167312
Short name T781
Test name
Test status
Simulation time 96293147 ps
CPU time 3.31 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241148 kb
Host smart-11ecef47-4d41-4596-aa9c-4d6f8f954aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985167312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2985167312
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3440809118
Short name T494
Test name
Test status
Simulation time 530112906 ps
CPU time 4.59 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:28 PM PDT 24
Peak memory 241768 kb
Host smart-f4dd336a-fac8-4f0a-9377-d03263052659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440809118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3440809118
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.4051753644
Short name T141
Test name
Test status
Simulation time 1856688646 ps
CPU time 7.19 seconds
Started Jul 21 06:37:20 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241344 kb
Host smart-20d1f350-8b06-4da2-8431-d778cb29f11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051753644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.4051753644
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.2777298687
Short name T601
Test name
Test status
Simulation time 91057511 ps
CPU time 3.06 seconds
Started Jul 21 06:37:20 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 241444 kb
Host smart-24d29cf1-9f5a-495d-9774-994628293833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777298687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2777298687
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3661379549
Short name T800
Test name
Test status
Simulation time 64569206 ps
CPU time 1.7 seconds
Started Jul 21 06:35:10 PM PDT 24
Finished Jul 21 06:35:13 PM PDT 24
Peak memory 239944 kb
Host smart-ce979770-adcb-4a1a-b274-f65c74a936bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661379549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3661379549
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.797100395
Short name T76
Test name
Test status
Simulation time 1574173819 ps
CPU time 13.51 seconds
Started Jul 21 06:35:01 PM PDT 24
Finished Jul 21 06:35:17 PM PDT 24
Peak memory 247948 kb
Host smart-758ca204-96c0-4877-9e77-066ae1facf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797100395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.797100395
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3013785086
Short name T190
Test name
Test status
Simulation time 207645749 ps
CPU time 11.99 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 241168 kb
Host smart-1919fd99-4533-4214-a55c-e94349df55f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013785086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3013785086
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.617741584
Short name T941
Test name
Test status
Simulation time 995617945 ps
CPU time 18.1 seconds
Started Jul 21 06:35:02 PM PDT 24
Finished Jul 21 06:35:22 PM PDT 24
Peak memory 241328 kb
Host smart-e9f6cef5-03d2-4989-9fff-9ab813da65f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617741584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.617741584
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.624328933
Short name T852
Test name
Test status
Simulation time 311578814 ps
CPU time 3.75 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 241496 kb
Host smart-311728d9-1f94-4121-ab47-8fac4a24004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624328933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.624328933
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.4058568775
Short name T650
Test name
Test status
Simulation time 943073794 ps
CPU time 9.7 seconds
Started Jul 21 06:34:59 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 241588 kb
Host smart-ab37b33b-ce56-4b12-bd1b-b907473c5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058568775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.4058568775
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.1434107802
Short name T400
Test name
Test status
Simulation time 233791933 ps
CPU time 5.91 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:08 PM PDT 24
Peak memory 241360 kb
Host smart-badf92df-e93d-4d5d-99ca-c8096ad5c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434107802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1434107802
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.1421656014
Short name T696
Test name
Test status
Simulation time 467993298 ps
CPU time 11.91 seconds
Started Jul 21 06:35:01 PM PDT 24
Finished Jul 21 06:35:15 PM PDT 24
Peak memory 241156 kb
Host smart-aa2f477b-084f-4b65-9a8c-42f64b1926dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421656014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1421656014
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.33540994
Short name T808
Test name
Test status
Simulation time 3222108052 ps
CPU time 27.57 seconds
Started Jul 21 06:35:02 PM PDT 24
Finished Jul 21 06:35:31 PM PDT 24
Peak memory 241552 kb
Host smart-74354584-4126-4bb3-8ad7-3a7cd5276158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33540994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.33540994
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.1782837464
Short name T999
Test name
Test status
Simulation time 267011992 ps
CPU time 3.07 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:06 PM PDT 24
Peak memory 247852 kb
Host smart-a807e81c-abec-462b-b0ad-866921462ef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782837464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1782837464
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2594719494
Short name T394
Test name
Test status
Simulation time 869430846 ps
CPU time 6.4 seconds
Started Jul 21 06:35:01 PM PDT 24
Finished Jul 21 06:35:10 PM PDT 24
Peak memory 241628 kb
Host smart-27e551f7-b755-4b67-a203-d42d2d30cfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594719494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2594719494
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1200698825
Short name T683
Test name
Test status
Simulation time 10090463229 ps
CPU time 113.87 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:37:01 PM PDT 24
Peak memory 247992 kb
Host smart-0eaeefca-8fe0-40b5-a7bf-461a71d3c0a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200698825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1200698825
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1717342607
Short name T710
Test name
Test status
Simulation time 10004972246 ps
CPU time 254.37 seconds
Started Jul 21 06:35:07 PM PDT 24
Finished Jul 21 06:39:23 PM PDT 24
Peak memory 250224 kb
Host smart-320fb219-557f-4e81-a47e-708043d50986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717342607 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.1717342607
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.677572920
Short name T418
Test name
Test status
Simulation time 907149126 ps
CPU time 20.05 seconds
Started Jul 21 06:35:00 PM PDT 24
Finished Jul 21 06:35:23 PM PDT 24
Peak memory 241960 kb
Host smart-c575ee01-503d-4f64-99bf-269d472de512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677572920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.677572920
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.449163135
Short name T498
Test name
Test status
Simulation time 333998600 ps
CPU time 5.15 seconds
Started Jul 21 06:37:19 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241104 kb
Host smart-e0f38c8b-6373-4820-8f2c-4cb82206559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449163135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.449163135
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3693302926
Short name T1083
Test name
Test status
Simulation time 145063981 ps
CPU time 3.65 seconds
Started Jul 21 06:37:16 PM PDT 24
Finished Jul 21 06:37:21 PM PDT 24
Peak memory 241308 kb
Host smart-f00fcc81-502a-4651-8cd9-bae63fe08361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693302926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3693302926
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.3567816230
Short name T872
Test name
Test status
Simulation time 119378404 ps
CPU time 3.51 seconds
Started Jul 21 06:37:18 PM PDT 24
Finished Jul 21 06:37:23 PM PDT 24
Peak memory 241384 kb
Host smart-de3961ee-a7ba-4e7c-8ecc-c1b5cf0cb8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567816230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3567816230
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.2878889679
Short name T631
Test name
Test status
Simulation time 137178967 ps
CPU time 3.62 seconds
Started Jul 21 06:37:25 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 241228 kb
Host smart-dd4b9d99-3507-4af9-a79a-d294694e2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878889679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2878889679
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.1191144983
Short name T132
Test name
Test status
Simulation time 160315124 ps
CPU time 4.05 seconds
Started Jul 21 06:37:21 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 241384 kb
Host smart-d717ab45-ab0b-4230-a239-2afdb1c3ec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191144983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1191144983
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3991376599
Short name T759
Test name
Test status
Simulation time 250094355 ps
CPU time 3.73 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:27 PM PDT 24
Peak memory 241260 kb
Host smart-4f3c2271-526c-4f6a-8b94-814ba289222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991376599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3991376599
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.3426614736
Short name T119
Test name
Test status
Simulation time 553259541 ps
CPU time 4.33 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:32 PM PDT 24
Peak memory 241232 kb
Host smart-0ae2d767-e166-488a-9262-c1dbc91f810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426614736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3426614736
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.4219678576
Short name T957
Test name
Test status
Simulation time 552874915 ps
CPU time 4.17 seconds
Started Jul 21 06:37:24 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 241440 kb
Host smart-6adc4bd8-e889-4c30-84e1-38e51534c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219678576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4219678576
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.257041671
Short name T745
Test name
Test status
Simulation time 1491776315 ps
CPU time 4.45 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241476 kb
Host smart-518aee4b-31e0-409a-ab0c-7a4d4d31b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257041671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.257041671
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.4233683926
Short name T150
Test name
Test status
Simulation time 1708866670 ps
CPU time 3.85 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:27 PM PDT 24
Peak memory 241124 kb
Host smart-54f6005b-321b-4078-a5d8-96186a9be4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233683926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.4233683926
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.1754947731
Short name T1133
Test name
Test status
Simulation time 208444266 ps
CPU time 1.96 seconds
Started Jul 21 06:35:05 PM PDT 24
Finished Jul 21 06:35:08 PM PDT 24
Peak memory 239948 kb
Host smart-945eeaa2-d67f-4e8c-bea7-3dd036dddc38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754947731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1754947731
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1462414614
Short name T1034
Test name
Test status
Simulation time 10090744673 ps
CPU time 20.07 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:32 PM PDT 24
Peak memory 242740 kb
Host smart-a1e139df-d451-4a1c-add2-3213dbc1149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462414614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1462414614
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.4099712691
Short name T151
Test name
Test status
Simulation time 3035825971 ps
CPU time 39.63 seconds
Started Jul 21 06:35:07 PM PDT 24
Finished Jul 21 06:35:48 PM PDT 24
Peak memory 250676 kb
Host smart-c7c3d224-c120-4427-877c-8fcee6f366c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099712691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.4099712691
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.3766187186
Short name T554
Test name
Test status
Simulation time 1276826147 ps
CPU time 16.6 seconds
Started Jul 21 06:35:08 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241880 kb
Host smart-98880b13-5b9e-4dd7-8994-460001707abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766187186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3766187186
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.668714409
Short name T25
Test name
Test status
Simulation time 328049419 ps
CPU time 4.42 seconds
Started Jul 21 06:35:05 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 241468 kb
Host smart-d951126d-ca54-435c-a925-e86c985655c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668714409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.668714409
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.3963996211
Short name T829
Test name
Test status
Simulation time 791470021 ps
CPU time 6.73 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:19 PM PDT 24
Peak memory 241224 kb
Host smart-93c5f7d4-5374-49ec-9e10-0b63e15d4c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963996211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3963996211
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.2597095554
Short name T260
Test name
Test status
Simulation time 1940694223 ps
CPU time 28.09 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 248040 kb
Host smart-a3c56a0c-96da-442c-b22a-d94a57ebdbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597095554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2597095554
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.841221609
Short name T424
Test name
Test status
Simulation time 4483076352 ps
CPU time 11.75 seconds
Started Jul 21 06:35:07 PM PDT 24
Finished Jul 21 06:35:20 PM PDT 24
Peak memory 241160 kb
Host smart-92b679ac-d47f-471c-acb7-132267bc0e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841221609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.841221609
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1237085331
Short name T711
Test name
Test status
Simulation time 3048840147 ps
CPU time 11.46 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 241724 kb
Host smart-0b7b5c6b-507a-4a6a-bfb5-90bb7c55298f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237085331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1237085331
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1808191868
Short name T1163
Test name
Test status
Simulation time 160327722 ps
CPU time 4.15 seconds
Started Jul 21 06:35:08 PM PDT 24
Finished Jul 21 06:35:13 PM PDT 24
Peak memory 241812 kb
Host smart-8db35e73-52cf-4863-9ede-1c0c06fdbfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808191868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1808191868
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.3626212955
Short name T1099
Test name
Test status
Simulation time 56487122890 ps
CPU time 246.89 seconds
Started Jul 21 06:35:04 PM PDT 24
Finished Jul 21 06:39:12 PM PDT 24
Peak memory 272672 kb
Host smart-d8dd2c57-d9a6-43bf-874c-a000e7d064fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626212955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.3626212955
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.4064297748
Short name T744
Test name
Test status
Simulation time 15952579647 ps
CPU time 38.37 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:52 PM PDT 24
Peak memory 242896 kb
Host smart-5b72a81a-6663-4384-858a-338415e7a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064297748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.4064297748
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.356091397
Short name T1056
Test name
Test status
Simulation time 446602545 ps
CPU time 3.89 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:28 PM PDT 24
Peak memory 241440 kb
Host smart-514f4e64-ab81-4bf7-9eaa-2300d6d1e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356091397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.356091397
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.1547227912
Short name T713
Test name
Test status
Simulation time 1522454238 ps
CPU time 4.99 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 241260 kb
Host smart-c1290883-ecc7-4d9e-89e8-244c1f82627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547227912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1547227912
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.4070150155
Short name T976
Test name
Test status
Simulation time 195033376 ps
CPU time 4 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:28 PM PDT 24
Peak memory 241432 kb
Host smart-ad1ad511-9df5-46b6-8a49-00c6857f7588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070150155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.4070150155
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.2175079457
Short name T747
Test name
Test status
Simulation time 156692592 ps
CPU time 3.46 seconds
Started Jul 21 06:37:24 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241516 kb
Host smart-07162e26-6b84-4cf0-9040-81ce170184ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175079457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2175079457
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2744098553
Short name T175
Test name
Test status
Simulation time 1993047344 ps
CPU time 4.87 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 241408 kb
Host smart-dc3308b7-cb7b-4f89-9312-3ab6c28ad6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744098553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2744098553
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.2934966644
Short name T569
Test name
Test status
Simulation time 252654149 ps
CPU time 4.1 seconds
Started Jul 21 06:37:25 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 241508 kb
Host smart-c3d90f0c-87db-4f5b-8823-b6f89040918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934966644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2934966644
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.3926456405
Short name T36
Test name
Test status
Simulation time 182606286 ps
CPU time 4.6 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:27 PM PDT 24
Peak memory 241480 kb
Host smart-58fa8d4c-657d-4abe-b583-f98c255ba547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926456405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3926456405
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2346568743
Short name T1175
Test name
Test status
Simulation time 1692838522 ps
CPU time 5.65 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241056 kb
Host smart-d73b786b-9622-4042-a2ad-9f1a87790be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346568743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2346568743
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2533619635
Short name T48
Test name
Test status
Simulation time 176241410 ps
CPU time 5.01 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241448 kb
Host smart-9c186c82-b61c-4ed9-bc91-5293be915b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533619635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2533619635
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.841028451
Short name T844
Test name
Test status
Simulation time 91224042 ps
CPU time 2.08 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 239956 kb
Host smart-6b01c4fe-d2f4-4b01-980c-7cdb27eab9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841028451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.841028451
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3148586134
Short name T756
Test name
Test status
Simulation time 744332252 ps
CPU time 26.14 seconds
Started Jul 21 06:35:07 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 242144 kb
Host smart-cafb7a8f-e625-4f91-9c57-79240f78933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148586134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3148586134
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.3287623504
Short name T925
Test name
Test status
Simulation time 6894213888 ps
CPU time 12.49 seconds
Started Jul 21 06:35:09 PM PDT 24
Finished Jul 21 06:35:22 PM PDT 24
Peak memory 241524 kb
Host smart-6f27745d-ab64-4ac1-b371-8efee5918a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287623504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3287623504
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1011897177
Short name T1058
Test name
Test status
Simulation time 2756241082 ps
CPU time 17.78 seconds
Started Jul 21 06:35:08 PM PDT 24
Finished Jul 21 06:35:27 PM PDT 24
Peak memory 241820 kb
Host smart-dffd5d10-2b61-4a50-8df9-9c2a8c5ef423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011897177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1011897177
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.1626019663
Short name T4
Test name
Test status
Simulation time 212576413 ps
CPU time 3.78 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 241352 kb
Host smart-e3e097ad-9e8a-403e-88c9-3416d657e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626019663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1626019663
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.4145847042
Short name T216
Test name
Test status
Simulation time 2563562714 ps
CPU time 36.2 seconds
Started Jul 21 06:35:08 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 256316 kb
Host smart-1002f75e-1f3a-4600-bd54-f4ade9ccea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145847042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4145847042
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.2734002853
Short name T626
Test name
Test status
Simulation time 139279869 ps
CPU time 6.93 seconds
Started Jul 21 06:35:05 PM PDT 24
Finished Jul 21 06:35:13 PM PDT 24
Peak memory 241652 kb
Host smart-1e756ecf-4a12-4c79-84ca-fc25f1052402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734002853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2734002853
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.3484387302
Short name T685
Test name
Test status
Simulation time 713149749 ps
CPU time 10.65 seconds
Started Jul 21 06:35:05 PM PDT 24
Finished Jul 21 06:35:17 PM PDT 24
Peak memory 241016 kb
Host smart-80c3e1f4-2a77-461b-a072-4ffd4bb20f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484387302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3484387302
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2601453209
Short name T387
Test name
Test status
Simulation time 883153191 ps
CPU time 6 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:20 PM PDT 24
Peak memory 247360 kb
Host smart-a881c09c-95f5-49cd-bd48-5f21cbf43201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601453209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2601453209
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.2900675082
Short name T561
Test name
Test status
Simulation time 245149224 ps
CPU time 4.77 seconds
Started Jul 21 06:35:07 PM PDT 24
Finished Jul 21 06:35:13 PM PDT 24
Peak memory 241428 kb
Host smart-2fec4c72-a150-42ec-87e6-0cfa9153197f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900675082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2900675082
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2406484934
Short name T463
Test name
Test status
Simulation time 1040585796 ps
CPU time 16.35 seconds
Started Jul 21 06:35:04 PM PDT 24
Finished Jul 21 06:35:22 PM PDT 24
Peak memory 241424 kb
Host smart-490a98c8-65fb-44a8-b1c4-71d07213d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406484934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2406484934
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2160278263
Short name T980
Test name
Test status
Simulation time 21838628770 ps
CPU time 128.04 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:37:16 PM PDT 24
Peak memory 261340 kb
Host smart-7351ce1b-d74d-4f38-b482-852cc1e2fc56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160278263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2160278263
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.1121229751
Short name T487
Test name
Test status
Simulation time 297521666 ps
CPU time 4.13 seconds
Started Jul 21 06:37:26 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241412 kb
Host smart-351156cd-c27e-41d8-ad53-16bbc58997f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121229751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1121229751
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1714012645
Short name T91
Test name
Test status
Simulation time 285379183 ps
CPU time 3.69 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:32 PM PDT 24
Peak memory 241500 kb
Host smart-4bc794ac-4ec4-4715-b64c-ba0a97b24504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714012645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1714012645
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.2241370035
Short name T133
Test name
Test status
Simulation time 219814434 ps
CPU time 4.88 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241444 kb
Host smart-4f3e2111-fd70-4c77-92ab-1b61a726ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241370035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2241370035
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3140973919
Short name T47
Test name
Test status
Simulation time 179434137 ps
CPU time 4.46 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:32 PM PDT 24
Peak memory 241388 kb
Host smart-7e8cc781-8b80-4113-b0f8-08c8d7225f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140973919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3140973919
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.4175042469
Short name T1119
Test name
Test status
Simulation time 1666962288 ps
CPU time 5.72 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:35 PM PDT 24
Peak memory 241388 kb
Host smart-77b2983a-1267-47fd-83bf-bcd7e4ed5dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175042469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.4175042469
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2499232891
Short name T1124
Test name
Test status
Simulation time 408431589 ps
CPU time 4.39 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241440 kb
Host smart-b759ba59-df19-4b6e-952c-f4fac7254c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499232891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2499232891
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.3080787582
Short name T556
Test name
Test status
Simulation time 614954623 ps
CPU time 5.31 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:28 PM PDT 24
Peak memory 241372 kb
Host smart-305a31ba-d307-4cd1-9a69-6ddbbb7d23ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080787582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3080787582
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.2869452119
Short name T629
Test name
Test status
Simulation time 257777645 ps
CPU time 4.92 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 241448 kb
Host smart-fff8397d-60f1-4d33-9d6c-3b5f5825bfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869452119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2869452119
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.1478321085
Short name T741
Test name
Test status
Simulation time 153318853 ps
CPU time 4.13 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:28 PM PDT 24
Peak memory 241300 kb
Host smart-ac2aac50-3398-4173-b9bc-920807ad2270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478321085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1478321085
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1088340295
Short name T624
Test name
Test status
Simulation time 51807737 ps
CPU time 1.77 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:16 PM PDT 24
Peak memory 239656 kb
Host smart-8467d897-c4be-4cb5-8e03-3589066932a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088340295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1088340295
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.698336707
Short name T116
Test name
Test status
Simulation time 964460476 ps
CPU time 9.79 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 248024 kb
Host smart-6c19a4aa-1c25-413b-89f3-9fc694be46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698336707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.698336707
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.648211388
Short name T339
Test name
Test status
Simulation time 931675342 ps
CPU time 18.5 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:33 PM PDT 24
Peak memory 241812 kb
Host smart-4df73f52-3c59-4d6d-8bac-83a0c4ffb640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648211388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.648211388
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.2775552437
Short name T1020
Test name
Test status
Simulation time 159434304 ps
CPU time 6.73 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:19 PM PDT 24
Peak memory 241720 kb
Host smart-667220a4-682b-4042-933e-33fb4b48fd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775552437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2775552437
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2944631082
Short name T940
Test name
Test status
Simulation time 214722340 ps
CPU time 4.11 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:35:11 PM PDT 24
Peak memory 241364 kb
Host smart-888def46-0caa-458f-abc1-197ef48cddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944631082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2944631082
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3111274508
Short name T344
Test name
Test status
Simulation time 1720955490 ps
CPU time 28.68 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:43 PM PDT 24
Peak memory 246876 kb
Host smart-56a15527-86c2-4324-8d53-b8cc4e1536ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111274508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3111274508
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.3525330443
Short name T986
Test name
Test status
Simulation time 155671706 ps
CPU time 7.32 seconds
Started Jul 21 06:35:15 PM PDT 24
Finished Jul 21 06:35:23 PM PDT 24
Peak memory 241128 kb
Host smart-87b50c92-3267-48b6-bf33-e86381192ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525330443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3525330443
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2028740036
Short name T1183
Test name
Test status
Simulation time 212236892 ps
CPU time 5.52 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 241100 kb
Host smart-ea82033e-03ef-4548-8e42-e72ab6d61063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028740036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2028740036
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3397810301
Short name T743
Test name
Test status
Simulation time 2832253866 ps
CPU time 26.68 seconds
Started Jul 21 06:35:15 PM PDT 24
Finished Jul 21 06:35:43 PM PDT 24
Peak memory 241124 kb
Host smart-3dccbbd8-de51-499a-ae3a-fc2a29bf4032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397810301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3397810301
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2577759060
Short name T788
Test name
Test status
Simulation time 313568772 ps
CPU time 10.14 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 240900 kb
Host smart-ec4ba569-4b7c-46e5-a14e-d05aee97260c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577759060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2577759060
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2620956450
Short name T786
Test name
Test status
Simulation time 4361256427 ps
CPU time 6.97 seconds
Started Jul 21 06:35:06 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 241652 kb
Host smart-38ae9c16-f976-4f9d-b2f8-56f54da77bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620956450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2620956450
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.449432723
Short name T792
Test name
Test status
Simulation time 18663825689 ps
CPU time 131.36 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 247280 kb
Host smart-feb01e49-259a-469d-9f09-211a857ed1f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449432723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
449432723
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3580611309
Short name T163
Test name
Test status
Simulation time 64293285141 ps
CPU time 485.02 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:43:23 PM PDT 24
Peak memory 368268 kb
Host smart-d2b2218d-25a6-4e27-9146-4a19071b3a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580611309 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3580611309
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.4085333611
Short name T1102
Test name
Test status
Simulation time 10592839793 ps
CPU time 31.92 seconds
Started Jul 21 06:35:10 PM PDT 24
Finished Jul 21 06:35:43 PM PDT 24
Peak memory 241836 kb
Host smart-2be6ad09-37b5-41e4-b23b-5bc81365067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085333611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.4085333611
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2939691282
Short name T693
Test name
Test status
Simulation time 386656899 ps
CPU time 4.11 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241200 kb
Host smart-c0a16806-d057-40fd-8f3b-79a72019835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939691282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2939691282
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1739534770
Short name T1105
Test name
Test status
Simulation time 139972145 ps
CPU time 3.47 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:27 PM PDT 24
Peak memory 241524 kb
Host smart-e964871e-36b4-42e1-857c-32dbc69f4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739534770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1739534770
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.2130041129
Short name T142
Test name
Test status
Simulation time 407018283 ps
CPU time 4.21 seconds
Started Jul 21 06:37:24 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 241692 kb
Host smart-ed270597-db05-41d0-a3bf-a6b7ffd7f7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130041129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2130041129
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2964741148
Short name T1062
Test name
Test status
Simulation time 385878412 ps
CPU time 5.45 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241304 kb
Host smart-ba5cb0c7-7ee6-44b7-ad3e-1d09fa914739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964741148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2964741148
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.1946688421
Short name T430
Test name
Test status
Simulation time 117049632 ps
CPU time 3.2 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:32 PM PDT 24
Peak memory 241808 kb
Host smart-6bc989ab-428b-4d42-b275-9d631a466451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946688421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1946688421
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.489120096
Short name T735
Test name
Test status
Simulation time 390581124 ps
CPU time 3.63 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241244 kb
Host smart-bdc6d4a9-9129-4cea-90e8-812dd9ea7bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489120096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.489120096
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.1050503421
Short name T816
Test name
Test status
Simulation time 246129480 ps
CPU time 5.28 seconds
Started Jul 21 06:37:24 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241436 kb
Host smart-a9ae6030-3670-40b1-baca-1570da2e7c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050503421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1050503421
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.2424140207
Short name T912
Test name
Test status
Simulation time 2563248683 ps
CPU time 5.78 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241304 kb
Host smart-4cd08f5e-1f86-4ff5-96be-3bb1255ed70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424140207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2424140207
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3615726434
Short name T989
Test name
Test status
Simulation time 167671010 ps
CPU time 4.32 seconds
Started Jul 21 06:37:23 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 241196 kb
Host smart-512d2321-7fa9-467c-ab0f-d45cdbbb65bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615726434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3615726434
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.2216918719
Short name T202
Test name
Test status
Simulation time 127466702 ps
CPU time 3.6 seconds
Started Jul 21 06:37:22 PM PDT 24
Finished Jul 21 06:37:27 PM PDT 24
Peak memory 241404 kb
Host smart-4d2915d5-77af-4e67-bf7e-7436b967a4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216918719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2216918719
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1492154372
Short name T457
Test name
Test status
Simulation time 1032515376 ps
CPU time 2.65 seconds
Started Jul 21 06:35:13 PM PDT 24
Finished Jul 21 06:35:18 PM PDT 24
Peak memory 239660 kb
Host smart-ff1e5ccc-1559-43df-9750-e5bb3b424f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492154372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1492154372
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.565773182
Short name T166
Test name
Test status
Simulation time 840365815 ps
CPU time 10.67 seconds
Started Jul 21 06:35:13 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241804 kb
Host smart-9605d93d-8e83-40a8-865e-66e817b74d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565773182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.565773182
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.840666086
Short name T495
Test name
Test status
Simulation time 311921465 ps
CPU time 16.32 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:29 PM PDT 24
Peak memory 241352 kb
Host smart-74d2e0db-a5c0-40a4-9311-14f9f537b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840666086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.840666086
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.290012365
Short name T914
Test name
Test status
Simulation time 2967519240 ps
CPU time 25.83 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:40 PM PDT 24
Peak memory 248044 kb
Host smart-7843c936-57a2-47ae-b038-c5fab00bd924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290012365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.290012365
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.849633222
Short name T176
Test name
Test status
Simulation time 405050700 ps
CPU time 4.57 seconds
Started Jul 21 06:35:14 PM PDT 24
Finished Jul 21 06:35:20 PM PDT 24
Peak memory 241400 kb
Host smart-585d53cf-f236-48e5-8e10-6e2559868099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849633222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.849633222
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3296775054
Short name T620
Test name
Test status
Simulation time 683515030 ps
CPU time 7.32 seconds
Started Jul 21 06:35:10 PM PDT 24
Finished Jul 21 06:35:19 PM PDT 24
Peak memory 242212 kb
Host smart-c66ce868-4d71-4624-9e46-632099b2cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296775054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3296775054
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.3491065065
Short name T187
Test name
Test status
Simulation time 1220043269 ps
CPU time 21.73 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 241956 kb
Host smart-b83c750a-7a07-4387-ad9a-a07927ba0b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491065065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3491065065
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3917394345
Short name T648
Test name
Test status
Simulation time 257767797 ps
CPU time 4.12 seconds
Started Jul 21 06:35:15 PM PDT 24
Finished Jul 21 06:35:20 PM PDT 24
Peak memory 241244 kb
Host smart-d0c9c442-bfad-43fc-933f-992972391ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917394345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3917394345
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.1464180391
Short name T593
Test name
Test status
Simulation time 865907285 ps
CPU time 19.39 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 240784 kb
Host smart-6f3cc185-05bc-46ea-96b4-e92ed70f3981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464180391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1464180391
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.1789360834
Short name T365
Test name
Test status
Simulation time 647850920 ps
CPU time 10.41 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 241360 kb
Host smart-69833639-15c2-493a-87c8-0f507f8bc036
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789360834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1789360834
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2589953503
Short name T823
Test name
Test status
Simulation time 2661994903 ps
CPU time 5.16 seconds
Started Jul 21 06:35:11 PM PDT 24
Finished Jul 21 06:35:18 PM PDT 24
Peak memory 241872 kb
Host smart-7ed9678e-bf9a-4b89-8edc-f5fd63ee709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589953503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2589953503
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.305815025
Short name T1048
Test name
Test status
Simulation time 456993589 ps
CPU time 11.53 seconds
Started Jul 21 06:35:10 PM PDT 24
Finished Jul 21 06:35:23 PM PDT 24
Peak memory 248044 kb
Host smart-b0490650-f811-49a3-8a9a-56223f813ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305815025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.305815025
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.313403093
Short name T526
Test name
Test status
Simulation time 145699801 ps
CPU time 3.6 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241508 kb
Host smart-23deb7d0-e235-419a-9623-ecb116b0de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313403093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.313403093
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.3432544774
Short name T727
Test name
Test status
Simulation time 432775085 ps
CPU time 4.08 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:32 PM PDT 24
Peak memory 241456 kb
Host smart-32efd315-22d2-45c3-b33f-e0c4b662a0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432544774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3432544774
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.179392515
Short name T768
Test name
Test status
Simulation time 469370901 ps
CPU time 3.74 seconds
Started Jul 21 06:37:21 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 241300 kb
Host smart-e0b2799a-68a2-49b1-8f5b-cbe159900164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179392515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.179392515
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.1980376934
Short name T729
Test name
Test status
Simulation time 134855543 ps
CPU time 2.83 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241252 kb
Host smart-1dab3303-42d8-4748-bdfd-344e47b29a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980376934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1980376934
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.4076968805
Short name T779
Test name
Test status
Simulation time 515353395 ps
CPU time 5.73 seconds
Started Jul 21 06:37:24 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 241440 kb
Host smart-f23cabec-1d4d-4ee6-9e68-b1c4b5d3a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076968805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.4076968805
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1551543393
Short name T455
Test name
Test status
Simulation time 177152409 ps
CPU time 4.82 seconds
Started Jul 21 06:37:24 PM PDT 24
Finished Jul 21 06:37:30 PM PDT 24
Peak memory 241212 kb
Host smart-6ac8e377-0e5d-4669-9e2a-241950f98c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551543393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1551543393
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3043032071
Short name T969
Test name
Test status
Simulation time 111379971 ps
CPU time 3.35 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241400 kb
Host smart-90a76121-b07d-455e-8456-64277b62bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043032071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3043032071
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.3425271569
Short name T156
Test name
Test status
Simulation time 254843528 ps
CPU time 4.07 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:36 PM PDT 24
Peak memory 241316 kb
Host smart-db8db3aa-c562-4a96-9ab8-b27e9203747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425271569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3425271569
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.1018712680
Short name T1028
Test name
Test status
Simulation time 237931332 ps
CPU time 4.22 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:36 PM PDT 24
Peak memory 241256 kb
Host smart-35943733-1b22-4435-9ae0-210afbf7cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018712680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1018712680
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3987930240
Short name T796
Test name
Test status
Simulation time 152594323 ps
CPU time 1.59 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:21 PM PDT 24
Peak memory 239704 kb
Host smart-c605a390-edb3-46b2-b68f-5fdb57c7624e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987930240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3987930240
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.1555422667
Short name T90
Test name
Test status
Simulation time 14392069982 ps
CPU time 34.78 seconds
Started Jul 21 06:35:19 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 245432 kb
Host smart-ea09437f-2e31-4901-9478-ca01d53657f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555422667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1555422667
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.802598647
Short name T340
Test name
Test status
Simulation time 984869325 ps
CPU time 24.41 seconds
Started Jul 21 06:35:18 PM PDT 24
Finished Jul 21 06:35:44 PM PDT 24
Peak memory 241564 kb
Host smart-5fc66b9e-7df4-4804-89be-19f9fddcd835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802598647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.802598647
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.2096155446
Short name T974
Test name
Test status
Simulation time 2271398709 ps
CPU time 13.93 seconds
Started Jul 21 06:35:21 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 241608 kb
Host smart-b2d3f60f-55b0-46e4-8fd1-b21bc3d2f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096155446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2096155446
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3998551441
Short name T83
Test name
Test status
Simulation time 605102579 ps
CPU time 4.66 seconds
Started Jul 21 06:35:12 PM PDT 24
Finished Jul 21 06:35:19 PM PDT 24
Peak memory 241436 kb
Host smart-cd58f915-b8fa-41f2-94f5-faf1d2d4f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998551441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3998551441
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.301878177
Short name T137
Test name
Test status
Simulation time 464465846 ps
CPU time 12.13 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:30 PM PDT 24
Peak memory 247996 kb
Host smart-32e8d82f-1705-4b9b-ac44-e90062a40043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301878177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.301878177
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3329136632
Short name T1026
Test name
Test status
Simulation time 486392504 ps
CPU time 11.76 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:30 PM PDT 24
Peak memory 241500 kb
Host smart-3c2f7f48-f3ab-4cbe-8067-1f171a23f5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329136632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3329136632
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1597881427
Short name T1101
Test name
Test status
Simulation time 262176304 ps
CPU time 5.88 seconds
Started Jul 21 06:35:18 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241520 kb
Host smart-e6bf62d7-0de9-4ff6-9673-2bc700964496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597881427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1597881427
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.947219843
Short name T613
Test name
Test status
Simulation time 259556322 ps
CPU time 7.64 seconds
Started Jul 21 06:35:19 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 241108 kb
Host smart-c995b5d5-317a-4757-90c5-f3ac41f6c31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947219843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.947219843
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.3126947428
Short name T619
Test name
Test status
Simulation time 511341467 ps
CPU time 8.57 seconds
Started Jul 21 06:35:19 PM PDT 24
Finished Jul 21 06:35:29 PM PDT 24
Peak memory 241532 kb
Host smart-6b5a24b5-362e-4061-a759-0453c24f6f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126947428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3126947428
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1356772607
Short name T1039
Test name
Test status
Simulation time 1244628712 ps
CPU time 10.23 seconds
Started Jul 21 06:35:15 PM PDT 24
Finished Jul 21 06:35:27 PM PDT 24
Peak memory 241352 kb
Host smart-34a13cc8-223b-481f-a371-14f585f1c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356772607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1356772607
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.3758182543
Short name T298
Test name
Test status
Simulation time 94686170 ps
CPU time 2.16 seconds
Started Jul 21 06:35:18 PM PDT 24
Finished Jul 21 06:35:23 PM PDT 24
Peak memory 240676 kb
Host smart-a2fb7335-a8e1-4797-97e6-fa6a40d62010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758182543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.3758182543
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.522549484
Short name T505
Test name
Test status
Simulation time 2892010644 ps
CPU time 7.04 seconds
Started Jul 21 06:35:19 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 241740 kb
Host smart-09322f45-c366-4bc3-aee1-4b631752f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522549484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.522549484
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3726176840
Short name T875
Test name
Test status
Simulation time 111780438 ps
CPU time 4.55 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:35 PM PDT 24
Peak memory 241568 kb
Host smart-0cf3eb9e-5368-4f9a-95bd-160d30cf39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726176840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3726176840
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.951506928
Short name T739
Test name
Test status
Simulation time 265599255 ps
CPU time 3.9 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 241432 kb
Host smart-013bcdb8-957b-4f37-a27b-69df053193e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951506928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.951506928
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.65871180
Short name T861
Test name
Test status
Simulation time 447849398 ps
CPU time 4.62 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241556 kb
Host smart-9424cbed-971f-4ddb-8808-fce5f67d42f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65871180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.65871180
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.862079490
Short name T432
Test name
Test status
Simulation time 1959359581 ps
CPU time 4.6 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241552 kb
Host smart-d60e8cdd-1add-477f-bdd9-eace9c8bf914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862079490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.862079490
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.612129380
Short name T794
Test name
Test status
Simulation time 117102488 ps
CPU time 4.2 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241692 kb
Host smart-de512451-5e2a-4863-b691-8494d81b8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612129380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.612129380
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.262399873
Short name T854
Test name
Test status
Simulation time 180684262 ps
CPU time 4.42 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:36 PM PDT 24
Peak memory 241232 kb
Host smart-a45a6d96-cb16-428d-bd76-4872ee263438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262399873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.262399873
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1138171594
Short name T956
Test name
Test status
Simulation time 2458808274 ps
CPU time 6 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 241476 kb
Host smart-a1ab217b-46c7-42c4-8d79-528069b6a370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138171594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1138171594
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.651400421
Short name T168
Test name
Test status
Simulation time 484054033 ps
CPU time 3.92 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 241124 kb
Host smart-d8e7cd11-4a39-40ff-95cd-62d25f30ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651400421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.651400421
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2699716035
Short name T825
Test name
Test status
Simulation time 670627495 ps
CPU time 4.97 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:36 PM PDT 24
Peak memory 241460 kb
Host smart-61af3ba5-d562-4040-8623-5a8126e0bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699716035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2699716035
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3470480248
Short name T994
Test name
Test status
Simulation time 84504807 ps
CPU time 2.1 seconds
Started Jul 21 06:35:21 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 239616 kb
Host smart-edbba41b-c868-4832-961d-109b5435e3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470480248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3470480248
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.840239445
Short name T341
Test name
Test status
Simulation time 1059702494 ps
CPU time 21.15 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:39 PM PDT 24
Peak memory 241352 kb
Host smart-790eb137-7556-4bb2-8029-c7efe3fe749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840239445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.840239445
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2939875128
Short name T136
Test name
Test status
Simulation time 1131057107 ps
CPU time 13.68 seconds
Started Jul 21 06:35:20 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 248092 kb
Host smart-098f88a7-cc12-4934-88d0-6d8a9624104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939875128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2939875128
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.1417541126
Short name T1067
Test name
Test status
Simulation time 140042944 ps
CPU time 4.19 seconds
Started Jul 21 06:35:18 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 241328 kb
Host smart-4c17ffdd-dcd1-48d5-ba4a-da8f0ce854c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417541126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1417541126
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.189912417
Short name T1155
Test name
Test status
Simulation time 1053142297 ps
CPU time 16.13 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:34 PM PDT 24
Peak memory 241292 kb
Host smart-02a26e24-bc39-47ec-b877-75bf37c64268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189912417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.189912417
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.4225077317
Short name T671
Test name
Test status
Simulation time 12202392702 ps
CPU time 33.63 seconds
Started Jul 21 06:35:20 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 241472 kb
Host smart-4b8f562c-0089-4e3f-a94c-5e2955e4f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225077317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4225077317
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.954036766
Short name T242
Test name
Test status
Simulation time 240172828 ps
CPU time 11.79 seconds
Started Jul 21 06:35:21 PM PDT 24
Finished Jul 21 06:35:34 PM PDT 24
Peak memory 241036 kb
Host smart-97256cdd-fdbb-426e-bf29-4cdf75774c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954036766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.954036766
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.2907830477
Short name T938
Test name
Test status
Simulation time 8983707614 ps
CPU time 20.97 seconds
Started Jul 21 06:35:18 PM PDT 24
Finished Jul 21 06:35:40 PM PDT 24
Peak memory 241732 kb
Host smart-d30ce629-53bb-439f-8b4a-edd39460bfe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907830477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2907830477
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.67893449
Short name T363
Test name
Test status
Simulation time 301194507 ps
CPU time 4.24 seconds
Started Jul 21 06:35:18 PM PDT 24
Finished Jul 21 06:35:24 PM PDT 24
Peak memory 241268 kb
Host smart-382329c0-8421-4ae5-b860-3c92649fa1f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67893449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.67893449
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.2142833809
Short name T1114
Test name
Test status
Simulation time 237329349 ps
CPU time 7.09 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241348 kb
Host smart-65a809c1-02cb-40a3-bf36-a6bcd34c530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142833809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2142833809
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.1279854452
Short name T1147
Test name
Test status
Simulation time 1315571836 ps
CPU time 23.83 seconds
Started Jul 21 06:35:21 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 242116 kb
Host smart-f3a064a0-6aa7-4448-b5ce-872e59c7891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279854452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1279854452
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2724671438
Short name T611
Test name
Test status
Simulation time 338808152 ps
CPU time 3.67 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:36 PM PDT 24
Peak memory 241712 kb
Host smart-3b03ff4c-d3da-4284-a7cc-a3eb64723024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724671438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2724671438
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.644483407
Short name T287
Test name
Test status
Simulation time 237025720 ps
CPU time 3.96 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 241176 kb
Host smart-fc787152-875d-4f0a-83db-f8838d3e8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644483407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.644483407
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.971932256
Short name T584
Test name
Test status
Simulation time 160565004 ps
CPU time 4.54 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 241220 kb
Host smart-69c18df7-bd38-418c-8944-0a599763d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971932256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.971932256
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.2171806646
Short name T571
Test name
Test status
Simulation time 1702128081 ps
CPU time 5.21 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:35 PM PDT 24
Peak memory 241328 kb
Host smart-035aec52-acf6-470e-b79f-d98b80c7b990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171806646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2171806646
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3395469511
Short name T640
Test name
Test status
Simulation time 266997522 ps
CPU time 3.65 seconds
Started Jul 21 06:37:32 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 241708 kb
Host smart-2f40d52c-eb15-4c05-b342-6b8be1c8eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395469511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3395469511
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.543312813
Short name T851
Test name
Test status
Simulation time 438154965 ps
CPU time 3.98 seconds
Started Jul 21 06:37:32 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 241496 kb
Host smart-6dcf664c-fef5-47db-9c4a-33308ca6800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543312813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.543312813
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.3184093274
Short name T909
Test name
Test status
Simulation time 106169953 ps
CPU time 4.28 seconds
Started Jul 21 06:37:29 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 241384 kb
Host smart-1ec4aa23-bf87-4f44-9993-0ee16d8457a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184093274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3184093274
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1382987831
Short name T1108
Test name
Test status
Simulation time 409753609 ps
CPU time 4.04 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:35 PM PDT 24
Peak memory 241392 kb
Host smart-4412d0cc-ecd7-48e0-9bc9-3b53414127df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382987831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1382987831
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3096127997
Short name T857
Test name
Test status
Simulation time 130909886 ps
CPU time 4.47 seconds
Started Jul 21 06:37:32 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 241436 kb
Host smart-15e0c846-bc30-4124-8f32-8ab669e622bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096127997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3096127997
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2671530632
Short name T1045
Test name
Test status
Simulation time 165697127 ps
CPU time 4.17 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 241204 kb
Host smart-ad5b3bee-6ee4-4327-848c-92578393ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671530632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2671530632
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2493828085
Short name T633
Test name
Test status
Simulation time 60850514 ps
CPU time 1.75 seconds
Started Jul 21 06:34:13 PM PDT 24
Finished Jul 21 06:34:19 PM PDT 24
Peak memory 239752 kb
Host smart-723f5de3-994a-49fb-aaf0-5788a7ce5193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493828085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2493828085
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.622616148
Short name T970
Test name
Test status
Simulation time 1624295095 ps
CPU time 11.29 seconds
Started Jul 21 06:34:14 PM PDT 24
Finished Jul 21 06:34:29 PM PDT 24
Peak memory 248028 kb
Host smart-dc1f3965-40b9-4e01-8147-0cd07084db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622616148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.622616148
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.2657288256
Short name T15
Test name
Test status
Simulation time 1609663421 ps
CPU time 11.99 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 241520 kb
Host smart-4214c49f-28dd-42b6-a5f7-60aea010220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657288256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2657288256
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.984147292
Short name T654
Test name
Test status
Simulation time 1892912695 ps
CPU time 30.13 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 241412 kb
Host smart-83017da5-cc91-45ce-8834-5f590c471312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984147292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.984147292
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.3536046445
Short name T80
Test name
Test status
Simulation time 1771453862 ps
CPU time 3.97 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:19 PM PDT 24
Peak memory 241424 kb
Host smart-17c03b42-151b-4a19-8a40-daf846f65db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536046445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3536046445
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.118332978
Short name T1146
Test name
Test status
Simulation time 2588489242 ps
CPU time 31.43 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 248076 kb
Host smart-5add3634-021c-4d02-8496-5e48f1a490ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118332978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.118332978
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.331654930
Short name T824
Test name
Test status
Simulation time 1855701202 ps
CPU time 10.81 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241552 kb
Host smart-749e79bf-1d45-44d5-8671-b4bb594918e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331654930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.331654930
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1536328938
Short name T677
Test name
Test status
Simulation time 1267233398 ps
CPU time 8.44 seconds
Started Jul 21 06:34:13 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241208 kb
Host smart-6dc47849-bb39-4b6a-9527-4e9a1416982b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536328938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1536328938
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.421498430
Short name T660
Test name
Test status
Simulation time 990290500 ps
CPU time 16.28 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:32 PM PDT 24
Peak memory 241416 kb
Host smart-2ed6c818-87d2-4ed6-8958-913d0e702df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421498430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.421498430
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.1784738125
Short name T358
Test name
Test status
Simulation time 171917931 ps
CPU time 4.88 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:19 PM PDT 24
Peak memory 241216 kb
Host smart-453f3030-a18c-42ca-88bb-d4a14649cf80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784738125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1784738125
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2598055944
Short name T23
Test name
Test status
Simulation time 10763833815 ps
CPU time 203.91 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 270476 kb
Host smart-4c8bf5e6-66a4-42a0-b6ef-322041ab6933
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598055944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2598055944
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.642700722
Short name T617
Test name
Test status
Simulation time 169496737 ps
CPU time 6.97 seconds
Started Jul 21 06:34:15 PM PDT 24
Finished Jul 21 06:34:25 PM PDT 24
Peak memory 241216 kb
Host smart-4fbe23b5-098a-48c8-8236-50513424d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642700722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.642700722
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.1002557672
Short name T772
Test name
Test status
Simulation time 1535088991 ps
CPU time 17.35 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:32 PM PDT 24
Peak memory 241348 kb
Host smart-c03686c5-043a-4e7c-adea-8e08da25ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002557672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1002557672
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.490409067
Short name T391
Test name
Test status
Simulation time 199282223 ps
CPU time 2.2 seconds
Started Jul 21 06:35:26 PM PDT 24
Finished Jul 21 06:35:31 PM PDT 24
Peak memory 239700 kb
Host smart-68723583-f074-4571-9028-f06948d71b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490409067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.490409067
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.2130686844
Short name T1144
Test name
Test status
Simulation time 1171033300 ps
CPU time 13.77 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 248008 kb
Host smart-77513b6a-69b1-45b2-b4f2-e08ec5793cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130686844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.2130686844
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.521419715
Short name T522
Test name
Test status
Simulation time 405487509 ps
CPU time 21.06 seconds
Started Jul 21 06:35:26 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 241280 kb
Host smart-e49dbd9e-cbae-40ee-a220-fca3fd600a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521419715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.521419715
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3911693288
Short name T409
Test name
Test status
Simulation time 2890430530 ps
CPU time 31.9 seconds
Started Jul 21 06:35:19 PM PDT 24
Finished Jul 21 06:35:52 PM PDT 24
Peak memory 242020 kb
Host smart-0a652f68-4ff9-49af-8509-48ae09fe59a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911693288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3911693288
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.3682666245
Short name T738
Test name
Test status
Simulation time 319693143 ps
CPU time 4.74 seconds
Started Jul 21 06:35:20 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241432 kb
Host smart-6b1eebfd-2d79-4f61-bcf8-0aea3a0b40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682666245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3682666245
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.803463858
Short name T39
Test name
Test status
Simulation time 1375048606 ps
CPU time 9.22 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:37 PM PDT 24
Peak memory 241408 kb
Host smart-656afa8d-83bc-4a6e-9e35-b12534aa7e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803463858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.803463858
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.944784822
Short name T730
Test name
Test status
Simulation time 1047492539 ps
CPU time 17.94 seconds
Started Jul 21 06:35:19 PM PDT 24
Finished Jul 21 06:35:39 PM PDT 24
Peak memory 241668 kb
Host smart-36ce1082-9acc-439b-87b8-740487d59c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944784822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.944784822
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1296988512
Short name T657
Test name
Test status
Simulation time 755579231 ps
CPU time 19.66 seconds
Started Jul 21 06:35:17 PM PDT 24
Finished Jul 21 06:35:39 PM PDT 24
Peak memory 241424 kb
Host smart-2c52c0ec-4b74-479e-9a86-c3d85176b87e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296988512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1296988512
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3592350554
Short name T1004
Test name
Test status
Simulation time 379911832 ps
CPU time 6.06 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:35:33 PM PDT 24
Peak memory 241264 kb
Host smart-a0eca354-8b49-4fd7-8bba-f2188f3345ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592350554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3592350554
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3095425481
Short name T507
Test name
Test status
Simulation time 306168212 ps
CPU time 4.56 seconds
Started Jul 21 06:35:21 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 241244 kb
Host smart-17f0011b-4090-4351-a854-a9240a5779e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095425481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3095425481
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.122889589
Short name T737
Test name
Test status
Simulation time 6938164912 ps
CPU time 49.81 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:36:17 PM PDT 24
Peak memory 243768 kb
Host smart-cd42000d-d24e-4a3f-ae48-4dca4b687504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122889589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
122889589
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.1404356622
Short name T1050
Test name
Test status
Simulation time 33454836334 ps
CPU time 392.54 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 270252 kb
Host smart-5cbf9cab-6bd7-49d6-8abe-d2a13d1dc2ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404356622 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.1404356622
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.741915312
Short name T906
Test name
Test status
Simulation time 464591387 ps
CPU time 9.9 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 241392 kb
Host smart-33998d35-e67a-423d-9c82-665d973c0181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741915312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.741915312
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.2601996023
Short name T565
Test name
Test status
Simulation time 842424220 ps
CPU time 2.4 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:31 PM PDT 24
Peak memory 240068 kb
Host smart-9aa21cb7-d885-4999-840a-6659268cc13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601996023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2601996023
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.2134992087
Short name T582
Test name
Test status
Simulation time 434062951 ps
CPU time 10.53 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 241936 kb
Host smart-e6aa41e3-d901-495d-9237-c98e9a58d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134992087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2134992087
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.3821072725
Short name T1128
Test name
Test status
Simulation time 349230529 ps
CPU time 14.88 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:35:40 PM PDT 24
Peak memory 241144 kb
Host smart-b0241d2b-13a1-428f-8d11-0f3f94fbdafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821072725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3821072725
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2204952228
Short name T758
Test name
Test status
Simulation time 697056586 ps
CPU time 7.86 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 241728 kb
Host smart-09be563b-604d-4700-b2a7-26fb2e8bed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204952228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2204952228
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.3588790931
Short name T1125
Test name
Test status
Simulation time 105895772 ps
CPU time 3.19 seconds
Started Jul 21 06:35:27 PM PDT 24
Finished Jul 21 06:35:33 PM PDT 24
Peak memory 241416 kb
Host smart-b3d5bc8c-eb2c-48b9-aebb-cc4ce8a93d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588790931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.3588790931
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2803897934
Short name T149
Test name
Test status
Simulation time 18665248628 ps
CPU time 44.48 seconds
Started Jul 21 06:35:26 PM PDT 24
Finished Jul 21 06:36:13 PM PDT 24
Peak memory 248108 kb
Host smart-bd04f552-f0e7-40e4-95a6-16a3405aefd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803897934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2803897934
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.1751617273
Short name T466
Test name
Test status
Simulation time 371455094 ps
CPU time 15.17 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 241740 kb
Host smart-e9820614-653a-4b4f-a843-148378288bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751617273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1751617273
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1573290044
Short name T899
Test name
Test status
Simulation time 1506577632 ps
CPU time 12.41 seconds
Started Jul 21 06:35:22 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 241544 kb
Host smart-094674c0-8df8-415f-90da-2ff347614d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573290044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1573290044
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2920898144
Short name T51
Test name
Test status
Simulation time 453584591 ps
CPU time 11.75 seconds
Started Jul 21 06:35:26 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 241328 kb
Host smart-6474b85e-e5d0-4fc2-8ec3-ca080483230f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920898144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2920898144
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1382799209
Short name T446
Test name
Test status
Simulation time 328472943 ps
CPU time 6.63 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 241584 kb
Host smart-090b95ce-05ba-4646-b54d-d0065128a849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382799209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1382799209
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.534150177
Short name T448
Test name
Test status
Simulation time 578033464 ps
CPU time 6.75 seconds
Started Jul 21 06:35:26 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 241312 kb
Host smart-110891cf-a10d-40c9-951d-bfee04c4fbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534150177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.534150177
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.2114034284
Short name T1132
Test name
Test status
Simulation time 18822620254 ps
CPU time 143.79 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 241668 kb
Host smart-e833dbd9-551a-49ae-ae1e-e92babe3cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114034284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2114034284
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.1601313776
Short name T951
Test name
Test status
Simulation time 237724573 ps
CPU time 1.95 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 240044 kb
Host smart-c25d2b6d-4c8e-435b-988d-6495a7d50100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601313776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1601313776
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.582465620
Short name T52
Test name
Test status
Simulation time 3332998011 ps
CPU time 36.87 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:36:04 PM PDT 24
Peak memory 248112 kb
Host smart-1b09aa30-2df1-406a-90cc-71dc3d93f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582465620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.582465620
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.192628150
Short name T211
Test name
Test status
Simulation time 669880836 ps
CPU time 20.4 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:35:47 PM PDT 24
Peak memory 241532 kb
Host smart-efb4c0c1-c02c-46b7-82bd-98e98cc24c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192628150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.192628150
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.1692086914
Short name T987
Test name
Test status
Simulation time 1485729880 ps
CPU time 34.54 seconds
Started Jul 21 06:35:27 PM PDT 24
Finished Jul 21 06:36:04 PM PDT 24
Peak memory 241640 kb
Host smart-b60a0d8b-5239-49d4-b621-e24edbdb6754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692086914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1692086914
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.669033150
Short name T639
Test name
Test status
Simulation time 321091385 ps
CPU time 4.07 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 241228 kb
Host smart-2cc450bc-9016-467d-af5d-5f4cdf46aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669033150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.669033150
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.4051771913
Short name T1171
Test name
Test status
Simulation time 3669564842 ps
CPU time 60.72 seconds
Started Jul 21 06:35:27 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 248020 kb
Host smart-8c9d2dbe-8b2d-4f81-83c7-a7506cf1be16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051771913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.4051771913
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3223575717
Short name T948
Test name
Test status
Simulation time 517299958 ps
CPU time 4.11 seconds
Started Jul 21 06:35:29 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 241256 kb
Host smart-0228ccdb-2636-480f-acec-9cc41da10989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223575717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3223575717
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3101806822
Short name T1135
Test name
Test status
Simulation time 419303949 ps
CPU time 4.93 seconds
Started Jul 21 06:35:28 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 241656 kb
Host smart-83fcf878-1f8a-459d-823f-dae088a44a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101806822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3101806822
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.233592199
Short name T422
Test name
Test status
Simulation time 702700950 ps
CPU time 10.38 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:35:34 PM PDT 24
Peak memory 241192 kb
Host smart-29613a90-948e-4e83-b1f1-22e70edbfdf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233592199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.233592199
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.2182127974
Short name T1051
Test name
Test status
Simulation time 2022843122 ps
CPU time 5.03 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:35:32 PM PDT 24
Peak memory 241568 kb
Host smart-1fd8c05d-e44a-4d04-8b84-cd7178d6b3bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182127974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2182127974
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1334804902
Short name T513
Test name
Test status
Simulation time 2625277562 ps
CPU time 6.7 seconds
Started Jul 21 06:35:29 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 241388 kb
Host smart-1b3001ab-308d-4273-9525-9b2e7a29fb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334804902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1334804902
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.4224921079
Short name T210
Test name
Test status
Simulation time 1730543174 ps
CPU time 40.19 seconds
Started Jul 21 06:35:25 PM PDT 24
Finished Jul 21 06:36:08 PM PDT 24
Peak memory 243072 kb
Host smart-8c1b31fb-9cb4-4235-8dbc-20c713337bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224921079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.4224921079
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3529646187
Short name T20
Test name
Test status
Simulation time 62928826576 ps
CPU time 1619.8 seconds
Started Jul 21 06:35:27 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 329756 kb
Host smart-a3304444-1e33-4bc8-b240-42d2ad53d72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529646187 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3529646187
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.1437904654
Short name T434
Test name
Test status
Simulation time 205546945 ps
CPU time 4.88 seconds
Started Jul 21 06:35:27 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 241316 kb
Host smart-b7006bdd-298d-40e2-88a0-ba466b628699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437904654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1437904654
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.874503237
Short name T566
Test name
Test status
Simulation time 44924844 ps
CPU time 1.64 seconds
Started Jul 21 06:35:33 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 239708 kb
Host smart-fe4341d2-197f-493c-8f5e-f4fcd6a9893d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874503237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.874503237
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.4170350133
Short name T472
Test name
Test status
Simulation time 1169316008 ps
CPU time 11.55 seconds
Started Jul 21 06:35:31 PM PDT 24
Finished Jul 21 06:35:44 PM PDT 24
Peak memory 241936 kb
Host smart-932162b8-6971-43ae-ada2-7ddbf1c147a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170350133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.4170350133
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1496082880
Short name T499
Test name
Test status
Simulation time 1156753090 ps
CPU time 18.34 seconds
Started Jul 21 06:35:28 PM PDT 24
Finished Jul 21 06:35:49 PM PDT 24
Peak memory 241116 kb
Host smart-bf2c8495-ced8-4a24-982c-8e26a9b2032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496082880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1496082880
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3705670019
Short name T577
Test name
Test status
Simulation time 1024480381 ps
CPU time 19.84 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 241680 kb
Host smart-8e3222ca-d2ee-4490-a8bc-778e5fb2095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705670019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3705670019
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.3014453494
Short name T1015
Test name
Test status
Simulation time 257247542 ps
CPU time 5.14 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:35:30 PM PDT 24
Peak memory 241712 kb
Host smart-c9646db7-a947-4c38-9170-c3b0747f4424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014453494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3014453494
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.4279528669
Short name T201
Test name
Test status
Simulation time 1842238191 ps
CPU time 33.15 seconds
Started Jul 21 06:35:31 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 245456 kb
Host smart-65ed48aa-35d5-4d72-b867-29648eae5575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279528669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.4279528669
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2317898025
Short name T407
Test name
Test status
Simulation time 3764948149 ps
CPU time 12.77 seconds
Started Jul 21 06:35:32 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 242304 kb
Host smart-a232c1b5-e068-44ed-a274-34d352a29b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317898025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2317898025
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3359137480
Short name T477
Test name
Test status
Simulation time 233595869 ps
CPU time 3.97 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:35:30 PM PDT 24
Peak memory 241276 kb
Host smart-43b6e662-64b3-48a3-9795-03eaffbf52cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359137480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3359137480
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1899981230
Short name T296
Test name
Test status
Simulation time 6688586321 ps
CPU time 13.14 seconds
Started Jul 21 06:35:23 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 241648 kb
Host smart-6ca6649c-dc48-4057-bc6a-1a916af85369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899981230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1899981230
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.508602094
Short name T115
Test name
Test status
Simulation time 266098055 ps
CPU time 9.21 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 241272 kb
Host smart-a9ce8a85-fd5d-40a0-a768-66918c2e8101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508602094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.508602094
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.577317915
Short name T895
Test name
Test status
Simulation time 323898344 ps
CPU time 9.35 seconds
Started Jul 21 06:35:24 PM PDT 24
Finished Jul 21 06:35:36 PM PDT 24
Peak memory 241324 kb
Host smart-fa6c7df3-320e-45e8-b08c-089c456be19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577317915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.577317915
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2858105500
Short name T103
Test name
Test status
Simulation time 14630099958 ps
CPU time 149.07 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 256180 kb
Host smart-1b41d145-ad88-42d9-850a-c1bed5d4dd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858105500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2858105500
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.636208753
Short name T1142
Test name
Test status
Simulation time 1931201983 ps
CPU time 38.15 seconds
Started Jul 21 06:35:29 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 248008 kb
Host smart-c205d56c-62dc-4a16-a670-1f5e6fe868d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636208753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.636208753
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.646290386
Short name T787
Test name
Test status
Simulation time 50432918 ps
CPU time 1.76 seconds
Started Jul 21 06:35:32 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 239632 kb
Host smart-fe1b39de-7f32-444e-b59d-6921f71f3355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646290386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.646290386
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3623267399
Short name T41
Test name
Test status
Simulation time 1649125498 ps
CPU time 10.35 seconds
Started Jul 21 06:35:29 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 241628 kb
Host smart-d25444b5-fb48-48ec-a4fe-8475572201fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623267399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3623267399
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2093894720
Short name T596
Test name
Test status
Simulation time 2474290013 ps
CPU time 8.62 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 241448 kb
Host smart-a63beea7-1c69-48e1-a000-42913f77d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093894720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2093894720
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.2323774568
Short name T608
Test name
Test status
Simulation time 5594128429 ps
CPU time 13.14 seconds
Started Jul 21 06:35:34 PM PDT 24
Finished Jul 21 06:35:48 PM PDT 24
Peak memory 241536 kb
Host smart-26d231bf-3ed5-4d45-86c7-750a208e8a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323774568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2323774568
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.4047739936
Short name T45
Test name
Test status
Simulation time 262961997 ps
CPU time 4.64 seconds
Started Jul 21 06:35:31 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 241432 kb
Host smart-ff4a7d6a-a790-4bab-bf65-25f12c612873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047739936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.4047739936
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.2046882464
Short name T1012
Test name
Test status
Simulation time 1851465735 ps
CPU time 27.27 seconds
Started Jul 21 06:35:32 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 243264 kb
Host smart-c6a44db9-82d3-4c49-991f-e4a1d0a6a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046882464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2046882464
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.2277463634
Short name T370
Test name
Test status
Simulation time 783979753 ps
CPU time 22.15 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:35:54 PM PDT 24
Peak memory 241956 kb
Host smart-f08f559f-ea07-4416-a270-6ec4426b37ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277463634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2277463634
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.4029862834
Short name T451
Test name
Test status
Simulation time 1796139237 ps
CPU time 16.63 seconds
Started Jul 21 06:35:29 PM PDT 24
Finished Jul 21 06:35:48 PM PDT 24
Peak memory 241672 kb
Host smart-fc4023a3-6e80-4b6d-a4d2-7a6b42cefd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029862834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.4029862834
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2841832587
Short name T982
Test name
Test status
Simulation time 1361857610 ps
CPU time 25.26 seconds
Started Jul 21 06:35:28 PM PDT 24
Finished Jul 21 06:35:56 PM PDT 24
Peak memory 241320 kb
Host smart-6136f7f7-a6c4-4f26-8f14-02b8d9482301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841832587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2841832587
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.857979647
Short name T907
Test name
Test status
Simulation time 520449697 ps
CPU time 4.51 seconds
Started Jul 21 06:35:31 PM PDT 24
Finished Jul 21 06:35:37 PM PDT 24
Peak memory 247976 kb
Host smart-269eabb7-2bf0-4c9d-865f-93d30c6f6e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857979647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.857979647
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.3366821606
Short name T481
Test name
Test status
Simulation time 350277527 ps
CPU time 6.59 seconds
Started Jul 21 06:35:32 PM PDT 24
Finished Jul 21 06:35:40 PM PDT 24
Peak memory 241320 kb
Host smart-055abb2c-8c22-4c2a-b637-078069c70942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366821606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3366821606
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.2775992638
Short name T101
Test name
Test status
Simulation time 916335736 ps
CPU time 30.58 seconds
Started Jul 21 06:35:34 PM PDT 24
Finished Jul 21 06:36:05 PM PDT 24
Peak memory 241516 kb
Host smart-2d89540c-fe60-4670-900d-1966992508c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775992638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.2775992638
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.855485371
Short name T1069
Test name
Test status
Simulation time 228786596149 ps
CPU time 1670.91 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 07:03:32 PM PDT 24
Peak memory 278056 kb
Host smart-b6548b38-2d37-4697-aa62-134b30e9250f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855485371 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.855485371
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.877619903
Short name T991
Test name
Test status
Simulation time 1740168333 ps
CPU time 8.61 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:35:48 PM PDT 24
Peak memory 241516 kb
Host smart-3b6d2ca7-05ff-41c5-9692-b6d92c769a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877619903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.877619903
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.3272210870
Short name T777
Test name
Test status
Simulation time 130133309 ps
CPU time 2.45 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:35:39 PM PDT 24
Peak memory 239620 kb
Host smart-85a9f014-0357-48fd-acd6-8c0ae02de844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272210870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3272210870
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.620815207
Short name T264
Test name
Test status
Simulation time 3885388473 ps
CPU time 21.29 seconds
Started Jul 21 06:35:32 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 241976 kb
Host smart-98e7365e-9045-4ce5-b981-e3d64269d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620815207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.620815207
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1794994291
Short name T733
Test name
Test status
Simulation time 1333317947 ps
CPU time 20.03 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:35:52 PM PDT 24
Peak memory 241424 kb
Host smart-a286ebd3-a2e2-4ba3-bc2b-9a3b6419cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794994291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1794994291
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1294396077
Short name T397
Test name
Test status
Simulation time 569050466 ps
CPU time 7.89 seconds
Started Jul 21 06:35:34 PM PDT 24
Finished Jul 21 06:35:42 PM PDT 24
Peak memory 241312 kb
Host smart-17d62a5e-b1b7-4ae2-8613-e7225c2dcbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294396077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1294396077
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1400840478
Short name T447
Test name
Test status
Simulation time 2509795661 ps
CPU time 4.95 seconds
Started Jul 21 06:35:31 PM PDT 24
Finished Jul 21 06:35:38 PM PDT 24
Peak memory 241404 kb
Host smart-4a1ee144-5116-4339-a190-823145543ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400840478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1400840478
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.1801460331
Short name T838
Test name
Test status
Simulation time 603992638 ps
CPU time 15.84 seconds
Started Jul 21 06:35:33 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 241532 kb
Host smart-0567aa8e-5739-4e52-8036-f99e5b4ab52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801460331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1801460331
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3630377399
Short name T6
Test name
Test status
Simulation time 17040045790 ps
CPU time 36.86 seconds
Started Jul 21 06:35:39 PM PDT 24
Finished Jul 21 06:36:18 PM PDT 24
Peak memory 242036 kb
Host smart-3f7fc356-5f43-4dc3-a068-5ded498e31fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630377399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3630377399
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3200851777
Short name T1066
Test name
Test status
Simulation time 235343782 ps
CPU time 4.74 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:35:42 PM PDT 24
Peak memory 241152 kb
Host smart-b262ee73-c86e-4026-8e52-6901f77ec0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200851777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3200851777
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.3852292909
Short name T931
Test name
Test status
Simulation time 1286736651 ps
CPU time 22.12 seconds
Started Jul 21 06:35:29 PM PDT 24
Finished Jul 21 06:35:54 PM PDT 24
Peak memory 247952 kb
Host smart-34dd1ead-3a62-44a0-a684-aaae2d3ca65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852292909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3852292909
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2878655605
Short name T1072
Test name
Test status
Simulation time 281393862 ps
CPU time 10.14 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:35:47 PM PDT 24
Peak memory 241312 kb
Host smart-98ada698-d038-4759-b576-530e601c8e4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878655605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2878655605
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.2847626641
Short name T923
Test name
Test status
Simulation time 467720320 ps
CPU time 8.93 seconds
Started Jul 21 06:35:30 PM PDT 24
Finished Jul 21 06:35:41 PM PDT 24
Peak memory 241500 kb
Host smart-81203320-6d62-4efa-9870-5f07616d6d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847626641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.2847626641
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.2428851440
Short name T867
Test name
Test status
Simulation time 6907322075 ps
CPU time 53.15 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:36:33 PM PDT 24
Peak memory 244192 kb
Host smart-f91a94ff-1a1c-4d97-b642-3071bb4ea9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428851440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.2428851440
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.2898290893
Short name T578
Test name
Test status
Simulation time 5223114506 ps
CPU time 31.22 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:36:10 PM PDT 24
Peak memory 241548 kb
Host smart-905efb26-c78f-458f-a89b-fc04615fbea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898290893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2898290893
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1055707229
Short name T13
Test name
Test status
Simulation time 300636922 ps
CPU time 2.94 seconds
Started Jul 21 06:35:41 PM PDT 24
Finished Jul 21 06:35:45 PM PDT 24
Peak memory 239856 kb
Host smart-d6045831-8f4a-43a4-a694-4da1b6f8e673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055707229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1055707229
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.2543098459
Short name T70
Test name
Test status
Simulation time 814118888 ps
CPU time 7.33 seconds
Started Jul 21 06:35:44 PM PDT 24
Finished Jul 21 06:35:53 PM PDT 24
Peak memory 241564 kb
Host smart-a55dc309-d877-4364-81cd-c96f6ebbed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543098459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2543098459
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2964140267
Short name T227
Test name
Test status
Simulation time 10575871758 ps
CPU time 30.69 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241316 kb
Host smart-066898fb-bee1-4e50-9774-2770e8a41a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964140267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2964140267
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2791303327
Short name T864
Test name
Test status
Simulation time 1438200969 ps
CPU time 12.35 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:35:49 PM PDT 24
Peak memory 247952 kb
Host smart-5d946d8b-24bb-437b-b798-cb647675a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791303327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2791303327
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.732320559
Short name T1077
Test name
Test status
Simulation time 2100120067 ps
CPU time 6.55 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:35:45 PM PDT 24
Peak memory 241464 kb
Host smart-c2674e8b-8e45-45a1-a413-678c58144d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732320559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.732320559
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1177004873
Short name T199
Test name
Test status
Simulation time 5634823003 ps
CPU time 13.86 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 241400 kb
Host smart-550ddab8-09f1-4b5d-a0c8-5f874e0aa32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177004873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1177004873
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.968823753
Short name T869
Test name
Test status
Simulation time 584337735 ps
CPU time 5.13 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 241244 kb
Host smart-ff23bbd4-95f0-4f7b-a688-373208c41bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968823753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.968823753
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3416306144
Short name T637
Test name
Test status
Simulation time 2181324029 ps
CPU time 18.56 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 247780 kb
Host smart-82d40023-b0ca-45ec-b7fc-2a767676df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416306144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3416306144
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.1828478719
Short name T1017
Test name
Test status
Simulation time 2169931315 ps
CPU time 19.78 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 241864 kb
Host smart-12be85bf-39c9-4b85-a054-2d632b89684b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828478719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1828478719
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.886578098
Short name T410
Test name
Test status
Simulation time 139003738 ps
CPU time 4.78 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 241772 kb
Host smart-949c037d-0d55-4303-948d-d3efa8622d04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886578098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.886578098
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.4110188561
Short name T638
Test name
Test status
Simulation time 174903613 ps
CPU time 4.37 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:45 PM PDT 24
Peak memory 241404 kb
Host smart-d1b1c8f1-c174-4f56-bc36-42f588f34d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110188561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.4110188561
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.1379070016
Short name T848
Test name
Test status
Simulation time 32351139229 ps
CPU time 210.84 seconds
Started Jul 21 06:35:39 PM PDT 24
Finished Jul 21 06:39:12 PM PDT 24
Peak memory 264476 kb
Host smart-467465e9-4ee8-4075-8992-22203e398ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379070016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.1379070016
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2938185271
Short name T721
Test name
Test status
Simulation time 447156264 ps
CPU time 5.85 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 241872 kb
Host smart-d6ecaebd-8500-4bc3-ac84-ecaac79a4a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938185271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2938185271
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.1941004733
Short name T776
Test name
Test status
Simulation time 669716737 ps
CPU time 2.02 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:42 PM PDT 24
Peak memory 239900 kb
Host smart-73b71bbc-a8c0-4f43-b67f-62972951486a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941004733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1941004733
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.4016824307
Short name T1106
Test name
Test status
Simulation time 466033720 ps
CPU time 12.86 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 242328 kb
Host smart-6ba84c06-5e55-472f-baba-e63546d46ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016824307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4016824307
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.2348485197
Short name T900
Test name
Test status
Simulation time 7539173208 ps
CPU time 12.92 seconds
Started Jul 21 06:35:39 PM PDT 24
Finished Jul 21 06:35:54 PM PDT 24
Peak memory 241536 kb
Host smart-33611802-b2aa-4f3b-8b22-f2340bc81f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348485197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2348485197
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2370946190
Short name T226
Test name
Test status
Simulation time 4639266043 ps
CPU time 26.46 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 242976 kb
Host smart-e791ac1f-3200-4bd1-b197-bfe086a1fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370946190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2370946190
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3374757961
Short name T985
Test name
Test status
Simulation time 214455003 ps
CPU time 3.9 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:44 PM PDT 24
Peak memory 241708 kb
Host smart-15d196c0-2005-4900-a201-db0a0d51b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374757961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3374757961
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.1304744218
Short name T515
Test name
Test status
Simulation time 3302776256 ps
CPU time 16.56 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:57 PM PDT 24
Peak memory 241552 kb
Host smart-1c5a37fa-c521-46e9-9d79-bd22f35bb5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304744218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1304744218
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.4087022741
Short name T549
Test name
Test status
Simulation time 1056661379 ps
CPU time 7.77 seconds
Started Jul 21 06:35:41 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 241124 kb
Host smart-56bac5a2-26a4-4655-bcad-5f0630bd72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087022741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4087022741
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.3249666228
Short name T826
Test name
Test status
Simulation time 239048139 ps
CPU time 7.93 seconds
Started Jul 21 06:35:39 PM PDT 24
Finished Jul 21 06:35:49 PM PDT 24
Peak memory 241408 kb
Host smart-2eeef71f-439c-4208-afc4-8b6a316c03e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249666228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3249666228
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.3028161142
Short name T356
Test name
Test status
Simulation time 1005402492 ps
CPU time 8.11 seconds
Started Jul 21 06:35:40 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 241612 kb
Host smart-baa3bf55-5b17-4d9a-811a-356534b93bd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028161142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3028161142
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2270250939
Short name T403
Test name
Test status
Simulation time 1764635124 ps
CPU time 4.86 seconds
Started Jul 21 06:35:39 PM PDT 24
Finished Jul 21 06:35:46 PM PDT 24
Peak memory 241576 kb
Host smart-d120247f-f51f-4add-9082-9bba2ca1a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270250939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2270250939
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3509871168
Short name T452
Test name
Test status
Simulation time 28207151227 ps
CPU time 97.46 seconds
Started Jul 21 06:35:36 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 257072 kb
Host smart-89d299f8-089a-4188-9fe3-2f8f4b353c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509871168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3509871168
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.4009553773
Short name T319
Test name
Test status
Simulation time 331129312399 ps
CPU time 1972.37 seconds
Started Jul 21 06:35:44 PM PDT 24
Finished Jul 21 07:08:38 PM PDT 24
Peak memory 642904 kb
Host smart-1f2a070e-72ab-4c08-96de-8c03bcea4f6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009553773 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.4009553773
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2627780138
Short name T528
Test name
Test status
Simulation time 3838155891 ps
CPU time 19.25 seconds
Started Jul 21 06:35:45 PM PDT 24
Finished Jul 21 06:36:05 PM PDT 24
Peak memory 241872 kb
Host smart-ee8ada42-9096-4140-9b16-bf46966c8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627780138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2627780138
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.3728567904
Short name T570
Test name
Test status
Simulation time 176280765 ps
CPU time 1.9 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:35:57 PM PDT 24
Peak memory 239672 kb
Host smart-ff3e7a30-0a06-4ad6-9563-d282e3329973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728567904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3728567904
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3189745857
Short name T32
Test name
Test status
Simulation time 30356804773 ps
CPU time 121.95 seconds
Started Jul 21 06:35:41 PM PDT 24
Finished Jul 21 06:37:44 PM PDT 24
Peak memory 242892 kb
Host smart-4512381e-3bd4-4601-a274-401c5762eb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189745857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3189745857
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.4274368540
Short name T751
Test name
Test status
Simulation time 1276345857 ps
CPU time 34.22 seconds
Started Jul 21 06:35:44 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 245616 kb
Host smart-dcbd29b4-aa47-4998-9b2d-9862fe1fd222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274368540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.4274368540
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2260856314
Short name T108
Test name
Test status
Simulation time 5680626004 ps
CPU time 62.46 seconds
Started Jul 21 06:35:45 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241484 kb
Host smart-c5170860-d2d6-4875-8cba-110e68ca0c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260856314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2260856314
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.702969592
Short name T606
Test name
Test status
Simulation time 450380904 ps
CPU time 4.89 seconds
Started Jul 21 06:35:38 PM PDT 24
Finished Jul 21 06:35:45 PM PDT 24
Peak memory 241436 kb
Host smart-0bb3ce59-53c1-4bf6-9cf0-502deab32a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702969592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.702969592
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3284102629
Short name T1070
Test name
Test status
Simulation time 15060862851 ps
CPU time 36.06 seconds
Started Jul 21 06:35:50 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 243824 kb
Host smart-af639a6b-52e4-4dfd-a221-974adaf4d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284102629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3284102629
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1390402104
Short name T164
Test name
Test status
Simulation time 3733670530 ps
CPU time 25 seconds
Started Jul 21 06:35:43 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241616 kb
Host smart-868a621b-44b0-468f-b829-e6b7d677b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390402104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1390402104
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2910878409
Short name T502
Test name
Test status
Simulation time 194738299 ps
CPU time 6.81 seconds
Started Jul 21 06:35:42 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 241520 kb
Host smart-37a97452-5ca1-4981-8ae3-49075b3cfc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910878409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2910878409
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3886062151
Short name T425
Test name
Test status
Simulation time 572387395 ps
CPU time 16.53 seconds
Started Jul 21 06:35:43 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 241152 kb
Host smart-f06fe763-8a31-46e8-be94-dd7d9872e5b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886062151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3886062151
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.4113223212
Short name T1178
Test name
Test status
Simulation time 990800434 ps
CPU time 10.09 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:03 PM PDT 24
Peak memory 241448 kb
Host smart-0beb9a15-050e-45ad-8327-f4bc60fddf28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113223212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.4113223212
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1143485411
Short name T690
Test name
Test status
Simulation time 832816893 ps
CPU time 11.14 seconds
Started Jul 21 06:35:37 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 241352 kb
Host smart-f21724ba-d2f2-4b3c-ad57-fb54fc393e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143485411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1143485411
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.323284680
Short name T1023
Test name
Test status
Simulation time 2730978629 ps
CPU time 15.9 seconds
Started Jul 21 06:35:43 PM PDT 24
Finished Jul 21 06:36:00 PM PDT 24
Peak memory 242096 kb
Host smart-269de586-1b5a-478d-8e22-6f3c0aee4a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323284680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.
323284680
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.2229013074
Short name T334
Test name
Test status
Simulation time 35219176438 ps
CPU time 1025.33 seconds
Started Jul 21 06:35:42 PM PDT 24
Finished Jul 21 06:52:49 PM PDT 24
Peak memory 323908 kb
Host smart-84a8871b-0624-471d-9605-2790e9ec248a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229013074 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.2229013074
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3852289585
Short name T1014
Test name
Test status
Simulation time 2255700818 ps
CPU time 26.62 seconds
Started Jul 21 06:35:43 PM PDT 24
Finished Jul 21 06:36:12 PM PDT 24
Peak memory 241472 kb
Host smart-8796dd9b-e098-43a6-8a2a-f2ad768560fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852289585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3852289585
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.2504462147
Short name T401
Test name
Test status
Simulation time 43257825 ps
CPU time 1.61 seconds
Started Jul 21 06:35:48 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 239692 kb
Host smart-901eca8e-acb2-4c66-9668-a87b713a9f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504462147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2504462147
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3391462595
Short name T138
Test name
Test status
Simulation time 1585921084 ps
CPU time 35.24 seconds
Started Jul 21 06:35:42 PM PDT 24
Finished Jul 21 06:36:19 PM PDT 24
Peak memory 246456 kb
Host smart-b9127887-5c65-49ca-8c0a-476820ba16b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391462595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3391462595
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1275557322
Short name T903
Test name
Test status
Simulation time 1619077108 ps
CPU time 29.42 seconds
Started Jul 21 06:35:42 PM PDT 24
Finished Jul 21 06:36:13 PM PDT 24
Peak memory 242456 kb
Host smart-166b10a3-d7a4-441b-a1b7-d2541aaf4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275557322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1275557322
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.1634668679
Short name T293
Test name
Test status
Simulation time 5101983810 ps
CPU time 21.92 seconds
Started Jul 21 06:35:41 PM PDT 24
Finished Jul 21 06:36:04 PM PDT 24
Peak memory 241684 kb
Host smart-2e932a71-72b5-44e5-ad1b-80ed474e84c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634668679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1634668679
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1006340213
Short name T423
Test name
Test status
Simulation time 632350899 ps
CPU time 5.07 seconds
Started Jul 21 06:35:51 PM PDT 24
Finished Jul 21 06:35:57 PM PDT 24
Peak memory 241452 kb
Host smart-39fd0d02-0742-4cc8-8235-1725e135f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006340213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1006340213
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2564517024
Short name T689
Test name
Test status
Simulation time 5958820501 ps
CPU time 14.84 seconds
Started Jul 21 06:35:44 PM PDT 24
Finished Jul 21 06:36:00 PM PDT 24
Peak memory 248100 kb
Host smart-346080ba-05f5-4be1-8b8f-2599122fcb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564517024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2564517024
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.1268987673
Short name T536
Test name
Test status
Simulation time 145405629 ps
CPU time 3.97 seconds
Started Jul 21 06:35:41 PM PDT 24
Finished Jul 21 06:35:47 PM PDT 24
Peak memory 241436 kb
Host smart-b2028986-2167-4a6f-a4f8-0c16bc70aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268987673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1268987673
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1059442514
Short name T524
Test name
Test status
Simulation time 788291570 ps
CPU time 6.44 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:00 PM PDT 24
Peak memory 241324 kb
Host smart-f72009c2-87e8-4f34-8808-9faee5f7898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059442514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1059442514
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.3036269488
Short name T1084
Test name
Test status
Simulation time 3938820804 ps
CPU time 8.18 seconds
Started Jul 21 06:35:49 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 241352 kb
Host smart-42bc0dcc-bde0-4f42-bdb6-cb2ca2c61412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036269488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3036269488
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.2911036233
Short name T666
Test name
Test status
Simulation time 494257534 ps
CPU time 7.55 seconds
Started Jul 21 06:35:43 PM PDT 24
Finished Jul 21 06:35:52 PM PDT 24
Peak memory 241328 kb
Host smart-c8e1830f-4dcd-4056-9429-7c5ee01436bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911036233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2911036233
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3208912375
Short name T530
Test name
Test status
Simulation time 80274432451 ps
CPU time 139.66 seconds
Started Jul 21 06:35:44 PM PDT 24
Finished Jul 21 06:38:05 PM PDT 24
Peak memory 256172 kb
Host smart-7e4f0438-e7e4-4036-bd37-549b12987383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208912375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3208912375
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.703725870
Short name T97
Test name
Test status
Simulation time 1015112260 ps
CPU time 10.57 seconds
Started Jul 21 06:35:43 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 241456 kb
Host smart-4ee60e3e-633b-4e35-b4ae-d7487382a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703725870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.703725870
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.1120987449
Short name T769
Test name
Test status
Simulation time 212427209 ps
CPU time 1.84 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 239868 kb
Host smart-922c5734-886e-4b32-9da4-ba28534f36f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120987449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1120987449
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.2579626225
Short name T511
Test name
Test status
Simulation time 594547182 ps
CPU time 12.49 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 241752 kb
Host smart-076df5d3-7178-410c-9a76-3d231ec2a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579626225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2579626225
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.913171404
Short name T990
Test name
Test status
Simulation time 15248402916 ps
CPU time 28.34 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 244120 kb
Host smart-e2821fed-ce1a-42b4-af60-51bad10d98e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913171404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.913171404
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.1853221938
Short name T643
Test name
Test status
Simulation time 17704944938 ps
CPU time 58.01 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 248128 kb
Host smart-a46e5c7a-eb9f-4c7b-a23a-87d1bdfb3092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853221938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1853221938
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.3876481907
Short name T610
Test name
Test status
Simulation time 575685893 ps
CPU time 4.25 seconds
Started Jul 21 06:34:14 PM PDT 24
Finished Jul 21 06:34:22 PM PDT 24
Peak memory 241292 kb
Host smart-d8e94c1e-bdac-4d94-a3d7-ed4810737aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876481907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3876481907
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3009573196
Short name T1008
Test name
Test status
Simulation time 155207336 ps
CPU time 3.68 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 241320 kb
Host smart-48656af2-c47b-4fe5-8e45-75ffe5bb2b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009573196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3009573196
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.572201316
Short name T489
Test name
Test status
Simulation time 2984171112 ps
CPU time 44.29 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 243408 kb
Host smart-2bfe23d5-61ad-430d-994b-a4840caafcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572201316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.572201316
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.2809359702
Short name T942
Test name
Test status
Simulation time 19804363090 ps
CPU time 46.02 seconds
Started Jul 21 06:34:13 PM PDT 24
Finished Jul 21 06:35:03 PM PDT 24
Peak memory 242280 kb
Host smart-2bdbc473-0cf1-4431-b793-ab474cc54d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809359702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.2809359702
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.4216188784
Short name T433
Test name
Test status
Simulation time 203025026 ps
CPU time 11.09 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 241424 kb
Host smart-2bd769e7-0b8f-49b4-b0df-9088feff4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216188784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4216188784
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.3860456397
Short name T482
Test name
Test status
Simulation time 9813783805 ps
CPU time 19.2 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:35 PM PDT 24
Peak memory 241228 kb
Host smart-fff3684b-e4b8-4461-b1ce-3d8285434ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860456397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.3860456397
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3912528724
Short name T24
Test name
Test status
Simulation time 22121544461 ps
CPU time 189.21 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:37:24 PM PDT 24
Peak memory 269872 kb
Host smart-75b3faf3-5d0f-4555-8b7c-dbaa3d28fa2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912528724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3912528724
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.3760717310
Short name T1139
Test name
Test status
Simulation time 242072669 ps
CPU time 6.19 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:22 PM PDT 24
Peak memory 247768 kb
Host smart-798c981c-fa39-468e-902a-2ea77a2bc784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760717310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3760717310
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.1847868460
Short name T885
Test name
Test status
Simulation time 8561647504 ps
CPU time 29.23 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241864 kb
Host smart-e44c2193-e165-4b47-a63c-f79fd3c76d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847868460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
1847868460
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.2562968852
Short name T512
Test name
Test status
Simulation time 27115558776 ps
CPU time 22.63 seconds
Started Jul 21 06:34:13 PM PDT 24
Finished Jul 21 06:34:39 PM PDT 24
Peak memory 242052 kb
Host smart-b5b246a9-6f51-4b30-ae09-25dd2b7cb457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562968852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2562968852
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2759711729
Short name T563
Test name
Test status
Simulation time 891056013 ps
CPU time 2.73 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 239848 kb
Host smart-d4530733-b391-49c9-8d88-4c7cae4f7cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759711729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2759711729
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.540588983
Short name T813
Test name
Test status
Simulation time 726276220 ps
CPU time 14.46 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:07 PM PDT 24
Peak memory 248076 kb
Host smart-657dae2b-76b4-460b-840f-ea46f251120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540588983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.540588983
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.778683765
Short name T804
Test name
Test status
Simulation time 946229883 ps
CPU time 21.52 seconds
Started Jul 21 06:35:51 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241140 kb
Host smart-dadfcb35-e370-418d-8193-ff82eb8a5bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778683765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.778683765
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.2017500727
Short name T1118
Test name
Test status
Simulation time 2389288071 ps
CPU time 16.2 seconds
Started Jul 21 06:35:50 PM PDT 24
Finished Jul 21 06:36:07 PM PDT 24
Peak memory 242228 kb
Host smart-255f9581-86e5-4078-b367-d738656084d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017500727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2017500727
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.632049055
Short name T224
Test name
Test status
Simulation time 317932666 ps
CPU time 4.18 seconds
Started Jul 21 06:35:41 PM PDT 24
Finished Jul 21 06:35:47 PM PDT 24
Peak memory 241216 kb
Host smart-ff6f6554-e986-44da-ae10-09f5a24e4716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632049055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.632049055
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.2619617477
Short name T1109
Test name
Test status
Simulation time 5844847760 ps
CPU time 16.78 seconds
Started Jul 21 06:35:50 PM PDT 24
Finished Jul 21 06:36:08 PM PDT 24
Peak memory 248084 kb
Host smart-73243718-d6ed-4afe-99f0-6603c699ab17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619617477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2619617477
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1017887695
Short name T937
Test name
Test status
Simulation time 502928654 ps
CPU time 4.79 seconds
Started Jul 21 06:35:45 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 241272 kb
Host smart-1455e81a-2b73-475d-9b7d-5c4dc0676d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017887695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1017887695
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1917391966
Short name T109
Test name
Test status
Simulation time 613516582 ps
CPU time 9.29 seconds
Started Jul 21 06:35:42 PM PDT 24
Finished Jul 21 06:35:53 PM PDT 24
Peak memory 241172 kb
Host smart-bbe0b768-b5d8-4cb7-b068-ead2fbcec288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917391966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1917391966
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1537103867
Short name T705
Test name
Test status
Simulation time 99685848 ps
CPU time 4.13 seconds
Started Jul 21 06:35:49 PM PDT 24
Finished Jul 21 06:35:54 PM PDT 24
Peak memory 241148 kb
Host smart-ecde21a9-7c3a-4fd8-b771-84cf15642a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537103867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1537103867
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.2296381387
Short name T627
Test name
Test status
Simulation time 539327969 ps
CPU time 6.44 seconds
Started Jul 21 06:35:49 PM PDT 24
Finished Jul 21 06:35:56 PM PDT 24
Peak memory 241628 kb
Host smart-6d6abe54-a297-44ba-82a5-fba9872d5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296381387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2296381387
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2715904517
Short name T954
Test name
Test status
Simulation time 3967224794 ps
CPU time 57.06 seconds
Started Jul 21 06:35:50 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 244848 kb
Host smart-7d141451-3677-4657-a503-1695d50629bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715904517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2715904517
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.3965270667
Short name T30
Test name
Test status
Simulation time 1473849107 ps
CPU time 26.34 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:24 PM PDT 24
Peak memory 242076 kb
Host smart-4258e075-f7c3-40c1-9d29-6d6f9c03d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965270667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3965270667
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3256966241
Short name T965
Test name
Test status
Simulation time 56141269 ps
CPU time 1.72 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:00 PM PDT 24
Peak memory 239648 kb
Host smart-9cc5a90a-a369-4a09-af37-9f4529c16412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256966241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3256966241
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.2919113005
Short name T1006
Test name
Test status
Simulation time 829243037 ps
CPU time 6.21 seconds
Started Jul 21 06:35:55 PM PDT 24
Finished Jul 21 06:36:03 PM PDT 24
Peak memory 248028 kb
Host smart-3ee8e598-5787-44a4-870a-eee53d34528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919113005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2919113005
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2564034121
Short name T1082
Test name
Test status
Simulation time 5056697063 ps
CPU time 35.35 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 243344 kb
Host smart-068e2dbb-4214-43e2-b27d-1d8bd7780bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564034121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2564034121
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.3502257850
Short name T157
Test name
Test status
Simulation time 543838745 ps
CPU time 6.07 seconds
Started Jul 21 06:35:51 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 241644 kb
Host smart-02fc29bd-0d42-4c02-b2e2-fcba5032db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502257850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3502257850
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.4261939390
Short name T1021
Test name
Test status
Simulation time 2450417710 ps
CPU time 8.27 seconds
Started Jul 21 06:35:59 PM PDT 24
Finished Jul 21 06:36:08 PM PDT 24
Peak memory 241768 kb
Host smart-4b1755c1-2419-4e95-a574-a1393a904bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261939390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.4261939390
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.3831432209
Short name T535
Test name
Test status
Simulation time 692894243 ps
CPU time 23.95 seconds
Started Jul 21 06:35:59 PM PDT 24
Finished Jul 21 06:36:25 PM PDT 24
Peak memory 243344 kb
Host smart-9b19734f-0441-4737-900f-6df1086e1dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831432209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3831432209
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.98827983
Short name T815
Test name
Test status
Simulation time 16581197757 ps
CPU time 37.05 seconds
Started Jul 21 06:35:55 PM PDT 24
Finished Jul 21 06:36:34 PM PDT 24
Peak memory 242696 kb
Host smart-de0a7225-7c95-45bb-aa5e-0ff8d280da72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98827983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.98827983
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.1559531572
Short name T1181
Test name
Test status
Simulation time 1361445879 ps
CPU time 22.25 seconds
Started Jul 21 06:35:57 PM PDT 24
Finished Jul 21 06:36:21 PM PDT 24
Peak memory 241268 kb
Host smart-bf6b747c-f3bd-466a-bb96-3ddd0a50c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559531572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1559531572
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.4294096404
Short name T793
Test name
Test status
Simulation time 13697771342 ps
CPU time 32.22 seconds
Started Jul 21 06:35:59 PM PDT 24
Finished Jul 21 06:36:33 PM PDT 24
Peak memory 248036 kb
Host smart-38aa2077-f92c-4bb8-bd9a-bbca8eede246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294096404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.4294096404
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.2260769454
Short name T291
Test name
Test status
Simulation time 506781385 ps
CPU time 4.69 seconds
Started Jul 21 06:35:50 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 241624 kb
Host smart-40e79138-a11e-485d-b060-c1087aed5505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260769454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2260769454
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.763874930
Short name T461
Test name
Test status
Simulation time 504951148 ps
CPU time 6.02 seconds
Started Jul 21 06:36:00 PM PDT 24
Finished Jul 21 06:36:08 PM PDT 24
Peak memory 241412 kb
Host smart-29711037-2f8f-4997-b07e-c127e733335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763874930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.763874930
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.4044052844
Short name T943
Test name
Test status
Simulation time 13417993261 ps
CPU time 134.58 seconds
Started Jul 21 06:35:55 PM PDT 24
Finished Jul 21 06:38:12 PM PDT 24
Peak memory 248492 kb
Host smart-5d16610b-4930-434f-9d27-4eeab287356a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044052844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.4044052844
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2936196234
Short name T279
Test name
Test status
Simulation time 251374041627 ps
CPU time 2795.34 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 07:22:34 PM PDT 24
Peak memory 282128 kb
Host smart-23f7ecfd-6f51-407e-8ab6-882b98bce4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936196234 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2936196234
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.3598992088
Short name T555
Test name
Test status
Simulation time 900056256 ps
CPU time 20.74 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 247940 kb
Host smart-db903843-7ce6-44b8-85e5-5a472e300805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598992088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3598992088
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2939226366
Short name T245
Test name
Test status
Simulation time 48292036 ps
CPU time 1.73 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 239592 kb
Host smart-cf6ecab1-e8f7-4eb0-ae50-024e54c90b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939226366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2939226366
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.2255507467
Short name T783
Test name
Test status
Simulation time 902813986 ps
CPU time 31.56 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 242036 kb
Host smart-598ea0b5-c2e3-4d32-8e12-5fe8984a7da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255507467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2255507467
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3909637115
Short name T598
Test name
Test status
Simulation time 4249492236 ps
CPU time 40.37 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 250084 kb
Host smart-cda2cb1d-7a9e-4b40-bd3f-10bc53694732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909637115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3909637115
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3180522590
Short name T408
Test name
Test status
Simulation time 2676712917 ps
CPU time 20.27 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:18 PM PDT 24
Peak memory 241732 kb
Host smart-447bc79e-c202-4aee-b2d8-640077ccb1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180522590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3180522590
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2591721226
Short name T217
Test name
Test status
Simulation time 147565348 ps
CPU time 3.8 seconds
Started Jul 21 06:35:50 PM PDT 24
Finished Jul 21 06:35:55 PM PDT 24
Peak memory 241464 kb
Host smart-a7f18cc1-4a14-4072-9ec2-affd2c0ad43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591721226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2591721226
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.2857202053
Short name T148
Test name
Test status
Simulation time 2686622797 ps
CPU time 19.21 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:15 PM PDT 24
Peak memory 244860 kb
Host smart-ea011411-68cf-4004-9452-e917bb8cab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857202053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2857202053
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.4078946930
Short name T717
Test name
Test status
Simulation time 491046702 ps
CPU time 6.81 seconds
Started Jul 21 06:35:57 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 241436 kb
Host smart-35c6bed0-3eff-4d5c-8d71-07f84dde21fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078946930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.4078946930
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.2548858902
Short name T368
Test name
Test status
Simulation time 331770649 ps
CPU time 7.9 seconds
Started Jul 21 06:35:51 PM PDT 24
Finished Jul 21 06:36:00 PM PDT 24
Peak memory 241220 kb
Host smart-face701f-282c-4f6c-8b41-d033e2151b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548858902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2548858902
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.770057913
Short name T1089
Test name
Test status
Simulation time 9612833158 ps
CPU time 22.04 seconds
Started Jul 21 06:35:55 PM PDT 24
Finished Jul 21 06:36:19 PM PDT 24
Peak memory 241420 kb
Host smart-9212c544-f4b4-4721-a38f-e5a895c9496b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770057913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.770057913
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3547069810
Short name T160
Test name
Test status
Simulation time 622767541 ps
CPU time 6.46 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:36:00 PM PDT 24
Peak memory 241284 kb
Host smart-ed99a288-5b76-4343-8a98-a6db76f61338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547069810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3547069810
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.3414738228
Short name T184
Test name
Test status
Simulation time 161261186 ps
CPU time 5.01 seconds
Started Jul 21 06:35:51 PM PDT 24
Finished Jul 21 06:35:57 PM PDT 24
Peak memory 241328 kb
Host smart-0be19111-551f-47c4-887c-b71ab7d56110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414738228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3414738228
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.90616756
Short name T235
Test name
Test status
Simulation time 4004954648 ps
CPU time 24.09 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 243444 kb
Host smart-e3514164-691e-478b-ae28-cd3cd45307f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90616756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.90616756
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2341053401
Short name T243
Test name
Test status
Simulation time 19593002769 ps
CPU time 453.19 seconds
Started Jul 21 06:36:00 PM PDT 24
Finished Jul 21 06:43:34 PM PDT 24
Peak memory 270108 kb
Host smart-dcb2067b-a26f-42bd-843a-ce634b3b86ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341053401 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2341053401
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.753082667
Short name T123
Test name
Test status
Simulation time 12254329244 ps
CPU time 40.5 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:34 PM PDT 24
Peak memory 242224 kb
Host smart-6709df0a-140b-4809-98c9-ec06d64c39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753082667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.753082667
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.532065565
Short name T1064
Test name
Test status
Simulation time 79314646 ps
CPU time 1.89 seconds
Started Jul 21 06:35:55 PM PDT 24
Finished Jul 21 06:35:59 PM PDT 24
Peak memory 239596 kb
Host smart-5c4deb23-cae8-402f-8c71-4b2a75c861e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532065565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.532065565
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.625207349
Short name T839
Test name
Test status
Simulation time 2856849783 ps
CPU time 34.84 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 243600 kb
Host smart-c4fcfc45-ab58-4fc0-a77e-9133e9b27d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625207349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.625207349
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.85673883
Short name T415
Test name
Test status
Simulation time 3055156765 ps
CPU time 37.94 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:36 PM PDT 24
Peak memory 241596 kb
Host smart-6cc06df2-a448-4c8b-8025-b32dc4d52db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85673883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.85673883
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.1331881830
Short name T398
Test name
Test status
Simulation time 974930725 ps
CPU time 25.26 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 241688 kb
Host smart-fa40606f-b330-4a75-9dc3-70af90a32bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331881830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1331881830
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1079113171
Short name T1049
Test name
Test status
Simulation time 253985430 ps
CPU time 3.66 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 241328 kb
Host smart-74713bcf-1280-488c-8686-5c9ab617b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079113171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1079113171
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2020288723
Short name T198
Test name
Test status
Simulation time 1696646702 ps
CPU time 26.92 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 248064 kb
Host smart-8b1c4614-ad9e-4788-8367-13e497bb9961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020288723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2020288723
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2329089783
Short name T996
Test name
Test status
Simulation time 1889082470 ps
CPU time 20.57 seconds
Started Jul 21 06:35:59 PM PDT 24
Finished Jul 21 06:36:21 PM PDT 24
Peak memory 241664 kb
Host smart-b558afe9-d324-401e-a811-93d3fc6a59fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329089783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2329089783
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1851009880
Short name T191
Test name
Test status
Simulation time 326043850 ps
CPU time 7.2 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:02 PM PDT 24
Peak memory 241260 kb
Host smart-d38532da-13b3-45e9-b9b6-d8b01f6898c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851009880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1851009880
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2540049880
Short name T688
Test name
Test status
Simulation time 3360481996 ps
CPU time 13.25 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:11 PM PDT 24
Peak memory 241460 kb
Host smart-7b0a744b-4144-4205-8827-03e0af311f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540049880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2540049880
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1398722315
Short name T749
Test name
Test status
Simulation time 934845217 ps
CPU time 7.31 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 241380 kb
Host smart-046de0bc-39fe-414d-b144-87ca3d28b494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398722315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1398722315
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.1258917803
Short name T266
Test name
Test status
Simulation time 872263819 ps
CPU time 12.88 seconds
Started Jul 21 06:36:00 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241352 kb
Host smart-ffb9a10e-4d64-4dd6-a5ef-55180274e187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258917803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1258917803
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2130461782
Short name T420
Test name
Test status
Simulation time 74916377761 ps
CPU time 112.56 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:37:50 PM PDT 24
Peak memory 249308 kb
Host smart-8071401c-e919-4cf4-ac29-ad4a9d38d0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130461782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2130461782
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2882563738
Short name T297
Test name
Test status
Simulation time 140897164315 ps
CPU time 916.66 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:51:12 PM PDT 24
Peak memory 374124 kb
Host smart-599daac0-c43c-4cec-9e90-a33a1a5ca83e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882563738 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2882563738
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.3799421768
Short name T518
Test name
Test status
Simulation time 150625735 ps
CPU time 5.75 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 241552 kb
Host smart-6cdc8698-8754-4fe6-ae31-d2694da9a57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799421768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.3799421768
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.136630198
Short name T1044
Test name
Test status
Simulation time 48584641 ps
CPU time 1.75 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 239584 kb
Host smart-20ebc3b8-fb26-4938-a138-0a31108cee30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136630198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.136630198
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3717456957
Short name T77
Test name
Test status
Simulation time 553323285 ps
CPU time 8.56 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:05 PM PDT 24
Peak memory 241568 kb
Host smart-b2956125-4cab-4a30-8ade-ff7deeb23b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717456957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3717456957
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.909129475
Short name T828
Test name
Test status
Simulation time 3598669347 ps
CPU time 34.57 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 245140 kb
Host smart-9cd3c6bc-0f93-4a3e-b760-8cd80a185397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909129475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.909129475
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.3788323482
Short name T581
Test name
Test status
Simulation time 337095770 ps
CPU time 8.78 seconds
Started Jul 21 06:35:59 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241664 kb
Host smart-01539f88-0d59-42d8-9057-dde265e10aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788323482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3788323482
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.3320197994
Short name T1140
Test name
Test status
Simulation time 511333471 ps
CPU time 4.3 seconds
Started Jul 21 06:35:53 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 241292 kb
Host smart-ccf9459e-df94-4621-99a7-0b1f9f17b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320197994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3320197994
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3408793608
Short name T215
Test name
Test status
Simulation time 3632412312 ps
CPU time 20.74 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 248048 kb
Host smart-0e739616-6a8e-489c-9992-0c61c4dd2890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408793608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3408793608
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2284414110
Short name T490
Test name
Test status
Simulation time 2427688246 ps
CPU time 34.08 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 242140 kb
Host smart-58bc484a-8302-4614-b137-c9b19c3b8fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284414110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2284414110
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.166085170
Short name T812
Test name
Test status
Simulation time 212721621 ps
CPU time 5.01 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:35:58 PM PDT 24
Peak memory 241148 kb
Host smart-f7424073-1177-4ae5-9bbf-3f2b657705a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166085170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.166085170
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2826987976
Short name T1157
Test name
Test status
Simulation time 676101119 ps
CPU time 10.41 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 241160 kb
Host smart-1b74537a-2633-47d9-97b5-b82635d0de7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826987976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2826987976
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3908689633
Short name T757
Test name
Test status
Simulation time 3581785262 ps
CPU time 7.72 seconds
Started Jul 21 06:35:52 PM PDT 24
Finished Jul 21 06:36:01 PM PDT 24
Peak memory 248040 kb
Host smart-1f907445-9f41-4d17-9418-8974a17bb27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3908689633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3908689633
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1585251048
Short name T1041
Test name
Test status
Simulation time 236066692 ps
CPU time 7.6 seconds
Started Jul 21 06:35:56 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 241380 kb
Host smart-6c8169b4-ead1-4f7e-87f0-490d73abb8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585251048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1585251048
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.2211292548
Short name T830
Test name
Test status
Simulation time 24134692131 ps
CPU time 137.12 seconds
Started Jul 21 06:36:00 PM PDT 24
Finished Jul 21 06:38:19 PM PDT 24
Peak memory 260176 kb
Host smart-b6ea673a-95c2-4018-8e33-ea4d74422991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211292548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.2211292548
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.3651320588
Short name T632
Test name
Test status
Simulation time 691324744192 ps
CPU time 1221.85 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:56:18 PM PDT 24
Peak memory 299708 kb
Host smart-67e659a4-9c5b-4e24-a94d-4f328bb4fe27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651320588 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.3651320588
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.2344552540
Short name T1033
Test name
Test status
Simulation time 2895209260 ps
CPU time 27.09 seconds
Started Jul 21 06:35:54 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241612 kb
Host smart-09094948-e8e7-4ef8-91ab-61a72889c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344552540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2344552540
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.4243598008
Short name T402
Test name
Test status
Simulation time 93587947 ps
CPU time 1.64 seconds
Started Jul 21 06:36:04 PM PDT 24
Finished Jul 21 06:36:07 PM PDT 24
Peak memory 239708 kb
Host smart-42581ad9-c272-490b-ad89-5ce533ba3612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243598008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.4243598008
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1256588584
Short name T58
Test name
Test status
Simulation time 780039724 ps
CPU time 14.28 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:19 PM PDT 24
Peak memory 241564 kb
Host smart-d249506f-21a6-4894-9bbd-7c4e106bf340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256588584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1256588584
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2981693032
Short name T548
Test name
Test status
Simulation time 417671315 ps
CPU time 10.56 seconds
Started Jul 21 06:35:59 PM PDT 24
Finished Jul 21 06:36:11 PM PDT 24
Peak memory 241524 kb
Host smart-9a27a4d2-421f-4e03-95c2-6f7fdb48236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981693032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2981693032
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.522984141
Short name T947
Test name
Test status
Simulation time 741330113 ps
CPU time 8.32 seconds
Started Jul 21 06:36:01 PM PDT 24
Finished Jul 21 06:36:11 PM PDT 24
Peak memory 241388 kb
Host smart-bd078820-afae-47cf-b134-b4c6b29c94c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522984141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.522984141
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1522098369
Short name T720
Test name
Test status
Simulation time 137600649 ps
CPU time 4.13 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241112 kb
Host smart-51270e8d-6a58-491c-8ce9-bfbed2046445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522098369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1522098369
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1761933376
Short name T961
Test name
Test status
Simulation time 323449089 ps
CPU time 7.48 seconds
Started Jul 21 06:36:02 PM PDT 24
Finished Jul 21 06:36:12 PM PDT 24
Peak memory 241516 kb
Host smart-d1f0f109-46cf-445d-bb85-82bf95fc0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761933376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1761933376
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1489483119
Short name T818
Test name
Test status
Simulation time 758298304 ps
CPU time 20.61 seconds
Started Jul 21 06:36:04 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241504 kb
Host smart-c7fe3d33-a6b2-4538-b320-f714f5a6a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489483119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1489483119
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.3369277808
Short name T723
Test name
Test status
Simulation time 4927926941 ps
CPU time 14.03 seconds
Started Jul 21 06:36:00 PM PDT 24
Finished Jul 21 06:36:16 PM PDT 24
Peak memory 241600 kb
Host smart-888f1e13-28bb-4b54-9371-daa4df88b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369277808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3369277808
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.46209273
Short name T1000
Test name
Test status
Simulation time 1475915458 ps
CPU time 23.94 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:29 PM PDT 24
Peak memory 241092 kb
Host smart-c8006a1a-658d-44bc-b456-126eacf29bac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46209273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.46209273
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2314606073
Short name T850
Test name
Test status
Simulation time 1122333214 ps
CPU time 10.91 seconds
Started Jul 21 06:36:01 PM PDT 24
Finished Jul 21 06:36:13 PM PDT 24
Peak memory 241328 kb
Host smart-4ba71df5-7fc1-43e7-8dd1-26ec9b0618fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314606073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2314606073
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.3741739552
Short name T612
Test name
Test status
Simulation time 102230527 ps
CPU time 4.6 seconds
Started Jul 21 06:36:02 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241672 kb
Host smart-255f9505-5815-492a-8ea1-169062f2f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741739552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3741739552
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.3551461790
Short name T1001
Test name
Test status
Simulation time 575441083870 ps
CPU time 1381.03 seconds
Started Jul 21 06:36:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 295616 kb
Host smart-e3b95864-ad7c-405e-b382-576587a4a9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551461790 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.3551461790
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.2407694271
Short name T1013
Test name
Test status
Simulation time 12703115919 ps
CPU time 21.94 seconds
Started Jul 21 06:36:02 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 242932 kb
Host smart-bdff3141-a197-4b77-91f6-4b42f5cc8e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407694271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2407694271
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.741017842
Short name T599
Test name
Test status
Simulation time 222799702 ps
CPU time 1.76 seconds
Started Jul 21 06:36:02 PM PDT 24
Finished Jul 21 06:36:06 PM PDT 24
Peak memory 239808 kb
Host smart-d345a7ba-3bc7-4cd2-9d27-1c5919df2fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741017842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.741017842
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2390732699
Short name T130
Test name
Test status
Simulation time 2581082301 ps
CPU time 18.98 seconds
Started Jul 21 06:36:04 PM PDT 24
Finished Jul 21 06:36:25 PM PDT 24
Peak memory 248124 kb
Host smart-ccaee542-30aa-4618-b582-b7afcda70493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390732699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2390732699
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.1237122214
Short name T562
Test name
Test status
Simulation time 17096271283 ps
CPU time 61.44 seconds
Started Jul 21 06:36:01 PM PDT 24
Finished Jul 21 06:37:04 PM PDT 24
Peak memory 248848 kb
Host smart-40d276b4-2e5e-4bc2-9512-af096b826371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237122214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1237122214
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1443600438
Short name T382
Test name
Test status
Simulation time 240583851 ps
CPU time 5.68 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:10 PM PDT 24
Peak memory 241396 kb
Host smart-17d22313-a9ea-42eb-82a7-ac7fff4904e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443600438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1443600438
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.429101998
Short name T449
Test name
Test status
Simulation time 1627013690 ps
CPU time 4.83 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:12 PM PDT 24
Peak memory 241396 kb
Host smart-bf4eff38-9d25-4398-9027-10c56b8e069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429101998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.429101998
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.691193428
Short name T1131
Test name
Test status
Simulation time 524318241 ps
CPU time 7.11 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:13 PM PDT 24
Peak memory 241448 kb
Host smart-c235693e-7c51-4976-bf47-c5a21c719c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691193428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.691193428
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.962900988
Short name T687
Test name
Test status
Simulation time 1515824259 ps
CPU time 19.72 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241428 kb
Host smart-1bddb581-a2f8-436a-9d2c-1ec94ffbb934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962900988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.962900988
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1619074913
Short name T373
Test name
Test status
Simulation time 1087859809 ps
CPU time 14.68 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241064 kb
Host smart-70b0af16-3021-4d88-b5e8-3170e95969df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619074913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1619074913
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3717488405
Short name T863
Test name
Test status
Simulation time 2023728489 ps
CPU time 25.46 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 241312 kb
Host smart-4230f808-4389-45ce-a5ca-6612e17bff73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3717488405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3717488405
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2624499173
Short name T113
Test name
Test status
Simulation time 1048330555 ps
CPU time 7.64 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241456 kb
Host smart-a75401b9-2026-4317-827b-5d18d8907574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624499173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2624499173
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3314798254
Short name T1098
Test name
Test status
Simulation time 3812422042 ps
CPU time 6.99 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241772 kb
Host smart-3e6a0914-da65-4d9a-846a-8320165579ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314798254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3314798254
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2504361491
Short name T1074
Test name
Test status
Simulation time 457048306386 ps
CPU time 1013.35 seconds
Started Jul 21 06:36:03 PM PDT 24
Finished Jul 21 06:52:59 PM PDT 24
Peak memory 341028 kb
Host smart-2cee489a-2b53-4ea7-8e70-f1486ccd1dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504361491 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.2504361491
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.632184148
Short name T855
Test name
Test status
Simulation time 859469231 ps
CPU time 6.13 seconds
Started Jul 21 06:36:01 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241336 kb
Host smart-b1a1cb46-465c-4b70-8449-23d5b29735b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632184148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.632184148
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1186043452
Short name T388
Test name
Test status
Simulation time 129723594 ps
CPU time 2.06 seconds
Started Jul 21 06:36:10 PM PDT 24
Finished Jul 21 06:36:16 PM PDT 24
Peak memory 239608 kb
Host smart-f7b03dae-cffe-4ab6-a965-3f61a7ace602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186043452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1186043452
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.914050238
Short name T134
Test name
Test status
Simulation time 777246217 ps
CPU time 10.48 seconds
Started Jul 21 06:36:09 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 241432 kb
Host smart-95fdf061-95db-4976-86b6-850eb2dd0eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914050238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.914050238
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.4217638105
Short name T866
Test name
Test status
Simulation time 1490502620 ps
CPU time 17.26 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241248 kb
Host smart-d34b1875-5e24-45fe-87ca-8f14e89d7ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217638105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.4217638105
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.559759982
Short name T647
Test name
Test status
Simulation time 6573212425 ps
CPU time 14.29 seconds
Started Jul 21 06:36:10 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241856 kb
Host smart-3ed9efc8-cf73-4b1a-98e1-d66496effb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559759982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.559759982
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3130713153
Short name T1143
Test name
Test status
Simulation time 318629795 ps
CPU time 4.91 seconds
Started Jul 21 06:36:02 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 241224 kb
Host smart-c9af79ab-3cb8-41bf-8e68-d90a661ecda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130713153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3130713153
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2221769845
Short name T342
Test name
Test status
Simulation time 7225483231 ps
CPU time 52.03 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:59 PM PDT 24
Peak memory 244796 kb
Host smart-b6b008a7-8adf-4a9f-b142-217f624828fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221769845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2221769845
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2639084517
Short name T547
Test name
Test status
Simulation time 14383583746 ps
CPU time 23.65 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241372 kb
Host smart-a010aafd-a353-4966-ab60-07a7611fc80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639084517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2639084517
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2571387944
Short name T237
Test name
Test status
Simulation time 185862906 ps
CPU time 10.31 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241504 kb
Host smart-12b2b4c6-738f-4e03-8cee-09651f2cc4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571387944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2571387944
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2842094969
Short name T1016
Test name
Test status
Simulation time 793450283 ps
CPU time 12.22 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241300 kb
Host smart-dff7b761-ad92-4815-9bcf-5bb3a8e4fdf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842094969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2842094969
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.3550468494
Short name T442
Test name
Test status
Simulation time 1269555176 ps
CPU time 11.02 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:36:25 PM PDT 24
Peak memory 241556 kb
Host smart-3163f153-d1a4-4b8f-9da5-697e3b368a49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550468494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3550468494
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3155552589
Short name T497
Test name
Test status
Simulation time 5107068442 ps
CPU time 14.94 seconds
Started Jul 21 06:36:02 PM PDT 24
Finished Jul 21 06:36:18 PM PDT 24
Peak memory 241428 kb
Host smart-0ab9e9db-2f97-4f8a-aa40-d5d67a5beb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155552589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3155552589
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.2439518498
Short name T107
Test name
Test status
Simulation time 3400683644 ps
CPU time 77.87 seconds
Started Jul 21 06:36:06 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 244680 kb
Host smart-e2e90782-7126-46c6-a94b-ad9e438f53ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439518498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.2439518498
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.565651331
Short name T450
Test name
Test status
Simulation time 16404602118 ps
CPU time 469.34 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:43:58 PM PDT 24
Peak memory 256356 kb
Host smart-a3b07fd3-f22f-4c27-b9e1-8f8647554d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565651331 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.565651331
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.2005408447
Short name T1096
Test name
Test status
Simulation time 5420952676 ps
CPU time 31.06 seconds
Started Jul 21 06:36:09 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241756 kb
Host smart-45f1e1b1-a2c9-4130-9361-ff9e1097aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005408447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2005408447
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.801604682
Short name T975
Test name
Test status
Simulation time 53407129 ps
CPU time 1.69 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 06:36:13 PM PDT 24
Peak memory 239600 kb
Host smart-dc9362a3-40fe-41ca-a021-3ffa9605f516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801604682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.801604682
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.375826641
Short name T31
Test name
Test status
Simulation time 1004700518 ps
CPU time 11.72 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 241416 kb
Host smart-76398ad6-f74b-43a9-8b19-4ec44159e8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375826641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.375826641
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.3195358701
Short name T392
Test name
Test status
Simulation time 1033387414 ps
CPU time 29.76 seconds
Started Jul 21 06:36:06 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 241248 kb
Host smart-63aeb6b7-6a39-48d3-92a6-1fa3c14014cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195358701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3195358701
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.2644038104
Short name T1162
Test name
Test status
Simulation time 200519524 ps
CPU time 6.65 seconds
Started Jul 21 06:36:05 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241796 kb
Host smart-b3c64fde-3cdf-4041-b201-3cfa0b9faaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644038104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2644038104
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.645248745
Short name T722
Test name
Test status
Simulation time 510648779 ps
CPU time 7.33 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:17 PM PDT 24
Peak memory 241488 kb
Host smart-365c50f1-8918-4b04-ade4-68072c624fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645248745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.645248745
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.1592957255
Short name T553
Test name
Test status
Simulation time 2349020390 ps
CPU time 23.59 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 247976 kb
Host smart-61d8ea26-4822-45ba-aa46-60f73564883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592957255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1592957255
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2368750413
Short name T959
Test name
Test status
Simulation time 103933968 ps
CPU time 4.14 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:21 PM PDT 24
Peak memory 246448 kb
Host smart-f599620a-9f10-4628-ae14-900342ddb4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368750413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2368750413
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.3097923477
Short name T1126
Test name
Test status
Simulation time 881587296 ps
CPU time 12.33 seconds
Started Jul 21 06:36:06 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 241184 kb
Host smart-1ba49966-de99-4dc9-a136-2852945cf4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097923477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3097923477
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.4251019079
Short name T362
Test name
Test status
Simulation time 102423462 ps
CPU time 3.44 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:14 PM PDT 24
Peak memory 241368 kb
Host smart-1479c861-0337-47ad-a99a-cc6a431a169a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251019079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.4251019079
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.4026895660
Short name T858
Test name
Test status
Simulation time 647358361 ps
CPU time 4.21 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:36:19 PM PDT 24
Peak memory 241636 kb
Host smart-940c9a99-bc7f-4724-820f-19c7c8407b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026895660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.4026895660
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3150950765
Short name T686
Test name
Test status
Simulation time 63437423831 ps
CPU time 1232.62 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:56:47 PM PDT 24
Peak memory 305544 kb
Host smart-141ffe69-6237-465e-a90c-6fbb431b7acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150950765 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3150950765
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1666803396
Short name T1169
Test name
Test status
Simulation time 1685636519 ps
CPU time 17.14 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241612 kb
Host smart-af78c8aa-4e7f-4be8-b9a5-5c8fd7647b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666803396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1666803396
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.2083501646
Short name T389
Test name
Test status
Simulation time 57158297 ps
CPU time 1.7 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:36:17 PM PDT 24
Peak memory 239576 kb
Host smart-48510d15-9094-4ebb-8042-6740053bfc42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083501646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2083501646
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.97621167
Short name T1172
Test name
Test status
Simulation time 325898421 ps
CPU time 16.64 seconds
Started Jul 21 06:36:06 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241208 kb
Host smart-0b5cddc5-8422-4ce5-a699-49d602c0532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97621167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.97621167
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.1544887569
Short name T492
Test name
Test status
Simulation time 3455456945 ps
CPU time 32.96 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241536 kb
Host smart-252c6470-9b06-4eed-8bb7-f2a0da2bf9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544887569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1544887569
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.982483924
Short name T809
Test name
Test status
Simulation time 118239568 ps
CPU time 3.68 seconds
Started Jul 21 06:36:06 PM PDT 24
Finished Jul 21 06:36:12 PM PDT 24
Peak memory 241260 kb
Host smart-e08cc55b-6ddd-4e82-b6d1-2055035375bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982483924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.982483924
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2951243414
Short name T625
Test name
Test status
Simulation time 994656043 ps
CPU time 15.76 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241848 kb
Host smart-d9ce61f0-1c26-4a45-84cc-c092834bd34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951243414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2951243414
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.838104301
Short name T1057
Test name
Test status
Simulation time 3378392946 ps
CPU time 10.39 seconds
Started Jul 21 06:36:09 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 248116 kb
Host smart-d1819ffb-f7b1-4d0a-86c8-0bf8b8a4e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838104301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.838104301
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3853257582
Short name T493
Test name
Test status
Simulation time 529845717 ps
CPU time 7.53 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241192 kb
Host smart-f9dc1441-3892-4bc8-922d-358cecc7caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853257582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3853257582
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1496610266
Short name T1097
Test name
Test status
Simulation time 1081026806 ps
CPU time 8.42 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:19 PM PDT 24
Peak memory 241472 kb
Host smart-9e83b0dc-ce18-4aeb-9101-53e2d1a77ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496610266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1496610266
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2275392816
Short name T725
Test name
Test status
Simulation time 604708844 ps
CPU time 5.12 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:16 PM PDT 24
Peak memory 241260 kb
Host smart-7d3264ad-4d24-4edd-89d2-16334ac9f5d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275392816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2275392816
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.4199444097
Short name T1136
Test name
Test status
Simulation time 512943966 ps
CPU time 7.08 seconds
Started Jul 21 06:36:07 PM PDT 24
Finished Jul 21 06:36:16 PM PDT 24
Peak memory 241124 kb
Host smart-79c36bd6-e81f-41bf-a9e7-875ede825da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199444097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.4199444097
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.1539508813
Short name T282
Test name
Test status
Simulation time 2931114041 ps
CPU time 46.25 seconds
Started Jul 21 06:36:11 PM PDT 24
Finished Jul 21 06:37:01 PM PDT 24
Peak memory 245684 kb
Host smart-2769681a-b440-4b10-b7b2-2b4b4fedfa55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539508813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.1539508813
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1720640237
Short name T153
Test name
Test status
Simulation time 131446344187 ps
CPU time 1518.45 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 07:01:30 PM PDT 24
Peak memory 333632 kb
Host smart-28930a58-0e04-48a6-b01b-20e1d801151c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720640237 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.1720640237
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.474220752
Short name T568
Test name
Test status
Simulation time 5857010202 ps
CPU time 30.36 seconds
Started Jul 21 06:36:10 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241496 kb
Host smart-3f26bf72-398b-4095-814d-a15e5ec3ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474220752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.474220752
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3882020327
Short name T846
Test name
Test status
Simulation time 93120709 ps
CPU time 1.76 seconds
Started Jul 21 06:34:20 PM PDT 24
Finished Jul 21 06:34:23 PM PDT 24
Peak memory 239916 kb
Host smart-e6d80e3e-e034-4e51-93f5-e2ae11890b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882020327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3882020327
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.3430690428
Short name T978
Test name
Test status
Simulation time 7973709248 ps
CPU time 20.93 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:37 PM PDT 24
Peak memory 242484 kb
Host smart-d73f2041-9c32-443f-b479-8e7f54a19783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430690428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3430690428
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.3051358475
Short name T427
Test name
Test status
Simulation time 8773455877 ps
CPU time 18.45 seconds
Started Jul 21 06:34:17 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241628 kb
Host smart-b7a88d12-edf1-4d29-8107-e9ff9f4d72d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051358475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3051358475
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.1042568071
Short name T1110
Test name
Test status
Simulation time 523734347 ps
CPU time 14 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:28 PM PDT 24
Peak memory 241700 kb
Host smart-91990ea9-e9d3-4c35-be06-0307a36b81d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042568071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1042568071
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.4213551741
Short name T897
Test name
Test status
Simulation time 2622156192 ps
CPU time 17.38 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:32 PM PDT 24
Peak memory 241872 kb
Host smart-2b98efe7-0521-4379-99c6-92dce8fb2fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213551741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.4213551741
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.1564255810
Short name T1085
Test name
Test status
Simulation time 4949606481 ps
CPU time 27.13 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:34:47 PM PDT 24
Peak memory 248052 kb
Host smart-78df437b-af62-431b-9ad9-2313140bde4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564255810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.1564255810
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.1617744367
Short name T746
Test name
Test status
Simulation time 12326653320 ps
CPU time 30.53 seconds
Started Jul 21 06:34:19 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 242664 kb
Host smart-007dd050-f2bf-4c9b-8e17-6c1e7ff24bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617744367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1617744367
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.3359966334
Short name T817
Test name
Test status
Simulation time 466436571 ps
CPU time 10.03 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:24 PM PDT 24
Peak memory 241124 kb
Host smart-3af9240a-787a-42af-985b-1b70869bc990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359966334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3359966334
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1697150234
Short name T386
Test name
Test status
Simulation time 650055369 ps
CPU time 8.5 seconds
Started Jul 21 06:34:11 PM PDT 24
Finished Jul 21 06:34:23 PM PDT 24
Peak memory 246860 kb
Host smart-014c200d-9572-469c-8e74-514367836ea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697150234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1697150234
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.2143872643
Short name T874
Test name
Test status
Simulation time 277835142 ps
CPU time 5.81 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:30 PM PDT 24
Peak memory 241328 kb
Host smart-db36ef08-8b99-4d8a-8c9b-506ac7c09bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143872643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2143872643
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3547964472
Short name T993
Test name
Test status
Simulation time 238201907 ps
CPU time 3.95 seconds
Started Jul 21 06:34:12 PM PDT 24
Finished Jul 21 06:34:20 PM PDT 24
Peak memory 241360 kb
Host smart-6b7011f9-60c5-4df4-9169-8c146deb5fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547964472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3547964472
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2968935609
Short name T665
Test name
Test status
Simulation time 61632172265 ps
CPU time 145.07 seconds
Started Jul 21 06:34:23 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 261340 kb
Host smart-2d5dd967-ee24-46a0-b555-57e4f507b00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968935609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2968935609
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1735481864
Short name T234
Test name
Test status
Simulation time 137219355448 ps
CPU time 917.86 seconds
Started Jul 21 06:34:17 PM PDT 24
Finished Jul 21 06:49:37 PM PDT 24
Peak memory 351688 kb
Host smart-bc1538d6-b823-48c7-8a3e-846ab944815e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735481864 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1735481864
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.1447379265
Short name T104
Test name
Test status
Simulation time 16224314578 ps
CPU time 40.58 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:35:01 PM PDT 24
Peak memory 241960 kb
Host smart-52964114-9e4d-49d8-8078-5263ba5360eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447379265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1447379265
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.525440315
Short name T1152
Test name
Test status
Simulation time 1576789382 ps
CPU time 6.9 seconds
Started Jul 21 06:36:08 PM PDT 24
Finished Jul 21 06:36:18 PM PDT 24
Peak memory 241472 kb
Host smart-a934bf89-2d74-48d7-8099-9f879aeeac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525440315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.525440315
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1251256628
Short name T883
Test name
Test status
Simulation time 227290359 ps
CPU time 4.79 seconds
Started Jul 21 06:36:14 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 241512 kb
Host smart-262c8363-ffaf-4b46-b412-6c320cba401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251256628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1251256628
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.2037273276
Short name T1173
Test name
Test status
Simulation time 256610582113 ps
CPU time 2186.59 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 07:12:43 PM PDT 24
Peak memory 608660 kb
Host smart-f5c926bd-b0c3-4ac1-a637-79c79cc28575
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037273276 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.2037273276
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.463153789
Short name T509
Test name
Test status
Simulation time 2665983061 ps
CPU time 5.85 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241876 kb
Host smart-6c3cb505-b3ea-477f-8214-1f316b3e5337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463153789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.463153789
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.3478178747
Short name T124
Test name
Test status
Simulation time 656620821 ps
CPU time 16.47 seconds
Started Jul 21 06:36:14 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241260 kb
Host smart-c4f5f384-2f1f-4bc3-9b61-db3c4ff0de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478178747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3478178747
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3189203486
Short name T865
Test name
Test status
Simulation time 142571015194 ps
CPU time 242 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:40:19 PM PDT 24
Peak memory 285952 kb
Host smart-128ce2c7-ef39-47a7-a391-ff9b5fcc1651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189203486 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3189203486
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1138332879
Short name T806
Test name
Test status
Simulation time 2347881289 ps
CPU time 5.8 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 241784 kb
Host smart-dc868dca-2c44-48ed-8ed2-841cc27ecb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138332879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1138332879
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2897272605
Short name T778
Test name
Test status
Simulation time 671095817 ps
CPU time 19.02 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 241696 kb
Host smart-8d452d31-e1c5-4873-9bb8-5406ff296159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897272605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2897272605
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.3231356303
Short name T37
Test name
Test status
Simulation time 368357808 ps
CPU time 5.57 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 06:36:24 PM PDT 24
Peak memory 241376 kb
Host smart-99314068-7c8c-4e3e-89d1-0644955b4e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231356303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3231356303
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3294228233
Short name T369
Test name
Test status
Simulation time 387508273 ps
CPU time 6.08 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241068 kb
Host smart-4e56eeda-9c7a-479c-93f3-9c386b71d542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294228233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3294228233
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3705269178
Short name T1112
Test name
Test status
Simulation time 159960303794 ps
CPU time 396.12 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 280968 kb
Host smart-1cbdf3aa-4786-421e-a8f2-67f6e11e177e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705269178 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3705269178
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2065617746
Short name T594
Test name
Test status
Simulation time 1624031578 ps
CPU time 6.62 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241316 kb
Host smart-f76cab02-de9b-4fc4-a6aa-63cd04031414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065617746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2065617746
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3808862569
Short name T331
Test name
Test status
Simulation time 610278918 ps
CPU time 8.44 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241268 kb
Host smart-5d3b14d8-e6c5-4c5f-b611-5159e44e0a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808862569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3808862569
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3864806739
Short name T732
Test name
Test status
Simulation time 858502284225 ps
CPU time 2361.6 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 07:15:40 PM PDT 24
Peak memory 342624 kb
Host smart-28292d70-32ba-455a-b6c8-d7ee02fd74b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864806739 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3864806739
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2660163097
Short name T207
Test name
Test status
Simulation time 458706678 ps
CPU time 3.58 seconds
Started Jul 21 06:36:14 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241440 kb
Host smart-391bf998-87d2-46c5-a92c-b97b8ed2ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660163097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2660163097
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.823808666
Short name T1161
Test name
Test status
Simulation time 1781740954 ps
CPU time 12.37 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 241468 kb
Host smart-f44dc231-a68f-4488-a0ef-2b12d5ef21f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823808666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.823808666
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.4061116845
Short name T1153
Test name
Test status
Simulation time 118537004865 ps
CPU time 2198.05 seconds
Started Jul 21 06:36:14 PM PDT 24
Finished Jul 21 07:12:57 PM PDT 24
Peak memory 516236 kb
Host smart-3c078852-8f9e-49e3-bbb6-eb1bd140accd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061116845 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.4061116845
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1630832239
Short name T973
Test name
Test status
Simulation time 343798208 ps
CPU time 4.74 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241412 kb
Host smart-4751c6bd-47b5-40f1-90be-42b48c77d413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630832239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1630832239
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.1404005600
Short name T950
Test name
Test status
Simulation time 1116102468 ps
CPU time 16.6 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:33 PM PDT 24
Peak memory 241496 kb
Host smart-349d3f86-217c-4793-9141-7943d533b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404005600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1404005600
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2601243183
Short name T277
Test name
Test status
Simulation time 286256062562 ps
CPU time 1879.56 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 07:07:40 PM PDT 24
Peak memory 283900 kb
Host smart-c73fe37c-557f-4700-b92a-af27951c6466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601243183 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2601243183
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.3426644455
Short name T579
Test name
Test status
Simulation time 267845428 ps
CPU time 4.12 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 241412 kb
Host smart-95b8ccb2-07e4-4c40-9489-fe08d9ffbc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426644455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3426644455
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1381573020
Short name T250
Test name
Test status
Simulation time 3046579180 ps
CPU time 7.45 seconds
Started Jul 21 06:36:14 PM PDT 24
Finished Jul 21 06:36:25 PM PDT 24
Peak memory 241324 kb
Host smart-d0a4a0bc-1c2c-4d8a-bc54-d382c6c54570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381573020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1381573020
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.256104879
Short name T605
Test name
Test status
Simulation time 903277230237 ps
CPU time 2035.81 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 07:10:15 PM PDT 24
Peak memory 493892 kb
Host smart-1ad2cd83-5419-4986-98ee-2fb770c3293d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256104879 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.256104879
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1268317617
Short name T712
Test name
Test status
Simulation time 629251778 ps
CPU time 4.66 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:24 PM PDT 24
Peak memory 241308 kb
Host smart-67b348fa-8e5e-4036-8c6e-821bc5f9fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268317617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1268317617
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2386850254
Short name T894
Test name
Test status
Simulation time 166350366 ps
CPU time 3.15 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 241524 kb
Host smart-d33873ba-3114-4767-8f4f-33252dcad74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386850254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2386850254
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.23697186
Short name T326
Test name
Test status
Simulation time 49320936516 ps
CPU time 849.22 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:50:27 PM PDT 24
Peak memory 284840 kb
Host smart-3b5e6bc6-f70b-4577-bb51-f6005139b5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23697186 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.23697186
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3711316573
Short name T1032
Test name
Test status
Simulation time 1862385945 ps
CPU time 4.1 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 06:36:20 PM PDT 24
Peak memory 241508 kb
Host smart-9b782839-8719-417a-a7a1-14f17572cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711316573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3711316573
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.3593202675
Short name T774
Test name
Test status
Simulation time 1528557211 ps
CPU time 10.56 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:31 PM PDT 24
Peak memory 241132 kb
Host smart-1161a090-f81f-457a-94b9-524016044ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593202675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3593202675
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3309525017
Short name T14
Test name
Test status
Simulation time 573374663880 ps
CPU time 1120.59 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 302744 kb
Host smart-1a3e36e7-fc6c-4f91-aa36-6778d169f87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309525017 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3309525017
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.3172591528
Short name T898
Test name
Test status
Simulation time 103290138 ps
CPU time 1.76 seconds
Started Jul 21 06:34:17 PM PDT 24
Finished Jul 21 06:34:21 PM PDT 24
Peak memory 239716 kb
Host smart-236ebbb6-afa7-4745-a5bb-c96ca7468dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172591528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3172591528
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.4050990902
Short name T527
Test name
Test status
Simulation time 720422123 ps
CPU time 20.99 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 248064 kb
Host smart-9d7c0a89-6880-4782-89a2-1fa3256d82c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050990902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.4050990902
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.211204984
Short name T926
Test name
Test status
Simulation time 708790856 ps
CPU time 13.5 seconds
Started Jul 21 06:34:20 PM PDT 24
Finished Jul 21 06:34:35 PM PDT 24
Peak memory 241600 kb
Host smart-a5de7d29-9005-4953-8566-f66aa506a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211204984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.211204984
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1906173049
Short name T541
Test name
Test status
Simulation time 630050321 ps
CPU time 13.68 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:34:34 PM PDT 24
Peak memory 241000 kb
Host smart-e2ef520f-250c-4ddc-afea-dff96ded16af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906173049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1906173049
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3809221934
Short name T773
Test name
Test status
Simulation time 5379912304 ps
CPU time 30.53 seconds
Started Jul 21 06:34:19 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 242304 kb
Host smart-9f37f0ec-3957-4290-8ca2-ad03f4a71d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809221934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3809221934
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.3725597237
Short name T771
Test name
Test status
Simulation time 133644231 ps
CPU time 3.68 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 241424 kb
Host smart-5e96b7ba-ea73-4146-b6c0-7718d6afebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725597237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3725597237
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.1600408915
Short name T343
Test name
Test status
Simulation time 27737484264 ps
CPU time 54.56 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 256308 kb
Host smart-754dc385-8b85-4058-8aaa-8c11a19c6d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600408915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1600408915
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.4247340195
Short name T162
Test name
Test status
Simulation time 456462100 ps
CPU time 9.66 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:34:30 PM PDT 24
Peak memory 241220 kb
Host smart-6f12318f-12ee-46d3-83ae-9ad383aba8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247340195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.4247340195
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.961309236
Short name T230
Test name
Test status
Simulation time 613677415 ps
CPU time 5.75 seconds
Started Jul 21 06:34:17 PM PDT 24
Finished Jul 21 06:34:25 PM PDT 24
Peak memory 241280 kb
Host smart-90cf030d-01bf-4848-b170-0fa6340b6204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961309236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.961309236
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1470177425
Short name T819
Test name
Test status
Simulation time 5686478700 ps
CPU time 16.23 seconds
Started Jul 21 06:34:17 PM PDT 24
Finished Jul 21 06:34:36 PM PDT 24
Peak memory 248040 kb
Host smart-0e959246-7123-4449-aa8b-dde38940eb41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470177425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1470177425
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.641965499
Short name T728
Test name
Test status
Simulation time 283378051 ps
CPU time 10.48 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:34:31 PM PDT 24
Peak memory 241220 kb
Host smart-abe647a7-8eae-4a58-9f4e-3fb18584437f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641965499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.641965499
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.4124680328
Short name T765
Test name
Test status
Simulation time 405901504 ps
CPU time 7.48 seconds
Started Jul 21 06:34:18 PM PDT 24
Finished Jul 21 06:34:28 PM PDT 24
Peak memory 241228 kb
Host smart-8cfceb25-44d8-46a2-aa50-482430fa164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124680328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.4124680328
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2601973128
Short name T572
Test name
Test status
Simulation time 13361477282 ps
CPU time 197.87 seconds
Started Jul 21 06:34:21 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 261788 kb
Host smart-3ddf3d9e-a69c-4ad3-87c0-8351fb6770d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601973128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2601973128
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1538449691
Short name T159
Test name
Test status
Simulation time 105172324 ps
CPU time 4.06 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:24 PM PDT 24
Peak memory 241664 kb
Host smart-7f00d45e-a678-4e50-9154-ac0421db0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538449691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1538449691
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1744760012
Short name T257
Test name
Test status
Simulation time 1854338610 ps
CPU time 23.58 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 06:36:42 PM PDT 24
Peak memory 241224 kb
Host smart-70475d8d-8198-4f04-8637-dc38c50593f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744760012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1744760012
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3417316228
Short name T320
Test name
Test status
Simulation time 392205524851 ps
CPU time 826.36 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:50:04 PM PDT 24
Peak memory 316772 kb
Host smart-d1a4d23f-f1df-4c08-90eb-8bb459def9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417316228 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3417316228
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.1705150874
Short name T65
Test name
Test status
Simulation time 2628053519 ps
CPU time 7.92 seconds
Started Jul 21 06:36:15 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241520 kb
Host smart-bc660cba-917a-4416-b732-c6bd9c564467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705150874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1705150874
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.1594696663
Short name T1061
Test name
Test status
Simulation time 2677481340 ps
CPU time 21.21 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:39 PM PDT 24
Peak memory 241260 kb
Host smart-2a0e03c7-24a5-45d5-bda2-0d0ae1f16d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594696663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1594696663
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.394927160
Short name T1042
Test name
Test status
Simulation time 63450555469 ps
CPU time 1709.32 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 280496 kb
Host smart-abe0d771-a9a9-413f-b0cc-701a07643616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394927160 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.394927160
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2316679798
Short name T1154
Test name
Test status
Simulation time 2727011901 ps
CPU time 7.31 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 06:36:23 PM PDT 24
Peak memory 241800 kb
Host smart-42d387d2-94cc-4db5-8f67-b513331f72b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316679798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2316679798
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3952835840
Short name T106
Test name
Test status
Simulation time 288571422 ps
CPU time 8.72 seconds
Started Jul 21 06:36:12 PM PDT 24
Finished Jul 21 06:36:25 PM PDT 24
Peak memory 241248 kb
Host smart-513001e9-01ee-4a59-9c7d-562015703e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952835840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3952835840
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2913923473
Short name T35
Test name
Test status
Simulation time 279305413 ps
CPU time 4.32 seconds
Started Jul 21 06:36:13 PM PDT 24
Finished Jul 21 06:36:22 PM PDT 24
Peak memory 241524 kb
Host smart-a89543ce-259b-4801-8b23-cfe943e4a050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913923473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2913923473
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.1627657328
Short name T414
Test name
Test status
Simulation time 214745072 ps
CPU time 3.94 seconds
Started Jul 21 06:36:25 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 241192 kb
Host smart-acc40210-5307-4108-bc41-a07d8571bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627657328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1627657328
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1693953714
Short name T467
Test name
Test status
Simulation time 315101463 ps
CPU time 5.02 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241372 kb
Host smart-422cc8de-9d06-4632-8b82-9cc8b8266eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693953714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1693953714
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2456501503
Short name T197
Test name
Test status
Simulation time 197466030 ps
CPU time 9.75 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:36:32 PM PDT 24
Peak memory 241132 kb
Host smart-4cbe6dc0-1407-4985-9534-00a57192b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456501503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2456501503
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2571180076
Short name T972
Test name
Test status
Simulation time 26409421024 ps
CPU time 665.34 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 06:47:29 PM PDT 24
Peak memory 277728 kb
Host smart-6e39af77-2b6f-41d6-bec6-61aa5d425bac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571180076 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.2571180076
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1700526469
Short name T55
Test name
Test status
Simulation time 147158690 ps
CPU time 3.83 seconds
Started Jul 21 06:36:23 PM PDT 24
Finished Jul 21 06:36:29 PM PDT 24
Peak memory 241460 kb
Host smart-5a177f37-6114-4e4a-aee8-58001c923a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700526469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1700526469
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2925242613
Short name T321
Test name
Test status
Simulation time 72506426784 ps
CPU time 1290.13 seconds
Started Jul 21 06:36:23 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 273072 kb
Host smart-57b2c3a1-5ee9-45be-86af-4a3d8940cf23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925242613 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.2925242613
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2954957419
Short name T702
Test name
Test status
Simulation time 258000672 ps
CPU time 3.69 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241132 kb
Host smart-f000d959-a9c8-4db3-b969-1387f67f7214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954957419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2954957419
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3148639645
Short name T607
Test name
Test status
Simulation time 1145281926 ps
CPU time 3.59 seconds
Started Jul 21 06:36:20 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241536 kb
Host smart-07a61408-9e04-4905-96ac-7bbba544c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148639645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3148639645
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1868916539
Short name T1103
Test name
Test status
Simulation time 271809746777 ps
CPU time 735.93 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:48:38 PM PDT 24
Peak memory 346488 kb
Host smart-fddbe548-c6f2-4000-90fa-c20701d07b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868916539 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.1868916539
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.1445989580
Short name T1168
Test name
Test status
Simulation time 2023445348 ps
CPU time 4.93 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241588 kb
Host smart-5abd389f-9e94-40b6-8878-8f7b64adecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445989580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.1445989580
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2330581356
Short name T383
Test name
Test status
Simulation time 184462736 ps
CPU time 3.8 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:36:24 PM PDT 24
Peak memory 241120 kb
Host smart-086ec580-6a08-4950-a47d-30a14d57d6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330581356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2330581356
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2302143517
Short name T913
Test name
Test status
Simulation time 344174270991 ps
CPU time 1923.39 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 07:08:27 PM PDT 24
Peak memory 281084 kb
Host smart-986b979a-b284-49eb-b0a7-31a045f60791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302143517 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.2302143517
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.2572175765
Short name T573
Test name
Test status
Simulation time 249745238 ps
CPU time 4.84 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241536 kb
Host smart-c5245702-e72c-40e0-8d46-4efa70bf283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572175765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2572175765
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.2526497427
Short name T255
Test name
Test status
Simulation time 38620560691 ps
CPU time 529.45 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 06:45:09 PM PDT 24
Peak memory 346440 kb
Host smart-6102f03e-c434-420d-918b-af99c0536543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526497427 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.2526497427
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.2078821322
Short name T1116
Test name
Test status
Simulation time 298206112 ps
CPU time 4.29 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241732 kb
Host smart-833fc698-9879-4f6f-8685-801cfeda8409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078821322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2078821322
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.387008279
Short name T1090
Test name
Test status
Simulation time 270509017 ps
CPU time 2.85 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:36:24 PM PDT 24
Peak memory 241480 kb
Host smart-649f8d80-e487-4089-8a70-1beeb236a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387008279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.387008279
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3976343673
Short name T182
Test name
Test status
Simulation time 1048632570765 ps
CPU time 2629.78 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 07:20:12 PM PDT 24
Peak memory 393776 kb
Host smart-2a8a1929-d77b-46f3-92d0-ec8f91875495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976343673 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3976343673
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.1131075880
Short name T1027
Test name
Test status
Simulation time 46936333 ps
CPU time 1.67 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:25 PM PDT 24
Peak memory 239704 kb
Host smart-7bfaf266-935c-48df-932e-4bf359373054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131075880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1131075880
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.1247367527
Short name T504
Test name
Test status
Simulation time 2653151593 ps
CPU time 27.28 seconds
Started Jul 21 06:34:17 PM PDT 24
Finished Jul 21 06:34:46 PM PDT 24
Peak memory 241872 kb
Host smart-8309db4e-5647-4ff9-b3db-1a334513f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247367527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1247367527
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.182226908
Short name T827
Test name
Test status
Simulation time 5688092707 ps
CPU time 12.77 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:36 PM PDT 24
Peak memory 243428 kb
Host smart-207afa3c-5b3b-4da3-9000-93f27e5403b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182226908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.182226908
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.427359313
Short name T1081
Test name
Test status
Simulation time 921179645 ps
CPU time 15.15 seconds
Started Jul 21 06:34:25 PM PDT 24
Finished Jul 21 06:34:42 PM PDT 24
Peak memory 241112 kb
Host smart-bf573b52-8395-448b-88ac-cb357cdcee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427359313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.427359313
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.2144682548
Short name T419
Test name
Test status
Simulation time 1262724998 ps
CPU time 13.85 seconds
Started Jul 21 06:34:23 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 241420 kb
Host smart-a4ccc118-5e4b-4eca-a9b0-7b8bb5632de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144682548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2144682548
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.387879063
Short name T697
Test name
Test status
Simulation time 227772455 ps
CPU time 3.89 seconds
Started Jul 21 06:34:20 PM PDT 24
Finished Jul 21 06:34:25 PM PDT 24
Peak memory 241400 kb
Host smart-5134a7c6-0cb2-43f9-86ae-8b9988e05caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387879063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.387879063
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.966037400
Short name T196
Test name
Test status
Simulation time 526988304 ps
CPU time 13.76 seconds
Started Jul 21 06:34:23 PM PDT 24
Finished Jul 21 06:34:38 PM PDT 24
Peak memory 243356 kb
Host smart-542273af-c9e2-4734-b2c4-7176cae9e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966037400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.966037400
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.1295422940
Short name T845
Test name
Test status
Simulation time 2812828926 ps
CPU time 6.69 seconds
Started Jul 21 06:34:26 PM PDT 24
Finished Jul 21 06:34:36 PM PDT 24
Peak memory 248004 kb
Host smart-6f249e3c-3371-4860-824c-5d3766bbfeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295422940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1295422940
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3686691174
Short name T859
Test name
Test status
Simulation time 538472663 ps
CPU time 15.83 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:46 PM PDT 24
Peak memory 241136 kb
Host smart-38cb50f2-c8b3-4955-bb82-e5bbbf7efbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686691174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3686691174
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2328636037
Short name T428
Test name
Test status
Simulation time 721408498 ps
CPU time 18.03 seconds
Started Jul 21 06:34:27 PM PDT 24
Finished Jul 21 06:34:48 PM PDT 24
Peak memory 241452 kb
Host smart-9f882e4e-f1b1-40ba-adf2-ba13297670a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328636037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2328636037
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.4163638145
Short name T458
Test name
Test status
Simulation time 271089001 ps
CPU time 6.38 seconds
Started Jul 21 06:34:26 PM PDT 24
Finished Jul 21 06:34:35 PM PDT 24
Peak memory 241304 kb
Host smart-903d1866-743f-4d50-826e-d51baa8598a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163638145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.4163638145
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1452353675
Short name T1009
Test name
Test status
Simulation time 2990531964 ps
CPU time 7.08 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:31 PM PDT 24
Peak memory 241356 kb
Host smart-de9f359c-fc2b-487e-b635-82a9b087ea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452353675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1452353675
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3768731727
Short name T506
Test name
Test status
Simulation time 241383758123 ps
CPU time 2507.13 seconds
Started Jul 21 06:34:27 PM PDT 24
Finished Jul 21 07:16:17 PM PDT 24
Peak memory 298568 kb
Host smart-02c75818-d92c-4fcf-95b1-d722d219c638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768731727 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3768731727
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.3491458035
Short name T1156
Test name
Test status
Simulation time 2133471469 ps
CPU time 34.48 seconds
Started Jul 21 06:34:27 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 241664 kb
Host smart-9d86bc46-0944-4593-9187-78aea4826931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491458035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.3491458035
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.799826830
Short name T841
Test name
Test status
Simulation time 327367628 ps
CPU time 4.94 seconds
Started Jul 21 06:36:20 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241412 kb
Host smart-72b5ddba-035e-415a-8a96-71dd26d1bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799826830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.799826830
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.37979677
Short name T396
Test name
Test status
Simulation time 182680132 ps
CPU time 3.56 seconds
Started Jul 21 06:36:21 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241644 kb
Host smart-a59d1720-5d1e-4fa4-8c24-43b5d585cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37979677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.37979677
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.1034557030
Short name T1094
Test name
Test status
Simulation time 229815096 ps
CPU time 4.28 seconds
Started Jul 21 06:36:17 PM PDT 24
Finished Jul 21 06:36:25 PM PDT 24
Peak memory 241156 kb
Host smart-faf462a9-dfa6-4d96-b8da-b315dffd6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034557030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1034557030
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2941236187
Short name T784
Test name
Test status
Simulation time 198701482 ps
CPU time 5 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:36:26 PM PDT 24
Peak memory 241440 kb
Host smart-8ba1b108-bf07-446c-b022-480a0bd66dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941236187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2941236187
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.915756486
Short name T879
Test name
Test status
Simulation time 538884287 ps
CPU time 4.76 seconds
Started Jul 21 06:36:19 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 241312 kb
Host smart-6d5e23a9-d04e-48a5-831f-6a320ede67a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915756486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.915756486
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.1824992925
Short name T338
Test name
Test status
Simulation time 502647277 ps
CPU time 5.6 seconds
Started Jul 21 06:36:22 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 241320 kb
Host smart-37721e7c-a726-4572-b0d2-5a49f0c19bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824992925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1824992925
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1425805091
Short name T1117
Test name
Test status
Simulation time 162248716201 ps
CPU time 364.56 seconds
Started Jul 21 06:36:23 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 264548 kb
Host smart-c979bd28-d756-40df-a9f5-77b468bd5a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425805091 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1425805091
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.442151479
Short name T1164
Test name
Test status
Simulation time 134373292 ps
CPU time 4 seconds
Started Jul 21 06:36:22 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241460 kb
Host smart-36106455-0104-4b15-b536-6a56ec00927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442151479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.442151479
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3217235894
Short name T232
Test name
Test status
Simulation time 304712814 ps
CPU time 17.19 seconds
Started Jul 21 06:36:18 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 241120 kb
Host smart-33454bca-47ad-454b-b3f7-aa33ef025c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217235894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3217235894
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3721123853
Short name T283
Test name
Test status
Simulation time 329311359642 ps
CPU time 2166.69 seconds
Started Jul 21 06:36:16 PM PDT 24
Finished Jul 21 07:12:27 PM PDT 24
Peak memory 272784 kb
Host smart-533ba80a-2627-444b-89bd-838ec8092ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721123853 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.3721123853
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.564392282
Short name T128
Test name
Test status
Simulation time 125505797 ps
CPU time 3.68 seconds
Started Jul 21 06:36:23 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 241432 kb
Host smart-cfc91ffe-4c72-4ddb-a916-fef608dcc24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564392282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.564392282
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1654389065
Short name T984
Test name
Test status
Simulation time 514083550 ps
CPU time 13.61 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241204 kb
Host smart-f26a603e-6eaa-47a6-bd9b-e59cb41a1bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654389065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1654389065
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1141362700
Short name T284
Test name
Test status
Simulation time 202361791061 ps
CPU time 865.57 seconds
Started Jul 21 06:36:29 PM PDT 24
Finished Jul 21 06:50:57 PM PDT 24
Peak memory 257384 kb
Host smart-0eeaebde-e4aa-4533-8a4c-18d69fe27dd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141362700 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1141362700
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3369929198
Short name T761
Test name
Test status
Simulation time 2079905968 ps
CPU time 5.1 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:34 PM PDT 24
Peak memory 241460 kb
Host smart-90a723aa-f1de-4250-acd2-1a986e582ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369929198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3369929198
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2194071242
Short name T544
Test name
Test status
Simulation time 448712371 ps
CPU time 12.53 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:41 PM PDT 24
Peak memory 241108 kb
Host smart-1e580544-38fa-4960-b069-f6fbc7fee96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194071242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2194071242
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.4102693975
Short name T278
Test name
Test status
Simulation time 64309991645 ps
CPU time 1656.6 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 432672 kb
Host smart-cfdb78c1-dfe0-4400-9e69-db738ad447e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102693975 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.4102693975
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.3404689150
Short name T1005
Test name
Test status
Simulation time 576535373 ps
CPU time 4.38 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:34 PM PDT 24
Peak memory 241692 kb
Host smart-9a1daa87-1f11-455f-9a07-531a44a8747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404689150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3404689150
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.670636262
Short name T822
Test name
Test status
Simulation time 50972017586 ps
CPU time 718.13 seconds
Started Jul 21 06:36:25 PM PDT 24
Finished Jul 21 06:48:24 PM PDT 24
Peak memory 256376 kb
Host smart-71ceddbf-441e-4c92-86f8-7f8e1c94dc4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670636262 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.670636262
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2520093571
Short name T742
Test name
Test status
Simulation time 185487496 ps
CPU time 9.18 seconds
Started Jul 21 06:36:26 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 241260 kb
Host smart-ca670ecf-ee57-4b54-bf6e-ceb84d64e9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520093571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2520093571
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.1622476682
Short name T630
Test name
Test status
Simulation time 105413871896 ps
CPU time 1577.35 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 391492 kb
Host smart-cc227edb-3f11-4b38-bf6b-c81cc1aad527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622476682 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.1622476682
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.107192560
Short name T61
Test name
Test status
Simulation time 2181774958 ps
CPU time 6.33 seconds
Started Jul 21 06:36:26 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241404 kb
Host smart-2eb41d86-3652-4c42-a43e-4db9fcdf4077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107192560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.107192560
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.493334630
Short name T971
Test name
Test status
Simulation time 209381514 ps
CPU time 7.63 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:37 PM PDT 24
Peak memory 241212 kb
Host smart-0b8f7bc6-b87e-408f-a569-5c465991050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493334630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.493334630
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.1607040296
Short name T516
Test name
Test status
Simulation time 238189567 ps
CPU time 4 seconds
Started Jul 21 06:36:26 PM PDT 24
Finished Jul 21 06:36:32 PM PDT 24
Peak memory 241156 kb
Host smart-42952ea8-c039-4b03-a686-a6393aaea0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607040296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1607040296
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3838053430
Short name T121
Test name
Test status
Simulation time 998361535 ps
CPU time 17.05 seconds
Started Jul 21 06:36:28 PM PDT 24
Finished Jul 21 06:36:47 PM PDT 24
Peak memory 241268 kb
Host smart-1992c50a-eaf1-4450-9e9a-76197626ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838053430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3838053430
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.4042926776
Short name T680
Test name
Test status
Simulation time 39493392678 ps
CPU time 804.64 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:49:57 PM PDT 24
Peak memory 270284 kb
Host smart-54107905-3aad-4cf0-9871-94186d192455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042926776 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.4042926776
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.347696123
Short name T416
Test name
Test status
Simulation time 90770596 ps
CPU time 2.14 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:33 PM PDT 24
Peak memory 239708 kb
Host smart-d90f537b-663d-42fc-827d-101eed8f4dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347696123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.347696123
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.825468211
Short name T1079
Test name
Test status
Simulation time 7327465718 ps
CPU time 56.87 seconds
Started Jul 21 06:34:26 PM PDT 24
Finished Jul 21 06:35:25 PM PDT 24
Peak memory 242108 kb
Host smart-c083ca3c-eed2-494f-a113-3d4a19d916bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825468211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.825468211
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.3772380035
Short name T122
Test name
Test status
Simulation time 13548727025 ps
CPU time 15.02 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:39 PM PDT 24
Peak memory 242268 kb
Host smart-2c5b69e0-d7a4-4177-bbba-cc6884013cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772380035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3772380035
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2723521302
Short name T707
Test name
Test status
Simulation time 16201575516 ps
CPU time 41.04 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 246092 kb
Host smart-185ee5fd-1541-4692-aee1-f4f62a914516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723521302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2723521302
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1280361134
Short name T667
Test name
Test status
Simulation time 7492631352 ps
CPU time 15.94 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:39 PM PDT 24
Peak memory 242144 kb
Host smart-30551436-26b7-45fc-abac-5ee18e6b1c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280361134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1280361134
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1215955190
Short name T1104
Test name
Test status
Simulation time 2325997913 ps
CPU time 28.17 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 248132 kb
Host smart-ab06d32d-339b-4ce0-96bc-4bb8f45e72cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215955190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1215955190
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.1847898601
Short name T979
Test name
Test status
Simulation time 1401731112 ps
CPU time 8.6 seconds
Started Jul 21 06:34:24 PM PDT 24
Finished Jul 21 06:34:35 PM PDT 24
Peak memory 248028 kb
Host smart-be48734e-0c98-424d-a592-00afe74cb963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847898601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1847898601
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.78975681
Short name T1007
Test name
Test status
Simulation time 646390249 ps
CPU time 18.17 seconds
Started Jul 21 06:34:25 PM PDT 24
Finished Jul 21 06:34:45 PM PDT 24
Peak memory 241140 kb
Host smart-e547440e-d267-4210-852e-1ed664811455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78975681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.78975681
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3435880289
Short name T645
Test name
Test status
Simulation time 1926834472 ps
CPU time 13.21 seconds
Started Jul 21 06:34:22 PM PDT 24
Finished Jul 21 06:34:37 PM PDT 24
Peak memory 247920 kb
Host smart-b328edc2-7270-405c-be23-af0a9fde8e07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435880289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3435880289
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.2256616450
Short name T112
Test name
Test status
Simulation time 494161724 ps
CPU time 4.15 seconds
Started Jul 21 06:34:27 PM PDT 24
Finished Jul 21 06:34:34 PM PDT 24
Peak memory 247412 kb
Host smart-0ae97da4-fc58-4630-8e8f-caf2d6df8e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256616450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2256616450
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.1414851146
Short name T265
Test name
Test status
Simulation time 5621613436 ps
CPU time 17.25 seconds
Started Jul 21 06:34:25 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 241280 kb
Host smart-a731dc95-3ed1-4fdc-9cce-7b4247b24a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414851146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1414851146
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3929320824
Short name T664
Test name
Test status
Simulation time 18509520523 ps
CPU time 129.96 seconds
Started Jul 21 06:34:27 PM PDT 24
Finished Jul 21 06:36:40 PM PDT 24
Peak memory 256324 kb
Host smart-981e913a-5100-45d6-ac2c-81992b169857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929320824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3929320824
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3695282777
Short name T378
Test name
Test status
Simulation time 6520436241 ps
CPU time 15.48 seconds
Started Jul 21 06:34:31 PM PDT 24
Finished Jul 21 06:34:49 PM PDT 24
Peak memory 242108 kb
Host smart-ed291d60-dd77-4a06-890a-a2b974b86146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695282777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3695282777
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1326368252
Short name T672
Test name
Test status
Simulation time 2336895853 ps
CPU time 7.83 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:36:37 PM PDT 24
Peak memory 241808 kb
Host smart-52df3e35-3344-421f-8e6a-2e69950631d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326368252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1326368252
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2299140849
Short name T1052
Test name
Test status
Simulation time 258087102 ps
CPU time 4.49 seconds
Started Jul 21 06:36:28 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241216 kb
Host smart-9b73c807-570b-4316-af54-292add0c3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299140849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2299140849
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.372569828
Short name T204
Test name
Test status
Simulation time 159677473 ps
CPU time 4.18 seconds
Started Jul 21 06:36:25 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 241264 kb
Host smart-c9accc3e-930c-4aa0-bac0-501dcf11b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372569828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.372569828
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3376465908
Short name T939
Test name
Test status
Simulation time 246374033 ps
CPU time 5.86 seconds
Started Jul 21 06:36:26 PM PDT 24
Finished Jul 21 06:36:34 PM PDT 24
Peak memory 241260 kb
Host smart-3e4d7299-a7e4-4d7c-968d-ab4f22812255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376465908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3376465908
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1343042268
Short name T17
Test name
Test status
Simulation time 109687148189 ps
CPU time 1168.78 seconds
Started Jul 21 06:36:27 PM PDT 24
Finished Jul 21 06:55:58 PM PDT 24
Peak memory 260492 kb
Host smart-3e20bbaf-2600-49de-8295-53f155297994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343042268 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1343042268
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.336506231
Short name T26
Test name
Test status
Simulation time 185989675 ps
CPU time 4.62 seconds
Started Jul 21 06:36:29 PM PDT 24
Finished Jul 21 06:36:36 PM PDT 24
Peak memory 241504 kb
Host smart-a91077b7-c086-4ead-bf87-2c5376a1498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336506231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.336506231
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.152214810
Short name T567
Test name
Test status
Simulation time 328379845 ps
CPU time 4.63 seconds
Started Jul 21 06:36:28 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241600 kb
Host smart-13c04450-e473-45ea-94c0-9e67623b5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152214810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.152214810
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.1908014096
Short name T38
Test name
Test status
Simulation time 29981042127 ps
CPU time 792.72 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:49:45 PM PDT 24
Peak memory 297332 kb
Host smart-d813107c-7baa-46b8-b3a3-d0c1c54782d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908014096 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.1908014096
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3821538169
Short name T1159
Test name
Test status
Simulation time 1754380082 ps
CPU time 3.78 seconds
Started Jul 21 06:36:26 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 241396 kb
Host smart-f4fe6630-a599-46f3-979f-ebd15d6c0b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821538169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3821538169
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3202132337
Short name T870
Test name
Test status
Simulation time 799237989 ps
CPU time 12.73 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:36:45 PM PDT 24
Peak memory 241680 kb
Host smart-97bf968d-983a-4d5a-ac3c-94c8b6374e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202132337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3202132337
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.4144768409
Short name T1166
Test name
Test status
Simulation time 469622843090 ps
CPU time 874.21 seconds
Started Jul 21 06:36:29 PM PDT 24
Finished Jul 21 06:51:06 PM PDT 24
Peak memory 329752 kb
Host smart-6568e915-2450-4c1d-abb3-75545e1b231e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144768409 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.4144768409
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3531992649
Short name T1030
Test name
Test status
Simulation time 254091649 ps
CPU time 5.21 seconds
Started Jul 21 06:36:33 PM PDT 24
Finished Jul 21 06:36:40 PM PDT 24
Peak memory 241704 kb
Host smart-ab9203a8-36dc-4bd7-81ea-ab72896980c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531992649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3531992649
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3540880796
Short name T576
Test name
Test status
Simulation time 100502073 ps
CPU time 3.94 seconds
Started Jul 21 06:36:31 PM PDT 24
Finished Jul 21 06:36:37 PM PDT 24
Peak memory 241504 kb
Host smart-7f878c2c-1af4-4fe4-b065-b759d871c77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540880796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3540880796
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3601420898
Short name T876
Test name
Test status
Simulation time 592701617227 ps
CPU time 1239.73 seconds
Started Jul 21 06:36:34 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 346488 kb
Host smart-2c9ba826-8faf-4fda-8b59-e7c9c4f64f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601420898 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3601420898
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.109407388
Short name T523
Test name
Test status
Simulation time 113359631 ps
CPU time 3.83 seconds
Started Jul 21 06:36:34 PM PDT 24
Finished Jul 21 06:36:39 PM PDT 24
Peak memory 241092 kb
Host smart-5f6e2ba1-e6f2-4f9e-8ee7-b721eb1c4f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109407388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.109407388
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1704466202
Short name T807
Test name
Test status
Simulation time 5023200586 ps
CPU time 16.72 seconds
Started Jul 21 06:36:29 PM PDT 24
Finished Jul 21 06:36:48 PM PDT 24
Peak memory 241328 kb
Host smart-c28bf4c9-751f-4595-bee4-75ad0202b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704466202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1704466202
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2359469985
Short name T152
Test name
Test status
Simulation time 36619164503 ps
CPU time 396.16 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 265668 kb
Host smart-65c70416-4282-44cd-8aff-61e03c3ba938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359469985 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.2359469985
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.3312874114
Short name T590
Test name
Test status
Simulation time 515875760 ps
CPU time 4.49 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:41 PM PDT 24
Peak memory 241548 kb
Host smart-de4304f4-8b06-463e-a13b-7a26a8f7223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312874114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3312874114
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3116117281
Short name T836
Test name
Test status
Simulation time 776424901 ps
CPU time 9.69 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:47 PM PDT 24
Peak memory 241192 kb
Host smart-ce7492cf-c532-437a-a279-621558abd96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116117281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3116117281
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3372825571
Short name T1046
Test name
Test status
Simulation time 245096015 ps
CPU time 3.56 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241276 kb
Host smart-b6994913-cddd-4b56-be87-83b8068fcb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372825571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3372825571
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.2200428503
Short name T623
Test name
Test status
Simulation time 938799244 ps
CPU time 6.75 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:47 PM PDT 24
Peak memory 241712 kb
Host smart-105e59cc-72bb-4431-8b7c-bf2405b1e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200428503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2200428503
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.4080839706
Short name T469
Test name
Test status
Simulation time 97984860235 ps
CPU time 1499.85 seconds
Started Jul 21 06:36:32 PM PDT 24
Finished Jul 21 07:01:34 PM PDT 24
Peak memory 319260 kb
Host smart-4cb049f0-558b-4c07-ad2c-bd73d7e6a7dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080839706 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.4080839706
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.720009030
Short name T1068
Test name
Test status
Simulation time 222862778 ps
CPU time 3.67 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:36:35 PM PDT 24
Peak memory 241396 kb
Host smart-417add6a-a1b9-4343-92c1-8ba15fae76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720009030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.720009030
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2740246162
Short name T595
Test name
Test status
Simulation time 2082508484 ps
CPU time 7.72 seconds
Started Jul 21 06:36:31 PM PDT 24
Finished Jul 21 06:36:41 PM PDT 24
Peak memory 241276 kb
Host smart-be68fd44-590d-4977-a3e4-7dd4565f81c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740246162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2740246162
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1033440285
Short name T337
Test name
Test status
Simulation time 49030274396 ps
CPU time 1068.97 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 317408 kb
Host smart-d8eadb82-2b7f-40fc-9555-1c3143e47892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033440285 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1033440285
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3301044614
Short name T775
Test name
Test status
Simulation time 292714202 ps
CPU time 4.33 seconds
Started Jul 21 06:36:31 PM PDT 24
Finished Jul 21 06:36:37 PM PDT 24
Peak memory 241488 kb
Host smart-79d2c6e1-2c08-4510-afc8-1cb0884bba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301044614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3301044614
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3920761518
Short name T1019
Test name
Test status
Simulation time 151794099 ps
CPU time 4.03 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:41 PM PDT 24
Peak memory 241528 kb
Host smart-01016be5-efbc-4819-a444-384f3f679eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920761518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3920761518
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3785308311
Short name T977
Test name
Test status
Simulation time 90222414518 ps
CPU time 1427.92 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 07:00:20 PM PDT 24
Peak memory 287732 kb
Host smart-12b554da-2d02-4e30-9dd4-6b1e9de6864d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785308311 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3785308311
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.4186200831
Short name T406
Test name
Test status
Simulation time 178200365 ps
CPU time 1.65 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:34:32 PM PDT 24
Peak memory 239900 kb
Host smart-9d515641-48f9-4ab1-9022-6547c07e4b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186200831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.4186200831
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1139079366
Short name T8
Test name
Test status
Simulation time 436147873 ps
CPU time 6.89 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:39 PM PDT 24
Peak memory 241316 kb
Host smart-3a08d5e5-d503-4b2e-9945-89217c3d6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139079366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1139079366
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2567982702
Short name T878
Test name
Test status
Simulation time 1022352661 ps
CPU time 10.16 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:42 PM PDT 24
Peak memory 243032 kb
Host smart-ad6902f4-6e37-4306-86ee-33cf6aac57bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567982702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2567982702
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2617474139
Short name T95
Test name
Test status
Simulation time 1118056624 ps
CPU time 18.79 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:51 PM PDT 24
Peak memory 241328 kb
Host smart-f66a50a7-f0fd-40d1-b263-1f27cbe1264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617474139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2617474139
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3770097911
Short name T706
Test name
Test status
Simulation time 2772323828 ps
CPU time 37.44 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:35:09 PM PDT 24
Peak memory 242556 kb
Host smart-c47fc955-a517-4c38-9683-71b574ac2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770097911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3770097911
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1978341596
Short name T835
Test name
Test status
Simulation time 144700997 ps
CPU time 3.76 seconds
Started Jul 21 06:34:31 PM PDT 24
Finished Jul 21 06:34:37 PM PDT 24
Peak memory 241380 kb
Host smart-8de24ce7-da8a-47d7-a2f0-eb4604122341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978341596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1978341596
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.1005222404
Short name T887
Test name
Test status
Simulation time 2187346327 ps
CPU time 27.06 seconds
Started Jul 21 06:34:31 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 246052 kb
Host smart-419a68b9-66fb-44e6-bf12-f8906a26033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005222404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1005222404
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2413392394
Short name T868
Test name
Test status
Simulation time 1340074207 ps
CPU time 9.99 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:41 PM PDT 24
Peak memory 247960 kb
Host smart-0e1dce8e-b5d8-48c9-a769-39383367f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413392394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2413392394
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.764363297
Short name T719
Test name
Test status
Simulation time 1186168032 ps
CPU time 11.86 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:44 PM PDT 24
Peak memory 241340 kb
Host smart-c1adf466-4ee2-41bb-94e2-d6d7c6ceb5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764363297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.764363297
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3963546304
Short name T1093
Test name
Test status
Simulation time 1211844719 ps
CPU time 17.9 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:50 PM PDT 24
Peak memory 241820 kb
Host smart-625bbc41-2f06-47b6-aa73-5b8d39b08f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963546304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3963546304
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1362672572
Short name T1055
Test name
Test status
Simulation time 1319108703 ps
CPU time 10.87 seconds
Started Jul 21 06:34:29 PM PDT 24
Finished Jul 21 06:34:43 PM PDT 24
Peak memory 241388 kb
Host smart-c062ff98-1d09-4f0c-8245-b57e0db1149c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362672572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1362672572
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.368626235
Short name T673
Test name
Test status
Simulation time 1293972920 ps
CPU time 8.84 seconds
Started Jul 21 06:34:30 PM PDT 24
Finished Jul 21 06:34:41 PM PDT 24
Peak memory 241612 kb
Host smart-1d4b92ad-a5d3-48eb-b04e-e3db6851cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368626235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.368626235
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.3882894799
Short name T998
Test name
Test status
Simulation time 87692302276 ps
CPU time 202.04 seconds
Started Jul 21 06:34:28 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 264400 kb
Host smart-7f334646-9bda-4b39-a88c-bfb3c7a53cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882894799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
3882894799
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.2232505951
Short name T560
Test name
Test status
Simulation time 23491106707 ps
CPU time 589.68 seconds
Started Jul 21 06:34:31 PM PDT 24
Finished Jul 21 06:44:23 PM PDT 24
Peak memory 256400 kb
Host smart-6513de88-56de-476b-9807-455aea96bce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232505951 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.2232505951
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.3906552572
Short name T93
Test name
Test status
Simulation time 1948486304 ps
CPU time 21.81 seconds
Started Jul 21 06:34:31 PM PDT 24
Finished Jul 21 06:34:55 PM PDT 24
Peak memory 241660 kb
Host smart-499a1010-04d8-4fa3-b264-c404eed4ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906552572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3906552572
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.1580084287
Short name T534
Test name
Test status
Simulation time 2455665568 ps
CPU time 4.81 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:36:36 PM PDT 24
Peak memory 241188 kb
Host smart-eb598e37-8152-4e4e-b48e-bffaac934c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580084287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1580084287
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3770331493
Short name T920
Test name
Test status
Simulation time 707722861 ps
CPU time 10.29 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:51 PM PDT 24
Peak memory 241304 kb
Host smart-aa602e4b-dccd-450e-9a65-0bf62cdeb4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770331493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3770331493
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3376239779
Short name T856
Test name
Test status
Simulation time 336329589721 ps
CPU time 461.43 seconds
Started Jul 21 06:36:31 PM PDT 24
Finished Jul 21 06:44:14 PM PDT 24
Peak memory 275668 kb
Host smart-436d2b2c-5008-43d8-a8af-ab77d378b460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376239779 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.3376239779
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.824780140
Short name T834
Test name
Test status
Simulation time 3042820361 ps
CPU time 11 seconds
Started Jul 21 06:36:33 PM PDT 24
Finished Jul 21 06:36:45 PM PDT 24
Peak memory 241316 kb
Host smart-782442f7-36d3-4c38-b9b1-bbaf45b318be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824780140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.824780140
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.1917373483
Short name T1113
Test name
Test status
Simulation time 228710897 ps
CPU time 4 seconds
Started Jul 21 06:36:39 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241276 kb
Host smart-acfe6a68-2f03-4385-a0ac-241be7892154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917373483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1917373483
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3927039132
Short name T336
Test name
Test status
Simulation time 208870870 ps
CPU time 4.62 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:36:37 PM PDT 24
Peak memory 241088 kb
Host smart-eef8ab97-6931-4803-8361-a663e82a8ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927039132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3927039132
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.3570768104
Short name T327
Test name
Test status
Simulation time 73328352327 ps
CPU time 293.8 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 264472 kb
Host smart-e5708a95-1afd-44dd-ba1e-015885845780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570768104 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.3570768104
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3997094361
Short name T785
Test name
Test status
Simulation time 170976477 ps
CPU time 3.76 seconds
Started Jul 21 06:36:38 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241500 kb
Host smart-81b1fc45-f800-41ab-9eff-ed0f55c3e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997094361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3997094361
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2528648164
Short name T181
Test name
Test status
Simulation time 193759980 ps
CPU time 5.34 seconds
Started Jul 21 06:36:35 PM PDT 24
Finished Jul 21 06:36:41 PM PDT 24
Peak memory 241192 kb
Host smart-2ab63042-ccdb-482a-a2fb-2a5e2fc0c016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528648164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2528648164
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3474546208
Short name T622
Test name
Test status
Simulation time 330727092129 ps
CPU time 2287.88 seconds
Started Jul 21 06:36:31 PM PDT 24
Finished Jul 21 07:14:41 PM PDT 24
Peak memory 283376 kb
Host smart-617efb37-572d-469d-be05-d01a196b3f47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474546208 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3474546208
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.2912852422
Short name T543
Test name
Test status
Simulation time 142013957 ps
CPU time 4.44 seconds
Started Jul 21 06:36:30 PM PDT 24
Finished Jul 21 06:36:36 PM PDT 24
Peak memory 241388 kb
Host smart-a4ffae46-2dfb-45f6-a1e3-21e8e1847418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912852422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2912852422
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.3698011482
Short name T381
Test name
Test status
Simulation time 690727796 ps
CPU time 10 seconds
Started Jul 21 06:36:33 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241668 kb
Host smart-fc9f309a-3109-4a95-b38c-9f58287e9321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698011482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3698011482
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1014355304
Short name T1095
Test name
Test status
Simulation time 364671035969 ps
CPU time 693.25 seconds
Started Jul 21 06:36:35 PM PDT 24
Finished Jul 21 06:48:10 PM PDT 24
Peak memory 272832 kb
Host smart-0dabc299-a365-46c9-8966-c2944b48d706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014355304 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.1014355304
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3599779554
Short name T218
Test name
Test status
Simulation time 121081023 ps
CPU time 4.1 seconds
Started Jul 21 06:36:33 PM PDT 24
Finished Jul 21 06:36:38 PM PDT 24
Peak memory 241388 kb
Host smart-bcca7b95-bd68-4c1b-9e9f-5eee08ae332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599779554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3599779554
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2948981834
Short name T1170
Test name
Test status
Simulation time 8853273338 ps
CPU time 19.54 seconds
Started Jul 21 06:36:35 PM PDT 24
Finished Jul 21 06:36:55 PM PDT 24
Peak memory 241248 kb
Host smart-8197407d-4741-4ee0-8fc1-398511bcb956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948981834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2948981834
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1924310449
Short name T465
Test name
Test status
Simulation time 376449852303 ps
CPU time 2208.76 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 07:13:27 PM PDT 24
Peak memory 563652 kb
Host smart-e71f0f27-1407-4ba8-aeb4-d4a205056e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924310449 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1924310449
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.793820204
Short name T170
Test name
Test status
Simulation time 218882377 ps
CPU time 4.15 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241788 kb
Host smart-1d6e7603-09d6-4362-8ea9-afbf8a837fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793820204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.793820204
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.533084403
Short name T393
Test name
Test status
Simulation time 1752139304 ps
CPU time 4.92 seconds
Started Jul 21 06:36:38 PM PDT 24
Finished Jul 21 06:36:45 PM PDT 24
Peak memory 241516 kb
Host smart-ad5a1dd2-0e1d-4570-997a-0d42b64533a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533084403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.533084403
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.4076534698
Short name T21
Test name
Test status
Simulation time 64782993189 ps
CPU time 1443.02 seconds
Started Jul 21 06:36:41 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 262344 kb
Host smart-8d358612-ea14-488d-bb8d-891d64231c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076534698 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.4076534698
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3267213288
Short name T178
Test name
Test status
Simulation time 203345779 ps
CPU time 3.87 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 241448 kb
Host smart-8e01f281-6f3f-4d87-bcde-eea763d567db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267213288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3267213288
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.1955813960
Short name T891
Test name
Test status
Simulation time 131114047 ps
CPU time 3.47 seconds
Started Jul 21 06:36:41 PM PDT 24
Finished Jul 21 06:36:46 PM PDT 24
Peak memory 241520 kb
Host smart-09d9b3d3-0d3c-4bfb-8ab0-674b89d5fd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955813960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1955813960
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1577777315
Short name T670
Test name
Test status
Simulation time 230390246 ps
CPU time 11.88 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 241248 kb
Host smart-9003f5cc-1ac4-498c-9d7d-4d11b2af39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577777315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1577777315
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.3540262701
Short name T328
Test name
Test status
Simulation time 10075691757 ps
CPU time 283.9 seconds
Started Jul 21 06:36:38 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 256372 kb
Host smart-2d2b6766-47a1-4d85-b1bf-1664cc9eddaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540262701 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.3540262701
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.1138605002
Short name T893
Test name
Test status
Simulation time 120080971 ps
CPU time 4.67 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:36:44 PM PDT 24
Peak memory 241416 kb
Host smart-ecffcf1a-d71e-4a52-a972-ca145d516a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138605002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1138605002
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.177605192
Short name T213
Test name
Test status
Simulation time 4653580577 ps
CPU time 10.78 seconds
Started Jul 21 06:36:36 PM PDT 24
Finished Jul 21 06:36:49 PM PDT 24
Peak memory 241576 kb
Host smart-b7eb2d16-e07d-4e8b-bffe-9a5178ecce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177605192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.177605192
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3697893843
Short name T656
Test name
Test status
Simulation time 219963638952 ps
CPU time 1374.87 seconds
Started Jul 21 06:36:37 PM PDT 24
Finished Jul 21 06:59:34 PM PDT 24
Peak memory 264448 kb
Host smart-f1b74511-a3d2-441a-b9b1-e633dffcc09d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697893843 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.3697893843
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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