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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10413 1 T1 6 T2 2 T3 3
true 16961 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11361 1 T1 6 T2 2 T3 3
true 17027 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T34 2 T94 2 T96 2
others[1] 90 1 T25 2 T89 2 T95 4
others[2] 86 1 T94 4 T104 2 T180 2
others[3] 92 1 T24 2 T34 4 T96 2
others[4] 112 1 T92 2 T94 6 T96 2
others[5] 106 1 T34 4 T94 6 T102 2
others[6] 92 1 T24 2 T34 2 T62 2
others[7] 140 1 T4 2 T34 2 T94 6
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T34 2 T94 2 T180 2
others[1] 106 1 T4 2 T94 2 T102 2
others[2] 84 1 T34 2 T94 2 T104 2
others[3] 60 1 T34 2 T94 2 T96 2
others[4] 96 1 T94 6 T95 2 T180 2
others[5] 118 1 T24 2 T94 10 T102 2
others[6] 96 1 T94 8 T96 4 T368 2
others[7] 122 1 T34 2 T94 2 T103 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T89 2 T94 4 T116 2
others[1] 72 1 T94 2 T128 2 T369 2
others[2] 106 1 T34 2 T94 2 T116 4
others[3] 110 1 T34 2 T94 4 T95 2
others[4] 96 1 T34 4 T94 4 T104 2
others[5] 88 1 T24 2 T62 2 T94 4
others[6] 92 1 T34 2 T94 4 T95 2
others[7] 110 1 T4 2 T34 2 T94 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 50 1 T94 4 T103 2 T96 2
others[1] 58 1 T94 4 T96 2 T192 2
others[2] 42 1 T180 4 T370 2 T371 4
others[3] 64 1 T34 4 T94 2 T128 2
others[4] 52 1 T242 2 T372 2 T373 4
others[5] 62 1 T34 2 T94 4 T297 2
others[6] 84 1 T94 2 T96 4 T178 2
others[7] 72 1 T94 6 T96 2 T128 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T25 2 T89 2 T34 2
others[1] 98 1 T94 4 T97 2 T180 2
others[2] 114 1 T24 2 T62 2 T94 2
others[3] 120 1 T89 2 T94 6 T99 4
others[4] 86 1 T92 2 T34 2 T94 2
others[5] 106 1 T34 4 T103 2 T180 2
others[6] 122 1 T57 2 T34 2 T94 6
others[7] 116 1 T24 2 T94 4 T96 4
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T94 2 T95 2 T192 2
others[1] 36 1 T89 2 T34 2 T94 2
others[2] 26 1 T25 2 T182 2 T60 2
others[3] 42 1 T24 2 T34 2 T94 2
others[4] 58 1 T94 4 T179 2 T374 2
others[5] 30 1 T24 2 T89 4 T347 2
others[6] 64 1 T34 2 T96 2 T179 2
others[7] 40 1 T128 2 T241 2 T347 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T4 2 T94 4 T96 4
others[1] 110 1 T34 4 T94 4 T96 4
others[2] 98 1 T89 2 T34 2 T94 6
others[3] 98 1 T94 4 T96 2 T180 4
others[4] 66 1 T34 2 T95 2 T99 2
others[5] 88 1 T62 2 T94 6 T97 2
others[6] 72 1 T34 2 T96 2 T182 2
others[7] 88 1 T94 2 T95 2 T98 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T34 2 T94 2 T96 2
others[1] 74 1 T24 2 T179 2 T180 2
others[2] 112 1 T34 2 T94 4 T104 2
others[3] 82 1 T94 4 T104 2 T99 2
others[4] 96 1 T89 2 T94 2 T96 2
others[5] 104 1 T24 2 T89 2 T34 2
others[6] 84 1 T34 2 T94 6 T103 2
others[7] 104 1 T25 2 T62 2 T94 6
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T25 2 T95 2 T96 4
others[1] 108 1 T34 4 T94 6 T116 2
others[2] 96 1 T57 2 T34 6 T94 4
others[3] 86 1 T94 2 T71 2 T96 4
others[4] 110 1 T25 2 T116 2 T96 2
others[5] 96 1 T4 2 T94 2 T104 2
others[6] 120 1 T92 2 T34 2 T94 2
others[7] 82 1 T89 2 T34 2 T94 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T34 2 T94 4 T95 2
others[1] 104 1 T94 6 T129 2 T96 2
others[2] 80 1 T34 2 T102 2 T95 2
others[3] 94 1 T94 2 T116 2 T104 2
others[4] 98 1 T95 2 T104 2 T192 2
others[5] 94 1 T25 4 T34 2 T94 6
others[6] 94 1 T24 2 T94 2 T96 4
others[7] 120 1 T89 2 T34 2 T94 6
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T94 2 T180 4 T369 2
others[1] 108 1 T34 2 T94 6 T96 2
others[2] 94 1 T34 2 T96 2 T128 4
others[3] 112 1 T34 2 T94 2 T182 2
others[4] 70 1 T89 2 T128 4 T130 2
others[5] 104 1 T89 2 T34 4 T94 4
others[6] 132 1 T89 2 T34 4 T94 6
others[7] 130 1 T94 6 T99 4 T155 2
false 14510 1 T1 6 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 29 1 T7 1 T32 1 T191 1
others[1] 29 1 T1 1 T215 1 T375 1
others[2] 39 1 T23 1 T9 2 T274 1
others[3] 30 1 T7 2 T8 2 T23 1
others[4] 29 1 T9 2 T274 2 T282 2
others[5] 35 1 T7 2 T8 1 T9 1
others[6] 25 1 T23 1 T278 1 T282 1
others[7] 47 1 T7 3 T8 1 T9 1
false 14510 1 T1 6 T2 4 T3 5
true 2356 1 T1 2 T3 2 T5 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 32 1 T7 1 T8 1 T9 2
others[1] 28 1 T7 2 T9 1 T94 2
others[2] 34 1 T9 1 T215 1 T282 2
others[3] 29 1 T1 1 T7 1 T8 1
others[4] 35 1 T7 2 T191 1 T274 1
others[5] 44 1 T7 1 T23 1 T32 1
others[6] 29 1 T8 2 T23 2 T9 2
others[7] 31 1 T7 1 T274 1 T286 1
false 11813 1 T1 6 T2 2 T3 4
true 19314 1 T1 8 T2 4 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 116 1 T25 2 T94 6 T96 2
others[1] 110 1 T89 2 T92 2 T94 2
others[2] 92 1 T94 6 T102 2 T96 2
others[3] 74 1 T24 2 T94 2 T95 2
others[4] 82 1 T24 2 T62 2 T94 2
others[5] 88 1 T34 4 T94 4 T96 2
others[6] 124 1 T4 2 T34 8 T95 2
others[7] 116 1 T34 2 T94 4 T96 4
false 7761 1 T1 6 T2 2 T3 4
true 17015 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T34 2 T96 4 T180 2
others[1] 82 1 T34 2 T94 6 T95 2
others[2] 102 1 T34 2 T94 6 T102 2
others[3] 90 1 T24 2 T102 2 T130 2
others[4] 110 1 T94 6 T96 6 T104 2
others[5] 108 1 T94 2 T95 2 T368 2
others[6] 102 1 T4 2 T94 6 T103 2
others[7] 94 1 T34 2 T94 8 T104 2
false 6960 1 T1 6 T2 2 T3 2
true 16793 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T94 2 T116 2 T96 2
others[1] 98 1 T34 2 T94 2 T104 2
others[2] 96 1 T94 4 T95 2 T97 2
others[3] 88 1 T34 2 T94 4 T178 2
others[4] 98 1 T34 2 T62 2 T94 4
others[5] 94 1 T24 2 T89 2 T96 2
others[6] 98 1 T34 2 T94 4 T96 2
others[7] 114 1 T4 2 T34 4 T94 6
false 7363 1 T1 6 T2 2 T3 3
true 16826 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 25 1 T8 1 T278 1 T298 1
others[1] 41 1 T7 1 T8 2 T34 2
others[2] 19 1 T278 1 T192 2 T375 1
others[3] 25 1 T7 3 T9 1 T211 1
others[4] 26 1 T9 1 T282 2 T375 1
others[5] 26 1 T32 1 T191 1 T278 1
others[6] 32 1 T8 1 T23 1 T9 2
others[7] 45 1 T7 2 T8 1 T9 3
false 11748 1 T1 6 T2 2 T3 4
true 19274 1 T1 8 T2 4 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 48 1 T94 2 T155 2 T376 2
others[1] 62 1 T34 2 T94 2 T96 2
others[2] 62 1 T34 2 T94 2 T178 2
others[3] 50 1 T94 4 T103 2 T96 2
others[4] 54 1 T96 2 T242 2 T261 2
others[5] 70 1 T94 4 T192 4 T193 2
others[6] 68 1 T94 6 T96 4 T180 2
others[7] 70 1 T34 2 T94 2 T242 2
false 9147 1 T1 6 T2 2 T3 4
true 17038 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 47 1 T7 1 T8 2 T9 2
others[1] 35 1 T7 1 T8 2 T23 2
others[2] 29 1 T7 1 T9 2 T282 1
others[3] 20 1 T23 1 T9 1 T282 1
others[4] 37 1 T8 1 T185 2 T274 2
others[5] 36 1 T1 2 T3 2 T9 1
others[6] 25 1 T9 2 T282 1 T375 1
others[7] 38 1 T7 2 T8 1 T23 1
false 11701 1 T1 6 T2 2 T3 4
true 19273 1 T1 8 T2 4 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T34 4 T94 2 T103 2
others[1] 110 1 T24 2 T94 2 T368 2
others[2] 84 1 T89 2 T94 2 T297 2
others[3] 110 1 T92 2 T34 2 T62 2
others[4] 110 1 T94 8 T96 2 T178 2
others[5] 88 1 T24 2 T89 2 T180 6
others[6] 96 1 T34 2 T94 2 T180 2
others[7] 140 1 T25 2 T57 2 T34 2
false 7712 1 T1 6 T2 2 T3 4
true 16951 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 29 1 T9 1 T274 1 T128 2
others[1] 34 1 T7 1 T25 2 T274 2
others[2] 27 1 T8 1 T23 1 T9 1
others[3] 38 1 T8 1 T9 2 T178 2
others[4] 29 1 T7 1 T23 1 T9 1
others[5] 26 1 T7 1 T8 1 T9 2
others[6] 29 1 T34 2 T141 2 T191 1
others[7] 32 1 T4 2 T9 1 T94 2
false 11665 1 T1 6 T2 2 T3 4
true 19219 1 T1 8 T2 4 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 40 1 T89 4 T377 2 T378 4
others[1] 38 1 T25 2 T34 2 T96 2
others[2] 54 1 T94 4 T192 2 T241 2
others[3] 36 1 T89 2 T179 2 T374 2
others[4] 44 1 T34 4 T94 2 T163 2
others[5] 28 1 T379 2 T380 2 T381 4
others[6] 46 1 T24 2 T94 4 T128 2
others[7] 48 1 T24 2 T95 2 T128 2
false 9988 1 T1 6 T2 2 T3 4
true 17019 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T34 2 T94 2 T95 2
others[1] 88 1 T94 4 T99 2 T179 2
others[2] 100 1 T94 4 T96 2 T97 2
others[3] 104 1 T34 2 T62 2 T95 2
others[4] 84 1 T34 4 T94 2 T257 2
others[5] 76 1 T89 2 T97 2 T128 4
others[6] 68 1 T34 2 T94 4 T182 2
others[7] 114 1 T4 2 T94 10 T96 6
false 7041 1 T1 6 T2 2 T3 2
true 16807 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T34 2 T94 4 T347 2
others[1] 88 1 T25 2 T62 2 T94 4
others[2] 98 1 T34 2 T94 4 T104 2
others[3] 92 1 T89 4 T96 2 T104 2
others[4] 88 1 T24 2 T94 4 T96 2
others[5] 98 1 T34 2 T94 2 T96 2
others[6] 92 1 T34 2 T94 4 T103 2
others[7] 88 1 T24 2 T94 2 T180 2
false 7041 1 T1 6 T2 2 T3 2
true 16807 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 116 1 T89 2 T34 2 T94 2
others[1] 94 1 T4 2 T57 2 T94 4
others[2] 84 1 T92 2 T34 2 T94 2
others[3] 100 1 T25 2 T71 2 T104 2
others[4] 98 1 T34 4 T94 6 T116 2
others[5] 106 1 T25 2 T34 2 T94 2
others[6] 98 1 T34 2 T280 2 T128 4
others[7] 88 1 T34 2 T94 2 T96 4
false 6483 1 T1 6 T2 1 T3 3
true 16797 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T94 2 T96 2 T104 2
others[1] 112 1 T24 2 T34 2 T94 2
others[2] 90 1 T94 6 T96 2 T180 2
others[3] 94 1 T25 2 T94 6 T129 2
others[4] 88 1 T25 2 T89 2 T34 6
others[5] 96 1 T94 2 T99 2 T128 2
others[6] 72 1 T94 2 T95 2 T96 2
others[7] 118 1 T94 6 T96 2 T104 2
false 6483 1 T1 6 T2 1 T3 3
true 16797 1 T1 7 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 54 1 T62 2 T94 2 T178 2
others[1] 52 1 T24 2 T34 4 T94 6
others[2] 74 1 T104 2 T128 2 T192 2
others[3] 64 1 T94 4 T96 2 T180 2
others[4] 76 1 T94 2 T179 2 T180 2
others[5] 76 1 T34 4 T94 2 T96 2
others[6] 52 1 T89 2 T94 2 T102 2
others[7] 80 1 T34 2 T96 2 T368 2
false 6970 1 T1 5 T2 1 T3 3
true 18281 1 T1 8 T2 4 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T25 2 T62 2 T94 2
others[1] 76 1 T94 2 T96 2 T276 4
others[2] 60 1 T24 2 T34 2 T94 4
others[3] 76 1 T34 2 T94 2 T116 2
others[4] 70 1 T89 2 T34 2 T95 2
others[5] 66 1 T24 2 T94 2 T128 2
others[6] 70 1 T24 2 T94 6 T97 2
others[7] 70 1 T24 2 T34 2 T94 4
false 6970 1 T1 5 T2 1 T3 3
true 18281 1 T1 8 T2 4 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T8 1 T23 1 T32 1
others[1] 21 1 T8 1 T274 2 T282 2
others[2] 33 1 T7 1 T8 1 T274 1
others[3] 28 1 T57 2 T9 1 T282 1
others[4] 30 1 T8 1 T9 1 T194 2
others[5] 39 1 T7 1 T8 1 T23 1
others[6] 25 1 T191 1 T116 2 T282 1
others[7] 52 1 T3 2 T7 2 T8 2
false 11893 1 T1 6 T2 3 T3 4
true 19383 1 T1 8 T2 5 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T94 2 T180 2 T257 2
others[1] 104 1 T89 2 T94 4 T116 2
others[2] 118 1 T94 6 T104 2 T182 2
others[3] 96 1 T89 4 T34 8 T94 2
others[4] 104 1 T34 2 T96 2 T99 2
others[5] 118 1 T34 2 T94 4 T96 2
others[6] 80 1 T94 4 T182 2 T371 2
others[7] 116 1 T34 2 T94 4 T96 2
false 7716 1 T1 6 T2 3 T3 2
true 16993 1 T1 7 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T282 2 T375 2 T382 1
others[1] 31 1 T8 2 T9 1 T282 1
others[2] 31 1 T7 1 T32 1 T34 2
others[3] 31 1 T9 2 T191 1 T339 1
others[4] 32 1 T7 1 T8 1 T23 1
others[5] 24 1 T9 2 T274 1 T278 1
others[6] 35 1 T7 3 T9 1 T180 2
others[7] 29 1 T7 1 T8 2 T9 1
false 14510 1 T1 6 T2 4 T3 5
true 2366 1 T1 2 T3 1 T5 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%