Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_0_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_0_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_0_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_0_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12608

1

T1

16

T3

2

T4

10

auto[1]

766

1

T7

3

T89

8

T34

13

---

Summary for Variable sram_0_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12472

1

T1

16

T3

2

T4

10

auto[1]

902

1

T7

5

T8

3

T89

5

---

Summary for Variable sram_0_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_0_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13342

1

T1

16

T3

2

T4

10

lc_esc_on

32

1

T16

1

T32

1

T226

1

---

Summary for Variable sram_0_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12675

1

T1

16

T3

2

T4

10

auto[1]

699

1

T7

5

T8

2

T89

5

---

Summary for Variable sram_0_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2286

1

T16

1

T24

10

T7

7

auto[1]

11088

1

T1

16

T3

2

T4

10

---

Summary for Variable sram_0_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10848

1

T1

8

T3

1

T4

10

auto[1]

2526

1

T1

8

T3

1

T16

1