Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47235	1			T5	59		T12	45		T55	198
access_err	60377	1			T2	14		T5	196		T11	13
write_blank_err	465	1			T9	7		T10	5		T183	6
ecc_uncorr_err	60847	1			T4	40		T9	1254		T10	1281
ecc_corr_err	1107	1			T4	3		T31	15		T115	9
no_err	90678	1			T2	49		T8	1		T4	6

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	873	1			T9	3		T10	5		T15	5
secret2	24954	1			T2	15		T4	2		T5	62
secret1	32077	1			T2	6		T4	3		T5	68
secret0	36710	1			T2	1		T8	1		T5	78
hw_cfg1	29022	1			T2	3		T4	41		T5	63
hw_cfg0	24023	1			T2	4		T5	64		T11	12
rot_creator_auth_state	21994	1			T2	11		T5	74		T11	8
rot_creator_auth_codesign	19850	1			T2	7		T5	95		T11	14
owner_sw_cfg	21100	1			T2	8		T4	2		T5	136
creator_sw_cfg	20420	1			T2	6		T5	96		T11	10
vendor_test	29686	1			T2	2		T4	1		T5	103

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2619	1			T73	37		T14	394		T19	31
fsm_err	secret1	7164	1			T12	45		T55	198		T215	154
fsm_err	secret0	3572	1			T10	149		T343	81		T255	11
fsm_err	hw_cfg1	2968	1			T113	79		T341	204		T293	62
fsm_err	hw_cfg0	5437	1			T344	40		T280	25		T294	73
fsm_err	rot_creator_auth_state	3955	1			T214	54		T196	25		T273	167
fsm_err	rot_creator_auth_codesign	2392	1			T73	3		T196	27		T197	55
fsm_err	owner_sw_cfg	3388	1			T5	59		T107	262		T249	330
fsm_err	creator_sw_cfg	3180	1			T243	188		T150	2		T345	123
fsm_err	vendor_test	12560	1			T9	192		T114	2		T31	118
access_err	life_cycle	873	1			T9	3		T10	5		T15	5
access_err	secret2	10529	1			T5	17		T30	4		T9	75
access_err	secret1	5998	1			T30	17		T9	38		T10	71
access_err	secret0	4659	1			T5	2		T11	2		T30	20
access_err	hw_cfg1	1270	1			T5	8		T30	3		T9	22
access_err	hw_cfg0	2178	1			T30	1		T9	7		T10	21
access_err	rot_creator_auth_state	5580	1			T5	31		T6	2		T30	14
access_err	rot_creator_auth_codesign	7474	1			T2	7		T5	47		T11	4
access_err	owner_sw_cfg	6747	1			T2	6		T5	26		T11	2
access_err	creator_sw_cfg	7885	1			T5	32		T11	5		T30	23
access_err	vendor_test	7184	1			T2	1		T5	33		T30	25
write_blank_err	secret2	15	1			T129	1		T346	1		T85	1
write_blank_err	secret1	22	1			T10	1		T101	1		T129	1
write_blank_err	secret0	60	1			T9	3		T10	1		T15	1
write_blank_err	hw_cfg1	56	1			T183	1		T253	1		T254	1
write_blank_err	hw_cfg0	13	1			T252	1		T254	1		T347	1
write_blank_err	rot_creator_auth_state	148	1			T9	1		T245	1		T348	3
write_blank_err	rot_creator_auth_codesign	67	1			T10	3		T183	5		T254	1
write_blank_err	owner_sw_cfg	39	1			T252	1		T253	6		T20	4
write_blank_err	creator_sw_cfg	18	1			T9	3		T20	4		T349	1
write_blank_err	vendor_test	27	1			T348	1		T254	4		T350	1
ecc_uncorr_err	secret2	6235	1			T141	78		T351	29		T346	601
ecc_uncorr_err	secret1	9981	1			T10	574		T101	385		T129	320
ecc_uncorr_err	secret0	19880	1			T9	1254		T10	707		T15	148
ecc_uncorr_err	hw_cfg1	13994	1			T4	40		T183	233		T151	3
ecc_uncorr_err	hw_cfg0	3995	1			T116	7		T141	74		T151	4
ecc_uncorr_err	rot_creator_auth_state	3475	1			T116	4		T245	711		T141	62
ecc_uncorr_err	rot_creator_auth_codesign	1089	1			T116	4		T352	56		T353	20
ecc_uncorr_err	owner_sw_cfg	1340	1			T152	38		T214	98		T197	113
ecc_uncorr_err	creator_sw_cfg	858	1			T116	8		T196	26		T193	30
ecc_corr_err	secret2	70	1			T4	1		T115	1		T116	1
ecc_corr_err	secret1	94	1			T116	1		T79	5		T141	1
ecc_corr_err	secret0	140	1			T115	2		T116	2		T141	5
ecc_corr_err	hw_cfg1	233	1			T31	2		T115	1		T116	1
ecc_corr_err	hw_cfg0	164	1			T31	3		T115	3		T72	1
ecc_corr_err	rot_creator_auth_state	120	1			T31	2		T115	2		T41	7
ecc_corr_err	rot_creator_auth_codesign	86	1			T31	3		T79	1		T141	4
ecc_corr_err	owner_sw_cfg	86	1			T4	2		T31	3		T116	1
ecc_corr_err	creator_sw_cfg	114	1			T31	2		T116	1		T141	2
no_err	secret2	5486	1			T2	15		T4	1		T5	45
no_err	secret1	8818	1			T2	6		T4	3		T5	68
no_err	secret0	8399	1			T2	1		T8	1		T5	76
no_err	hw_cfg1	10501	1			T2	3		T4	1		T5	55
no_err	hw_cfg0	12236	1			T2	4		T5	64		T11	12
no_err	rot_creator_auth_state	8716	1			T2	11		T5	43		T11	8
no_err	rot_creator_auth_codesign	8742	1			T5	48		T11	10		T6	1
no_err	owner_sw_cfg	9500	1			T2	2		T5	51		T11	2
no_err	creator_sw_cfg	8365	1			T2	6		T5	64		T11	5
no_err	vendor_test	9915	1			T2	1		T4	1		T5	70

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded