dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 9724 1 T1 8 T2 2 T3 9
true 16023 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10571 1 T1 11 T2 2 T3 9
true 16074 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T1 2 T28 2 T94 4
others[1] 68 1 T124 2 T118 2 T176 2
others[2] 64 1 T7 4 T200 2 T247 2
others[3] 94 1 T97 2 T118 2 T247 2
others[4] 88 1 T72 2 T118 2 T365 2
others[5] 102 1 T28 2 T92 4 T74 2
others[6] 76 1 T7 4 T100 2 T200 2
others[7] 64 1 T7 2 T116 2 T118 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T93 2 T96 2 T118 6
others[1] 126 1 T7 2 T100 2 T116 4
others[2] 88 1 T3 2 T7 2 T93 2
others[3] 86 1 T7 6 T94 2 T74 2
others[4] 94 1 T99 2 T118 4 T366 2
others[5] 84 1 T3 2 T7 2 T115 2
others[6] 92 1 T3 2 T98 2 T94 2
others[7] 94 1 T3 2 T28 2 T7 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T118 2 T271 2 T247 2
others[1] 84 1 T7 2 T118 2 T271 2
others[2] 80 1 T95 2 T96 2 T115 2
others[3] 94 1 T3 2 T92 2 T99 4
others[4] 70 1 T51 2 T118 2 T271 2
others[5] 70 1 T28 2 T72 2 T115 4
others[6] 78 1 T1 2 T7 2 T74 2
others[7] 98 1 T1 2 T7 4 T74 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 42 1 T7 2 T367 2 T368 2
others[1] 46 1 T92 2 T93 2 T94 2
others[2] 42 1 T118 2 T366 2 T338 2
others[3] 40 1 T7 2 T94 2 T96 2
others[4] 64 1 T7 2 T97 2 T118 2
others[5] 46 1 T116 2 T271 2 T183 2
others[6] 46 1 T94 2 T118 4 T369 2
others[7] 56 1 T93 2 T74 2 T174 4
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T3 2 T100 4 T74 2
others[1] 92 1 T93 2 T100 2 T115 2
others[2] 72 1 T200 2 T118 2 T370 2
others[3] 96 1 T1 2 T92 2 T118 4
others[4] 92 1 T28 2 T96 2 T116 2
others[5] 66 1 T116 6 T247 2 T199 4
others[6] 70 1 T7 4 T72 2 T97 2
others[7] 80 1 T7 2 T200 2 T116 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 30 1 T7 4 T116 2 T176 2
others[1] 36 1 T175 2 T197 2 T198 2
others[2] 34 1 T7 2 T95 2 T248 2
others[3] 24 1 T7 2 T175 2 T197 2
others[4] 42 1 T3 2 T198 2 T329 2
others[5] 38 1 T3 4 T7 4 T95 2
others[6] 46 1 T116 2 T118 2 T197 2
others[7] 36 1 T3 2 T116 4 T371 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T94 2 T197 2 T198 4
others[1] 92 1 T7 2 T96 2 T116 4
others[2] 84 1 T7 2 T372 2 T183 2
others[3] 90 1 T7 4 T95 2 T96 2
others[4] 130 1 T3 2 T7 2 T95 4
others[5] 88 1 T1 2 T7 2 T92 2
others[6] 90 1 T93 2 T118 4 T198 4
others[7] 114 1 T1 2 T93 2 T95 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 52 1 T7 4 T373 2 T198 2
others[1] 84 1 T98 2 T115 2 T118 4
others[2] 58 1 T7 4 T74 2 T370 2
others[3] 84 1 T1 2 T7 2 T74 2
others[4] 78 1 T93 2 T271 2 T365 2
others[5] 76 1 T7 4 T95 2 T116 4
others[6] 72 1 T7 2 T94 2 T116 6
others[7] 112 1 T7 4 T92 2 T116 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T3 2 T7 6 T99 2
others[1] 80 1 T67 2 T7 4 T115 2
others[2] 98 1 T7 4 T116 4 T198 2
others[3] 84 1 T28 2 T51 2 T74 2
others[4] 76 1 T93 2 T116 4 T118 2
others[5] 52 1 T100 2 T118 2 T271 2
others[6] 64 1 T7 2 T94 2 T95 2
others[7] 94 1 T94 2 T74 2 T96 4
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T28 2 T67 2 T7 6
others[1] 90 1 T7 6 T124 2 T95 2
others[2] 90 1 T51 2 T74 2 T118 2
others[3] 74 1 T7 2 T100 4 T124 2
others[4] 84 1 T7 4 T93 2 T95 2
others[5] 72 1 T1 2 T51 2 T7 4
others[6] 96 1 T92 4 T115 2 T97 2
others[7] 74 1 T7 2 T94 2 T118 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T51 4 T200 2 T118 2
others[1] 82 1 T7 2 T99 4 T94 2
others[2] 84 1 T1 2 T3 2 T51 2
others[3] 90 1 T1 2 T28 2 T93 2
others[4] 94 1 T7 2 T94 2 T116 2
others[5] 78 1 T74 2 T95 2 T96 2
others[6] 96 1 T7 6 T93 2 T74 2
others[7] 76 1 T7 2 T176 2 T197 2
false 13593 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 35 1 T1 2 T3 2 T13 2
others[1] 36 1 T15 1 T17 1 T326 1
others[2] 40 1 T97 2 T118 2 T374 1
others[3] 23 1 T202 2 T234 1 T110 2
others[4] 32 1 T6 1 T202 1 T183 2
others[5] 31 1 T3 2 T51 2 T7 2
others[6] 37 1 T6 1 T96 2 T17 1
others[7] 31 1 T6 1 T17 1 T202 1
false 13593 1 T1 12 T2 4 T3 18
true 2102 1 T1 2 T3 7 T6 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 35 1 T51 2 T14 1 T17 1
others[1] 39 1 T7 2 T202 1 T272 1
others[2] 35 1 T3 2 T6 1 T118 2
others[3] 24 1 T3 2 T6 1 T96 2
others[4] 29 1 T97 2 T17 1 T202 1
others[5] 33 1 T1 2 T13 1 T15 1
others[6] 28 1 T6 1 T17 1 T202 1
others[7] 42 1 T13 1 T15 1 T17 1
false 11065 1 T1 11 T2 3 T3 9
true 18120 1 T1 14 T2 5 T3 25


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T7 2 T94 4 T115 2
others[1] 64 1 T7 2 T92 2 T74 2
others[2] 84 1 T1 2 T28 2 T7 4
others[3] 86 1 T28 2 T92 2 T72 2
others[4] 62 1 T100 2 T96 2 T97 2
others[5] 52 1 T118 2 T324 2 T372 2
others[6] 108 1 T7 2 T200 4 T118 2
others[7] 110 1 T124 2 T118 4 T247 2
false 7703 1 T1 1 T2 3 T3 2
true 16144 1 T1 12 T2 5 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 106 1 T3 2 T92 2 T94 2
others[1] 88 1 T3 2 T93 2 T97 4
others[2] 98 1 T7 4 T116 4 T199 2
others[3] 102 1 T3 2 T7 2 T74 2
others[4] 78 1 T98 2 T100 2 T94 2
others[5] 78 1 T3 2 T28 2 T7 2
others[6] 82 1 T7 2 T116 2 T174 2
others[7] 116 1 T7 4 T118 12 T370 4
false 6727 1 T1 1 T2 2 T3 1
true 15917 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T115 2 T44 2 T197 2
others[1] 56 1 T74 2 T97 2 T199 2
others[2] 66 1 T118 2 T271 2 T247 2
others[3] 90 1 T1 2 T28 2 T93 2
others[4] 98 1 T1 2 T7 2 T99 4
others[5] 78 1 T3 2 T7 2 T92 2
others[6] 92 1 T51 2 T7 4 T94 2
others[7] 100 1 T96 2 T200 2 T118 2
false 7162 1 T1 1 T2 2 T3 1
true 15930 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 25 1 T93 2 T197 2 T18 1
others[1] 35 1 T13 1 T118 2 T37 2
others[2] 24 1 T13 1 T202 1 T37 2
others[3] 26 1 T3 2 T272 1 T239 1
others[4] 22 1 T367 2 T239 1 T314 1
others[5] 32 1 T100 2 T17 1 T19 1
others[6] 24 1 T14 1 T17 1 T141 2
others[7] 36 1 T202 2 T223 1 T19 1
false 11003 1 T1 11 T2 3 T3 9
true 18095 1 T1 16 T2 5 T3 24


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T94 2 T97 2 T370 2
others[1] 46 1 T93 2 T271 2 T375 2
others[2] 42 1 T7 2 T118 2 T366 2
others[3] 50 1 T376 2 T52 2 T337 8
others[4] 64 1 T7 4 T94 2 T118 6
others[5] 50 1 T93 2 T96 2 T116 2
others[6] 44 1 T92 2 T74 2 T377 2
others[7] 50 1 T94 2 T174 2 T271 2
false 8734 1 T1 1 T2 3 T3 9
true 16120 1 T1 12 T2 5 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T18 1 T37 1 T19 1
others[1] 32 1 T6 1 T245 2 T202 1
others[2] 23 1 T15 1 T17 2 T202 1
others[3] 39 1 T118 2 T223 1 T378 2
others[4] 20 1 T93 2 T14 1 T15 1
others[5] 26 1 T15 1 T17 1 T266 1
others[6] 43 1 T74 2 T379 2 T37 1
others[7] 43 1 T93 2 T202 1 T37 2
false 10950 1 T1 11 T2 2 T3 9
true 18031 1 T1 17 T2 4 T3 24


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T7 2 T100 2 T200 2
others[1] 96 1 T7 2 T93 2 T116 2
others[2] 82 1 T92 2 T118 2 T271 4
others[3] 86 1 T1 2 T3 2 T72 2
others[4] 80 1 T7 2 T100 2 T116 2
others[5] 62 1 T372 2 T376 2 T366 2
others[6] 84 1 T100 2 T74 2 T96 2
others[7] 100 1 T28 2 T97 2 T200 2
false 7587 1 T1 1 T2 2 T3 2
true 16074 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 31 1 T367 2 T18 1 T37 1
others[1] 38 1 T17 1 T202 2 T118 4
others[2] 37 1 T74 2 T15 2 T118 2
others[3] 23 1 T95 2 T15 1 T202 1
others[4] 23 1 T72 2 T116 2 T202 3
others[5] 29 1 T13 1 T202 1 T378 2
others[6] 29 1 T13 1 T15 1 T18 1
others[7] 34 1 T13 1 T14 1 T202 1
false 10896 1 T1 11 T2 2 T3 9
true 18022 1 T1 17 T2 4 T3 24


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T3 2 T175 2 T198 2
others[1] 44 1 T118 2 T380 2 T381 2
others[2] 34 1 T3 2 T7 2 T95 2
others[3] 26 1 T3 2 T7 2 T366 2
others[4] 26 1 T7 2 T116 4 T382 2
others[5] 34 1 T3 2 T197 4 T248 2
others[6] 40 1 T7 4 T95 2 T116 2
others[7] 46 1 T7 2 T116 2 T197 2
false 9459 1 T1 11 T2 2 T3 1
true 16092 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T7 2 T74 2 T197 2
others[1] 74 1 T3 2 T118 6 T365 2
others[2] 98 1 T1 2 T7 2 T94 2
others[3] 94 1 T7 4 T93 2 T118 4
others[4] 98 1 T176 2 T30 2 T197 2
others[5] 92 1 T93 2 T74 2 T96 2
others[6] 84 1 T268 2 T116 2 T367 2
others[7] 122 1 T1 2 T7 4 T92 2
false 6883 1 T1 1 T2 2 T3 1
true 15911 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T98 2 T94 2 T116 4
others[1] 70 1 T7 4 T95 2 T115 2
others[2] 98 1 T7 6 T93 2 T74 2
others[3] 80 1 T1 2 T7 4 T74 2
others[4] 78 1 T118 2 T247 2 T367 2
others[5] 70 1 T370 2 T198 2 T145 2
others[6] 62 1 T7 4 T118 2 T197 2
others[7] 88 1 T7 2 T92 2 T116 4
false 6883 1 T1 1 T2 2 T3 1
true 15911 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T94 4 T95 2 T198 2
others[1] 70 1 T7 4 T93 2 T116 2
others[2] 58 1 T7 4 T96 2 T133 2
others[3] 106 1 T7 6 T99 2 T271 2
others[4] 62 1 T100 2 T116 2 T370 2
others[5] 80 1 T74 2 T97 2 T133 2
others[6] 74 1 T3 2 T96 2 T268 2
others[7] 104 1 T28 2 T51 2 T67 2
false 6269 1 T1 5 T2 1 T3 1
true 15907 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T94 2 T74 2 T124 4
others[1] 84 1 T7 2 T92 2 T118 2
others[2] 84 1 T51 2 T7 10 T100 2
others[3] 78 1 T67 2 T7 2 T116 2
others[4] 80 1 T1 2 T7 2 T92 2
others[5] 82 1 T7 2 T92 2 T94 2
others[6] 70 1 T28 2 T51 2 T93 2
others[7] 94 1 T7 6 T100 2 T115 2
false 6269 1 T1 5 T2 1 T3 1
true 15907 1 T1 12 T2 4 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T7 2 T92 2 T74 2
others[1] 56 1 T7 2 T94 2 T118 2
others[2] 54 1 T93 2 T95 4 T133 4
others[3] 54 1 T116 2 T183 4 T329 2
others[4] 44 1 T1 2 T3 2 T100 2
others[5] 56 1 T3 2 T96 2 T116 2
others[6] 54 1 T74 2 T72 2 T118 2
others[7] 60 1 T7 2 T96 2 T118 4
false 6745 1 T1 2 T2 1 T3 3
true 17229 1 T1 12 T2 4 T3 20


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T7 2 T92 2 T96 2
others[1] 70 1 T3 2 T7 2 T116 2
others[2] 70 1 T1 2 T93 2 T96 2
others[3] 50 1 T95 2 T133 2 T118 2
others[4] 84 1 T3 2 T118 2 T176 2
others[5] 64 1 T7 2 T133 2 T116 4
others[6] 78 1 T7 4 T100 2 T94 2
others[7] 54 1 T7 2 T383 2 T183 2
false 6745 1 T1 2 T2 1 T3 3
true 17229 1 T1 12 T2 4 T3 20


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 41 1 T14 1 T116 2 T202 2
others[1] 30 1 T51 2 T13 2 T384 2
others[2] 28 1 T15 1 T118 2 T110 2
others[3] 29 1 T17 1 T18 2 T272 1
others[4] 42 1 T3 2 T202 1 T272 2
others[5] 24 1 T13 1 T14 1 T17 1
others[6] 22 1 T202 2 T118 2 T37 1
others[7] 39 1 T18 1 T37 2 T326 1
false 11146 1 T1 11 T2 3 T3 9
true 18171 1 T1 16 T2 5 T3 23


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 62 1 T99 2 T116 2 T118 2
others[1] 84 1 T51 4 T7 2 T95 4
others[2] 72 1 T28 2 T7 2 T93 2
others[3] 74 1 T1 2 T99 2 T200 2
others[4] 94 1 T7 2 T94 2 T96 2
others[5] 90 1 T51 2 T74 2 T271 2
others[6] 110 1 T7 6 T92 2 T74 2
others[7] 118 1 T1 2 T3 2 T93 2
false 7619 1 T1 1 T2 3 T3 3
true 16105 1 T1 12 T2 5 T3 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 33 1 T13 1 T100 2 T197 2
others[1] 39 1 T93 2 T202 1 T118 2
others[2] 29 1 T3 2 T14 1 T141 2
others[3] 27 1 T13 1 T17 1 T202 1
others[4] 24 1 T239 2 T329 2 T214 1
others[5] 17 1 T202 1 T223 1 T266 1
others[6] 22 1 T17 1 T19 1 T272 2
others[7] 34 1 T18 1 T19 1 T239 1
false 13593 1 T1 12 T2 4 T3 18
true 2127 1 T1 4 T3 6 T9 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%