SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 0 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
otbn_req_during_flash_addr_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_flash_data_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
otbn_req_during_otp_idle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_sram_0_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_sram_1_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12061 | 1 | T1 | 6 | T3 | 20 | T8 | 2 | ||||
auto[1] | 941 | 1 | T7 | 10 | T92 | 6 | T13 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 11892 | 1 | T1 | 6 | T3 | 20 | T8 | 2 | ||||
auto[1] | 1110 | 1 | T7 | 13 | T92 | 6 | T13 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lc_esc_off | 12970 | 1 | T1 | 6 | T3 | 20 | T8 | 2 | ||||
lc_esc_on | 32 | 1 | T6 | 2 | T329 | 1 | T387 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2443 | 1 | T1 | 2 | T8 | 1 | T6 | 4 | ||||
auto[1] | 10559 | 1 | T1 | 4 | T3 | 20 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 11853 | 1 | T1 | 6 | T3 | 20 | T8 | 2 | ||||
auto[1] | 1149 | 1 | T7 | 16 | T92 | 14 | T13 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12513 | 1 | T1 | 6 | T3 | 20 | T8 | 2 | ||||
auto[1] | 489 | 1 | T7 | 10 | T92 | 10 | T13 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |