Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_0_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_0_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_0_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_0_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12322 1 T1 6 T3 20 T4 6
auto[1] 912 1 T7 12 T92 12 T13 3



Summary for Variable sram_0_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12247 1 T1 6 T3 20 T4 6
auto[1] 987 1 T7 18 T92 7 T13 2



Summary for Variable sram_0_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_0_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13206 1 T1 6 T3 20 T4 6
lc_esc_on 28 1 T90 1 T7 1 T169 1



Summary for Variable sram_0_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12258 1 T1 6 T3 20 T4 6
auto[1] 976 1 T7 17 T92 14 T13 4



Summary for Variable sram_0_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2162 1 T90 1 T51 2 T7 56
auto[1] 11072 1 T1 6 T3 20 T4 6



Summary for Variable sram_0_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11010 1 T1 3 T3 20 T4 3
auto[1] 2224 1 T1 3 T4 3 T12 1

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