Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50547	1			T8	29		T9	243		T29	308
access_err	56389	1			T1	121		T3	151		T5	4
write_blank_err	491	1			T5	4		T91	4		T173	2
ecc_uncorr_err	75764	1			T5	566		T91	142		T173	279
ecc_corr_err	1311	1			T5	1		T173	1		T67	41
no_err	82783	1			T1	148		T3	150		T5	27

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	812	1			T5	4		T7	12		T15	4
secret2	21815	1			T1	26		T3	34		T9	3
secret1	26805	1			T1	24		T3	28		T5	4
secret0	34385	1			T1	27		T3	25		T5	2
hw_cfg1	41881	1			T1	26		T3	24		T5	572
hw_cfg0	28017	1			T1	27		T3	28		T5	4
rot_creator_auth_state	22259	1			T1	22		T3	29		T5	9
rot_creator_auth_codesign	21127	1			T1	34		T3	41		T5	2
owner_sw_cfg	20551	1			T1	20		T3	21		T5	3
creator_sw_cfg	20186	1			T1	34		T3	13		T9	5
vendor_test	29447	1			T1	29		T3	58		T8	29

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3592	1			T90	114		T6	462		T290	307
fsm_err	secret1	3741	1			T13	66		T325	5		T326	34
fsm_err	secret0	3298	1			T169	237		T116	215		T207	268
fsm_err	hw_cfg1	3700	1			T17	415		T327	395		T232	340
fsm_err	hw_cfg0	4367	1			T328	267		T267	49		T212	62
fsm_err	rot_creator_auth_state	6268	1			T29	308		T6	93		T7	116
fsm_err	rot_creator_auth_codesign	4372	1			T6	212		T329	210		T166	52
fsm_err	owner_sw_cfg	3771	1			T98	20		T330	87		T326	502
fsm_err	creator_sw_cfg	3758	1			T141	30		T331	89		T332	124
fsm_err	vendor_test	13680	1			T8	29		T9	243		T136	597
access_err	life_cycle	812	1			T5	4		T7	12		T15	4
access_err	secret2	9644	1			T1	13		T3	27		T6	23
access_err	secret1	5672	1			T1	1		T3	23		T28	4
access_err	secret0	4171	1			T1	23		T3	22		T6	1
access_err	hw_cfg1	1238	1			T1	4		T3	5		T6	3
access_err	hw_cfg0	2227	1			T1	8		T3	4		T28	2
access_err	rot_creator_auth_state	5259	1			T1	7		T3	14		T9	1
access_err	rot_creator_auth_codesign	7289	1			T1	25		T3	25		T6	7
access_err	owner_sw_cfg	6353	1			T1	13		T3	3		T9	2
access_err	creator_sw_cfg	7060	1			T1	8		T3	9		T6	8
access_err	vendor_test	6664	1			T1	19		T3	19		T6	11
write_blank_err	secret2	13	1			T7	1		T118	1		T321	1
write_blank_err	secret1	25	1			T333	1		T197	2		T267	1
write_blank_err	secret0	46	1			T173	1		T7	2		T202	1
write_blank_err	hw_cfg1	87	1			T5	2		T91	1		T173	1
write_blank_err	hw_cfg0	22	1			T13	1		T222	1		T334	1
write_blank_err	rot_creator_auth_state	145	1			T5	2		T91	2		T7	2
write_blank_err	rot_creator_auth_codesign	63	1			T266	2		T183	2		T267	1
write_blank_err	owner_sw_cfg	36	1			T335	1		T336	1		T234	3
write_blank_err	creator_sw_cfg	21	1			T91	1		T321	2		T337	3
write_blank_err	vendor_test	33	1			T7	1		T338	1		T287	1
ecc_uncorr_err	secret2	3542	1			T7	55		T141	34		T192	43
ecc_uncorr_err	secret1	9047	1			T98	9		T333	177		T192	50
ecc_uncorr_err	secret0	18971	1			T173	279		T7	358		T339	9
ecc_uncorr_err	hw_cfg1	26842	1			T5	566		T91	142		T98	23
ecc_uncorr_err	hw_cfg0	10159	1			T13	672		T222	323		T141	69
ecc_uncorr_err	rot_creator_auth_state	2802	1			T200	513		T141	33		T224	360
ecc_uncorr_err	rot_creator_auth_codesign	1069	1			T98	19		T267	60		T142	5
ecc_uncorr_err	owner_sw_cfg	1774	1			T248	24		T340	47		T166	45
ecc_uncorr_err	creator_sw_cfg	1558	1			T339	11		T192	58		T248	56
ecc_corr_err	secret2	81	1			T67	5		T128	2		T72	1
ecc_corr_err	secret1	131	1			T67	3		T98	4		T128	2
ecc_corr_err	secret0	165	1			T67	6		T7	7		T98	3
ecc_corr_err	hw_cfg1	232	1			T5	1		T173	1		T7	1
ecc_corr_err	hw_cfg0	213	1			T67	14		T98	1		T128	6
ecc_corr_err	rot_creator_auth_state	107	1			T67	1		T128	1		T72	1
ecc_corr_err	rot_creator_auth_codesign	104	1			T67	1		T128	5		T72	11
ecc_corr_err	owner_sw_cfg	121	1			T67	7		T98	1		T128	1
ecc_corr_err	creator_sw_cfg	157	1			T67	4		T128	2		T72	6
no_err	secret2	4943	1			T1	13		T3	7		T9	3
no_err	secret1	8189	1			T1	23		T3	5		T5	4
no_err	secret0	7734	1			T1	4		T3	3		T5	2
no_err	hw_cfg1	9782	1			T1	22		T3	19		T5	3
no_err	hw_cfg0	11029	1			T1	19		T3	24		T5	4
no_err	rot_creator_auth_state	7678	1			T1	15		T3	15		T5	7
no_err	rot_creator_auth_codesign	8230	1			T1	9		T3	16		T5	2
no_err	owner_sw_cfg	8496	1			T1	7		T3	18		T5	3
no_err	creator_sw_cfg	7632	1			T1	26		T3	4		T9	5
no_err	vendor_test	9070	1			T1	10		T3	39		T5	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded