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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 9855 1 T1 2 T2 3 T3 4
true 16000 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10658 1 T1 2 T2 3 T3 7
true 16054 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T9 2 T38 2 T98 2
others[1] 92 1 T27 6 T107 2 T99 2
others[2] 74 1 T9 2 T121 2 T352 2
others[3] 88 1 T9 2 T27 2 T38 2
others[4] 110 1 T9 4 T27 2 T28 2
others[5] 72 1 T28 2 T202 2 T352 2
others[6] 66 1 T27 6 T100 2 T101 2
others[7] 100 1 T27 4 T28 2 T98 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T27 4 T100 2 T121 2
others[1] 90 1 T9 2 T27 4 T99 2
others[2] 80 1 T9 4 T27 2 T28 2
others[3] 88 1 T103 2 T105 2 T236 2
others[4] 72 1 T108 2 T109 2 T200 2
others[5] 78 1 T10 2 T27 2 T98 2
others[6] 76 1 T38 2 T98 2 T200 2
others[7] 106 1 T9 4 T100 2 T102 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T9 2 T27 4 T28 4
others[1] 94 1 T27 6 T28 2 T202 2
others[2] 72 1 T9 2 T27 2 T352 2
others[3] 76 1 T9 2 T27 6 T201 2
others[4] 68 1 T9 2 T203 4 T362 2
others[5] 66 1 T107 2 T98 2 T29 2
others[6] 66 1 T352 2 T233 2 T256 2
others[7] 112 1 T100 2 T98 4 T109 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 48 1 T352 4 T393 2 T394 2
others[1] 50 1 T28 4 T394 2 T395 2
others[2] 70 1 T27 2 T105 2 T200 2
others[3] 60 1 T27 2 T28 2 T38 2
others[4] 58 1 T202 2 T394 2 T126 2
others[5] 62 1 T27 4 T98 2 T199 2
others[6] 50 1 T38 2 T102 2 T396 2
others[7] 84 1 T397 2 T398 2 T234 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T10 2 T28 2 T203 2
others[1] 62 1 T10 2 T27 2 T28 2
others[2] 78 1 T9 2 T27 2 T109 4
others[3] 70 1 T27 2 T38 2 T352 2
others[4] 78 1 T9 2 T202 4 T203 2
others[5] 88 1 T9 2 T201 2 T395 2
others[6] 82 1 T9 2 T27 2 T104 2
others[7] 90 1 T28 2 T100 2 T199 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 34 1 T9 2 T99 2 T203 2
others[1] 32 1 T27 6 T104 2 T203 2
others[2] 30 1 T28 2 T103 2 T104 2
others[3] 30 1 T9 2 T27 4 T399 2
others[4] 46 1 T27 4 T109 2 T400 2
others[5] 32 1 T28 2 T99 2 T401 2
others[6] 14 1 T101 2 T203 2 T402 2
others[7] 34 1 T9 2 T100 2 T103 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T38 2 T352 2 T233 2
others[1] 100 1 T10 2 T27 2 T121 2
others[2] 80 1 T9 2 T27 2 T98 2
others[3] 126 1 T9 2 T27 4 T394 6
others[4] 64 1 T27 4 T101 2 T102 2
others[5] 78 1 T9 2 T27 2 T98 2
others[6] 86 1 T9 2 T27 2 T200 2
others[7] 92 1 T27 4 T28 2 T38 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T27 2 T121 4 T203 4
others[1] 100 1 T104 2 T200 2 T202 2
others[2] 62 1 T27 4 T28 2 T98 2
others[3] 114 1 T9 2 T27 2 T102 2
others[4] 82 1 T9 2 T27 2 T38 2
others[5] 50 1 T27 2 T102 2 T29 2
others[6] 82 1 T27 2 T28 2 T100 2
others[7] 106 1 T27 6 T38 2 T98 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T27 4 T28 2 T100 2
others[1] 88 1 T9 4 T27 4 T99 2
others[2] 96 1 T9 2 T27 2 T109 2
others[3] 72 1 T9 2 T38 2 T103 2
others[4] 94 1 T27 6 T100 2 T105 2
others[5] 74 1 T98 2 T199 2 T246 4
others[6] 106 1 T104 2 T121 4 T126 2
others[7] 94 1 T9 2 T29 2 T202 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T9 2 T99 2 T121 2
others[1] 100 1 T27 4 T105 2 T200 2
others[2] 78 1 T9 4 T102 2 T236 2
others[3] 86 1 T9 2 T27 2 T98 2
others[4] 70 1 T27 2 T28 2 T104 2
others[5] 54 1 T9 2 T27 2 T403 4
others[6] 74 1 T121 2 T352 4 T126 2
others[7] 92 1 T10 2 T27 2 T102 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T9 2 T28 2 T98 2
others[1] 108 1 T9 2 T28 2 T99 2
others[2] 104 1 T9 4 T27 2 T121 2
others[3] 104 1 T9 2 T27 2 T100 2
others[4] 94 1 T10 2 T27 2 T28 2
others[5] 76 1 T9 2 T27 4 T38 2
others[6] 86 1 T27 4 T28 2 T203 2
others[7] 112 1 T27 2 T105 2 T246 2
false 13658 1 T1 5 T2 4 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 22 1 T37 1 T350 1 T239 2
others[1] 29 1 T15 1 T16 1 T26 1
others[2] 28 1 T12 1 T27 2 T15 1
others[3] 38 1 T6 1 T27 2 T70 1
others[4] 22 1 T12 1 T132 1 T239 1
others[5] 29 1 T37 1 T137 1 T404 1
others[6] 40 1 T6 1 T12 1 T15 1
others[7] 32 1 T121 2 T350 1 T132 2
false 13658 1 T1 5 T2 4 T3 8
true 2140 1 T1 1 T4 1 T5 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 22 1 T15 1 T37 1 T132 2
others[1] 30 1 T12 1 T27 2 T15 1
others[2] 24 1 T132 2 T346 1 T17 1
others[3] 28 1 T12 1 T37 2 T350 1
others[4] 34 1 T12 1 T27 2 T37 3
others[5] 34 1 T6 2 T350 2 T239 1
others[6] 30 1 T16 1 T26 1 T201 2
others[7] 39 1 T15 1 T70 1 T350 2
false 11125 1 T1 2 T2 3 T3 7
true 18130 1 T1 6 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T9 2 T121 2 T400 2
others[1] 78 1 T28 2 T104 2 T396 2
others[2] 104 1 T9 4 T27 2 T28 4
others[3] 64 1 T9 2 T27 4 T38 2
others[4] 70 1 T100 2 T107 2 T99 2
others[5] 106 1 T27 4 T38 2 T98 2
others[6] 94 1 T9 2 T27 4 T98 2
others[7] 104 1 T27 6 T101 4 T203 2
false 7581 1 T1 2 T2 3 T3 7
true 16105 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T9 2 T10 2 T27 4
others[1] 68 1 T108 2 T121 2 T202 2
others[2] 72 1 T27 2 T28 2 T99 2
others[3] 108 1 T100 2 T38 2 T103 4
others[4] 90 1 T9 4 T100 2 T109 2
others[5] 72 1 T9 4 T98 2 T203 2
others[6] 86 1 T103 2 T104 2 T352 2
others[7] 112 1 T27 6 T98 2 T102 2
false 6861 1 T1 2 T2 3 T3 4
true 15891 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T9 6 T27 4 T28 2
others[1] 62 1 T100 2 T98 2 T109 2
others[2] 106 1 T98 2 T105 2 T394 2
others[3] 76 1 T9 2 T27 2 T29 2
others[4] 86 1 T27 2 T28 2 T201 2
others[5] 74 1 T27 4 T352 2 T405 2
others[6] 70 1 T27 4 T28 2 T246 2
others[7] 90 1 T27 2 T107 2 T98 2
false 7222 1 T1 2 T2 3 T3 7
true 15911 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 30 1 T13 2 T202 2 T132 1
others[1] 33 1 T6 1 T15 2 T350 1
others[2] 24 1 T26 1 T350 1 T406 2
others[3] 26 1 T26 2 T102 2 T37 1
others[4] 20 1 T407 2 T213 1 T408 2
others[5] 27 1 T7 1 T37 1 T132 1
others[6] 25 1 T15 1 T70 1 T137 1
others[7] 36 1 T6 1 T27 2 T15 1
false 11059 1 T1 2 T2 3 T3 7
true 18119 1 T1 6 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T28 2 T38 2 T199 2
others[1] 62 1 T27 2 T352 2 T394 2
others[2] 54 1 T28 2 T201 2 T352 2
others[3] 50 1 T38 2 T352 2 T394 4
others[4] 68 1 T27 2 T98 2 T394 4
others[5] 70 1 T27 2 T98 2 T102 2
others[6] 50 1 T246 2 T396 2 T234 2
others[7] 70 1 T27 2 T28 2 T105 2
false 8668 1 T1 2 T2 3 T3 7
true 16113 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 32 1 T15 1 T26 1 T37 1
others[1] 32 1 T12 1 T28 2 T26 1
others[2] 28 1 T15 1 T104 2 T70 1
others[3] 38 1 T37 1 T274 1 T132 2
others[4] 27 1 T26 1 T70 1 T350 1
others[5] 28 1 T394 2 T239 1 T247 1
others[6] 23 1 T15 1 T350 1 T132 1
others[7] 38 1 T15 3 T37 1 T350 3
false 11011 1 T1 2 T2 3 T3 7
true 18071 1 T1 6 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T9 4 T27 2 T199 2
others[1] 78 1 T109 2 T201 2 T203 4
others[2] 86 1 T9 2 T27 2 T28 4
others[3] 72 1 T202 2 T203 2 T395 2
others[4] 72 1 T10 2 T27 2 T28 2
others[5] 82 1 T9 2 T27 2 T121 2
others[6] 62 1 T100 2 T38 2 T203 2
others[7] 114 1 T10 2 T109 2 T105 2
false 7561 1 T1 2 T2 3 T3 7
true 16023 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 31 1 T70 2 T350 1 T132 1
others[1] 37 1 T132 2 T130 2 T239 1
others[2] 13 1 T409 2 T410 2 T411 2
others[3] 39 1 T6 1 T26 1 T37 1
others[4] 24 1 T37 1 T130 1 T239 1
others[5] 32 1 T15 1 T121 2 T350 1
others[6] 30 1 T28 2 T37 1 T350 1
others[7] 30 1 T6 1 T70 1 T350 1
false 10962 1 T1 2 T2 3 T3 7
true 18101 1 T1 6 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 46 1 T27 2 T101 2 T109 2
others[1] 28 1 T27 2 T28 2 T412 2
others[2] 28 1 T203 2 T413 2 T414 2
others[3] 30 1 T9 2 T100 2 T400 2
others[4] 34 1 T27 2 T99 2 T104 2
others[5] 26 1 T9 2 T27 4 T99 2
others[6] 22 1 T27 4 T28 2 T104 2
others[7] 38 1 T9 2 T103 2 T126 2
false 9634 1 T1 2 T2 3 T3 7
true 16061 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T27 2 T98 4 T233 2
others[1] 82 1 T101 2 T352 2 T394 4
others[2] 96 1 T27 2 T102 2 T200 2
others[3] 76 1 T9 4 T27 2 T394 2
others[4] 88 1 T28 2 T38 2 T201 2
others[5] 94 1 T9 2 T27 4 T38 2
others[6] 54 1 T27 2 T104 2 T168 2
others[7] 132 1 T9 2 T10 2 T27 8
false 6892 1 T1 2 T2 3 T3 6
true 15887 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T102 2 T200 2 T121 2
others[1] 68 1 T27 4 T98 4 T104 2
others[2] 92 1 T28 2 T100 2 T102 2
others[3] 72 1 T27 4 T38 2 T102 2
others[4] 64 1 T104 2 T202 2 T415 2
others[5] 90 1 T9 2 T27 2 T103 2
others[6] 84 1 T38 2 T121 2 T352 2
others[7] 136 1 T9 2 T27 10 T28 2
false 6892 1 T1 2 T2 3 T3 6
true 15887 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T27 2 T100 2 T38 2
others[1] 108 1 T27 4 T29 2 T121 2
others[2] 110 1 T9 2 T27 2 T28 2
others[3] 64 1 T27 2 T98 2 T126 2
others[4] 56 1 T9 2 T27 2 T99 2
others[5] 86 1 T9 4 T27 2 T103 2
others[6] 86 1 T9 2 T202 2 T352 2
others[7] 110 1 T27 2 T100 2 T199 2
false 6317 1 T1 2 T2 3 T3 4
true 15887 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T10 2 T27 4 T104 2
others[1] 84 1 T27 2 T203 2 T126 6
others[2] 68 1 T9 2 T27 2 T105 4
others[3] 62 1 T9 2 T27 2 T102 2
others[4] 90 1 T9 2 T28 2 T98 2
others[5] 78 1 T9 2 T102 2 T416 2
others[6] 98 1 T9 2 T121 2 T352 6
others[7] 72 1 T27 2 T99 2 T200 2
false 6317 1 T1 2 T2 3 T3 4
true 15887 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 60 1 T9 2 T27 4 T98 4
others[1] 62 1 T27 4 T203 4 T415 2
others[2] 58 1 T27 2 T28 2 T98 2
others[3] 48 1 T28 2 T100 2 T121 2
others[4] 60 1 T203 2 T397 2 T234 2
others[5] 62 1 T27 2 T28 2 T98 2
others[6] 56 1 T9 2 T27 2 T233 2
others[7] 72 1 T9 2 T27 8 T200 2
false 6768 1 T1 2 T2 2 T3 4
true 17164 1 T1 7 T2 5 T3 12


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 56 1 T102 2 T352 2 T246 2
others[1] 48 1 T396 2 T276 2 T417 2
others[2] 72 1 T27 6 T38 2 T102 2
others[3] 62 1 T9 2 T27 2 T105 2
others[4] 46 1 T27 2 T200 2 T393 2
others[5] 76 1 T9 4 T28 2 T98 2
others[6] 50 1 T9 2 T101 2 T200 2
others[7] 56 1 T28 2 T100 2 T102 2
false 6768 1 T1 2 T2 2 T3 4
true 17164 1 T1 7 T2 5 T3 12


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 37 1 T12 1 T274 1 T203 2
others[1] 21 1 T274 1 T346 1 T418 2
others[2] 19 1 T6 1 T364 2 T130 1
others[3] 34 1 T27 2 T37 1 T350 1
others[4] 32 1 T350 1 T419 1 T213 1
others[5] 30 1 T37 2 T350 1 T130 1
others[6] 28 1 T6 1 T12 1 T137 1
others[7] 25 1 T15 1 T70 1 T132 1
false 11206 1 T1 2 T2 3 T3 7
true 18224 1 T1 6 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 118 1 T199 2 T156 2 T202 2
others[1] 92 1 T9 2 T27 2 T28 2
others[2] 90 1 T9 2 T28 2 T99 2
others[3] 72 1 T10 2 T27 4 T28 2
others[4] 94 1 T9 2 T27 2 T101 2
others[5] 116 1 T9 4 T27 4 T28 2
others[6] 80 1 T9 2 T27 4 T102 2
others[7] 100 1 T100 2 T121 2 T233 2
false 7603 1 T1 2 T2 3 T3 7
true 16103 1 T1 5 T2 5 T3 10


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 22 1 T6 1 T15 1 T37 2
others[1] 35 1 T13 2 T26 1 T70 1
others[2] 18 1 T350 1 T231 1 T239 1
others[3] 38 1 T6 1 T15 1 T26 1
others[4] 28 1 T15 1 T26 1 T130 1
others[5] 18 1 T350 1 T247 2 T416 2
others[6] 24 1 T132 1 T231 1 T404 1
others[7] 39 1 T7 1 T27 2 T15 1
false 13658 1 T1 5 T2 4 T3 8
true 2166 1 T1 1 T2 1 T4 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%