Summary for Variable dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for dai_access_cmd
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
dai_digest |
2254 |
1 |
|
|
T1 |
5 |
|
T3 |
18 |
|
T5 |
3 |
dai_wr |
4161 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T3 |
10 |
dai_rd |
7307 |
1 |
|
|
T1 |
16 |
|
T2 |
1 |
|
T3 |
36 |
Summary for Variable lc_creator_seed_sw_rw_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_creator_seed_sw_rw_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6177 |
1 |
|
|
T1 |
16 |
|
T2 |
4 |
|
T3 |
53 |
auto[1] |
7545 |
1 |
|
|
T1 |
10 |
|
T3 |
11 |
|
T7 |
2 |
Summary for Cross dai_access_secret2
Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for dai_access_secret2
Bins
lc_creator_seed_sw_rw_en | dai_access_cmd | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
dai_digest |
1235 |
1 |
|
|
T1 |
4 |
|
T3 |
16 |
|
T5 |
1 |
auto[0] |
dai_wr |
1524 |
1 |
|
|
T2 |
3 |
|
T3 |
7 |
|
T5 |
4 |
auto[0] |
dai_rd |
3418 |
1 |
|
|
T1 |
12 |
|
T2 |
1 |
|
T3 |
30 |
auto[1] |
dai_digest |
1019 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T5 |
2 |
auto[1] |
dai_wr |
2637 |
1 |
|
|
T1 |
5 |
|
T3 |
3 |
|
T7 |
1 |
auto[1] |
dai_rd |
3889 |
1 |
|
|
T1 |
4 |
|
T3 |
6 |
|
T7 |
1 |