Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53849	1			T2	546		T4	50		T9	382
access_err	59352	1			T1	175		T2	19		T3	331
write_blank_err	423	1			T1	1		T3	4		T11	5
ecc_uncorr_err	67652	1			T1	97		T3	702		T159	42
ecc_corr_err	1291	1			T23	16		T144	4		T12	2
no_err	89527	1			T1	258		T2	49		T3	881

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	750	1			T1	7		T11	11		T12	11
secret2	27184	1			T1	42		T2	8		T3	90
secret1	27066	1			T1	34		T2	9		T3	113
secret0	37448	1			T1	139		T2	2		T3	97
hw_cfg1	35955	1			T1	30		T2	3		T3	798
hw_cfg0	26472	1			T1	42		T2	555		T3	148
rot_creator_auth_state	23282	1			T1	46		T2	10		T3	137
rot_creator_auth_codesign	21450	1			T1	78		T2	10		T3	128
owner_sw_cfg	20285	1			T1	41		T2	10		T3	156
creator_sw_cfg	19946	1			T1	30		T2	2		T3	112
vendor_test	32256	1			T1	42		T2	5		T3	139

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4203	1			T67	148		T187	73		T161	89
fsm_err	secret1	4870	1			T4	50		T146	127		T101	76
fsm_err	secret0	7046	1			T164	212		T166	65		T67	273
fsm_err	hw_cfg1	3243	1			T336	140		T141	21		T162	83
fsm_err	hw_cfg0	5358	1			T2	546		T146	228		T153	128
fsm_err	rot_creator_auth_state	4706	1			T337	254		T224	43		T166	122
fsm_err	rot_creator_auth_codesign	3837	1			T333	239		T338	454		T181	55
fsm_err	owner_sw_cfg	3289	1			T226	76		T67	35		T339	388
fsm_err	creator_sw_cfg	2466	1			T188	106		T340	300		T341	1
fsm_err	vendor_test	14831	1			T9	382		T23	89		T116	3
access_err	life_cycle	750	1			T1	7		T11	11		T12	11
access_err	secret2	10651	1			T1	29		T2	8		T3	75
access_err	secret1	5778	1			T5	54		T8	1		T42	46
access_err	secret0	4533	1			T1	2		T5	21		T6	2
access_err	hw_cfg1	1201	1			T1	1		T2	3		T3	2
access_err	hw_cfg0	2053	1			T1	3		T5	7		T42	15
access_err	rot_creator_auth_state	5662	1			T1	23		T2	3		T3	57
access_err	rot_creator_auth_codesign	7364	1			T1	44		T2	4		T3	50
access_err	owner_sw_cfg	6433	1			T1	28		T3	67		T5	38
access_err	creator_sw_cfg	7513	1			T1	14		T3	36		T4	1
access_err	vendor_test	7414	1			T1	24		T2	1		T3	44
write_blank_err	secret2	18	1			T192	1		T342	1		T320	1
write_blank_err	secret1	19	1			T67	1		T320	1		T161	1
write_blank_err	secret0	47	1			T1	1		T343	1		T161	1
write_blank_err	hw_cfg1	75	1			T3	1		T12	2		T67	2
write_blank_err	hw_cfg0	20	1			T11	2		T171	1		T242	2
write_blank_err	rot_creator_auth_state	115	1			T3	1		T11	3		T67	1
write_blank_err	rot_creator_auth_codesign	51	1			T3	2		T12	1		T192	2
write_blank_err	owner_sw_cfg	39	1			T343	1		T320	4		T135	1
write_blank_err	creator_sw_cfg	12	1			T12	1		T343	1		T344	1
write_blank_err	vendor_test	27	1			T343	1		T342	1		T135	1
ecc_uncorr_err	secret2	6911	1			T192	255		T342	292		T320	301
ecc_uncorr_err	secret1	7171	1			T67	396		T320	303		T161	257
ecc_uncorr_err	secret0	17438	1			T1	97		T343	252		T161	427
ecc_uncorr_err	hw_cfg1	20917	1			T3	702		T159	42		T12	59
ecc_uncorr_err	hw_cfg0	6867	1			T11	792		T166	69		T171	664
ecc_uncorr_err	rot_creator_auth_state	4337	1			T180	46		T167	27		T332	169
ecc_uncorr_err	rot_creator_auth_codesign	1511	1			T170	7		T167	48		T181	58
ecc_uncorr_err	owner_sw_cfg	819	1			T166	73		T345	127		T180	41
ecc_uncorr_err	creator_sw_cfg	1681	1			T345	49		T167	25		T346	42
ecc_corr_err	secret2	66	1			T23	1		T102	4		T71	1
ecc_corr_err	secret1	84	1			T23	3		T102	3		T71	1
ecc_corr_err	secret0	141	1			T23	4		T102	11		T166	1
ecc_corr_err	hw_cfg1	284	1			T23	8		T12	2		T102	23
ecc_corr_err	hw_cfg0	255	1			T144	3		T102	32		T166	1
ecc_corr_err	rot_creator_auth_state	130	1			T102	25		T166	1		T71	1
ecc_corr_err	rot_creator_auth_codesign	122	1			T102	11		T166	1		T346	1
ecc_corr_err	owner_sw_cfg	108	1			T144	1		T102	12		T180	1
ecc_corr_err	creator_sw_cfg	101	1			T102	5		T166	1		T345	2
no_err	secret2	5335	1			T1	13		T3	15		T5	21
no_err	secret1	9144	1			T1	34		T2	9		T3	113
no_err	secret0	8243	1			T1	39		T2	2		T3	97
no_err	hw_cfg1	10235	1			T1	29		T3	93		T5	46
no_err	hw_cfg0	11919	1			T1	39		T2	9		T3	148
no_err	rot_creator_auth_state	8332	1			T1	23		T2	7		T3	79
no_err	rot_creator_auth_codesign	8565	1			T1	34		T2	6		T3	76
no_err	owner_sw_cfg	9597	1			T1	13		T2	10		T3	89
no_err	creator_sw_cfg	8173	1			T1	16		T2	2		T3	76
no_err	vendor_test	9984	1			T1	18		T2	4		T3	95

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded