Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
84.44 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 1 17 94.44
Crosses 72 13 59 81.94


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 1 6 85.71 100 1 1 0
partition 11 0 11 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_err_code_for_all_partitions 72 13 59 81.94 100 1 1 0


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 43475 1 T3 291 T5 4 T11 359
access_err 58555 1 T3 3 T4 2 T5 2
write_blank_err 372 1 T4 1 T13 1 T8 4
ecc_uncorr_err 61039 1 T4 511 T5 21 T13 454
ecc_corr_err 1297 1 T5 11 T12 34 T130 8
no_err 86309 1 T1 7 T3 34 T4 19



Summary for Variable partition

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for partition

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_idx 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
life_cycle 612 1 T8 6 T15 10 T16 7
secret2 22825 1 T1 5 T3 2 T4 2
secret1 30657 1 T3 4 T4 516 T5 4
secret0 32510 1 T3 7 T5 2 T10 5
hw_cfg1 31557 1 T3 3 T5 2 T10 4
hw_cfg0 24400 1 T3 4 T4 2 T5 9
rot_creator_auth_state 18832 1 T4 2 T5 2 T10 6
rot_creator_auth_codesign 18799 1 T3 4 T4 4 T5 5
owner_sw_cfg 21783 1 T3 300 T5 7 T10 8
creator_sw_cfg 19146 1 T1 1 T3 1 T4 2
vendor_test 29926 1 T1 1 T3 3 T4 5



Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 72 13 59 81.94 13
Automatically Generated Cross Bins 72 13 59 81.94 13
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins
err_code_valspartitionCOUNTAT LEASTNUMBERSTATUS
[fsm_err] [life_cycle] 0 1 1
[ecc_corr_err] [vendor_test] 0 1 1
[macro_err] [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] -- -- 10
[no_err] [life_cycle] 0 1 1


Covered bins
err_code_valspartitionCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err secret2 2695 1 T186 321 T248 126 T319 220
fsm_err secret1 5207 1 T11 270 T267 15 T233 107
fsm_err secret0 3886 1 T148 94 T72 332 T320 251
fsm_err hw_cfg1 3709 1 T321 183 T248 51 T322 462
fsm_err hw_cfg0 4057 1 T11 89 T96 187 T225 30
fsm_err rot_creator_auth_state 2540 1 T323 146 T324 11 T107 63
fsm_err rot_creator_auth_codesign 1375 1 T247 197 T285 576 T140 53
fsm_err owner_sw_cfg 4520 1 T3 291 T139 33 T217 483
fsm_err creator_sw_cfg 2224 1 T5 4 T92 129 T325 70
fsm_err vendor_test 13262 1 T180 30 T43 48 T138 108
access_err life_cycle 612 1 T8 6 T15 10 T16 7
access_err secret2 10454 1 T3 2 T5 1 T11 109
access_err secret1 5374 1 T11 68 T12 24 T29 1
access_err secret0 4371 1 T11 47 T12 37 T7 3
access_err hw_cfg1 1228 1 T3 1 T5 1 T11 10
access_err hw_cfg0 2011 1 T11 18 T12 3 T97 2
access_err rot_creator_auth_state 5959 1 T11 23 T12 20 T29 1
access_err rot_creator_auth_codesign 7904 1 T4 2 T11 88 T12 26
access_err owner_sw_cfg 6277 1 T11 35 T12 18 T100 1
access_err creator_sw_cfg 7281 1 T11 78 T12 13 T7 75
access_err vendor_test 7084 1 T11 43 T12 41 T29 1
write_blank_err secret2 10 1 T13 1 T8 1 T326 1
write_blank_err secret1 31 1 T4 1 T16 1 T184 1
write_blank_err secret0 42 1 T18 1 T98 1 T184 1
write_blank_err hw_cfg1 55 1 T66 1 T15 1 T184 1
write_blank_err hw_cfg0 21 1 T237 2 T316 1 T327 1
write_blank_err rot_creator_auth_state 131 1 T8 3 T16 4 T326 3
write_blank_err rot_creator_auth_codesign 29 1 T16 2 T326 1 T217 1
write_blank_err owner_sw_cfg 25 1 T319 1 T328 2 T272 4
write_blank_err creator_sw_cfg 7 1 T238 1 T329 1 T330 1
write_blank_err vendor_test 21 1 T184 1 T303 1 T238 1
ecc_uncorr_err secret2 4615 1 T5 10 T13 454 T8 256
ecc_uncorr_err secret1 11232 1 T4 511 T130 45 T189 30
ecc_uncorr_err secret0 15865 1 T5 2 T18 636 T98 666
ecc_uncorr_err hw_cfg1 16338 1 T130 37 T66 634 T15 433
ecc_uncorr_err hw_cfg0 6476 1 T5 9 T189 58 T237 270
ecc_uncorr_err rot_creator_auth_state 2124 1 T189 33 T328 289 T331 42
ecc_uncorr_err rot_creator_auth_codesign 820 1 T189 35 T160 2 T188 56
ecc_uncorr_err owner_sw_cfg 1858 1 T130 53 T189 38 T140 39
ecc_uncorr_err creator_sw_cfg 1711 1 T139 31 T252 23 T140 31
ecc_corr_err secret2 63 1 T12 4 T51 1 T147 1
ecc_corr_err secret1 90 1 T12 7 T189 2 T147 2
ecc_corr_err secret0 158 1 T12 2 T51 1 T52 12
ecc_corr_err hw_cfg1 257 1 T5 1 T12 9 T130 1
ecc_corr_err hw_cfg0 178 1 T12 2 T130 1 T52 9
ecc_corr_err rot_creator_auth_state 135 1 T12 3 T52 2 T44 3
ecc_corr_err rot_creator_auth_codesign 123 1 T5 4 T12 2 T52 12
ecc_corr_err owner_sw_cfg 149 1 T5 4 T130 5 T56 5
ecc_corr_err creator_sw_cfg 144 1 T5 2 T12 5 T130 1
no_err secret2 4988 1 T1 5 T4 2 T10 8
no_err secret1 8723 1 T3 4 T4 4 T5 4
no_err secret0 8188 1 T3 7 T10 5 T11 30
no_err hw_cfg1 9970 1 T3 2 T10 4 T11 64
no_err hw_cfg0 11657 1 T3 4 T4 2 T10 6
no_err rot_creator_auth_state 7943 1 T4 2 T5 2 T10 6
no_err rot_creator_auth_codesign 8548 1 T3 4 T4 2 T5 1
no_err owner_sw_cfg 8954 1 T3 9 T5 3 T10 8
no_err creator_sw_cfg 7779 1 T1 1 T3 1 T4 2
no_err vendor_test 9559 1 T1 1 T3 3 T4 5


User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins
NAMECOUNTSTATUS
vendor_test_ecc_uncorrectable_err 0 Illegal
life_cycle_ignore 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%