Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	57024	1			T2	242		T3	28		T4	518
access_err	64816	1			T1	4		T5	1		T11	60
write_blank_err	428	1			T8	1		T9	4		T14	1
ecc_uncorr_err	70807	1			T8	302		T9	406		T101	552
ecc_corr_err	1326	1			T12	14		T29	16		T101	18
no_err	97394	1			T1	40		T2	1		T5	11

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	776	1			T9	6		T14	6		T15	6
secret2	31161	1			T1	3		T11	15		T12	7
secret1	28930	1			T1	2		T5	1		T10	6
secret0	36064	1			T1	4		T10	3		T11	15
hw_cfg1	42626	1			T1	6		T5	2		T11	8
hw_cfg0	26976	1			T1	3		T5	3		T11	11
rot_creator_auth_state	21953	1			T1	3		T11	9		T12	7
rot_creator_auth_codesign	23161	1			T1	3		T10	1		T11	13
owner_sw_cfg	24363	1			T1	3		T5	3		T11	20
creator_sw_cfg	20811	1			T1	13		T11	9		T12	4
vendor_test	34974	1			T1	4		T2	243		T3	28

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5411	1			T193	405		T17	367		T206	143
fsm_err	secret1	5039	1			T10	6		T160	498		T132	365
fsm_err	secret0	4992	1			T231	99		T320	123		T321	318
fsm_err	hw_cfg1	3231	1			T130	89		T322	130		T323	287
fsm_err	hw_cfg0	7068	1			T7	147		T64	35		T324	281
fsm_err	rot_creator_auth_state	3887	1			T8	346		T73	635		T236	54
fsm_err	rot_creator_auth_codesign	2901	1			T8	143		T237	145		T150	78
fsm_err	owner_sw_cfg	4886	1			T17	472		T146	39		T191	182
fsm_err	creator_sw_cfg	2996	1			T7	11		T146	44		T147	3
fsm_err	vendor_test	16613	1			T2	242		T3	28		T4	518
access_err	life_cycle	776	1			T9	6		T14	6		T15	6
access_err	secret2	11596	1			T11	9		T12	5		T7	21
access_err	secret1	5956	1			T11	16		T12	17		T29	20
access_err	secret0	4864	1			T11	6		T12	9		T29	5
access_err	hw_cfg1	1319	1			T5	1		T11	1		T7	1
access_err	hw_cfg0	2267	1			T12	9		T29	4		T16	7
access_err	rot_creator_auth_state	5984	1			T1	1		T11	2		T12	1
access_err	rot_creator_auth_codesign	8619	1			T11	12		T12	2		T7	9
access_err	owner_sw_cfg	7476	1			T1	1		T11	5		T12	9
access_err	creator_sw_cfg	8198	1			T11	3		T12	4		T7	11
access_err	vendor_test	7761	1			T1	2		T11	6		T12	1
write_blank_err	secret2	22	1			T18	2		T225	1		T325	1
write_blank_err	secret1	21	1			T129	1		T263	1		T326	1
write_blank_err	secret0	45	1			T8	1		T191	1		T327	1
write_blank_err	hw_cfg1	89	1			T9	1		T148	1		T15	1
write_blank_err	hw_cfg0	19	1			T14	1		T18	1		T264	1
write_blank_err	rot_creator_auth_state	120	1			T9	2		T64	3		T18	1
write_blank_err	rot_creator_auth_codesign	48	1			T129	1		T191	3		T226	2
write_blank_err	owner_sw_cfg	22	1			T227	1		T326	3		T119	2
write_blank_err	creator_sw_cfg	10	1			T9	1		T226	1		T328	2
write_blank_err	vendor_test	32	1			T129	2		T320	3		T120	4
ecc_uncorr_err	secret2	8333	1			T101	101		T18	343		T329	65
ecc_uncorr_err	secret1	7798	1			T101	62		T146	42		T329	44
ecc_uncorr_err	secret0	16795	1			T8	302		T146	66		T147	26
ecc_uncorr_err	hw_cfg1	26041	1			T9	406		T101	127		T146	51
ecc_uncorr_err	hw_cfg0	4849	1			T14	438		T147	7		T149	28
ecc_uncorr_err	rot_creator_auth_state	2819	1			T129	125		T330	8		T182	74
ecc_uncorr_err	rot_creator_auth_codesign	1704	1			T150	77		T197	58		T331	50
ecc_uncorr_err	owner_sw_cfg	1799	1			T101	205		T330	24		T182	140
ecc_uncorr_err	creator_sw_cfg	669	1			T101	57		T147	12		T332	20
ecc_corr_err	secret2	95	1			T12	1		T29	2		T101	2
ecc_corr_err	secret1	84	1			T101	4		T146	4		T147	1
ecc_corr_err	secret0	201	1			T12	2		T101	3		T146	3
ecc_corr_err	hw_cfg1	237	1			T12	6		T29	8		T101	3
ecc_corr_err	hw_cfg0	234	1			T12	4		T29	3		T146	4
ecc_corr_err	rot_creator_auth_state	137	1			T29	2		T101	1		T39	3
ecc_corr_err	rot_creator_auth_codesign	112	1			T101	3		T44	1		T149	1
ecc_corr_err	owner_sw_cfg	105	1			T12	1		T101	2		T147	1
ecc_corr_err	creator_sw_cfg	121	1			T29	1		T147	3		T65	6
no_err	secret2	5704	1			T1	3		T11	6		T12	1
no_err	secret1	10032	1			T1	2		T5	1		T11	4
no_err	secret0	9167	1			T1	4		T10	3		T11	9
no_err	hw_cfg1	11709	1			T1	6		T5	1		T11	7
no_err	hw_cfg0	12539	1			T1	3		T5	3		T11	11
no_err	rot_creator_auth_state	9006	1			T1	2		T11	7		T12	6
no_err	rot_creator_auth_codesign	9777	1			T1	3		T10	1		T11	1
no_err	owner_sw_cfg	10075	1			T1	2		T5	3		T11	15
no_err	creator_sw_cfg	8817	1			T1	13		T11	6		T7	14
no_err	vendor_test	10568	1			T1	2		T2	1		T5	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded