Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.75 93.81 96.15 95.57 90.93 97.10 96.34 93.35


Total test records in report: 1323
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html

T1052 /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1799398394 Jul 28 05:27:27 PM PDT 24 Jul 28 05:27:41 PM PDT 24 549032947 ps
T1053 /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.877430013 Jul 28 05:29:55 PM PDT 24 Jul 28 05:30:01 PM PDT 24 385708651 ps
T1054 /workspace/coverage/default/283.otp_ctrl_init_fail.860304130 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:34 PM PDT 24 146370645 ps
T1055 /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.601204599 Jul 28 05:29:13 PM PDT 24 Jul 28 05:29:25 PM PDT 24 1591817676 ps
T1056 /workspace/coverage/default/28.otp_ctrl_dai_errs.2723535590 Jul 28 05:28:46 PM PDT 24 Jul 28 05:29:27 PM PDT 24 2092923684 ps
T1057 /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.2658395916 Jul 28 05:30:24 PM PDT 24 Jul 28 05:30:27 PM PDT 24 100764186 ps
T1058 /workspace/coverage/default/7.otp_ctrl_macro_errs.1357577313 Jul 28 05:27:44 PM PDT 24 Jul 28 05:28:43 PM PDT 24 21752688069 ps
T1059 /workspace/coverage/default/29.otp_ctrl_regwen.817819437 Jul 28 05:28:50 PM PDT 24 Jul 28 05:28:53 PM PDT 24 116713590 ps
T1060 /workspace/coverage/default/6.otp_ctrl_init_fail.4079743362 Jul 28 05:27:38 PM PDT 24 Jul 28 05:27:41 PM PDT 24 175142225 ps
T1061 /workspace/coverage/default/27.otp_ctrl_dai_lock.3931540158 Jul 28 05:28:44 PM PDT 24 Jul 28 05:29:04 PM PDT 24 483391443 ps
T1062 /workspace/coverage/default/14.otp_ctrl_init_fail.1961418930 Jul 28 05:27:57 PM PDT 24 Jul 28 05:28:01 PM PDT 24 118668554 ps
T1063 /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1044524350 Jul 28 05:29:14 PM PDT 24 Jul 28 05:40:19 PM PDT 24 26275584238 ps
T1064 /workspace/coverage/default/21.otp_ctrl_stress_all.2422689290 Jul 28 05:28:28 PM PDT 24 Jul 28 05:30:57 PM PDT 24 19434730943 ps
T1065 /workspace/coverage/default/22.otp_ctrl_dai_lock.336220874 Jul 28 05:28:28 PM PDT 24 Jul 28 05:29:09 PM PDT 24 4216362653 ps
T1066 /workspace/coverage/default/56.otp_ctrl_init_fail.3568727686 Jul 28 05:29:55 PM PDT 24 Jul 28 05:30:00 PM PDT 24 1609667249 ps
T1067 /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.2911128363 Jul 28 05:28:06 PM PDT 24 Jul 28 05:28:17 PM PDT 24 4631487379 ps
T1068 /workspace/coverage/default/3.otp_ctrl_check_fail.1530576825 Jul 28 05:27:28 PM PDT 24 Jul 28 05:27:35 PM PDT 24 924958634 ps
T1069 /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.2985065837 Jul 28 05:28:13 PM PDT 24 Jul 28 05:40:30 PM PDT 24 359369623510 ps
T1070 /workspace/coverage/default/69.otp_ctrl_init_fail.1748938247 Jul 28 05:30:08 PM PDT 24 Jul 28 05:30:12 PM PDT 24 96011117 ps
T1071 /workspace/coverage/default/15.otp_ctrl_stress_all.141541527 Jul 28 05:28:13 PM PDT 24 Jul 28 05:29:25 PM PDT 24 30762917404 ps
T1072 /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.347599890 Jul 28 05:29:57 PM PDT 24 Jul 28 05:30:19 PM PDT 24 4026443956 ps
T1073 /workspace/coverage/default/28.otp_ctrl_test_access.3577300148 Jul 28 05:28:53 PM PDT 24 Jul 28 05:28:59 PM PDT 24 378141138 ps
T1074 /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.269716382 Jul 28 05:29:18 PM PDT 24 Jul 28 05:29:29 PM PDT 24 975711444 ps
T1075 /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.4156444040 Jul 28 05:30:15 PM PDT 24 Jul 28 05:30:24 PM PDT 24 4475996684 ps
T1076 /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.2472465507 Jul 28 05:30:08 PM PDT 24 Jul 28 05:30:21 PM PDT 24 1059582977 ps
T1077 /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.3888747962 Jul 28 05:30:22 PM PDT 24 Jul 28 05:30:33 PM PDT 24 391813472 ps
T238 /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.2671063035 Jul 28 05:29:56 PM PDT 24 Jul 28 05:57:01 PM PDT 24 801240254026 ps
T1078 /workspace/coverage/default/10.otp_ctrl_init_fail.397328575 Jul 28 05:27:49 PM PDT 24 Jul 28 05:27:54 PM PDT 24 538641333 ps
T159 /workspace/coverage/default/286.otp_ctrl_init_fail.3400198550 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:35 PM PDT 24 287311588 ps
T1079 /workspace/coverage/default/7.otp_ctrl_background_chks.2687237666 Jul 28 05:27:35 PM PDT 24 Jul 28 05:28:47 PM PDT 24 8027673428 ps
T51 /workspace/coverage/default/35.otp_ctrl_check_fail.1772458456 Jul 28 05:29:10 PM PDT 24 Jul 28 05:29:32 PM PDT 24 2054860262 ps
T1080 /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2782255966 Jul 28 05:28:35 PM PDT 24 Jul 28 05:28:38 PM PDT 24 91865940 ps
T1081 /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2281209852 Jul 28 05:28:26 PM PDT 24 Jul 28 05:28:48 PM PDT 24 2890867618 ps
T1082 /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.28978448 Jul 28 05:30:22 PM PDT 24 Jul 28 05:30:26 PM PDT 24 107068037 ps
T1083 /workspace/coverage/default/62.otp_ctrl_init_fail.3318139839 Jul 28 05:30:01 PM PDT 24 Jul 28 05:30:05 PM PDT 24 339245422 ps
T155 /workspace/coverage/default/277.otp_ctrl_init_fail.2829299765 Jul 28 05:31:27 PM PDT 24 Jul 28 05:31:31 PM PDT 24 411374734 ps
T195 /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.127781656 Jul 28 05:30:47 PM PDT 24 Jul 28 05:30:54 PM PDT 24 556348880 ps
T1084 /workspace/coverage/default/48.otp_ctrl_alert_test.736188739 Jul 28 05:29:47 PM PDT 24 Jul 28 05:29:49 PM PDT 24 146886269 ps
T1085 /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3267603300 Jul 28 05:29:56 PM PDT 24 Jul 28 05:30:03 PM PDT 24 194373980 ps
T85 /workspace/coverage/default/47.otp_ctrl_init_fail.2784585021 Jul 28 05:29:49 PM PDT 24 Jul 28 05:29:53 PM PDT 24 211078528 ps
T1086 /workspace/coverage/default/235.otp_ctrl_init_fail.361288447 Jul 28 05:31:22 PM PDT 24 Jul 28 05:31:26 PM PDT 24 665195949 ps
T1087 /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1775437508 Jul 28 05:27:57 PM PDT 24 Jul 28 05:43:04 PM PDT 24 67939895342 ps
T1088 /workspace/coverage/default/276.otp_ctrl_init_fail.724789979 Jul 28 05:31:29 PM PDT 24 Jul 28 05:31:33 PM PDT 24 254655765 ps
T1089 /workspace/coverage/default/225.otp_ctrl_init_fail.3191508662 Jul 28 05:31:13 PM PDT 24 Jul 28 05:31:16 PM PDT 24 326861225 ps
T1090 /workspace/coverage/default/191.otp_ctrl_init_fail.2172142460 Jul 28 05:31:07 PM PDT 24 Jul 28 05:31:12 PM PDT 24 2020440514 ps
T1091 /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3691388332 Jul 28 05:31:01 PM PDT 24 Jul 28 05:31:07 PM PDT 24 118166904 ps
T1092 /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1451206308 Jul 28 05:30:48 PM PDT 24 Jul 28 05:30:56 PM PDT 24 169058554 ps
T1093 /workspace/coverage/default/58.otp_ctrl_init_fail.3647629220 Jul 28 05:29:54 PM PDT 24 Jul 28 05:30:00 PM PDT 24 1524991238 ps
T1094 /workspace/coverage/default/184.otp_ctrl_init_fail.840267343 Jul 28 05:31:00 PM PDT 24 Jul 28 05:31:04 PM PDT 24 252821250 ps
T1095 /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1141863252 Jul 28 05:28:57 PM PDT 24 Jul 28 05:29:12 PM PDT 24 512037461 ps
T1096 /workspace/coverage/default/27.otp_ctrl_test_access.4251507599 Jul 28 05:28:41 PM PDT 24 Jul 28 05:28:51 PM PDT 24 363222517 ps
T1097 /workspace/coverage/default/14.otp_ctrl_alert_test.3625877102 Jul 28 05:28:06 PM PDT 24 Jul 28 05:28:09 PM PDT 24 674486322 ps
T1098 /workspace/coverage/default/25.otp_ctrl_init_fail.1294378744 Jul 28 05:28:35 PM PDT 24 Jul 28 05:28:39 PM PDT 24 140229758 ps
T346 /workspace/coverage/default/44.otp_ctrl_regwen.390568696 Jul 28 05:29:34 PM PDT 24 Jul 28 05:29:43 PM PDT 24 296640353 ps
T1099 /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2508319865 Jul 28 05:30:45 PM PDT 24 Jul 28 05:30:58 PM PDT 24 782570388 ps
T1100 /workspace/coverage/default/27.otp_ctrl_macro_errs.269423773 Jul 28 05:28:43 PM PDT 24 Jul 28 05:29:01 PM PDT 24 2571450508 ps
T1101 /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1167572397 Jul 28 05:30:10 PM PDT 24 Jul 28 05:47:54 PM PDT 24 76953297749 ps
T56 /workspace/coverage/default/135.otp_ctrl_init_fail.3322778174 Jul 28 05:30:42 PM PDT 24 Jul 28 05:30:45 PM PDT 24 158395739 ps
T1102 /workspace/coverage/default/27.otp_ctrl_dai_errs.541932810 Jul 28 05:28:44 PM PDT 24 Jul 28 05:29:12 PM PDT 24 3285055774 ps
T1103 /workspace/coverage/default/264.otp_ctrl_init_fail.3189967377 Jul 28 05:31:24 PM PDT 24 Jul 28 05:31:30 PM PDT 24 2112488068 ps
T1104 /workspace/coverage/default/26.otp_ctrl_init_fail.1664351953 Jul 28 05:28:42 PM PDT 24 Jul 28 05:28:46 PM PDT 24 217855902 ps
T1105 /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3611513290 Jul 28 05:30:32 PM PDT 24 Jul 28 05:30:40 PM PDT 24 169354321 ps
T1106 /workspace/coverage/default/41.otp_ctrl_stress_all.2931973561 Jul 28 05:29:28 PM PDT 24 Jul 28 05:33:13 PM PDT 24 23144168020 ps
T1107 /workspace/coverage/default/1.otp_ctrl_dai_lock.2213568181 Jul 28 05:27:24 PM PDT 24 Jul 28 05:27:30 PM PDT 24 368680436 ps
T1108 /workspace/coverage/default/280.otp_ctrl_init_fail.2016904530 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:34 PM PDT 24 129535262 ps
T1109 /workspace/coverage/default/194.otp_ctrl_init_fail.3820370466 Jul 28 05:31:06 PM PDT 24 Jul 28 05:31:11 PM PDT 24 555752843 ps
T1110 /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.801820364 Jul 28 05:28:19 PM PDT 24 Jul 28 05:28:36 PM PDT 24 276475642 ps
T1111 /workspace/coverage/default/257.otp_ctrl_init_fail.4146889819 Jul 28 05:31:23 PM PDT 24 Jul 28 05:31:27 PM PDT 24 216061798 ps
T1112 /workspace/coverage/default/28.otp_ctrl_dai_lock.1687377681 Jul 28 05:28:43 PM PDT 24 Jul 28 05:28:58 PM PDT 24 579945852 ps
T1113 /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.4227121822 Jul 28 05:29:46 PM PDT 24 Jul 28 05:37:21 PM PDT 24 19547082132 ps
T1114 /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1206861735 Jul 28 05:30:17 PM PDT 24 Jul 28 05:48:06 PM PDT 24 384346356062 ps
T1115 /workspace/coverage/default/6.otp_ctrl_dai_lock.4285916886 Jul 28 05:27:38 PM PDT 24 Jul 28 05:27:53 PM PDT 24 8206789690 ps
T1116 /workspace/coverage/default/254.otp_ctrl_init_fail.3902114144 Jul 28 05:31:22 PM PDT 24 Jul 28 05:31:26 PM PDT 24 242061774 ps
T1117 /workspace/coverage/default/11.otp_ctrl_dai_lock.1847759701 Jul 28 05:27:50 PM PDT 24 Jul 28 05:28:17 PM PDT 24 5124139523 ps
T1118 /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.724208852 Jul 28 05:28:32 PM PDT 24 Jul 28 06:06:17 PM PDT 24 153936813366 ps
T1119 /workspace/coverage/default/47.otp_ctrl_alert_test.574208085 Jul 28 05:29:48 PM PDT 24 Jul 28 05:29:50 PM PDT 24 72915211 ps
T1120 /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.4285936323 Jul 28 05:29:26 PM PDT 24 Jul 28 05:47:55 PM PDT 24 78889457737 ps
T1121 /workspace/coverage/default/19.otp_ctrl_alert_test.3767918131 Jul 28 05:28:29 PM PDT 24 Jul 28 05:28:31 PM PDT 24 96773502 ps
T1122 /workspace/coverage/default/43.otp_ctrl_smoke.2721542773 Jul 28 05:29:40 PM PDT 24 Jul 28 05:29:58 PM PDT 24 6352208022 ps
T1123 /workspace/coverage/default/23.otp_ctrl_smoke.327015524 Jul 28 05:28:38 PM PDT 24 Jul 28 05:28:47 PM PDT 24 249434809 ps
T1124 /workspace/coverage/default/11.otp_ctrl_macro_errs.222679132 Jul 28 05:27:57 PM PDT 24 Jul 28 05:28:19 PM PDT 24 3660262274 ps
T1125 /workspace/coverage/default/99.otp_ctrl_init_fail.4133945789 Jul 28 05:30:27 PM PDT 24 Jul 28 05:30:31 PM PDT 24 89679064 ps
T1126 /workspace/coverage/default/0.otp_ctrl_stress_all.157296785 Jul 28 05:27:19 PM PDT 24 Jul 28 05:29:45 PM PDT 24 11924534759 ps
T1127 /workspace/coverage/default/266.otp_ctrl_init_fail.1771037529 Jul 28 05:31:19 PM PDT 24 Jul 28 05:31:24 PM PDT 24 293878865 ps
T1128 /workspace/coverage/default/49.otp_ctrl_macro_errs.4213127561 Jul 28 05:29:55 PM PDT 24 Jul 28 05:30:20 PM PDT 24 3630284003 ps
T1129 /workspace/coverage/default/88.otp_ctrl_init_fail.1412272197 Jul 28 05:30:15 PM PDT 24 Jul 28 05:30:20 PM PDT 24 201723005 ps
T1130 /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.670648045 Jul 28 05:31:06 PM PDT 24 Jul 28 05:31:10 PM PDT 24 136974612 ps
T1131 /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.3459957532 Jul 28 05:29:55 PM PDT 24 Jul 28 05:39:54 PM PDT 24 21173860112 ps
T1132 /workspace/coverage/default/5.otp_ctrl_alert_test.1187829117 Jul 28 05:27:34 PM PDT 24 Jul 28 05:27:36 PM PDT 24 80924050 ps
T1133 /workspace/coverage/default/10.otp_ctrl_dai_errs.2954263757 Jul 28 05:27:50 PM PDT 24 Jul 28 05:28:31 PM PDT 24 1479227048 ps
T1134 /workspace/coverage/default/5.otp_ctrl_dai_lock.4025945622 Jul 28 05:27:35 PM PDT 24 Jul 28 05:28:00 PM PDT 24 3817619111 ps
T1135 /workspace/coverage/default/32.otp_ctrl_init_fail.3952783028 Jul 28 05:28:56 PM PDT 24 Jul 28 05:29:00 PM PDT 24 510745049 ps
T1136 /workspace/coverage/default/285.otp_ctrl_init_fail.1372436299 Jul 28 05:31:33 PM PDT 24 Jul 28 05:31:38 PM PDT 24 137324097 ps
T1137 /workspace/coverage/default/12.otp_ctrl_alert_test.27888964 Jul 28 05:28:03 PM PDT 24 Jul 28 05:28:06 PM PDT 24 239475448 ps
T1138 /workspace/coverage/default/241.otp_ctrl_init_fail.221099571 Jul 28 05:31:20 PM PDT 24 Jul 28 05:31:24 PM PDT 24 135487031 ps
T1139 /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2240218516 Jul 28 05:30:14 PM PDT 24 Jul 28 05:30:20 PM PDT 24 207389856 ps
T1140 /workspace/coverage/default/30.otp_ctrl_macro_errs.473127642 Jul 28 05:28:49 PM PDT 24 Jul 28 05:29:03 PM PDT 24 431607489 ps
T1141 /workspace/coverage/default/38.otp_ctrl_test_access.2317302690 Jul 28 05:29:17 PM PDT 24 Jul 28 05:30:00 PM PDT 24 17979260587 ps
T1142 /workspace/coverage/default/11.otp_ctrl_regwen.2730284165 Jul 28 05:28:00 PM PDT 24 Jul 28 05:28:06 PM PDT 24 139932876 ps
T1143 /workspace/coverage/default/34.otp_ctrl_alert_test.1255486969 Jul 28 05:29:05 PM PDT 24 Jul 28 05:29:07 PM PDT 24 180663552 ps
T1144 /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.18377170 Jul 28 05:30:37 PM PDT 24 Jul 28 05:31:07 PM PDT 24 908387404 ps
T1145 /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.303060040 Jul 28 05:30:28 PM PDT 24 Jul 28 05:30:32 PM PDT 24 524764523 ps
T1146 /workspace/coverage/default/25.otp_ctrl_parallel_key_req.2418614562 Jul 28 05:28:42 PM PDT 24 Jul 28 05:29:16 PM PDT 24 1673330073 ps
T1147 /workspace/coverage/default/7.otp_ctrl_regwen.925594846 Jul 28 05:27:43 PM PDT 24 Jul 28 05:27:51 PM PDT 24 2917732941 ps
T1148 /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.941452576 Jul 28 05:28:58 PM PDT 24 Jul 28 05:37:37 PM PDT 24 207723166344 ps
T1149 /workspace/coverage/default/11.otp_ctrl_init_fail.3391118016 Jul 28 05:27:54 PM PDT 24 Jul 28 05:27:58 PM PDT 24 162389998 ps
T1150 /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.2776086653 Jul 28 05:27:28 PM PDT 24 Jul 28 05:56:19 PM PDT 24 163354301703 ps
T1151 /workspace/coverage/default/42.otp_ctrl_init_fail.496594767 Jul 28 05:29:30 PM PDT 24 Jul 28 05:29:34 PM PDT 24 147614603 ps
T1152 /workspace/coverage/default/35.otp_ctrl_parallel_key_req.2051178379 Jul 28 05:29:12 PM PDT 24 Jul 28 05:29:20 PM PDT 24 331817252 ps
T1153 /workspace/coverage/default/15.otp_ctrl_regwen.1063507550 Jul 28 05:28:03 PM PDT 24 Jul 28 05:28:08 PM PDT 24 156847253 ps
T1154 /workspace/coverage/default/227.otp_ctrl_init_fail.4213921432 Jul 28 05:31:15 PM PDT 24 Jul 28 05:31:19 PM PDT 24 306316995 ps
T239 /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.357246397 Jul 28 05:29:11 PM PDT 24 Jul 28 05:29:17 PM PDT 24 178127170 ps
T1155 /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2977405719 Jul 28 05:27:59 PM PDT 24 Jul 28 05:28:23 PM PDT 24 816046901 ps
T1156 /workspace/coverage/default/179.otp_ctrl_init_fail.292961532 Jul 28 05:31:00 PM PDT 24 Jul 28 05:31:04 PM PDT 24 133665239 ps
T1157 /workspace/coverage/default/43.otp_ctrl_regwen.1987892997 Jul 28 05:29:40 PM PDT 24 Jul 28 05:29:46 PM PDT 24 231854511 ps
T1158 /workspace/coverage/default/12.otp_ctrl_init_fail.1694439760 Jul 28 05:27:58 PM PDT 24 Jul 28 05:28:03 PM PDT 24 668186428 ps
T240 /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2346614703 Jul 28 05:28:05 PM PDT 24 Jul 28 05:28:28 PM PDT 24 1786219776 ps
T1159 /workspace/coverage/default/0.otp_ctrl_alert_test.1289129043 Jul 28 05:27:22 PM PDT 24 Jul 28 05:27:25 PM PDT 24 722784743 ps
T1160 /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1156290026 Jul 28 05:28:34 PM PDT 24 Jul 28 05:28:38 PM PDT 24 141621453 ps
T1161 /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.605400628 Jul 28 05:27:44 PM PDT 24 Jul 28 05:58:54 PM PDT 24 230280493352 ps
T1162 /workspace/coverage/default/287.otp_ctrl_init_fail.2217409044 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:33 PM PDT 24 153568579 ps
T1163 /workspace/coverage/default/41.otp_ctrl_test_access.3098979468 Jul 28 05:29:29 PM PDT 24 Jul 28 05:29:42 PM PDT 24 818572757 ps
T1164 /workspace/coverage/default/155.otp_ctrl_init_fail.2738414293 Jul 28 05:30:46 PM PDT 24 Jul 28 05:30:50 PM PDT 24 530333475 ps
T1165 /workspace/coverage/default/0.otp_ctrl_macro_errs.1397395046 Jul 28 05:27:22 PM PDT 24 Jul 28 05:27:33 PM PDT 24 763389000 ps
T1166 /workspace/coverage/default/33.otp_ctrl_alert_test.1215867613 Jul 28 05:29:05 PM PDT 24 Jul 28 05:29:08 PM PDT 24 261347088 ps
T1167 /workspace/coverage/default/260.otp_ctrl_init_fail.473823214 Jul 28 05:31:23 PM PDT 24 Jul 28 05:31:27 PM PDT 24 148177254 ps
T1168 /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.3676442357 Jul 28 05:30:15 PM PDT 24 Jul 28 05:55:59 PM PDT 24 94579571293 ps
T1169 /workspace/coverage/default/0.otp_ctrl_partition_walk.3136230734 Jul 28 05:27:17 PM PDT 24 Jul 28 05:27:37 PM PDT 24 766279136 ps
T1170 /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3350611608 Jul 28 05:30:10 PM PDT 24 Jul 28 05:52:27 PM PDT 24 150284815236 ps
T1171 /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.4251800021 Jul 28 05:28:35 PM PDT 24 Jul 28 05:37:00 PM PDT 24 108887927515 ps
T1172 /workspace/coverage/default/28.otp_ctrl_alert_test.531001675 Jul 28 05:28:49 PM PDT 24 Jul 28 05:28:52 PM PDT 24 811007998 ps
T1173 /workspace/coverage/default/6.otp_ctrl_alert_test.1937926946 Jul 28 05:27:38 PM PDT 24 Jul 28 05:27:39 PM PDT 24 114067781 ps
T381 /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1318157019 Jul 28 05:29:57 PM PDT 24 Jul 28 05:44:47 PM PDT 24 172004906315 ps
T1174 /workspace/coverage/default/10.otp_ctrl_stress_all.3725253061 Jul 28 05:27:55 PM PDT 24 Jul 28 05:30:38 PM PDT 24 73359896918 ps
T1175 /workspace/coverage/default/26.otp_ctrl_regwen.985014017 Jul 28 05:28:44 PM PDT 24 Jul 28 05:28:50 PM PDT 24 309161839 ps
T1176 /workspace/coverage/default/43.otp_ctrl_check_fail.3317405029 Jul 28 05:29:34 PM PDT 24 Jul 28 05:29:44 PM PDT 24 1070301364 ps
T1177 /workspace/coverage/default/278.otp_ctrl_init_fail.1061152045 Jul 28 05:31:29 PM PDT 24 Jul 28 05:31:33 PM PDT 24 207312880 ps
T1178 /workspace/coverage/default/46.otp_ctrl_init_fail.678603141 Jul 28 05:29:41 PM PDT 24 Jul 28 05:29:47 PM PDT 24 2634228386 ps
T1179 /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.88425387 Jul 28 05:30:23 PM PDT 24 Jul 28 06:05:34 PM PDT 24 693756209820 ps
T1180 /workspace/coverage/default/248.otp_ctrl_init_fail.798660627 Jul 28 05:31:24 PM PDT 24 Jul 28 05:31:29 PM PDT 24 358509724 ps
T1181 /workspace/coverage/default/5.otp_ctrl_parallel_key_req.2428148302 Jul 28 05:27:34 PM PDT 24 Jul 28 05:27:41 PM PDT 24 280724696 ps
T1182 /workspace/coverage/default/157.otp_ctrl_init_fail.1732042035 Jul 28 05:30:45 PM PDT 24 Jul 28 05:30:50 PM PDT 24 160185723 ps
T1183 /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.869409539 Jul 28 05:27:25 PM PDT 24 Jul 28 05:27:30 PM PDT 24 474981843 ps
T1184 /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.2098743994 Jul 28 05:30:12 PM PDT 24 Jul 28 05:30:17 PM PDT 24 602318475 ps
T1185 /workspace/coverage/default/0.otp_ctrl_init_fail.3507916496 Jul 28 05:27:22 PM PDT 24 Jul 28 05:27:27 PM PDT 24 1802978985 ps
T1186 /workspace/coverage/default/4.otp_ctrl_macro_errs.2033651983 Jul 28 05:27:36 PM PDT 24 Jul 28 05:27:48 PM PDT 24 844398005 ps
T1187 /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1007340204 Jul 28 05:30:50 PM PDT 24 Jul 28 05:30:53 PM PDT 24 211691722 ps
T1188 /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1816368987 Jul 28 05:30:15 PM PDT 24 Jul 28 05:54:54 PM PDT 24 75037545306 ps
T1189 /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.3568034662 Jul 28 05:27:49 PM PDT 24 Jul 28 05:27:53 PM PDT 24 149513748 ps
T1190 /workspace/coverage/default/12.otp_ctrl_check_fail.2361610152 Jul 28 05:28:00 PM PDT 24 Jul 28 05:28:03 PM PDT 24 279496709 ps
T1191 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3002155040 Jul 28 05:21:00 PM PDT 24 Jul 28 05:21:02 PM PDT 24 592175365 ps
T262 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2874208141 Jul 28 05:20:25 PM PDT 24 Jul 28 05:20:30 PM PDT 24 1694885181 ps
T1192 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3173880023 Jul 28 05:20:38 PM PDT 24 Jul 28 05:20:40 PM PDT 24 37788954 ps
T257 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3717338993 Jul 28 05:20:38 PM PDT 24 Jul 28 05:21:16 PM PDT 24 19709557336 ps
T1193 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2007705701 Jul 28 05:20:47 PM PDT 24 Jul 28 05:20:49 PM PDT 24 137442849 ps
T260 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.926651847 Jul 28 05:20:56 PM PDT 24 Jul 28 05:21:00 PM PDT 24 250586618 ps
T258 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1898043912 Jul 28 05:21:04 PM PDT 24 Jul 28 05:21:27 PM PDT 24 3808491316 ps
T1194 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3037364234 Jul 28 05:21:17 PM PDT 24 Jul 28 05:21:19 PM PDT 24 562487377 ps
T1195 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2998544064 Jul 28 05:21:11 PM PDT 24 Jul 28 05:21:13 PM PDT 24 569627544 ps
T1196 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3208614862 Jul 28 05:21:08 PM PDT 24 Jul 28 05:21:09 PM PDT 24 41362576 ps
T297 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4118634303 Jul 28 05:21:05 PM PDT 24 Jul 28 05:21:07 PM PDT 24 703303751 ps
T259 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2577889069 Jul 28 05:21:00 PM PDT 24 Jul 28 05:21:28 PM PDT 24 20743262567 ps
T298 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.4275710847 Jul 28 05:20:27 PM PDT 24 Jul 28 05:20:30 PM PDT 24 88616235 ps
T1197 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1123046150 Jul 28 05:20:30 PM PDT 24 Jul 28 05:20:36 PM PDT 24 149807755 ps
T1198 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.698544434 Jul 28 05:20:24 PM PDT 24 Jul 28 05:20:26 PM PDT 24 109209142 ps
T333 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2078935238 Jul 28 05:21:06 PM PDT 24 Jul 28 05:21:36 PM PDT 24 20173649549 ps
T1199 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1071019587 Jul 28 05:21:12 PM PDT 24 Jul 28 05:21:14 PM PDT 24 551157396 ps
T1200 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.4151883225 Jul 28 05:21:07 PM PDT 24 Jul 28 05:21:09 PM PDT 24 75707286 ps
T275 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3887609637 Jul 28 05:21:08 PM PDT 24 Jul 28 05:21:09 PM PDT 24 40448420 ps
T1201 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2843990869 Jul 28 05:20:33 PM PDT 24 Jul 28 05:20:35 PM PDT 24 69224197 ps
T1202 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.749760273 Jul 28 05:21:06 PM PDT 24 Jul 28 05:21:09 PM PDT 24 250483089 ps
T1203 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3982734839 Jul 28 05:21:05 PM PDT 24 Jul 28 05:21:07 PM PDT 24 204247314 ps
T335 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.823548534 Jul 28 05:21:00 PM PDT 24 Jul 28 05:21:22 PM PDT 24 4865921170 ps
T1204 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.533219535 Jul 28 05:20:46 PM PDT 24 Jul 28 05:20:54 PM PDT 24 180473558 ps
T1205 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.770306126 Jul 28 05:21:07 PM PDT 24 Jul 28 05:21:09 PM PDT 24 92017206 ps
T1206 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.34138710 Jul 28 05:20:18 PM PDT 24 Jul 28 05:20:23 PM PDT 24 384917202 ps
T334 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.82209355 Jul 28 05:20:49 PM PDT 24 Jul 28 05:21:11 PM PDT 24 4541110873 ps
T299 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.645857384 Jul 28 05:20:54 PM PDT 24 Jul 28 05:20:55 PM PDT 24 148509540 ps
T1207 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3245834536 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:14 PM PDT 24 133757030 ps
T1208 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.37917479 Jul 28 05:20:58 PM PDT 24 Jul 28 05:21:03 PM PDT 24 110954534 ps
T1209 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1329265110 Jul 28 05:21:15 PM PDT 24 Jul 28 05:21:16 PM PDT 24 56057987 ps
T1210 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3833740707 Jul 28 05:20:53 PM PDT 24 Jul 28 05:20:57 PM PDT 24 393477913 ps
T1211 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3695504057 Jul 28 05:20:32 PM PDT 24 Jul 28 05:20:33 PM PDT 24 138672898 ps
T1212 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2770834108 Jul 28 05:21:00 PM PDT 24 Jul 28 05:21:04 PM PDT 24 1723556392 ps
T1213 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3484928118 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:15 PM PDT 24 570611999 ps
T1214 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1481868787 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:15 PM PDT 24 76373450 ps
T1215 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3026090750 Jul 28 05:21:06 PM PDT 24 Jul 28 05:21:09 PM PDT 24 125128809 ps
T300 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.327799116 Jul 28 05:20:39 PM PDT 24 Jul 28 05:20:42 PM PDT 24 1092684046 ps
T308 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1632569978 Jul 28 05:20:40 PM PDT 24 Jul 28 05:20:46 PM PDT 24 216289675 ps
T1216 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3984014268 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:14 PM PDT 24 38994547 ps
T1217 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2971160829 Jul 28 05:21:07 PM PDT 24 Jul 28 05:21:15 PM PDT 24 172899412 ps
T1218 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1416954246 Jul 28 05:21:12 PM PDT 24 Jul 28 05:21:13 PM PDT 24 542753306 ps
T309 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.726429162 Jul 28 05:20:29 PM PDT 24 Jul 28 05:20:33 PM PDT 24 60650006 ps
T301 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2362257982 Jul 28 05:20:46 PM PDT 24 Jul 28 05:20:49 PM PDT 24 258492254 ps
T1219 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1748369365 Jul 28 05:21:12 PM PDT 24 Jul 28 05:21:14 PM PDT 24 60365449 ps
T302 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2225119447 Jul 28 05:21:05 PM PDT 24 Jul 28 05:21:09 PM PDT 24 209871027 ps
T303 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1665772943 Jul 28 05:20:32 PM PDT 24 Jul 28 05:20:36 PM PDT 24 519764756 ps
T1220 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1930822839 Jul 28 05:20:30 PM PDT 24 Jul 28 05:20:34 PM PDT 24 384172752 ps
T1221 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1937438334 Jul 28 05:20:26 PM PDT 24 Jul 28 05:20:28 PM PDT 24 156811546 ps
T1222 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.42078164 Jul 28 05:20:25 PM PDT 24 Jul 28 05:20:30 PM PDT 24 259692259 ps
T340 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2464600231 Jul 28 05:20:38 PM PDT 24 Jul 28 05:20:56 PM PDT 24 1344627762 ps
T1223 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2476661690 Jul 28 05:20:32 PM PDT 24 Jul 28 05:20:43 PM PDT 24 638601359 ps
T1224 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1721920367 Jul 28 05:20:57 PM PDT 24 Jul 28 05:20:59 PM PDT 24 40548717 ps
T1225 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.837137173 Jul 28 05:21:17 PM PDT 24 Jul 28 05:21:19 PM PDT 24 595997175 ps
T1226 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1217720433 Jul 28 05:21:04 PM PDT 24 Jul 28 05:21:10 PM PDT 24 297856143 ps
T1227 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3097218035 Jul 28 05:21:11 PM PDT 24 Jul 28 05:21:13 PM PDT 24 118566273 ps
T1228 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2520542184 Jul 28 05:20:33 PM PDT 24 Jul 28 05:20:35 PM PDT 24 67170801 ps
T341 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3847945135 Jul 28 05:20:54 PM PDT 24 Jul 28 05:21:14 PM PDT 24 4991546833 ps
T1229 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2894994134 Jul 28 05:20:19 PM PDT 24 Jul 28 05:20:21 PM PDT 24 132721334 ps
T1230 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.4194697067 Jul 28 05:21:15 PM PDT 24 Jul 28 05:21:16 PM PDT 24 81788438 ps
T276 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.345152832 Jul 28 05:20:28 PM PDT 24 Jul 28 05:20:30 PM PDT 24 173858493 ps
T1231 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2616633808 Jul 28 05:20:46 PM PDT 24 Jul 28 05:20:51 PM PDT 24 108627781 ps
T280 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3794811518 Jul 28 05:21:04 PM PDT 24 Jul 28 05:21:06 PM PDT 24 183581734 ps
T1232 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2953330293 Jul 28 05:21:07 PM PDT 24 Jul 28 05:21:09 PM PDT 24 40717608 ps
T1233 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1049684238 Jul 28 05:20:27 PM PDT 24 Jul 28 05:20:32 PM PDT 24 1862791667 ps
T1234 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3282908091 Jul 28 05:21:05 PM PDT 24 Jul 28 05:21:09 PM PDT 24 1678577674 ps
T1235 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.167329068 Jul 28 05:20:29 PM PDT 24 Jul 28 05:20:31 PM PDT 24 64128318 ps
T1236 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1276296561 Jul 28 05:21:04 PM PDT 24 Jul 28 05:21:06 PM PDT 24 145893749 ps
T343 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3399511854 Jul 28 05:20:30 PM PDT 24 Jul 28 05:20:45 PM PDT 24 1280049677 ps
T1237 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2021863056 Jul 28 05:20:27 PM PDT 24 Jul 28 05:20:29 PM PDT 24 101388275 ps
T1238 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.608249259 Jul 28 05:21:12 PM PDT 24 Jul 28 05:21:14 PM PDT 24 42709579 ps
T1239 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2850642878 Jul 28 05:20:28 PM PDT 24 Jul 28 05:20:30 PM PDT 24 86613348 ps
T342 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3068690046 Jul 28 05:20:32 PM PDT 24 Jul 28 05:20:51 PM PDT 24 2540161804 ps
T304 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.448001035 Jul 28 05:20:45 PM PDT 24 Jul 28 05:20:49 PM PDT 24 187092633 ps
T1240 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.324491832 Jul 28 05:20:46 PM PDT 24 Jul 28 05:20:52 PM PDT 24 306738580 ps
T1241 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1135124043 Jul 28 05:21:00 PM PDT 24 Jul 28 05:21:03 PM PDT 24 106886740 ps
T1242 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4215496598 Jul 28 05:20:47 PM PDT 24 Jul 28 05:20:57 PM PDT 24 1917280050 ps
T1243 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2073826155 Jul 28 05:21:02 PM PDT 24 Jul 28 05:21:04 PM PDT 24 150547528 ps
T1244 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.164716251 Jul 28 05:21:07 PM PDT 24 Jul 28 05:21:09 PM PDT 24 64686763 ps
T1245 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2737944074 Jul 28 05:20:47 PM PDT 24 Jul 28 05:20:48 PM PDT 24 165608668 ps
T1246 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.4033485729 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:15 PM PDT 24 39301892 ps
T1247 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2142409770 Jul 28 05:20:50 PM PDT 24 Jul 28 05:20:53 PM PDT 24 140747687 ps
T1248 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3266892372 Jul 28 05:21:08 PM PDT 24 Jul 28 05:21:10 PM PDT 24 539603712 ps
T1249 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1929306494 Jul 28 05:21:05 PM PDT 24 Jul 28 05:21:07 PM PDT 24 76727444 ps
T261 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.4090862892 Jul 28 05:20:50 PM PDT 24 Jul 28 05:21:02 PM PDT 24 1058065946 ps
T277 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3682442449 Jul 28 05:20:45 PM PDT 24 Jul 28 05:20:47 PM PDT 24 43324991 ps
T1250 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.4212766301 Jul 28 05:20:59 PM PDT 24 Jul 28 05:21:01 PM PDT 24 664392737 ps
T1251 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3581228472 Jul 28 05:20:39 PM PDT 24 Jul 28 05:20:41 PM PDT 24 68462940 ps
T1252 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1703642263 Jul 28 05:20:39 PM PDT 24 Jul 28 05:20:40 PM PDT 24 74625049 ps
T1253 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2701438632 Jul 28 05:20:45 PM PDT 24 Jul 28 05:20:50 PM PDT 24 1067290955 ps
T1254 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3832041229 Jul 28 05:21:05 PM PDT 24 Jul 28 05:21:08 PM PDT 24 82125384 ps
T279 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1560952840 Jul 28 05:20:45 PM PDT 24 Jul 28 05:20:47 PM PDT 24 117807264 ps
T1255 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2954499893 Jul 28 05:20:30 PM PDT 24 Jul 28 05:20:36 PM PDT 24 242279967 ps
T1256 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1723119555 Jul 28 05:20:30 PM PDT 24 Jul 28 05:20:39 PM PDT 24 678717015 ps
T1257 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2513988348 Jul 28 05:20:40 PM PDT 24 Jul 28 05:20:43 PM PDT 24 345417520 ps
T1258 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1134613267 Jul 28 05:21:14 PM PDT 24 Jul 28 05:21:16 PM PDT 24 54477165 ps
T278 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.724614624 Jul 28 05:20:39 PM PDT 24 Jul 28 05:20:41 PM PDT 24 91889439 ps
T1259 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.155791970 Jul 28 05:20:34 PM PDT 24 Jul 28 05:20:40 PM PDT 24 122487191 ps
T1260 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3779259963 Jul 28 05:20:32 PM PDT 24 Jul 28 05:20:35 PM PDT 24 892113436 ps
T1261 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2104645678 Jul 28 05:20:32 PM PDT 24 Jul 28 05:20:40 PM PDT 24 3119520237 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%