Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	54389	1			T4	141		T5	13		T9	110
access_err	61633	1			T3	12		T4	261		T8	6
write_blank_err	424	1			T3	11		T5	1		T13	1
ecc_uncorr_err	68822	1			T3	655		T5	394		T101	82
ecc_corr_err	1405	1			T3	2		T4	75		T101	4
no_err	90969	1			T3	35		T4	167		T8	33

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	792	1			T3	8		T5	2		T14	3
secret2	25261	1			T3	8		T4	57		T8	17
secret1	30706	1			T3	6		T4	48		T8	1
secret0	32848	1			T3	668		T4	43		T8	2
hw_cfg1	39691	1			T3	1		T4	29		T8	3
hw_cfg0	25130	1			T3	4		T4	57		T5	53
rot_creator_auth_state	21164	1			T3	11		T4	46		T8	2
rot_creator_auth_codesign	25549	1			T3	2		T4	55		T8	3
owner_sw_cfg	21464	1			T3	2		T4	57		T8	4
creator_sw_cfg	23037	1			T3	4		T4	80		T5	79
vendor_test	32000	1			T3	1		T4	172		T8	7

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3705	1			T9	110		T329	15		T99	226
fsm_err	secret1	3690	1			T250	214		T94	126		T197	139
fsm_err	secret0	3498	1			T150	47		T169	43		T245	38
fsm_err	hw_cfg1	3412	1			T94	206		T99	479		T324	15
fsm_err	hw_cfg0	6277	1			T102	468		T204	435		T330	223
fsm_err	rot_creator_auth_state	2218	1			T104	250		T205	83		T331	47
fsm_err	rot_creator_auth_codesign	7197	1			T196	497		T167	12		T189	35
fsm_err	owner_sw_cfg	4196	1			T101	30		T156	413		T332	347
fsm_err	creator_sw_cfg	5576	1			T155	72		T215	266		T165	54
fsm_err	vendor_test	14620	1			T4	141		T5	13		T11	356
access_err	life_cycle	792	1			T3	8		T5	2		T14	3
access_err	secret2	10647	1			T4	45		T5	68		T6	12
access_err	secret1	5631	1			T4	42		T5	61		T6	5
access_err	secret0	4659	1			T3	1		T4	15		T5	33
access_err	hw_cfg1	1252	1			T4	4		T8	1		T5	9
access_err	hw_cfg0	2124	1			T4	6		T5	13		T6	1
access_err	rot_creator_auth_state	6196	1			T4	25		T5	30		T16	39
access_err	rot_creator_auth_codesign	8074	1			T4	31		T8	2		T5	77
access_err	owner_sw_cfg	7032	1			T4	32		T8	1		T5	32
access_err	creator_sw_cfg	7784	1			T3	3		T4	49		T5	39
access_err	vendor_test	7442	1			T4	12		T8	2		T5	71
write_blank_err	secret2	12	1			T99	1		T19	1		T20	1
write_blank_err	secret1	28	1			T5	1		T94	1		T322	1
write_blank_err	secret0	39	1			T3	2		T13	1		T161	1
write_blank_err	hw_cfg1	81	1			T14	2		T160	1		T94	1
write_blank_err	hw_cfg0	12	1			T94	1		T317	1		T64	1
write_blank_err	rot_creator_auth_state	114	1			T3	7		T160	5		T161	4
write_blank_err	rot_creator_auth_codesign	41	1			T160	1		T333	7		T172	2
write_blank_err	owner_sw_cfg	35	1			T3	2		T161	1		T312	2
write_blank_err	creator_sw_cfg	29	1			T160	1		T94	1		T64	1
write_blank_err	vendor_test	33	1			T160	5		T94	1		T161	1
ecc_uncorr_err	secret2	5449	1			T99	212		T191	62		T19	622
ecc_uncorr_err	secret1	11830	1			T5	394		T101	29		T155	79
ecc_uncorr_err	secret0	16008	1			T3	655		T101	22		T13	597
ecc_uncorr_err	hw_cfg1	23906	1			T14	710		T160	447		T94	355
ecc_uncorr_err	hw_cfg0	4130	1			T94	727		T334	46		T189	25
ecc_uncorr_err	rot_creator_auth_state	3999	1			T167	16		T335	42		T336	52
ecc_uncorr_err	rot_creator_auth_codesign	1241	1			T101	31		T165	49		T189	33
ecc_uncorr_err	owner_sw_cfg	935	1			T155	81		T167	12		T165	110
ecc_uncorr_err	creator_sw_cfg	1324	1			T94	450		T167	29		T335	45
ecc_corr_err	secret2	95	1			T4	5		T69	13		T70	1
ecc_corr_err	secret1	109	1			T4	3		T69	1		T70	3
ecc_corr_err	secret0	152	1			T3	2		T4	8		T101	2
ecc_corr_err	hw_cfg1	310	1			T4	12		T69	25		T167	4
ecc_corr_err	hw_cfg0	244	1			T4	14		T69	11		T189	2
ecc_corr_err	rot_creator_auth_state	120	1			T4	5		T155	1		T70	1
ecc_corr_err	rot_creator_auth_codesign	138	1			T4	10		T101	1		T69	3
ecc_corr_err	owner_sw_cfg	112	1			T4	10		T69	2		T51	4
ecc_corr_err	creator_sw_cfg	125	1			T4	8		T101	1		T69	3
no_err	secret2	5353	1			T3	8		T4	7		T8	17
no_err	secret1	9418	1			T3	6		T4	3		T8	1
no_err	secret0	8492	1			T3	8		T4	20		T8	2
no_err	hw_cfg1	10730	1			T3	1		T4	13		T8	2
no_err	hw_cfg0	12343	1			T3	4		T4	37		T5	40
no_err	rot_creator_auth_state	8517	1			T3	4		T4	16		T8	2
no_err	rot_creator_auth_codesign	8858	1			T3	2		T4	14		T8	1
no_err	owner_sw_cfg	9154	1			T4	15		T8	3		T5	42
no_err	creator_sw_cfg	8199	1			T3	1		T4	23		T5	40
no_err	vendor_test	9905	1			T3	1		T4	19		T8	5

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded