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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.93 93.76 96.67 96.09 91.17 97.19 96.34 93.28


Total test records in report: 1327
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T1265 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3653507777 Jul 29 05:49:48 PM PDT 24 Jul 29 05:49:49 PM PDT 24 47058980 ps
T290 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3199431791 Jul 29 05:50:19 PM PDT 24 Jul 29 05:50:21 PM PDT 24 159231776 ps
T1266 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1530597851 Jul 29 05:50:08 PM PDT 24 Jul 29 05:50:11 PM PDT 24 715615650 ps
T1267 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.715710433 Jul 29 05:50:03 PM PDT 24 Jul 29 05:50:05 PM PDT 24 385116074 ps
T291 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3928461853 Jul 29 05:50:13 PM PDT 24 Jul 29 05:50:16 PM PDT 24 116215611 ps
T1268 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2130202195 Jul 29 05:50:23 PM PDT 24 Jul 29 05:50:25 PM PDT 24 175485322 ps
T1269 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3319716539 Jul 29 05:50:44 PM PDT 24 Jul 29 05:50:45 PM PDT 24 41872585 ps
T1270 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3925437667 Jul 29 05:50:26 PM PDT 24 Jul 29 05:50:28 PM PDT 24 140064944 ps
T1271 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.171467219 Jul 29 05:50:41 PM PDT 24 Jul 29 05:50:43 PM PDT 24 628031114 ps
T1272 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2395259221 Jul 29 05:50:45 PM PDT 24 Jul 29 05:50:47 PM PDT 24 43868206 ps
T1273 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2562450985 Jul 29 05:50:27 PM PDT 24 Jul 29 05:50:29 PM PDT 24 74557499 ps
T1274 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.493129063 Jul 29 05:50:22 PM PDT 24 Jul 29 05:50:24 PM PDT 24 51952563 ps
T342 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2713254186 Jul 29 05:50:15 PM PDT 24 Jul 29 05:50:40 PM PDT 24 20085991649 ps
T1275 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1910662457 Jul 29 05:50:32 PM PDT 24 Jul 29 05:50:35 PM PDT 24 395961539 ps
T343 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1140807523 Jul 29 05:50:27 PM PDT 24 Jul 29 05:50:46 PM PDT 24 1264926204 ps
T1276 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2616146796 Jul 29 05:50:23 PM PDT 24 Jul 29 05:50:25 PM PDT 24 91750577 ps
T1277 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.695896315 Jul 29 05:50:41 PM PDT 24 Jul 29 05:50:42 PM PDT 24 130790432 ps
T1278 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.921647009 Jul 29 05:50:25 PM PDT 24 Jul 29 05:50:27 PM PDT 24 685874946 ps
T296 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3765557761 Jul 29 05:50:11 PM PDT 24 Jul 29 05:50:13 PM PDT 24 266973310 ps
T1279 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3608562283 Jul 29 05:50:13 PM PDT 24 Jul 29 05:50:17 PM PDT 24 956762079 ps
T1280 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2985976501 Jul 29 05:50:22 PM PDT 24 Jul 29 05:50:27 PM PDT 24 150963848 ps
T1281 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1014955656 Jul 29 05:50:27 PM PDT 24 Jul 29 05:50:29 PM PDT 24 44419235 ps
T1282 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2226700055 Jul 29 05:50:26 PM PDT 24 Jul 29 05:50:28 PM PDT 24 74139736 ps
T1283 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.609641997 Jul 29 05:50:04 PM PDT 24 Jul 29 05:50:06 PM PDT 24 1016649149 ps
T1284 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.4039065360 Jul 29 05:50:36 PM PDT 24 Jul 29 05:50:37 PM PDT 24 75406460 ps
T1285 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.766894039 Jul 29 05:50:47 PM PDT 24 Jul 29 05:50:48 PM PDT 24 104032679 ps
T1286 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2380236562 Jul 29 05:50:38 PM PDT 24 Jul 29 05:50:40 PM PDT 24 104487871 ps
T1287 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2961576886 Jul 29 05:50:40 PM PDT 24 Jul 29 05:50:42 PM PDT 24 154893201 ps
T1288 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.248128211 Jul 29 05:50:47 PM PDT 24 Jul 29 05:50:48 PM PDT 24 558101789 ps
T338 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2826543131 Jul 29 05:50:33 PM PDT 24 Jul 29 05:50:44 PM PDT 24 896972558 ps
T1289 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1962779420 Jul 29 05:50:11 PM PDT 24 Jul 29 05:50:14 PM PDT 24 380662727 ps
T1290 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1120633660 Jul 29 05:50:43 PM PDT 24 Jul 29 05:50:44 PM PDT 24 63742543 ps
T1291 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3025643572 Jul 29 05:50:22 PM PDT 24 Jul 29 05:50:24 PM PDT 24 269856179 ps
T1292 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1876688032 Jul 29 05:49:53 PM PDT 24 Jul 29 05:49:56 PM PDT 24 128089754 ps
T1293 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1829888595 Jul 29 05:50:31 PM PDT 24 Jul 29 05:50:42 PM PDT 24 3064358492 ps
T340 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1161823128 Jul 29 05:50:18 PM PDT 24 Jul 29 05:50:38 PM PDT 24 1519882932 ps
T1294 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1867622250 Jul 29 05:50:07 PM PDT 24 Jul 29 05:50:15 PM PDT 24 359849068 ps
T1295 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2964187349 Jul 29 05:50:45 PM PDT 24 Jul 29 05:50:46 PM PDT 24 41127714 ps
T292 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4270456369 Jul 29 05:50:17 PM PDT 24 Jul 29 05:50:24 PM PDT 24 238884845 ps
T293 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1199426514 Jul 29 05:49:47 PM PDT 24 Jul 29 05:49:54 PM PDT 24 170027052 ps
T1296 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2155903507 Jul 29 05:50:41 PM PDT 24 Jul 29 05:50:42 PM PDT 24 44869277 ps
T1297 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3978149806 Jul 29 05:49:58 PM PDT 24 Jul 29 05:49:59 PM PDT 24 40578749 ps
T1298 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3139016797 Jul 29 05:50:14 PM PDT 24 Jul 29 05:50:19 PM PDT 24 220586562 ps
T1299 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2239900909 Jul 29 05:50:14 PM PDT 24 Jul 29 05:50:19 PM PDT 24 117595176 ps
T1300 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.957446843 Jul 29 05:50:25 PM PDT 24 Jul 29 05:50:27 PM PDT 24 170839210 ps
T1301 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2453082790 Jul 29 05:50:27 PM PDT 24 Jul 29 05:51:05 PM PDT 24 18968933744 ps
T1302 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.4108231346 Jul 29 05:49:59 PM PDT 24 Jul 29 05:50:06 PM PDT 24 341681770 ps
T1303 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2210127794 Jul 29 05:50:42 PM PDT 24 Jul 29 05:50:43 PM PDT 24 71014445 ps
T1304 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.914691141 Jul 29 05:50:22 PM PDT 24 Jul 29 05:50:26 PM PDT 24 1624129451 ps
T1305 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1251500186 Jul 29 05:50:41 PM PDT 24 Jul 29 05:50:42 PM PDT 24 46193443 ps
T1306 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1912200681 Jul 29 05:50:32 PM PDT 24 Jul 29 05:50:34 PM PDT 24 140513334 ps
T1307 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3191479469 Jul 29 05:49:54 PM PDT 24 Jul 29 05:49:57 PM PDT 24 164220590 ps
T1308 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.639513092 Jul 29 05:49:47 PM PDT 24 Jul 29 05:49:53 PM PDT 24 164374654 ps
T1309 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.688396704 Jul 29 05:50:27 PM PDT 24 Jul 29 05:50:33 PM PDT 24 280106087 ps
T1310 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3623774985 Jul 29 05:50:36 PM PDT 24 Jul 29 05:50:38 PM PDT 24 42689103 ps
T346 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3854307796 Jul 29 05:50:16 PM PDT 24 Jul 29 05:50:30 PM PDT 24 1144167333 ps
T1311 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3794163296 Jul 29 05:50:10 PM PDT 24 Jul 29 05:50:12 PM PDT 24 157126512 ps
T270 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1791777533 Jul 29 05:50:21 PM PDT 24 Jul 29 05:50:44 PM PDT 24 1952054296 ps
T1312 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1034187080 Jul 29 05:50:33 PM PDT 24 Jul 29 05:50:37 PM PDT 24 125023440 ps
T294 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2442729706 Jul 29 05:50:23 PM PDT 24 Jul 29 05:50:25 PM PDT 24 93055771 ps
T1313 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2840907488 Jul 29 05:50:36 PM PDT 24 Jul 29 05:50:40 PM PDT 24 1501504752 ps
T1314 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2924781723 Jul 29 05:49:47 PM PDT 24 Jul 29 05:49:58 PM PDT 24 778874842 ps
T1315 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.176384101 Jul 29 05:50:18 PM PDT 24 Jul 29 05:50:21 PM PDT 24 71925598 ps
T1316 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2340300842 Jul 29 05:50:17 PM PDT 24 Jul 29 05:50:19 PM PDT 24 128813132 ps
T295 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2603447930 Jul 29 05:50:07 PM PDT 24 Jul 29 05:50:09 PM PDT 24 89637206 ps
T347 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2758166776 Jul 29 05:50:26 PM PDT 24 Jul 29 05:50:50 PM PDT 24 2591930206 ps
T1317 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2602319092 Jul 29 05:49:47 PM PDT 24 Jul 29 05:49:51 PM PDT 24 464722161 ps
T1318 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.64882446 Jul 29 05:50:14 PM PDT 24 Jul 29 05:50:17 PM PDT 24 78208612 ps
T1319 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2034848453 Jul 29 05:50:41 PM PDT 24 Jul 29 05:50:42 PM PDT 24 90288921 ps
T1320 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.358300124 Jul 29 05:50:46 PM PDT 24 Jul 29 05:50:48 PM PDT 24 144514144 ps
T1321 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2450373778 Jul 29 05:49:51 PM PDT 24 Jul 29 05:49:53 PM PDT 24 139352788 ps
T1322 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1630955231 Jul 29 05:50:26 PM PDT 24 Jul 29 05:50:28 PM PDT 24 143992130 ps
T1323 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2856632045 Jul 29 05:50:17 PM PDT 24 Jul 29 05:50:18 PM PDT 24 155307454 ps
T1324 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1107158893 Jul 29 05:50:27 PM PDT 24 Jul 29 05:50:32 PM PDT 24 1502487595 ps
T1325 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2255654472 Jul 29 05:50:17 PM PDT 24 Jul 29 05:50:19 PM PDT 24 138802185 ps
T1326 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2906334680 Jul 29 05:50:41 PM PDT 24 Jul 29 05:50:43 PM PDT 24 71021832 ps
T1327 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3752050844 Jul 29 05:50:15 PM PDT 24 Jul 29 05:50:19 PM PDT 24 1709274664 ps

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.3194244902
Short name T5
Test name
Test status
Simulation time 51706036237 ps
CPU time 164.09 seconds
Started Jul 29 07:42:44 PM PDT 24
Finished Jul 29 07:45:28 PM PDT 24
Peak memory 257416 kb
Host smart-d6011c20-488a-4289-a090-820ee2c1264e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194244902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.3194244902
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2875691435
Short name T13
Test name
Test status
Simulation time 62079476650 ps
CPU time 1563.87 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 08:13:57 PM PDT 24
Peak memory 328300 kb
Host smart-ce6dde8a-1b49-4ba6-bf8e-1a1f546cacf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875691435 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.2875691435
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.3238450847
Short name T99
Test name
Test status
Simulation time 56616772039 ps
CPU time 323.13 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:45:50 PM PDT 24
Peak memory 276980 kb
Host smart-2c2c2af5-6a9e-431d-8f05-1e995dfcf008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238450847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
3238450847
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.4035853363
Short name T64
Test name
Test status
Simulation time 164980480179 ps
CPU time 343.41 seconds
Started Jul 29 07:42:49 PM PDT 24
Finished Jul 29 07:48:33 PM PDT 24
Peak memory 293284 kb
Host smart-ebb74135-a001-4ed6-897e-85c566897030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035853363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.4035853363
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.2815353736
Short name T4
Test name
Test status
Simulation time 919196339 ps
CPU time 27.55 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:54 PM PDT 24
Peak memory 248660 kb
Host smart-652d886b-9549-45cc-99b0-a2459bafce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815353736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2815353736
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.2382530355
Short name T163
Test name
Test status
Simulation time 162255734 ps
CPU time 4.41 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 241960 kb
Host smart-8e5c25a7-d651-4e07-9418-08ea4af02f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382530355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2382530355
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1936316994
Short name T24
Test name
Test status
Simulation time 165040256622 ps
CPU time 304.18 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:45:46 PM PDT 24
Peak memory 271048 kb
Host smart-6cb2bda6-1da9-4069-8bad-e7c250e224e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936316994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1936316994
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2746099886
Short name T26
Test name
Test status
Simulation time 391349522 ps
CPU time 3.79 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:34 PM PDT 24
Peak memory 242208 kb
Host smart-36214b2b-a4bf-4065-ad01-562c051ea740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746099886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2746099886
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3693229339
Short name T136
Test name
Test status
Simulation time 27733861268 ps
CPU time 213.27 seconds
Started Jul 29 07:47:39 PM PDT 24
Finished Jul 29 07:51:13 PM PDT 24
Peak memory 257276 kb
Host smart-30d12fa8-8d62-420d-acd6-b1fe8bf0f8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693229339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3693229339
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1626626304
Short name T269
Test name
Test status
Simulation time 4952835427 ps
CPU time 18.6 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 244668 kb
Host smart-80c2b019-1d26-4bdc-9f8b-35caa37637e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626626304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1626626304
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1931872012
Short name T61
Test name
Test status
Simulation time 245958209 ps
CPU time 3.51 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242232 kb
Host smart-65bd3c90-1685-4406-9682-5d62d7ff32bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931872012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1931872012
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1431632554
Short name T27
Test name
Test status
Simulation time 384447001 ps
CPU time 5.38 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242172 kb
Host smart-f61984d2-f384-4f02-9e2c-db90a181e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431632554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1431632554
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.1625941017
Short name T45
Test name
Test status
Simulation time 2338828899 ps
CPU time 5.13 seconds
Started Jul 29 07:49:11 PM PDT 24
Finished Jul 29 07:49:16 PM PDT 24
Peak memory 242436 kb
Host smart-62903bef-ccb9-4002-b1b8-669c77470704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625941017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1625941017
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.1814316104
Short name T277
Test name
Test status
Simulation time 556433405860 ps
CPU time 3341.88 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 08:38:51 PM PDT 24
Peak memory 343036 kb
Host smart-7a06286b-a43d-4e6d-912e-46396ff64cbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814316104 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.1814316104
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.1180159626
Short name T94
Test name
Test status
Simulation time 48622658979 ps
CPU time 157.55 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:44:10 PM PDT 24
Peak memory 260824 kb
Host smart-cc87e110-12eb-4022-a652-db8de32d2924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180159626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.1180159626
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1978061699
Short name T51
Test name
Test status
Simulation time 1710098865 ps
CPU time 20.64 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:43:08 PM PDT 24
Peak memory 248580 kb
Host smart-fe3ca09c-a0e8-4899-8487-b84b40b508c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978061699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1978061699
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.522959722
Short name T192
Test name
Test status
Simulation time 1701591260 ps
CPU time 24.73 seconds
Started Jul 29 07:43:34 PM PDT 24
Finished Jul 29 07:43:59 PM PDT 24
Peak memory 243904 kb
Host smart-901e794a-16b9-4eeb-bc8f-c3ed4e27d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522959722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.522959722
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.4071860986
Short name T70
Test name
Test status
Simulation time 460959703 ps
CPU time 9.48 seconds
Started Jul 29 07:43:33 PM PDT 24
Finished Jul 29 07:43:42 PM PDT 24
Peak memory 248592 kb
Host smart-7a266bb0-254e-45a9-a9d2-715989bd43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071860986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.4071860986
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1881109514
Short name T15
Test name
Test status
Simulation time 414264065343 ps
CPU time 3233.71 seconds
Started Jul 29 07:41:43 PM PDT 24
Finished Jul 29 08:35:37 PM PDT 24
Peak memory 379192 kb
Host smart-9f598570-1a4e-4ba3-b0b9-25b26cf1d922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881109514 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1881109514
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1360715939
Short name T834
Test name
Test status
Simulation time 151909586 ps
CPU time 3.69 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 241944 kb
Host smart-d3362eee-d2ed-481f-8cdf-55fca160e401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360715939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1360715939
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1638730878
Short name T218
Test name
Test status
Simulation time 1543570662 ps
CPU time 20.4 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:42:13 PM PDT 24
Peak memory 243704 kb
Host smart-08b8ea11-b2b4-49f3-8716-9ac3a9bd6337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638730878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1638730878
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.2643161690
Short name T412
Test name
Test status
Simulation time 663390157 ps
CPU time 1.78 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:40:28 PM PDT 24
Peak memory 240484 kb
Host smart-f9744daa-837d-4356-9d64-1770e195af5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643161690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2643161690
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.1774033709
Short name T59
Test name
Test status
Simulation time 2266724273 ps
CPU time 6.19 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:26 PM PDT 24
Peak memory 241976 kb
Host smart-8c80cba6-4ec5-4a4a-8155-1ae69a1008ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774033709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1774033709
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.3582184121
Short name T265
Test name
Test status
Simulation time 44253698724 ps
CPU time 213.87 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:45:57 PM PDT 24
Peak memory 264876 kb
Host smart-cbaf6874-e0fb-4e9d-9e25-4a6fe676c653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582184121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.3582184121
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.43005400
Short name T206
Test name
Test status
Simulation time 97850542655 ps
CPU time 264.87 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:51:49 PM PDT 24
Peak memory 266072 kb
Host smart-1294e0e8-1bf6-4b2b-9419-a77eb8b49714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43005400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.43005400
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1711791027
Short name T63
Test name
Test status
Simulation time 201141930 ps
CPU time 4.03 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 242336 kb
Host smart-accce1d8-d7de-4697-9215-898a8fdb8fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711791027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1711791027
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.2580405000
Short name T20
Test name
Test status
Simulation time 362758661512 ps
CPU time 1746.23 seconds
Started Jul 29 07:47:57 PM PDT 24
Finished Jul 29 08:17:04 PM PDT 24
Peak memory 499764 kb
Host smart-ca0622be-ab13-44f4-a8c2-23e2658d9af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580405000 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.2580405000
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2565489582
Short name T67
Test name
Test status
Simulation time 185961852 ps
CPU time 3.84 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 241920 kb
Host smart-9eca5c17-75d8-4e09-a56d-508247683e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565489582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2565489582
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3585870826
Short name T1
Test name
Test status
Simulation time 144635310 ps
CPU time 4.97 seconds
Started Jul 29 07:49:03 PM PDT 24
Finished Jul 29 07:49:08 PM PDT 24
Peak memory 242312 kb
Host smart-e1ed87b0-4a4a-4d17-8e2f-da9a3c2bb038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585870826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3585870826
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.3623427574
Short name T10
Test name
Test status
Simulation time 2308598544 ps
CPU time 4.55 seconds
Started Jul 29 07:48:52 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242204 kb
Host smart-82d9175c-262e-498a-b316-b6e6b5bbd2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623427574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3623427574
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.4258117569
Short name T128
Test name
Test status
Simulation time 34495084733 ps
CPU time 293.14 seconds
Started Jul 29 07:47:42 PM PDT 24
Finished Jul 29 07:52:35 PM PDT 24
Peak memory 259028 kb
Host smart-c44d0a95-3d8e-4ed3-87b9-9ce08c0bb4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258117569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.4258117569
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.660725501
Short name T266
Test name
Test status
Simulation time 20787895913 ps
CPU time 179.8 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:44:53 PM PDT 24
Peak memory 259432 kb
Host smart-c184537d-8681-4476-a744-5ace7bc60d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660725501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.
660725501
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.2077087412
Short name T181
Test name
Test status
Simulation time 224740398 ps
CPU time 3.87 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 241920 kb
Host smart-ba4dfca2-8636-4fbc-8682-15c97b60ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077087412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2077087412
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1284688287
Short name T82
Test name
Test status
Simulation time 1208325190 ps
CPU time 19.87 seconds
Started Jul 29 07:43:01 PM PDT 24
Finished Jul 29 07:43:21 PM PDT 24
Peak memory 243144 kb
Host smart-d0a9f163-37f5-45fd-9337-85925b16e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284688287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1284688287
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.3150199177
Short name T571
Test name
Test status
Simulation time 264080097 ps
CPU time 4.48 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 242384 kb
Host smart-ef206cbf-b61e-47d5-905b-df480d799809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150199177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3150199177
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1929105508
Short name T102
Test name
Test status
Simulation time 4375907579 ps
CPU time 21.31 seconds
Started Jul 29 07:48:03 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 241940 kb
Host smart-5e84ecc0-71b5-4221-8665-ce8f1a41b288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929105508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1929105508
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.10296766
Short name T142
Test name
Test status
Simulation time 208292419 ps
CPU time 9.63 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:38 PM PDT 24
Peak memory 242148 kb
Host smart-04aa44c3-2278-433b-84f3-5e229216281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10296766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.10296766
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.170083556
Short name T35
Test name
Test status
Simulation time 3713764989 ps
CPU time 11.46 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:43:09 PM PDT 24
Peak memory 242436 kb
Host smart-ac5a5901-106a-415b-a5b6-005d277180c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170083556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.170083556
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1161823128
Short name T340
Test name
Test status
Simulation time 1519882932 ps
CPU time 19.52 seconds
Started Jul 29 05:50:18 PM PDT 24
Finished Jul 29 05:50:38 PM PDT 24
Peak memory 238904 kb
Host smart-873c0865-69b5-4828-9339-8fab2ae22675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161823128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1161823128
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2670921056
Short name T589
Test name
Test status
Simulation time 3554914129 ps
CPU time 6.69 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:42:52 PM PDT 24
Peak memory 242404 kb
Host smart-5b944353-2875-4b91-a909-62a71aac434e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670921056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2670921056
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.413214117
Short name T38
Test name
Test status
Simulation time 23229944622 ps
CPU time 54.12 seconds
Started Jul 29 07:43:23 PM PDT 24
Finished Jul 29 07:44:17 PM PDT 24
Peak memory 245600 kb
Host smart-0599f4bd-7dea-470b-af60-85465c65d689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413214117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.413214117
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.2161845386
Short name T127
Test name
Test status
Simulation time 116776782 ps
CPU time 4.17 seconds
Started Jul 29 07:49:03 PM PDT 24
Finished Jul 29 07:49:07 PM PDT 24
Peak memory 242300 kb
Host smart-d0976b29-3eb4-4228-a090-9828c93c5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161845386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2161845386
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1136877948
Short name T256
Test name
Test status
Simulation time 191115510329 ps
CPU time 1138.36 seconds
Started Jul 29 07:42:28 PM PDT 24
Finished Jul 29 08:01:27 PM PDT 24
Peak memory 331668 kb
Host smart-c22cf808-752d-4c8c-ac59-661c7136415a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136877948 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.1136877948
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3115733789
Short name T148
Test name
Test status
Simulation time 124914599089 ps
CPU time 276.56 seconds
Started Jul 29 07:41:07 PM PDT 24
Finished Jul 29 07:45:44 PM PDT 24
Peak memory 281464 kb
Host smart-345a69d7-9d77-44de-a6f5-95c68fb50072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115733789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3115733789
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.4221530107
Short name T288
Test name
Test status
Simulation time 40967293 ps
CPU time 1.6 seconds
Started Jul 29 05:50:18 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 241064 kb
Host smart-6d4f44e8-db4e-4682-9dee-c5eb0f253213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221530107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.4221530107
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.796732651
Short name T43
Test name
Test status
Simulation time 22661704145 ps
CPU time 44.88 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:54 PM PDT 24
Peak memory 245236 kb
Host smart-5eaae277-afd7-4c87-bf8f-0a863b2bb455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796732651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.796732651
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3392036388
Short name T30
Test name
Test status
Simulation time 1693322480 ps
CPU time 31.97 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:43:17 PM PDT 24
Peak memory 242708 kb
Host smart-36b139ab-a59b-4d2c-a698-3ef960ac6b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392036388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3392036388
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3452014655
Short name T249
Test name
Test status
Simulation time 771799075 ps
CPU time 23.19 seconds
Started Jul 29 07:48:15 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 242424 kb
Host smart-e3e056ee-146e-4a1a-88fe-f549605ea235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452014655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3452014655
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2456327567
Short name T11
Test name
Test status
Simulation time 1994404518 ps
CPU time 18.05 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 241760 kb
Host smart-faccbc73-99ea-4d17-a42f-3f1761d4aacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456327567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2456327567
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2130905305
Short name T66
Test name
Test status
Simulation time 657224063 ps
CPU time 6.16 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:33 PM PDT 24
Peak memory 242100 kb
Host smart-8a0a7888-ff8f-4b5f-9b69-1ce8d6c2ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130905305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2130905305
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3589466783
Short name T158
Test name
Test status
Simulation time 5538706608 ps
CPU time 30.41 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:44:14 PM PDT 24
Peak memory 248896 kb
Host smart-c9d2e047-960d-4a5b-939a-f86803d289c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589466783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3589466783
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.619992934
Short name T247
Test name
Test status
Simulation time 42756274787 ps
CPU time 156.1 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:50:01 PM PDT 24
Peak memory 256832 kb
Host smart-3482fe0f-89a8-49de-b7fb-31c1e0b50b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619992934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.
619992934
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.294950022
Short name T140
Test name
Test status
Simulation time 2330521347 ps
CPU time 8.71 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:47:59 PM PDT 24
Peak memory 242396 kb
Host smart-355e244c-7f2a-49ac-ac88-565d034bddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294950022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.294950022
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2398748803
Short name T68
Test name
Test status
Simulation time 309969749 ps
CPU time 5.6 seconds
Started Jul 29 07:41:05 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 241912 kb
Host smart-feaa6e0c-e4a9-4a29-9118-5137294b4f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398748803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2398748803
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1742857810
Short name T358
Test name
Test status
Simulation time 369563024 ps
CPU time 9.47 seconds
Started Jul 29 07:43:33 PM PDT 24
Finished Jul 29 07:43:43 PM PDT 24
Peak memory 241832 kb
Host smart-6662a83e-de65-4c1c-9d92-803a903a9060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742857810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1742857810
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3717067824
Short name T138
Test name
Test status
Simulation time 96692503349 ps
CPU time 1813.95 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 08:11:06 PM PDT 24
Peak memory 469080 kb
Host smart-dfbde25e-f855-4a9d-93a8-fdf44f568bad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717067824 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.3717067824
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.680520598
Short name T84
Test name
Test status
Simulation time 125700902 ps
CPU time 3.61 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:33 PM PDT 24
Peak memory 242172 kb
Host smart-78c383c2-7e9d-4952-8540-e02995c622a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680520598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.680520598
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.2255385892
Short name T379
Test name
Test status
Simulation time 23589583122 ps
CPU time 153.67 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:43:01 PM PDT 24
Peak memory 252440 kb
Host smart-222915ce-a318-4ccc-96fc-ff06fc9cb30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255385892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
2255385892
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2453082790
Short name T1301
Test name
Test status
Simulation time 18968933744 ps
CPU time 38.3 seconds
Started Jul 29 05:50:27 PM PDT 24
Finished Jul 29 05:51:05 PM PDT 24
Peak memory 244732 kb
Host smart-ad1bcc04-bafc-473e-b686-34441003e5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453082790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2453082790
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3111524700
Short name T733
Test name
Test status
Simulation time 341984320 ps
CPU time 10.49 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:42:16 PM PDT 24
Peak memory 241912 kb
Host smart-61c9a3e2-352a-4758-9756-3894cda93682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111524700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3111524700
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2544613606
Short name T390
Test name
Test status
Simulation time 117455042656 ps
CPU time 2854.73 seconds
Started Jul 29 07:47:52 PM PDT 24
Finished Jul 29 08:35:27 PM PDT 24
Peak memory 462152 kb
Host smart-9543689d-cbeb-4bdc-b006-9404d558c8c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544613606 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2544613606
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.1239868882
Short name T74
Test name
Test status
Simulation time 606863656 ps
CPU time 18.18 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 242624 kb
Host smart-5fffc75c-8ce0-452b-9d9f-1066213c1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239868882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1239868882
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2931232699
Short name T348
Test name
Test status
Simulation time 418874267 ps
CPU time 7.08 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:28 PM PDT 24
Peak memory 241940 kb
Host smart-c5a114cb-78ca-482e-aee5-fde12fa05cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931232699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2931232699
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.538597299
Short name T244
Test name
Test status
Simulation time 1403946200 ps
CPU time 11.37 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:48 PM PDT 24
Peak memory 242424 kb
Host smart-c3aacf1f-9fb3-4c51-b173-34ad87a8ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538597299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.538597299
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.1141847458
Short name T217
Test name
Test status
Simulation time 1641597765 ps
CPU time 5.6 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 241992 kb
Host smart-0b169672-5270-4e8a-b5bd-146865abf18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141847458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1141847458
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.611809308
Short name T263
Test name
Test status
Simulation time 348437463 ps
CPU time 3.98 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 242216 kb
Host smart-ebee5918-feb5-49b5-a9b8-ab2ed4aee1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611809308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.611809308
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.881913437
Short name T477
Test name
Test status
Simulation time 184430766 ps
CPU time 4.14 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242348 kb
Host smart-37dfb271-d409-4937-9680-b9c072b70625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881913437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.881913437
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1719363253
Short name T107
Test name
Test status
Simulation time 2187961245 ps
CPU time 24.16 seconds
Started Jul 29 07:41:25 PM PDT 24
Finished Jul 29 07:41:49 PM PDT 24
Peak memory 242000 kb
Host smart-38f00817-534f-4a2c-930f-d539a0f3278d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719363253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1719363253
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.420939069
Short name T672
Test name
Test status
Simulation time 12240619315 ps
CPU time 217.86 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:45:10 PM PDT 24
Peak memory 257680 kb
Host smart-67108cbe-f2c0-4d59-b947-1ccfb630f36b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420939069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.
420939069
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2442729706
Short name T294
Test name
Test status
Simulation time 93055771 ps
CPU time 1.68 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:25 PM PDT 24
Peak memory 240928 kb
Host smart-da7bac6d-0049-4fc7-81aa-ef181462051e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442729706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2442729706
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1389099054
Short name T159
Test name
Test status
Simulation time 51324407 ps
CPU time 1.71 seconds
Started Jul 29 07:39:59 PM PDT 24
Finished Jul 29 07:40:01 PM PDT 24
Peak memory 240476 kb
Host smart-eb5d310b-face-4848-b355-ed33050eab27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1389099054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1389099054
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3297219414
Short name T108
Test name
Test status
Simulation time 1328610470 ps
CPU time 28.42 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:42:20 PM PDT 24
Peak memory 242356 kb
Host smart-9ed01f68-45a5-4dca-88aa-151e84de686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297219414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3297219414
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.3677143895
Short name T234
Test name
Test status
Simulation time 122832661608 ps
CPU time 616.2 seconds
Started Jul 29 07:40:53 PM PDT 24
Finished Jul 29 07:51:09 PM PDT 24
Peak memory 260196 kb
Host smart-69713e33-f5be-4e8d-88d0-636dcd08fd34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677143895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
3677143895
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.1692134595
Short name T81
Test name
Test status
Simulation time 1815811927 ps
CPU time 4.79 seconds
Started Jul 29 07:48:58 PM PDT 24
Finished Jul 29 07:49:03 PM PDT 24
Peak memory 241992 kb
Host smart-3c2ce5a1-d955-42dc-aab3-31bef248ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692134595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1692134595
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4136561395
Short name T268
Test name
Test status
Simulation time 720798270 ps
CPU time 10.4 seconds
Started Jul 29 05:49:53 PM PDT 24
Finished Jul 29 05:50:03 PM PDT 24
Peak memory 243584 kb
Host smart-c5fbb436-bbe2-4b39-97c2-ddaa48b36da9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136561395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.4136561395
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1791777533
Short name T270
Test name
Test status
Simulation time 1952054296 ps
CPU time 22.8 seconds
Started Jul 29 05:50:21 PM PDT 24
Finished Jul 29 05:50:44 PM PDT 24
Peak memory 244032 kb
Host smart-a11f9504-0317-4af7-8174-e1764437279e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791777533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.1791777533
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2102162076
Short name T271
Test name
Test status
Simulation time 5367734122 ps
CPU time 19.03 seconds
Started Jul 29 05:50:34 PM PDT 24
Finished Jul 29 05:50:53 PM PDT 24
Peak memory 244636 kb
Host smart-0365a43f-b044-455d-badf-b08d6cca019f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102162076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2102162076
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.3018602729
Short name T258
Test name
Test status
Simulation time 743139620 ps
CPU time 14.41 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:35 PM PDT 24
Peak memory 242360 kb
Host smart-7140f524-8b1c-4994-91c5-0ca414e401ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018602729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3018602729
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2363049934
Short name T257
Test name
Test status
Simulation time 583767483 ps
CPU time 5.27 seconds
Started Jul 29 07:47:23 PM PDT 24
Finished Jul 29 07:47:28 PM PDT 24
Peak memory 242168 kb
Host smart-90a4ab37-26ba-40f8-8465-f780a0057bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363049934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2363049934
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3875735352
Short name T76
Test name
Test status
Simulation time 240799864 ps
CPU time 3.84 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 242016 kb
Host smart-b3fe3ab6-7e89-49a1-9a30-3097e4022efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875735352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3875735352
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.3506788188
Short name T77
Test name
Test status
Simulation time 259745843 ps
CPU time 4.1 seconds
Started Jul 29 07:48:54 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 242156 kb
Host smart-e55db401-cfcf-405b-9283-5675f875174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506788188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3506788188
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1901243398
Short name T395
Test name
Test status
Simulation time 3225845258 ps
CPU time 9.96 seconds
Started Jul 29 07:43:31 PM PDT 24
Finished Jul 29 07:43:41 PM PDT 24
Peak memory 242148 kb
Host smart-b26bdda2-b288-4d1e-b8a7-4dc76ad3aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901243398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1901243398
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1969828643
Short name T75
Test name
Test status
Simulation time 414899132 ps
CPU time 4.01 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 242092 kb
Host smart-b094009e-44e3-46f7-91a3-194bebce9724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969828643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1969828643
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3635717184
Short name T307
Test name
Test status
Simulation time 331135974 ps
CPU time 5.69 seconds
Started Jul 29 05:49:48 PM PDT 24
Finished Jul 29 05:49:54 PM PDT 24
Peak memory 241296 kb
Host smart-2e38b577-4738-48c9-ac66-08ff16036590
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635717184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.3635717184
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1199426514
Short name T293
Test name
Test status
Simulation time 170027052 ps
CPU time 6.09 seconds
Started Jul 29 05:49:47 PM PDT 24
Finished Jul 29 05:49:54 PM PDT 24
Peak memory 230628 kb
Host smart-b3385c60-10c3-4fa7-80f9-6660d0f69e80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199426514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1199426514
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.420906173
Short name T1262
Test name
Test status
Simulation time 118627938 ps
CPU time 2.45 seconds
Started Jul 29 05:49:49 PM PDT 24
Finished Jul 29 05:49:51 PM PDT 24
Peak memory 238732 kb
Host smart-8ab6d3cf-bba9-42c4-a491-1ee70eca7a7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420906173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.420906173
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.990737472
Short name T1203
Test name
Test status
Simulation time 107696459 ps
CPU time 3.86 seconds
Started Jul 29 05:49:50 PM PDT 24
Finished Jul 29 05:49:54 PM PDT 24
Peak memory 247100 kb
Host smart-ca4c0a3f-addb-4b6b-a1d7-901e07536fa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990737472 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.990737472
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2586223660
Short name T302
Test name
Test status
Simulation time 46174885 ps
CPU time 1.66 seconds
Started Jul 29 05:49:48 PM PDT 24
Finished Jul 29 05:49:49 PM PDT 24
Peak memory 241048 kb
Host smart-6d36a4ce-c0f0-40d3-8bd2-85ed88b08a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586223660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2586223660
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3653507777
Short name T1265
Test name
Test status
Simulation time 47058980 ps
CPU time 1.46 seconds
Started Jul 29 05:49:48 PM PDT 24
Finished Jul 29 05:49:49 PM PDT 24
Peak memory 230596 kb
Host smart-0b9c28f5-df14-450e-8d90-10795a7978d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653507777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3653507777
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1677489588
Short name T1233
Test name
Test status
Simulation time 132282568 ps
CPU time 1.32 seconds
Started Jul 29 05:49:49 PM PDT 24
Finished Jul 29 05:49:50 PM PDT 24
Peak memory 229480 kb
Host smart-4f0f2fbf-5bac-498f-a459-9ddd2d564894
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677489588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1677489588
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1766714594
Short name T1250
Test name
Test status
Simulation time 39663307 ps
CPU time 1.4 seconds
Started Jul 29 05:49:49 PM PDT 24
Finished Jul 29 05:49:51 PM PDT 24
Peak memory 230484 kb
Host smart-cd4efdac-2d14-41e6-a312-40c45ef08ec0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766714594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.1766714594
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2602319092
Short name T1317
Test name
Test status
Simulation time 464722161 ps
CPU time 3.29 seconds
Started Jul 29 05:49:47 PM PDT 24
Finished Jul 29 05:49:51 PM PDT 24
Peak memory 238896 kb
Host smart-29382c61-186d-4a0a-9882-8f3ce39a5aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602319092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.2602319092
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.639513092
Short name T1308
Test name
Test status
Simulation time 164374654 ps
CPU time 5.82 seconds
Started Jul 29 05:49:47 PM PDT 24
Finished Jul 29 05:49:53 PM PDT 24
Peak memory 246340 kb
Host smart-83f5cf0f-13df-472b-8c87-0ec29b5ec973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639513092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.639513092
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2924781723
Short name T1314
Test name
Test status
Simulation time 778874842 ps
CPU time 10.81 seconds
Started Jul 29 05:49:47 PM PDT 24
Finished Jul 29 05:49:58 PM PDT 24
Peak memory 243624 kb
Host smart-81b9fe11-7cb5-4edf-8f62-9cd99f027db4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924781723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.2924781723
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.307136902
Short name T308
Test name
Test status
Simulation time 149488273 ps
CPU time 4.71 seconds
Started Jul 29 05:49:52 PM PDT 24
Finished Jul 29 05:49:57 PM PDT 24
Peak memory 238848 kb
Host smart-37cfdfbb-4309-4ffd-adfd-80d9be5b4cfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307136902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.307136902
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3184674512
Short name T306
Test name
Test status
Simulation time 623168750 ps
CPU time 5.81 seconds
Started Jul 29 05:49:54 PM PDT 24
Finished Jul 29 05:50:00 PM PDT 24
Peak memory 238820 kb
Host smart-084c6520-30dd-473a-a9ba-b5153adc2732
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184674512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.3184674512
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1337162010
Short name T1200
Test name
Test status
Simulation time 252684603 ps
CPU time 1.9 seconds
Started Jul 29 05:49:52 PM PDT 24
Finished Jul 29 05:49:54 PM PDT 24
Peak memory 238832 kb
Host smart-ae240397-d943-4843-9a8d-0f02ced1f5d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337162010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1337162010
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3191479469
Short name T1307
Test name
Test status
Simulation time 164220590 ps
CPU time 2.26 seconds
Started Jul 29 05:49:54 PM PDT 24
Finished Jul 29 05:49:57 PM PDT 24
Peak memory 245732 kb
Host smart-b3ad0750-577c-47b5-8b46-45b275244b8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191479469 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3191479469
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3767297720
Short name T286
Test name
Test status
Simulation time 44484508 ps
CPU time 1.73 seconds
Started Jul 29 05:49:52 PM PDT 24
Finished Jul 29 05:49:54 PM PDT 24
Peak memory 241064 kb
Host smart-eb240698-7c83-4372-9353-75474b523ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767297720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3767297720
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3393062117
Short name T1219
Test name
Test status
Simulation time 516135067 ps
CPU time 1.65 seconds
Started Jul 29 05:49:53 PM PDT 24
Finished Jul 29 05:49:55 PM PDT 24
Peak memory 230196 kb
Host smart-0349a4c4-69c6-4946-ab52-4248082255bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393062117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3393062117
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2450373778
Short name T1321
Test name
Test status
Simulation time 139352788 ps
CPU time 1.36 seconds
Started Jul 29 05:49:51 PM PDT 24
Finished Jul 29 05:49:53 PM PDT 24
Peak memory 230456 kb
Host smart-04be7fcc-02d1-4b4d-a0d9-7bbff76b1a22
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450373778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2450373778
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3537571454
Short name T1202
Test name
Test status
Simulation time 525846156 ps
CPU time 1.85 seconds
Started Jul 29 05:49:54 PM PDT 24
Finished Jul 29 05:49:56 PM PDT 24
Peak memory 230036 kb
Host smart-36477b6c-1e91-4e6e-a389-03324c065205
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537571454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.3537571454
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1876688032
Short name T1292
Test name
Test status
Simulation time 128089754 ps
CPU time 2.37 seconds
Started Jul 29 05:49:53 PM PDT 24
Finished Jul 29 05:49:56 PM PDT 24
Peak memory 238844 kb
Host smart-0629ed6b-0d42-4538-98a2-d159b0f8fe01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876688032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.1876688032
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1730410429
Short name T1234
Test name
Test status
Simulation time 756791912 ps
CPU time 3.87 seconds
Started Jul 29 05:49:54 PM PDT 24
Finished Jul 29 05:49:58 PM PDT 24
Peak memory 245984 kb
Host smart-146725b1-c944-4ab9-8225-0d9ab4673274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730410429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1730410429
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.176384101
Short name T1315
Test name
Test status
Simulation time 71925598 ps
CPU time 2.31 seconds
Started Jul 29 05:50:18 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 247040 kb
Host smart-881abb03-3ee6-433c-a2c5-cee24d0580d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176384101 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.176384101
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3199431791
Short name T290
Test name
Test status
Simulation time 159231776 ps
CPU time 1.72 seconds
Started Jul 29 05:50:19 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 238824 kb
Host smart-00c7dc5e-f398-4047-90d4-4b1b1e10509d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199431791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3199431791
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1369199684
Short name T1240
Test name
Test status
Simulation time 111659829 ps
CPU time 1.52 seconds
Started Jul 29 05:50:19 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 229912 kb
Host smart-ac877445-7334-4d32-bd7b-9f7a001d7e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369199684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1369199684
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2739408376
Short name T298
Test name
Test status
Simulation time 94685351 ps
CPU time 1.88 seconds
Started Jul 29 05:50:19 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 238856 kb
Host smart-553e1c41-0711-442d-a9a6-1df7775c8647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739408376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2739408376
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4012111383
Short name T1232
Test name
Test status
Simulation time 425043141 ps
CPU time 4.12 seconds
Started Jul 29 05:50:17 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 245908 kb
Host smart-e632afe2-8101-43de-b328-3ad743eee2da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012111383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.4012111383
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1156191363
Short name T1241
Test name
Test status
Simulation time 650515027 ps
CPU time 8.93 seconds
Started Jul 29 05:50:16 PM PDT 24
Finished Jul 29 05:50:25 PM PDT 24
Peak memory 243592 kb
Host smart-424a12d7-46e2-4b38-808b-c80701af5c69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156191363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.1156191363
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1423566726
Short name T1239
Test name
Test status
Simulation time 209519772 ps
CPU time 3.02 seconds
Started Jul 29 05:50:21 PM PDT 24
Finished Jul 29 05:50:24 PM PDT 24
Peak memory 247028 kb
Host smart-c2122eb8-c65d-4fab-8ae1-28125eeb4f31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423566726 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1423566726
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.837595183
Short name T1199
Test name
Test status
Simulation time 50352858 ps
CPU time 1.61 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:25 PM PDT 24
Peak memory 240928 kb
Host smart-51c5450c-9f2f-4db1-a82a-d0111a434e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837595183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.837595183
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2409294721
Short name T1251
Test name
Test status
Simulation time 549534815 ps
CPU time 1.73 seconds
Started Jul 29 05:50:19 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 229908 kb
Host smart-e048d72c-9153-4672-9271-3cfb63a7aeb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409294721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2409294721
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3050296122
Short name T272
Test name
Test status
Simulation time 950504515 ps
CPU time 2.89 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:26 PM PDT 24
Peak memory 238824 kb
Host smart-91777fb0-c303-4a24-ac31-3f88d0f57af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050296122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3050296122
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1701559694
Short name T1242
Test name
Test status
Simulation time 283193277 ps
CPU time 5.5 seconds
Started Jul 29 05:50:16 PM PDT 24
Finished Jul 29 05:50:22 PM PDT 24
Peak memory 245888 kb
Host smart-3005afb6-e9d0-4fed-863c-b1cfc012375f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701559694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1701559694
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1760942989
Short name T267
Test name
Test status
Simulation time 20066720971 ps
CPU time 29.28 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:44 PM PDT 24
Peak memory 244524 kb
Host smart-7dee630b-10d1-49c1-a7d5-8f32b8948d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760942989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.1760942989
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.297878067
Short name T1227
Test name
Test status
Simulation time 219545991 ps
CPU time 2.85 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:26 PM PDT 24
Peak memory 247100 kb
Host smart-893e279b-14ee-4341-b1bd-ac502d08c3eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297878067 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.297878067
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1049154787
Short name T1258
Test name
Test status
Simulation time 141846820 ps
CPU time 1.59 seconds
Started Jul 29 05:50:21 PM PDT 24
Finished Jul 29 05:50:23 PM PDT 24
Peak memory 238852 kb
Host smart-7a57c256-7d7f-4fac-8a89-13c3f6ce0c5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049154787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1049154787
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2616146796
Short name T1276
Test name
Test status
Simulation time 91750577 ps
CPU time 1.45 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:25 PM PDT 24
Peak memory 230628 kb
Host smart-13e9d8fb-5e5b-4fba-9ee7-43e6560d8bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616146796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2616146796
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3684774982
Short name T304
Test name
Test status
Simulation time 943406023 ps
CPU time 2.66 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:29 PM PDT 24
Peak memory 238884 kb
Host smart-e0584072-c277-468f-9067-64967ce76676
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684774982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3684774982
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2985976501
Short name T1280
Test name
Test status
Simulation time 150963848 ps
CPU time 4.85 seconds
Started Jul 29 05:50:22 PM PDT 24
Finished Jul 29 05:50:27 PM PDT 24
Peak memory 245792 kb
Host smart-ddb83ad4-08d6-45cb-b899-51a6daca7a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985976501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2985976501
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3025643572
Short name T1291
Test name
Test status
Simulation time 269856179 ps
CPU time 2.36 seconds
Started Jul 29 05:50:22 PM PDT 24
Finished Jul 29 05:50:24 PM PDT 24
Peak memory 244976 kb
Host smart-d43d58c7-c92c-4b8c-9c62-664e6bb5bccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025643572 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3025643572
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.493129063
Short name T1274
Test name
Test status
Simulation time 51952563 ps
CPU time 1.73 seconds
Started Jul 29 05:50:22 PM PDT 24
Finished Jul 29 05:50:24 PM PDT 24
Peak memory 241284 kb
Host smart-f4c9b206-cabd-4bc9-844b-c24eedbf13ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493129063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.493129063
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3677279566
Short name T1223
Test name
Test status
Simulation time 74114545 ps
CPU time 1.47 seconds
Started Jul 29 05:50:22 PM PDT 24
Finished Jul 29 05:50:24 PM PDT 24
Peak memory 229888 kb
Host smart-b7b5651f-7f04-483c-ac23-acca8162afe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677279566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3677279566
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2130202195
Short name T1268
Test name
Test status
Simulation time 175485322 ps
CPU time 2.16 seconds
Started Jul 29 05:50:23 PM PDT 24
Finished Jul 29 05:50:25 PM PDT 24
Peak memory 239052 kb
Host smart-9c91df60-67bd-4f83-afe2-d8ff998a8faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130202195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.2130202195
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.688396704
Short name T1309
Test name
Test status
Simulation time 280106087 ps
CPU time 5.83 seconds
Started Jul 29 05:50:27 PM PDT 24
Finished Jul 29 05:50:33 PM PDT 24
Peak memory 245892 kb
Host smart-f9e46c57-1b9d-4cad-960c-715a9c1964fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688396704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.688396704
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3787378010
Short name T1214
Test name
Test status
Simulation time 1762313542 ps
CPU time 3.63 seconds
Started Jul 29 05:50:28 PM PDT 24
Finished Jul 29 05:50:32 PM PDT 24
Peak memory 247128 kb
Host smart-af4d345f-8595-46a8-b69a-c3fc38e70513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787378010 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.3787378010
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3024331450
Short name T1254
Test name
Test status
Simulation time 92138813 ps
CPU time 1.41 seconds
Started Jul 29 05:50:24 PM PDT 24
Finished Jul 29 05:50:26 PM PDT 24
Peak memory 229776 kb
Host smart-e7f94d63-853d-481e-a887-61bf486c4089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024331450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3024331450
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.921647009
Short name T1278
Test name
Test status
Simulation time 685874946 ps
CPU time 1.86 seconds
Started Jul 29 05:50:25 PM PDT 24
Finished Jul 29 05:50:27 PM PDT 24
Peak memory 238788 kb
Host smart-44bf6f16-a40a-4aef-a839-b1c4b0d1af22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921647009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c
trl_same_csr_outstanding.921647009
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.914691141
Short name T1304
Test name
Test status
Simulation time 1624129451 ps
CPU time 3.76 seconds
Started Jul 29 05:50:22 PM PDT 24
Finished Jul 29 05:50:26 PM PDT 24
Peak memory 245704 kb
Host smart-b262582f-9033-4c92-baa1-020a04febe22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914691141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.914691141
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1304599917
Short name T1247
Test name
Test status
Simulation time 252300317 ps
CPU time 2.84 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:29 PM PDT 24
Peak memory 246968 kb
Host smart-bab73fe8-9122-499b-b57c-ea513c37c9e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304599917 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1304599917
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3925437667
Short name T1270
Test name
Test status
Simulation time 140064944 ps
CPU time 1.62 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:28 PM PDT 24
Peak memory 240612 kb
Host smart-d09acccb-de22-4d5f-8800-532a4bbd2faf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925437667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3925437667
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1014955656
Short name T1281
Test name
Test status
Simulation time 44419235 ps
CPU time 1.49 seconds
Started Jul 29 05:50:27 PM PDT 24
Finished Jul 29 05:50:29 PM PDT 24
Peak memory 229896 kb
Host smart-c1b35b2f-15d7-427d-a91b-4f83475fdf3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014955656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1014955656
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2226700055
Short name T1282
Test name
Test status
Simulation time 74139736 ps
CPU time 2.27 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:28 PM PDT 24
Peak memory 238816 kb
Host smart-5d32c4df-a6fe-469f-96dc-9e67dbaff204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226700055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2226700055
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1107158893
Short name T1324
Test name
Test status
Simulation time 1502487595 ps
CPU time 5.4 seconds
Started Jul 29 05:50:27 PM PDT 24
Finished Jul 29 05:50:32 PM PDT 24
Peak memory 246116 kb
Host smart-16fb7fcf-14a4-4fe6-b0cb-7292b32bd53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107158893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1107158893
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2758166776
Short name T347
Test name
Test status
Simulation time 2591930206 ps
CPU time 23.92 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:50 PM PDT 24
Peak memory 238936 kb
Host smart-8f660a46-663a-4fd2-a2be-54c6f84982f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758166776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2758166776
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2562450985
Short name T1273
Test name
Test status
Simulation time 74557499 ps
CPU time 1.99 seconds
Started Jul 29 05:50:27 PM PDT 24
Finished Jul 29 05:50:29 PM PDT 24
Peak memory 244044 kb
Host smart-92fbabcd-c094-49d2-9dcf-aec8a809b607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562450985 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2562450985
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1630955231
Short name T1322
Test name
Test status
Simulation time 143992130 ps
CPU time 1.52 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:28 PM PDT 24
Peak memory 241116 kb
Host smart-1a280f36-5891-4d03-aa09-e3d2cd1d3397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630955231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1630955231
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3324436906
Short name T1209
Test name
Test status
Simulation time 609940172 ps
CPU time 1.77 seconds
Started Jul 29 05:50:26 PM PDT 24
Finished Jul 29 05:50:28 PM PDT 24
Peak memory 230592 kb
Host smart-149a82ea-18b9-48fb-966a-1236a457cf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324436906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3324436906
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.957446843
Short name T1300
Test name
Test status
Simulation time 170839210 ps
CPU time 1.96 seconds
Started Jul 29 05:50:25 PM PDT 24
Finished Jul 29 05:50:27 PM PDT 24
Peak memory 241976 kb
Host smart-84f245c3-1c30-4559-b322-f32329ee64eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957446843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.957446843
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3686692601
Short name T1198
Test name
Test status
Simulation time 113662971 ps
CPU time 3.89 seconds
Started Jul 29 05:50:25 PM PDT 24
Finished Jul 29 05:50:29 PM PDT 24
Peak memory 245884 kb
Host smart-81813eb4-b0dc-44fc-b1be-02e49d0b8a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686692601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3686692601
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1140807523
Short name T343
Test name
Test status
Simulation time 1264926204 ps
CPU time 18.86 seconds
Started Jul 29 05:50:27 PM PDT 24
Finished Jul 29 05:50:46 PM PDT 24
Peak memory 243688 kb
Host smart-799037fe-10db-447b-b223-82a8c38c513b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140807523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.1140807523
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2003288711
Short name T1252
Test name
Test status
Simulation time 126381910 ps
CPU time 2.04 seconds
Started Jul 29 05:50:33 PM PDT 24
Finished Jul 29 05:50:35 PM PDT 24
Peak memory 244956 kb
Host smart-8b82b934-6539-4df6-a181-080dcf5e51f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003288711 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.2003288711
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3400289590
Short name T297
Test name
Test status
Simulation time 680972985 ps
CPU time 2.14 seconds
Started Jul 29 05:50:33 PM PDT 24
Finished Jul 29 05:50:36 PM PDT 24
Peak memory 240628 kb
Host smart-6b37567e-71e6-4fd0-8bd3-3ca9ee41899e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400289590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3400289590
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.283343380
Short name T1236
Test name
Test status
Simulation time 146936633 ps
CPU time 1.45 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:43 PM PDT 24
Peak memory 230488 kb
Host smart-38a9850a-23de-4ad5-b675-5114e2272a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283343380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.283343380
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2675661204
Short name T299
Test name
Test status
Simulation time 1449701310 ps
CPU time 2.92 seconds
Started Jul 29 05:50:32 PM PDT 24
Finished Jul 29 05:50:35 PM PDT 24
Peak memory 238876 kb
Host smart-d87cbe65-e5d1-4655-ad28-57993cf7193a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675661204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.2675661204
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2178902832
Short name T1215
Test name
Test status
Simulation time 1856308709 ps
CPU time 4.85 seconds
Started Jul 29 05:50:28 PM PDT 24
Finished Jul 29 05:50:33 PM PDT 24
Peak memory 246104 kb
Host smart-9741f33f-b9c9-4721-abca-02a2f8438bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178902832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.2178902832
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.738908698
Short name T341
Test name
Test status
Simulation time 3284884357 ps
CPU time 14.02 seconds
Started Jul 29 05:50:31 PM PDT 24
Finished Jul 29 05:50:45 PM PDT 24
Peak memory 244268 kb
Host smart-c530cda2-c01c-442e-b766-5e5fa82ed331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738908698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in
tg_err.738908698
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1910662457
Short name T1275
Test name
Test status
Simulation time 395961539 ps
CPU time 2.69 seconds
Started Jul 29 05:50:32 PM PDT 24
Finished Jul 29 05:50:35 PM PDT 24
Peak memory 238916 kb
Host smart-2d5db072-92e3-4238-b99b-f1293ee54f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910662457 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1910662457
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1442915997
Short name T1207
Test name
Test status
Simulation time 152948691 ps
CPU time 1.82 seconds
Started Jul 29 05:50:33 PM PDT 24
Finished Jul 29 05:50:35 PM PDT 24
Peak memory 240712 kb
Host smart-57a8160b-1794-4a51-8e4f-4904228af383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442915997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1442915997
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1912200681
Short name T1306
Test name
Test status
Simulation time 140513334 ps
CPU time 1.46 seconds
Started Jul 29 05:50:32 PM PDT 24
Finished Jul 29 05:50:34 PM PDT 24
Peak memory 230604 kb
Host smart-13b9e839-5398-4386-b9a3-9b496a139f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912200681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1912200681
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1034187080
Short name T1312
Test name
Test status
Simulation time 125023440 ps
CPU time 3.17 seconds
Started Jul 29 05:50:33 PM PDT 24
Finished Jul 29 05:50:37 PM PDT 24
Peak memory 238920 kb
Host smart-411ac263-5b85-4cf5-94b8-7ed9ae077d7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034187080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1034187080
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2243870860
Short name T1195
Test name
Test status
Simulation time 240309755 ps
CPU time 3.83 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:45 PM PDT 24
Peak memory 245468 kb
Host smart-06253d5f-1bb8-4ee1-8122-9caa17188105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243870860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2243870860
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2826543131
Short name T338
Test name
Test status
Simulation time 896972558 ps
CPU time 10.85 seconds
Started Jul 29 05:50:33 PM PDT 24
Finished Jul 29 05:50:44 PM PDT 24
Peak memory 243568 kb
Host smart-0ed70d81-7739-42bb-b942-adb2f791bd6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826543131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.2826543131
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2840907488
Short name T1313
Test name
Test status
Simulation time 1501504752 ps
CPU time 3.64 seconds
Started Jul 29 05:50:36 PM PDT 24
Finished Jul 29 05:50:40 PM PDT 24
Peak memory 247080 kb
Host smart-52a0cf98-3d9b-4769-a817-19d98248514a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840907488 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2840907488
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2380236562
Short name T1286
Test name
Test status
Simulation time 104487871 ps
CPU time 1.54 seconds
Started Jul 29 05:50:38 PM PDT 24
Finished Jul 29 05:50:40 PM PDT 24
Peak memory 238828 kb
Host smart-481b661e-2c0b-4b78-b00a-e64eeaf58831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380236562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2380236562
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1706478241
Short name T1235
Test name
Test status
Simulation time 39028056 ps
CPU time 1.4 seconds
Started Jul 29 05:50:31 PM PDT 24
Finished Jul 29 05:50:33 PM PDT 24
Peak memory 230652 kb
Host smart-81316b99-c70d-4252-8a9b-396086b90da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706478241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1706478241
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1542031515
Short name T1253
Test name
Test status
Simulation time 51248983 ps
CPU time 2.06 seconds
Started Jul 29 05:50:37 PM PDT 24
Finished Jul 29 05:50:39 PM PDT 24
Peak memory 238736 kb
Host smart-89131a48-95d3-408a-b5e4-a8c2ca741ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542031515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1542031515
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1829888595
Short name T1293
Test name
Test status
Simulation time 3064358492 ps
CPU time 10.15 seconds
Started Jul 29 05:50:31 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 246504 kb
Host smart-1b49cb49-fc7b-4485-9f5e-2bc9b04a8a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829888595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1829888595
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.494459979
Short name T1229
Test name
Test status
Simulation time 309149689 ps
CPU time 6.06 seconds
Started Jul 29 05:50:04 PM PDT 24
Finished Jul 29 05:50:10 PM PDT 24
Peak memory 238712 kb
Host smart-4c9af37a-390c-4b30-a325-37d312d9af31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494459979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.494459979
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1867622250
Short name T1294
Test name
Test status
Simulation time 359849068 ps
CPU time 8.38 seconds
Started Jul 29 05:50:07 PM PDT 24
Finished Jul 29 05:50:15 PM PDT 24
Peak memory 230616 kb
Host smart-32d74d13-3941-47b4-8485-a62aa3ae2348
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867622250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.1867622250
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.715710433
Short name T1267
Test name
Test status
Simulation time 385116074 ps
CPU time 2.2 seconds
Started Jul 29 05:50:03 PM PDT 24
Finished Jul 29 05:50:05 PM PDT 24
Peak memory 240976 kb
Host smart-78ae5fb5-1a1d-4b75-a86f-f0a487e27f59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715710433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.715710433
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3418484902
Short name T289
Test name
Test status
Simulation time 43771949 ps
CPU time 1.58 seconds
Started Jul 29 05:50:02 PM PDT 24
Finished Jul 29 05:50:03 PM PDT 24
Peak memory 240812 kb
Host smart-d6d12b62-bee2-4611-83c7-1824ccfe7dc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418484902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3418484902
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2323081821
Short name T1230
Test name
Test status
Simulation time 137000677 ps
CPU time 1.37 seconds
Started Jul 29 05:49:56 PM PDT 24
Finished Jul 29 05:49:58 PM PDT 24
Peak memory 230628 kb
Host smart-666b1f32-5d4b-465f-9946-427b9ac52ea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323081821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2323081821
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3278757031
Short name T1216
Test name
Test status
Simulation time 528156277 ps
CPU time 1.4 seconds
Started Jul 29 05:49:56 PM PDT 24
Finished Jul 29 05:49:58 PM PDT 24
Peak memory 230436 kb
Host smart-7fbfe5cb-fe84-4ca0-adcb-e2315e2666d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278757031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3278757031
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3978149806
Short name T1297
Test name
Test status
Simulation time 40578749 ps
CPU time 1.35 seconds
Started Jul 29 05:49:58 PM PDT 24
Finished Jul 29 05:49:59 PM PDT 24
Peak memory 229644 kb
Host smart-f5707cde-0d5b-4b1e-8969-af53a1b8285d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978149806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3978149806
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1239812326
Short name T300
Test name
Test status
Simulation time 141385239 ps
CPU time 2.39 seconds
Started Jul 29 05:50:03 PM PDT 24
Finished Jul 29 05:50:05 PM PDT 24
Peak memory 238872 kb
Host smart-f6954537-f36f-483a-b677-4d5986755641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239812326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1239812326
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.4108231346
Short name T1302
Test name
Test status
Simulation time 341681770 ps
CPU time 6.78 seconds
Started Jul 29 05:49:59 PM PDT 24
Finished Jul 29 05:50:06 PM PDT 24
Peak memory 246120 kb
Host smart-ddcdb2ba-6a19-4cd3-9787-c4a0108d3493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108231346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.4108231346
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.641426173
Short name T337
Test name
Test status
Simulation time 4030012105 ps
CPU time 19.81 seconds
Started Jul 29 05:49:58 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 244692 kb
Host smart-0fc12df7-4449-4e69-a3a7-6c4ad20ca110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641426173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int
g_err.641426173
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3623774985
Short name T1310
Test name
Test status
Simulation time 42689103 ps
CPU time 1.43 seconds
Started Jul 29 05:50:36 PM PDT 24
Finished Jul 29 05:50:38 PM PDT 24
Peak memory 229820 kb
Host smart-c10f535f-8787-416f-9d2c-9a8e8331eb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623774985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3623774985
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1176240134
Short name T1201
Test name
Test status
Simulation time 82216461 ps
CPU time 1.51 seconds
Started Jul 29 05:50:42 PM PDT 24
Finished Jul 29 05:50:43 PM PDT 24
Peak memory 230140 kb
Host smart-cb225105-973c-4597-ad29-2328848dc8f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176240134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1176240134
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1730297955
Short name T1224
Test name
Test status
Simulation time 151500785 ps
CPU time 1.54 seconds
Started Jul 29 05:50:40 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 230492 kb
Host smart-832ae0e8-1a8b-4928-a061-a204323b299c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730297955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1730297955
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.519127205
Short name T1196
Test name
Test status
Simulation time 78549996 ps
CPU time 1.5 seconds
Started Jul 29 05:50:37 PM PDT 24
Finished Jul 29 05:50:38 PM PDT 24
Peak memory 229900 kb
Host smart-d752c9a3-1a8b-45f0-8145-d55a5baa7630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519127205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.519127205
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3269753558
Short name T1205
Test name
Test status
Simulation time 75732356 ps
CPU time 1.43 seconds
Started Jul 29 05:50:42 PM PDT 24
Finished Jul 29 05:50:43 PM PDT 24
Peak memory 230496 kb
Host smart-9e01e424-43e6-4489-b503-c8b6fff2e082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269753558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3269753558
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.56561825
Short name T1210
Test name
Test status
Simulation time 43273492 ps
CPU time 1.51 seconds
Started Jul 29 05:50:37 PM PDT 24
Finished Jul 29 05:50:39 PM PDT 24
Peak memory 229912 kb
Host smart-e017a7c2-3034-4192-827c-b1cb296169e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56561825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.56561825
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.4039065360
Short name T1284
Test name
Test status
Simulation time 75406460 ps
CPU time 1.47 seconds
Started Jul 29 05:50:36 PM PDT 24
Finished Jul 29 05:50:37 PM PDT 24
Peak memory 229932 kb
Host smart-15b21f49-c62c-47c2-b771-9c1d48fd102c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039065360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.4039065360
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.3172951322
Short name T1212
Test name
Test status
Simulation time 140580139 ps
CPU time 1.41 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 229980 kb
Host smart-0cdd499d-2ba9-420d-8146-a3e852249d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172951322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3172951322
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2906334680
Short name T1326
Test name
Test status
Simulation time 71021832 ps
CPU time 1.49 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:43 PM PDT 24
Peak memory 230248 kb
Host smart-a019c31e-cb0b-4154-aa8c-ad9e3aa37005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906334680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2906334680
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1415814348
Short name T1208
Test name
Test status
Simulation time 88796134 ps
CPU time 1.44 seconds
Started Jul 29 05:50:43 PM PDT 24
Finished Jul 29 05:50:44 PM PDT 24
Peak memory 229856 kb
Host smart-937cdb03-b647-4ae6-844c-40446e6d3ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415814348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1415814348
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3928461853
Short name T291
Test name
Test status
Simulation time 116215611 ps
CPU time 2.93 seconds
Started Jul 29 05:50:13 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 238828 kb
Host smart-9f50b1a6-260c-4513-8cd6-c8d99c10f939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928461853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.3928461853
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4055233573
Short name T1246
Test name
Test status
Simulation time 227362367 ps
CPU time 5.28 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 238764 kb
Host smart-98074aaa-3f4c-4977-9724-3ce9da6d2616
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055233573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.4055233573
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.609641997
Short name T1283
Test name
Test status
Simulation time 1016649149 ps
CPU time 2.07 seconds
Started Jul 29 05:50:04 PM PDT 24
Finished Jul 29 05:50:06 PM PDT 24
Peak memory 240444 kb
Host smart-49ffe080-fa3f-4fdd-bfd6-043ccfde92af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609641997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.609641997
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.4273057102
Short name T1213
Test name
Test status
Simulation time 105422291 ps
CPU time 2.67 seconds
Started Jul 29 05:50:09 PM PDT 24
Finished Jul 29 05:50:12 PM PDT 24
Peak memory 238780 kb
Host smart-9fa91f2c-e87b-4511-812d-927163257fca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273057102 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.4273057102
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2603447930
Short name T295
Test name
Test status
Simulation time 89637206 ps
CPU time 1.75 seconds
Started Jul 29 05:50:07 PM PDT 24
Finished Jul 29 05:50:09 PM PDT 24
Peak memory 241096 kb
Host smart-78fb4278-e983-496b-b664-0f02c5f28bae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603447930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2603447930
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.4196536201
Short name T1220
Test name
Test status
Simulation time 41957507 ps
CPU time 1.47 seconds
Started Jul 29 05:50:05 PM PDT 24
Finished Jul 29 05:50:07 PM PDT 24
Peak memory 229928 kb
Host smart-71ce3b96-c773-4595-8024-c2ad8edf778a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196536201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.4196536201
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3209856059
Short name T1257
Test name
Test status
Simulation time 93181666 ps
CPU time 1.36 seconds
Started Jul 29 05:50:03 PM PDT 24
Finished Jul 29 05:50:04 PM PDT 24
Peak memory 230400 kb
Host smart-b82c55c2-e2f5-4f41-9b9f-96132161f0f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209856059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.3209856059
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1122320646
Short name T1206
Test name
Test status
Simulation time 39179752 ps
CPU time 1.34 seconds
Started Jul 29 05:50:05 PM PDT 24
Finished Jul 29 05:50:06 PM PDT 24
Peak memory 229772 kb
Host smart-6d411013-0d81-4c50-a3d0-64f61df1380f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122320646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.1122320646
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1530597851
Short name T1266
Test name
Test status
Simulation time 715615650 ps
CPU time 2.73 seconds
Started Jul 29 05:50:08 PM PDT 24
Finished Jul 29 05:50:11 PM PDT 24
Peak memory 238824 kb
Host smart-62d24342-872a-42c7-a3bc-62fa20a8cdcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530597851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1530597851
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3404715968
Short name T1260
Test name
Test status
Simulation time 252233528 ps
CPU time 5.42 seconds
Started Jul 29 05:50:02 PM PDT 24
Finished Jul 29 05:50:08 PM PDT 24
Peak memory 246000 kb
Host smart-1b8f17f9-2b32-44e1-83cd-7837c4e220b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404715968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3404715968
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3048132037
Short name T344
Test name
Test status
Simulation time 1262435240 ps
CPU time 9.18 seconds
Started Jul 29 05:50:04 PM PDT 24
Finished Jul 29 05:50:13 PM PDT 24
Peak memory 243356 kb
Host smart-a01ffbd0-2700-4686-aed8-48d953ea6fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048132037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3048132037
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1251500186
Short name T1305
Test name
Test status
Simulation time 46193443 ps
CPU time 1.44 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 230184 kb
Host smart-a23bb48b-f2b4-45bd-994b-3c474bbf9b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251500186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1251500186
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2155903507
Short name T1296
Test name
Test status
Simulation time 44869277 ps
CPU time 1.44 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 229940 kb
Host smart-f2b2a692-4887-4bd1-9b26-f92efb4e71b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155903507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2155903507
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2961576886
Short name T1287
Test name
Test status
Simulation time 154893201 ps
CPU time 1.54 seconds
Started Jul 29 05:50:40 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 229904 kb
Host smart-d3bc5e56-dbac-49d3-ae04-cd73afce38c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961576886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2961576886
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1120633660
Short name T1290
Test name
Test status
Simulation time 63742543 ps
CPU time 1.47 seconds
Started Jul 29 05:50:43 PM PDT 24
Finished Jul 29 05:50:44 PM PDT 24
Peak memory 229940 kb
Host smart-cb8a71cf-440f-46ce-a31e-d2bd81574ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120633660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1120633660
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2210127794
Short name T1303
Test name
Test status
Simulation time 71014445 ps
CPU time 1.42 seconds
Started Jul 29 05:50:42 PM PDT 24
Finished Jul 29 05:50:43 PM PDT 24
Peak memory 230056 kb
Host smart-dd107971-bc48-4530-aaa6-9172126fbefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210127794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2210127794
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3319716539
Short name T1269
Test name
Test status
Simulation time 41872585 ps
CPU time 1.37 seconds
Started Jul 29 05:50:44 PM PDT 24
Finished Jul 29 05:50:45 PM PDT 24
Peak memory 230164 kb
Host smart-0e427655-3f8c-4ab8-a24a-a57742ac5b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319716539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3319716539
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.171467219
Short name T1271
Test name
Test status
Simulation time 628031114 ps
CPU time 1.93 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:43 PM PDT 24
Peak memory 230360 kb
Host smart-50e5d4ad-d58a-4e01-8161-fc1f0c8b8f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171467219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.171467219
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.695896315
Short name T1277
Test name
Test status
Simulation time 130790432 ps
CPU time 1.46 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 230200 kb
Host smart-7e0b7e0c-f66f-4a2c-be8b-f0e1b1169e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695896315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.695896315
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2034848453
Short name T1319
Test name
Test status
Simulation time 90288921 ps
CPU time 1.45 seconds
Started Jul 29 05:50:41 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 229856 kb
Host smart-287662f4-855f-4e07-9af7-149151bc6c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034848453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2034848453
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.749165413
Short name T1243
Test name
Test status
Simulation time 73246058 ps
CPU time 1.43 seconds
Started Jul 29 05:50:45 PM PDT 24
Finished Jul 29 05:50:47 PM PDT 24
Peak memory 230592 kb
Host smart-81f0ad8d-e626-4f84-9cab-b4fdfe1bacb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749165413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.749165413
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4270456369
Short name T292
Test name
Test status
Simulation time 238884845 ps
CPU time 6.56 seconds
Started Jul 29 05:50:17 PM PDT 24
Finished Jul 29 05:50:24 PM PDT 24
Peak memory 238860 kb
Host smart-5ef36f4b-b52e-4fbe-b496-c1d068786983
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270456369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.4270456369
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2724536982
Short name T1259
Test name
Test status
Simulation time 315137023 ps
CPU time 3.59 seconds
Started Jul 29 05:50:09 PM PDT 24
Finished Jul 29 05:50:12 PM PDT 24
Peak memory 239012 kb
Host smart-5aa918df-07ed-4e28-b374-13593bef8b58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724536982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2724536982
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3765557761
Short name T296
Test name
Test status
Simulation time 266973310 ps
CPU time 2.4 seconds
Started Jul 29 05:50:11 PM PDT 24
Finished Jul 29 05:50:13 PM PDT 24
Peak memory 241240 kb
Host smart-236222d1-a22c-42aa-ac6e-3bad52003419
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765557761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3765557761
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1125429789
Short name T1221
Test name
Test status
Simulation time 1719180076 ps
CPU time 4.89 seconds
Started Jul 29 05:50:13 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 247096 kb
Host smart-88bfd003-5eed-4a36-8f74-730c74c6ab2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125429789 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1125429789
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3794163296
Short name T1311
Test name
Test status
Simulation time 157126512 ps
CPU time 1.6 seconds
Started Jul 29 05:50:10 PM PDT 24
Finished Jul 29 05:50:12 PM PDT 24
Peak memory 238832 kb
Host smart-65746511-bca0-4ef8-9758-7b9f784ca77a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794163296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3794163296
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.4255857234
Short name T1263
Test name
Test status
Simulation time 44138364 ps
CPU time 1.36 seconds
Started Jul 29 05:50:08 PM PDT 24
Finished Jul 29 05:50:09 PM PDT 24
Peak memory 230096 kb
Host smart-1edd7173-673c-4ae8-a5e0-12b248f9b386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255857234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.4255857234
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2007336068
Short name T1225
Test name
Test status
Simulation time 538692994 ps
CPU time 1.48 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 229676 kb
Host smart-08631f44-f7f9-41e7-8b4e-029c3dfc3333
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007336068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.2007336068
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.4202163
Short name T1204
Test name
Test status
Simulation time 501807425 ps
CPU time 1.69 seconds
Started Jul 29 05:50:08 PM PDT 24
Finished Jul 29 05:50:10 PM PDT 24
Peak memory 229724 kb
Host smart-a5819396-2ec7-4549-92a9-4dabf509c77c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.4202163
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.522961893
Short name T1256
Test name
Test status
Simulation time 56274644 ps
CPU time 2.38 seconds
Started Jul 29 05:50:19 PM PDT 24
Finished Jul 29 05:50:22 PM PDT 24
Peak memory 238780 kb
Host smart-c77e9866-715f-415e-b310-ba91299401aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522961893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_same_csr_outstanding.522961893
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3807343096
Short name T1237
Test name
Test status
Simulation time 252107634 ps
CPU time 5.07 seconds
Started Jul 29 05:50:13 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 246164 kb
Host smart-cf4198f2-0451-40d8-8981-3949d3c9ee44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807343096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3807343096
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1377831170
Short name T273
Test name
Test status
Simulation time 2543482281 ps
CPU time 12.36 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:27 PM PDT 24
Peak memory 238968 kb
Host smart-6b9177b1-d76d-49b7-b488-714f37c698ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377831170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.1377831170
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2395259221
Short name T1272
Test name
Test status
Simulation time 43868206 ps
CPU time 1.42 seconds
Started Jul 29 05:50:45 PM PDT 24
Finished Jul 29 05:50:47 PM PDT 24
Peak memory 229896 kb
Host smart-0acf3898-1ac4-40d8-b064-7377ffe02e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395259221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2395259221
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2964187349
Short name T1295
Test name
Test status
Simulation time 41127714 ps
CPU time 1.33 seconds
Started Jul 29 05:50:45 PM PDT 24
Finished Jul 29 05:50:46 PM PDT 24
Peak memory 230624 kb
Host smart-c23e5dc0-75e2-4f9e-bb4a-777ec1e71ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964187349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2964187349
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2517160854
Short name T1245
Test name
Test status
Simulation time 39524110 ps
CPU time 1.34 seconds
Started Jul 29 05:50:46 PM PDT 24
Finished Jul 29 05:50:47 PM PDT 24
Peak memory 229796 kb
Host smart-3cd0204f-3353-4614-8907-0eeb157bfbf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517160854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2517160854
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1318400973
Short name T1238
Test name
Test status
Simulation time 109546767 ps
CPU time 1.43 seconds
Started Jul 29 05:50:45 PM PDT 24
Finished Jul 29 05:50:46 PM PDT 24
Peak memory 230068 kb
Host smart-c9fb8351-5084-46e3-9174-f9bb4ddb67e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318400973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1318400973
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.248128211
Short name T1288
Test name
Test status
Simulation time 558101789 ps
CPU time 1.4 seconds
Started Jul 29 05:50:47 PM PDT 24
Finished Jul 29 05:50:48 PM PDT 24
Peak memory 230668 kb
Host smart-313ee5f2-4cb4-40ea-a1a6-73e41b51a4c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248128211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.248128211
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1133715979
Short name T1197
Test name
Test status
Simulation time 143258497 ps
CPU time 1.4 seconds
Started Jul 29 05:50:47 PM PDT 24
Finished Jul 29 05:50:49 PM PDT 24
Peak memory 230236 kb
Host smart-f34ef5f4-016a-4ce9-b436-9d479bc28faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133715979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1133715979
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3302866642
Short name T1211
Test name
Test status
Simulation time 75467727 ps
CPU time 1.49 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 05:50:51 PM PDT 24
Peak memory 229904 kb
Host smart-c82520c9-7f04-4a1f-9aff-7aa91068abde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302866642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3302866642
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1062771503
Short name T1248
Test name
Test status
Simulation time 617238175 ps
CPU time 2.25 seconds
Started Jul 29 05:50:45 PM PDT 24
Finished Jul 29 05:50:48 PM PDT 24
Peak memory 229916 kb
Host smart-83f6fc38-4e39-43b2-a008-762dd81806fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062771503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1062771503
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.766894039
Short name T1285
Test name
Test status
Simulation time 104032679 ps
CPU time 1.45 seconds
Started Jul 29 05:50:47 PM PDT 24
Finished Jul 29 05:50:48 PM PDT 24
Peak memory 229868 kb
Host smart-1a4aba06-1b37-43db-9f67-1562708e2537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766894039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.766894039
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.358300124
Short name T1320
Test name
Test status
Simulation time 144514144 ps
CPU time 1.43 seconds
Started Jul 29 05:50:46 PM PDT 24
Finished Jul 29 05:50:48 PM PDT 24
Peak memory 229924 kb
Host smart-b4584f38-b48c-480a-9cfb-faaf91243cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358300124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.358300124
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2477565252
Short name T1231
Test name
Test status
Simulation time 145838390 ps
CPU time 2.01 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 243676 kb
Host smart-7fe7c489-1942-43af-ad1d-6b07e796a2c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477565252 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2477565252
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.518069087
Short name T287
Test name
Test status
Simulation time 41557249 ps
CPU time 1.55 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 240504 kb
Host smart-37ea006f-7cd6-4044-8566-dc2a5f05d689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518069087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.518069087
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3755764601
Short name T1249
Test name
Test status
Simulation time 76804289 ps
CPU time 1.46 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 230660 kb
Host smart-d89357a2-aba3-41a5-9548-c92c4b214da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755764601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3755764601
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1962779420
Short name T1289
Test name
Test status
Simulation time 380662727 ps
CPU time 3.08 seconds
Started Jul 29 05:50:11 PM PDT 24
Finished Jul 29 05:50:14 PM PDT 24
Peak memory 238876 kb
Host smart-71812741-5fe7-4674-aec5-b56a6f9f5808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962779420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1962779420
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.749606759
Short name T1244
Test name
Test status
Simulation time 139411413 ps
CPU time 5.5 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 246508 kb
Host smart-9966664d-6f6b-42c2-a79e-64127ff35d55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749606759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.749606759
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3938518016
Short name T345
Test name
Test status
Simulation time 10403337087 ps
CPU time 12.84 seconds
Started Jul 29 05:50:06 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 244320 kb
Host smart-4c8701f0-56d7-4182-8595-88b29645362d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938518016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3938518016
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3857608194
Short name T1218
Test name
Test status
Simulation time 425729460 ps
CPU time 3.19 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 247064 kb
Host smart-893c30d0-d06f-41ea-a96e-ce7227b12b1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857608194 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.3857608194
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2856632045
Short name T1323
Test name
Test status
Simulation time 155307454 ps
CPU time 1.61 seconds
Started Jul 29 05:50:17 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 240664 kb
Host smart-f329320b-d847-4aac-85ec-ad413fac800e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856632045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2856632045
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2790595559
Short name T1226
Test name
Test status
Simulation time 147351698 ps
CPU time 1.37 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 230656 kb
Host smart-d31d2038-f333-47bb-a9bd-8b33600b68ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790595559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2790595559
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1792275277
Short name T303
Test name
Test status
Simulation time 1134291585 ps
CPU time 2.46 seconds
Started Jul 29 05:50:18 PM PDT 24
Finished Jul 29 05:50:21 PM PDT 24
Peak memory 238796 kb
Host smart-4019b2b5-75e7-47c5-b81d-319ca68b0b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792275277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1792275277
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.391054134
Short name T1255
Test name
Test status
Simulation time 166122284 ps
CPU time 5.82 seconds
Started Jul 29 05:50:11 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 246268 kb
Host smart-6937f7a0-d933-44ce-94c8-b5c3535ae664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391054134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.391054134
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2713254186
Short name T342
Test name
Test status
Simulation time 20085991649 ps
CPU time 24.82 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:40 PM PDT 24
Peak memory 244672 kb
Host smart-f2220f24-2c55-4077-bcf3-d95094baa514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713254186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2713254186
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3752050844
Short name T1327
Test name
Test status
Simulation time 1709274664 ps
CPU time 3.48 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 247052 kb
Host smart-74e8d064-db7b-460f-b914-656496e48a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752050844 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3752050844
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.805095501
Short name T301
Test name
Test status
Simulation time 74312454 ps
CPU time 1.62 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:16 PM PDT 24
Peak memory 240584 kb
Host smart-47cab0b6-7a00-4c37-bbb0-c9542f7e81e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805095501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.805095501
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3555186932
Short name T1217
Test name
Test status
Simulation time 71399961 ps
CPU time 1.37 seconds
Started Jul 29 05:50:17 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 230648 kb
Host smart-b5e1e118-2e05-49c4-b853-36e49a7ab04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555186932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3555186932
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.456655473
Short name T305
Test name
Test status
Simulation time 1077305791 ps
CPU time 3.18 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 238808 kb
Host smart-35d57594-3771-4cd9-8e42-3fe859eec134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456655473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.456655473
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3608562283
Short name T1279
Test name
Test status
Simulation time 956762079 ps
CPU time 3.59 seconds
Started Jul 29 05:50:13 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 245808 kb
Host smart-3720d200-e2c0-4dfa-9d06-d331a0d3c79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608562283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3608562283
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1646464251
Short name T339
Test name
Test status
Simulation time 2336673617 ps
CPU time 10.3 seconds
Started Jul 29 05:50:13 PM PDT 24
Finished Jul 29 05:50:23 PM PDT 24
Peak memory 238884 kb
Host smart-f4a09621-7a76-489b-b61c-35efdcc98014
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646464251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1646464251
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3139016797
Short name T1298
Test name
Test status
Simulation time 220586562 ps
CPU time 4.25 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 247088 kb
Host smart-8dbd6b52-3b51-476c-9dc0-ee615ea1c95c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139016797 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3139016797
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2394305555
Short name T1222
Test name
Test status
Simulation time 99911728 ps
CPU time 1.67 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 240592 kb
Host smart-89be2929-6f8c-434f-9ef8-f33b83e17a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394305555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2394305555
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.6087362
Short name T1228
Test name
Test status
Simulation time 43508622 ps
CPU time 1.35 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 229900 kb
Host smart-e48f6adb-0220-4d9d-9024-97cccf920b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6087362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.6087362
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1570488602
Short name T1261
Test name
Test status
Simulation time 114545428 ps
CPU time 2.56 seconds
Started Jul 29 05:50:15 PM PDT 24
Finished Jul 29 05:50:18 PM PDT 24
Peak memory 242044 kb
Host smart-0ed6d5bd-cb68-4eb8-9048-5316b8b1345e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570488602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.1570488602
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.64882446
Short name T1318
Test name
Test status
Simulation time 78208612 ps
CPU time 3.14 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:17 PM PDT 24
Peak memory 245392 kb
Host smart-d33961fe-34e2-4cf3-b37f-aac1a914f220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64882446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.64882446
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3854307796
Short name T346
Test name
Test status
Simulation time 1144167333 ps
CPU time 13.21 seconds
Started Jul 29 05:50:16 PM PDT 24
Finished Jul 29 05:50:30 PM PDT 24
Peak memory 243776 kb
Host smart-7351d1f2-97cc-4ce2-a9f5-c613e0a9705b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854307796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3854307796
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2255654472
Short name T1325
Test name
Test status
Simulation time 138802185 ps
CPU time 2.24 seconds
Started Jul 29 05:50:17 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 245032 kb
Host smart-c8bb177d-8d6d-462b-bce7-67f78b428943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255654472 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.2255654472
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2340300842
Short name T1316
Test name
Test status
Simulation time 128813132 ps
CPU time 1.36 seconds
Started Jul 29 05:50:17 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 229940 kb
Host smart-f465a788-c088-493f-b083-76515eb29639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340300842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2340300842
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2096855747
Short name T1264
Test name
Test status
Simulation time 173744235 ps
CPU time 2.02 seconds
Started Jul 29 05:50:20 PM PDT 24
Finished Jul 29 05:50:22 PM PDT 24
Peak memory 238884 kb
Host smart-d0c0ea7e-e3ad-45da-8e6e-100b2902fca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096855747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.2096855747
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2239900909
Short name T1299
Test name
Test status
Simulation time 117595176 ps
CPU time 4.19 seconds
Started Jul 29 05:50:14 PM PDT 24
Finished Jul 29 05:50:19 PM PDT 24
Peak memory 239024 kb
Host smart-3ff6d029-678d-4fb0-88ef-66bbd65eb464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239900909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2239900909
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1195188589
Short name T416
Test name
Test status
Simulation time 207857976 ps
CPU time 2.18 seconds
Started Jul 29 07:40:12 PM PDT 24
Finished Jul 29 07:40:14 PM PDT 24
Peak memory 240908 kb
Host smart-244f587d-c761-4f42-92de-9d5cfe4e5618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195188589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1195188589
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.66344757
Short name T1064
Test name
Test status
Simulation time 1489986935 ps
CPU time 11.85 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:23 PM PDT 24
Peak memory 242180 kb
Host smart-09c12443-9362-42e0-8bf6-24dde2be1f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66344757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.66344757
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.725610462
Short name T536
Test name
Test status
Simulation time 389197059 ps
CPU time 8.97 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:20 PM PDT 24
Peak memory 242924 kb
Host smart-e1729bdf-5c75-4b7f-a64d-a1cacc30261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725610462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.725610462
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.2416580651
Short name T505
Test name
Test status
Simulation time 368521550 ps
CPU time 9.89 seconds
Started Jul 29 07:40:13 PM PDT 24
Finished Jul 29 07:40:23 PM PDT 24
Peak memory 242296 kb
Host smart-931340ad-c7c5-4cdf-9609-59cdeae0d3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416580651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2416580651
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.326851482
Short name T900
Test name
Test status
Simulation time 375771419 ps
CPU time 12.52 seconds
Started Jul 29 07:40:13 PM PDT 24
Finished Jul 29 07:40:25 PM PDT 24
Peak memory 242376 kb
Host smart-7803f26e-b307-4eb5-88cd-1bf0b5b18d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326851482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.326851482
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3589089351
Short name T719
Test name
Test status
Simulation time 2268941191 ps
CPU time 4.57 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:15 PM PDT 24
Peak memory 242048 kb
Host smart-1a5e1e77-65de-4df1-8b9f-d8fdcb6c9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589089351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3589089351
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1241529783
Short name T203
Test name
Test status
Simulation time 7581651418 ps
CPU time 17.54 seconds
Started Jul 29 07:40:13 PM PDT 24
Finished Jul 29 07:40:30 PM PDT 24
Peak memory 240620 kb
Host smart-45454b3f-84ba-43b3-b93e-62b37c12e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241529783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1241529783
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.587028393
Short name T587
Test name
Test status
Simulation time 3296639998 ps
CPU time 36.21 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:48 PM PDT 24
Peak memory 248628 kb
Host smart-adac3461-f9ee-4846-9469-0c7beaf43393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587028393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.587028393
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.87953206
Short name T994
Test name
Test status
Simulation time 2014256386 ps
CPU time 24.56 seconds
Started Jul 29 07:40:12 PM PDT 24
Finished Jul 29 07:40:37 PM PDT 24
Peak memory 242852 kb
Host smart-259d6d9d-76f5-4bd0-9f88-2b0119bdf144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87953206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.87953206
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2186479816
Short name T398
Test name
Test status
Simulation time 147105047 ps
CPU time 7.23 seconds
Started Jul 29 07:40:14 PM PDT 24
Finished Jul 29 07:40:21 PM PDT 24
Peak memory 241944 kb
Host smart-ab1e0e37-7483-492e-8181-abea86798572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186479816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2186479816
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3893240268
Short name T603
Test name
Test status
Simulation time 755484583 ps
CPU time 10.82 seconds
Started Jul 29 07:40:09 PM PDT 24
Finished Jul 29 07:40:20 PM PDT 24
Peak memory 248488 kb
Host smart-6053b774-2916-43a9-aa48-7b580003ec3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893240268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3893240268
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1357772501
Short name T813
Test name
Test status
Simulation time 816140381 ps
CPU time 21.6 seconds
Started Jul 29 07:40:09 PM PDT 24
Finished Jul 29 07:40:31 PM PDT 24
Peak memory 241520 kb
Host smart-ba483c4f-20ce-467d-a896-2b3678c2a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357772501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1357772501
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3516157310
Short name T632
Test name
Test status
Simulation time 237927271 ps
CPU time 3.99 seconds
Started Jul 29 07:40:10 PM PDT 24
Finished Jul 29 07:40:15 PM PDT 24
Peak memory 241904 kb
Host smart-1871744e-3729-4957-975d-deb14e457bd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516157310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3516157310
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.2488248684
Short name T243
Test name
Test status
Simulation time 28353356673 ps
CPU time 181.5 seconds
Started Jul 29 07:40:10 PM PDT 24
Finished Jul 29 07:43:12 PM PDT 24
Peak memory 274672 kb
Host smart-7b4ae3dd-6d8c-4c75-8f3d-07d4fd01831f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488248684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2488248684
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.1867933692
Short name T474
Test name
Test status
Simulation time 4871649262 ps
CPU time 36.11 seconds
Started Jul 29 07:39:58 PM PDT 24
Finished Jul 29 07:40:34 PM PDT 24
Peak memory 248684 kb
Host smart-062e64b3-a20d-444a-8382-adc8fedd48aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867933692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1867933692
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.1534526965
Short name T666
Test name
Test status
Simulation time 1268836054 ps
CPU time 42.07 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:54 PM PDT 24
Peak memory 246084 kb
Host smart-57ee7574-c12e-45a1-b983-bcab073423e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534526965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
1534526965
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3513965049
Short name T1057
Test name
Test status
Simulation time 32922794609 ps
CPU time 283.15 seconds
Started Jul 29 07:40:09 PM PDT 24
Finished Jul 29 07:44:52 PM PDT 24
Peak memory 273320 kb
Host smart-a0374fdb-c778-481b-83e7-033861f17407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513965049 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3513965049
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2294731421
Short name T85
Test name
Test status
Simulation time 3227901915 ps
CPU time 38.59 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:49 PM PDT 24
Peak memory 242372 kb
Host smart-9c194bbf-5c78-4fe1-b829-db2407e0df47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294731421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2294731421
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.886614014
Short name T602
Test name
Test status
Simulation time 3379722522 ps
CPU time 19.63 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:31 PM PDT 24
Peak memory 248716 kb
Host smart-d26d269c-72f0-4c8f-9142-41cf70648270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886614014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.886614014
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1368200034
Short name T816
Test name
Test status
Simulation time 430897371 ps
CPU time 7.61 seconds
Started Jul 29 07:40:25 PM PDT 24
Finished Jul 29 07:40:33 PM PDT 24
Peak memory 242012 kb
Host smart-1ae3bcfa-2f13-40eb-b801-c2963e6ff4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368200034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1368200034
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1417691211
Short name T3
Test name
Test status
Simulation time 3768057895 ps
CPU time 44.16 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 252884 kb
Host smart-bd3dace1-2b19-4f66-8169-bfed9f1f9202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417691211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1417691211
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.2101038328
Short name T751
Test name
Test status
Simulation time 142775101 ps
CPU time 5.57 seconds
Started Jul 29 07:40:31 PM PDT 24
Finished Jul 29 07:40:37 PM PDT 24
Peak memory 241904 kb
Host smart-a8a3b2ee-ec40-4e6f-87a5-29ef1384a29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101038328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2101038328
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.145599918
Short name T927
Test name
Test status
Simulation time 423231861 ps
CPU time 4.16 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:16 PM PDT 24
Peak memory 242300 kb
Host smart-83d609c6-7b12-438c-8c4d-2b0fe408026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145599918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.145599918
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.1945014555
Short name T871
Test name
Test status
Simulation time 5894638581 ps
CPU time 44.8 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 256852 kb
Host smart-0d513069-d015-4992-82c2-19ba64622a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945014555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1945014555
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.2984569055
Short name T808
Test name
Test status
Simulation time 496240179 ps
CPU time 7.34 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:40:35 PM PDT 24
Peak memory 241916 kb
Host smart-1fe04797-8b95-42ac-9297-ed1437caf065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984569055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2984569055
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.3769427843
Short name T202
Test name
Test status
Simulation time 94622262 ps
CPU time 2.69 seconds
Started Jul 29 07:40:09 PM PDT 24
Finished Jul 29 07:40:12 PM PDT 24
Peak memory 241832 kb
Host smart-40260f04-b460-4f5f-8ab5-7cc85327225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769427843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3769427843
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.1166795401
Short name T635
Test name
Test status
Simulation time 2076512942 ps
CPU time 25.64 seconds
Started Jul 29 07:40:11 PM PDT 24
Finished Jul 29 07:40:36 PM PDT 24
Peak memory 242124 kb
Host smart-3bb0c3f3-16fb-43c0-ac82-83e66ccf56f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166795401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1166795401
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.1439847344
Short name T796
Test name
Test status
Simulation time 239778230 ps
CPU time 4.79 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:31 PM PDT 24
Peak memory 242056 kb
Host smart-515fe5e7-c15d-4da6-97e8-2c9a3b2e8c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439847344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1439847344
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1839986469
Short name T25
Test name
Test status
Simulation time 10277397647 ps
CPU time 197.39 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:43:45 PM PDT 24
Peak memory 266172 kb
Host smart-843e10b6-d178-4bb1-9952-82bb5485b0ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839986469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1839986469
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2657041833
Short name T1022
Test name
Test status
Simulation time 647629068 ps
CPU time 11.12 seconds
Started Jul 29 07:40:12 PM PDT 24
Finished Jul 29 07:40:23 PM PDT 24
Peak memory 242020 kb
Host smart-424d7947-ea73-4feb-920e-c381059e269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657041833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2657041833
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3311570348
Short name T832
Test name
Test status
Simulation time 2195116332 ps
CPU time 45.72 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:41:13 PM PDT 24
Peak memory 242564 kb
Host smart-05439bb8-ced6-434f-a1b4-61df1d95ef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311570348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3311570348
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.341396424
Short name T437
Test name
Test status
Simulation time 109895718 ps
CPU time 2 seconds
Started Jul 29 07:41:17 PM PDT 24
Finished Jul 29 07:41:19 PM PDT 24
Peak memory 240520 kb
Host smart-87d19e03-a5d2-4a86-9588-62d2b1913d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341396424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.341396424
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.3930276220
Short name T1081
Test name
Test status
Simulation time 754920650 ps
CPU time 5.42 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:16 PM PDT 24
Peak memory 248456 kb
Host smart-212e4519-2931-48b8-9ebc-4765759aa4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930276220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3930276220
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.4033320978
Short name T447
Test name
Test status
Simulation time 5130948222 ps
CPU time 25.63 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:37 PM PDT 24
Peak memory 242364 kb
Host smart-c524a6c4-3dd3-446b-8b65-1763f899b22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033320978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.4033320978
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.931189816
Short name T473
Test name
Test status
Simulation time 492148080 ps
CPU time 5.75 seconds
Started Jul 29 07:41:12 PM PDT 24
Finished Jul 29 07:41:18 PM PDT 24
Peak memory 242200 kb
Host smart-367cfcdc-d104-4f75-8685-33103bdac5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931189816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.931189816
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.430287368
Short name T1157
Test name
Test status
Simulation time 236502497 ps
CPU time 4.71 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:16 PM PDT 24
Peak memory 242160 kb
Host smart-633175c8-afd6-4b7d-a0dd-6a7007cf8082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430287368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.430287368
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.1362555839
Short name T1154
Test name
Test status
Simulation time 225717782 ps
CPU time 3.81 seconds
Started Jul 29 07:41:21 PM PDT 24
Finished Jul 29 07:41:25 PM PDT 24
Peak memory 248568 kb
Host smart-8e988113-a8b0-4146-a829-cef930b2e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362555839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1362555839
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.2679320279
Short name T1189
Test name
Test status
Simulation time 5875072676 ps
CPU time 18.7 seconds
Started Jul 29 07:41:12 PM PDT 24
Finished Jul 29 07:41:30 PM PDT 24
Peak memory 242460 kb
Host smart-953c270c-061c-468b-a977-aaf8be1cfd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679320279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.2679320279
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2461768390
Short name T584
Test name
Test status
Simulation time 998236037 ps
CPU time 20.95 seconds
Started Jul 29 07:41:20 PM PDT 24
Finished Jul 29 07:41:41 PM PDT 24
Peak memory 241904 kb
Host smart-32b46f25-a34a-4c0c-999f-36a177b8a5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461768390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2461768390
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.478629438
Short name T1153
Test name
Test status
Simulation time 637018393 ps
CPU time 18.53 seconds
Started Jul 29 07:41:12 PM PDT 24
Finished Jul 29 07:41:31 PM PDT 24
Peak memory 242160 kb
Host smart-7b1ec8ce-972f-422b-9821-a802f93fb982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478629438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.478629438
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.3258266247
Short name T400
Test name
Test status
Simulation time 187501343 ps
CPU time 3.36 seconds
Started Jul 29 07:41:13 PM PDT 24
Finished Jul 29 07:41:16 PM PDT 24
Peak memory 242080 kb
Host smart-150ec5ad-6ff9-42de-a371-717b16d73678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258266247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3258266247
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.3865577257
Short name T1063
Test name
Test status
Simulation time 265841571 ps
CPU time 6.89 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:18 PM PDT 24
Peak memory 242000 kb
Host smart-e5cd10c4-45f6-4b88-98da-37ecc9f24a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865577257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3865577257
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1794498957
Short name T223
Test name
Test status
Simulation time 137217070914 ps
CPU time 207.1 seconds
Started Jul 29 07:41:20 PM PDT 24
Finished Jul 29 07:44:47 PM PDT 24
Peak memory 265300 kb
Host smart-3577949a-367b-4d90-9549-f104b6952c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794498957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1794498957
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.809370405
Short name T833
Test name
Test status
Simulation time 17984381450 ps
CPU time 194.81 seconds
Started Jul 29 07:41:20 PM PDT 24
Finished Jul 29 07:44:35 PM PDT 24
Peak memory 275452 kb
Host smart-70ae33d6-364a-493e-b946-1112cb6c6622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809370405 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.809370405
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.3199134048
Short name T16
Test name
Test status
Simulation time 1212685187 ps
CPU time 26.38 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:38 PM PDT 24
Peak memory 248668 kb
Host smart-7834e114-64a4-483c-bcac-132c05d1822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199134048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3199134048
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.3144336778
Short name T1062
Test name
Test status
Simulation time 322800249 ps
CPU time 3.65 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:08 PM PDT 24
Peak memory 242004 kb
Host smart-55bc5388-601e-4d83-a87e-44daf2c085c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144336778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3144336778
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2888291813
Short name T985
Test name
Test status
Simulation time 3459671440 ps
CPU time 10.24 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242240 kb
Host smart-9230a204-88b9-4ea0-90fc-3aa55c7a752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888291813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2888291813
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3873075413
Short name T618
Test name
Test status
Simulation time 143751120 ps
CPU time 4.29 seconds
Started Jul 29 07:48:13 PM PDT 24
Finished Jul 29 07:48:18 PM PDT 24
Peak memory 242376 kb
Host smart-2d7693d8-e36a-4224-8734-5f24600f12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873075413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3873075413
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.4253978365
Short name T226
Test name
Test status
Simulation time 432720331 ps
CPU time 5.69 seconds
Started Jul 29 07:48:12 PM PDT 24
Finished Jul 29 07:48:17 PM PDT 24
Peak memory 241880 kb
Host smart-3bda004f-19df-4d28-9c98-415c2c786494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253978365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.4253978365
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.4156605370
Short name T1116
Test name
Test status
Simulation time 1639124997 ps
CPU time 3.94 seconds
Started Jul 29 07:48:17 PM PDT 24
Finished Jul 29 07:48:21 PM PDT 24
Peak memory 242148 kb
Host smart-1c46625b-87f5-4085-b235-0db56c8ac9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156605370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.4156605370
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.4205926717
Short name T204
Test name
Test status
Simulation time 1787435664 ps
CPU time 21.06 seconds
Started Jul 29 07:48:16 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241932 kb
Host smart-e4cd3589-dc80-4d11-8a48-f4c5f7a4060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205926717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.4205926717
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.2469902901
Short name T404
Test name
Test status
Simulation time 104220183 ps
CPU time 3.68 seconds
Started Jul 29 07:48:10 PM PDT 24
Finished Jul 29 07:48:14 PM PDT 24
Peak memory 242152 kb
Host smart-40149d04-677d-41ec-aea0-9f15aacff4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469902901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2469902901
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1902870067
Short name T494
Test name
Test status
Simulation time 278063264 ps
CPU time 3.89 seconds
Started Jul 29 07:48:17 PM PDT 24
Finished Jul 29 07:48:21 PM PDT 24
Peak memory 241732 kb
Host smart-6ba1d782-63aa-490d-8401-eaf1e36f1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902870067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1902870067
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.3317926442
Short name T1165
Test name
Test status
Simulation time 819374528 ps
CPU time 5.32 seconds
Started Jul 29 07:48:17 PM PDT 24
Finished Jul 29 07:48:22 PM PDT 24
Peak memory 242136 kb
Host smart-c02ab937-393f-4f29-b48d-50c11eb3740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317926442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3317926442
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.2844900685
Short name T745
Test name
Test status
Simulation time 132616937 ps
CPU time 4.01 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 242088 kb
Host smart-bab9b186-2012-434b-ac3b-cdd3a6429c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844900685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2844900685
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1633278564
Short name T47
Test name
Test status
Simulation time 295197607 ps
CPU time 4.9 seconds
Started Jul 29 07:48:15 PM PDT 24
Finished Jul 29 07:48:20 PM PDT 24
Peak memory 242068 kb
Host smart-f6f88ce4-3a61-446d-a788-988b181336ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633278564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1633278564
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.2980594628
Short name T1079
Test name
Test status
Simulation time 319911515 ps
CPU time 4.88 seconds
Started Jul 29 07:48:15 PM PDT 24
Finished Jul 29 07:48:20 PM PDT 24
Peak memory 241840 kb
Host smart-49610739-c698-4c98-8aaa-95142043e04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980594628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2980594628
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.1938597097
Short name T208
Test name
Test status
Simulation time 499876905 ps
CPU time 9.73 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242044 kb
Host smart-73f597ba-1158-4697-8b15-76395cfe6918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938597097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1938597097
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.3050759187
Short name T823
Test name
Test status
Simulation time 209386177 ps
CPU time 4.99 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242276 kb
Host smart-29306c35-583d-4632-8496-2d2875c75cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050759187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3050759187
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.2475881989
Short name T596
Test name
Test status
Simulation time 1319706333 ps
CPU time 20.08 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:39 PM PDT 24
Peak memory 242432 kb
Host smart-2cc8a4e6-a292-4a80-9fcc-2d97b8303964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475881989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.2475881989
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.802562608
Short name T709
Test name
Test status
Simulation time 387931675 ps
CPU time 4.37 seconds
Started Jul 29 07:48:15 PM PDT 24
Finished Jul 29 07:48:20 PM PDT 24
Peak memory 242292 kb
Host smart-b59df3e8-54a8-48bb-9547-ed9fa6fba1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802562608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.802562608
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.2913681066
Short name T332
Test name
Test status
Simulation time 8896017060 ps
CPU time 27.16 seconds
Started Jul 29 07:48:14 PM PDT 24
Finished Jul 29 07:48:42 PM PDT 24
Peak memory 242436 kb
Host smart-9bafe6e0-5e74-412b-baaa-d7e9cc268325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913681066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2913681066
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.1433469357
Short name T876
Test name
Test status
Simulation time 115734080 ps
CPU time 4.08 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 242004 kb
Host smart-71fd31d5-24b1-49e9-ab8e-a5f5c4c1bda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433469357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1433469357
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2119074903
Short name T459
Test name
Test status
Simulation time 255441600 ps
CPU time 14 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241996 kb
Host smart-37bfb835-86d9-456f-8a54-365ad5acf7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119074903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2119074903
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.353608996
Short name T886
Test name
Test status
Simulation time 140573596 ps
CPU time 2.02 seconds
Started Jul 29 07:41:24 PM PDT 24
Finished Jul 29 07:41:26 PM PDT 24
Peak memory 240512 kb
Host smart-12339df1-262a-4bd0-a533-65eee196dd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353608996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.353608996
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2189491220
Short name T1014
Test name
Test status
Simulation time 1049212567 ps
CPU time 6.76 seconds
Started Jul 29 07:41:17 PM PDT 24
Finished Jul 29 07:41:24 PM PDT 24
Peak memory 242120 kb
Host smart-9f5f2ecc-bf01-45cd-a108-1f1eabd1f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189491220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2189491220
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.2534906652
Short name T453
Test name
Test status
Simulation time 282373803 ps
CPU time 15.63 seconds
Started Jul 29 07:41:18 PM PDT 24
Finished Jul 29 07:41:34 PM PDT 24
Peak memory 242200 kb
Host smart-a4b41358-6dc9-4d0e-b803-8f3780d27571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534906652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.2534906652
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.3191399145
Short name T512
Test name
Test status
Simulation time 291030788 ps
CPU time 5.45 seconds
Started Jul 29 07:41:19 PM PDT 24
Finished Jul 29 07:41:24 PM PDT 24
Peak memory 242476 kb
Host smart-08c2f21f-8138-4a29-a766-d2fbf420f772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191399145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3191399145
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.2440024647
Short name T405
Test name
Test status
Simulation time 243587148 ps
CPU time 3.48 seconds
Started Jul 29 07:41:17 PM PDT 24
Finished Jul 29 07:41:21 PM PDT 24
Peak memory 242388 kb
Host smart-48e3a214-6a30-4986-860e-dcb9b5ca21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440024647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2440024647
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.2730094465
Short name T189
Test name
Test status
Simulation time 5482939324 ps
CPU time 57.89 seconds
Started Jul 29 07:41:18 PM PDT 24
Finished Jul 29 07:42:16 PM PDT 24
Peak memory 258776 kb
Host smart-da859acb-e5b1-4e33-9e0e-a507c8dd2d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730094465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2730094465
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2059441051
Short name T861
Test name
Test status
Simulation time 5124663625 ps
CPU time 19.66 seconds
Started Jul 29 07:41:17 PM PDT 24
Finished Jul 29 07:41:37 PM PDT 24
Peak memory 242720 kb
Host smart-ee5ca58c-6cd5-4fab-a666-dc561e4176f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059441051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2059441051
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2110179927
Short name T714
Test name
Test status
Simulation time 630108282 ps
CPU time 17.47 seconds
Started Jul 29 07:41:19 PM PDT 24
Finished Jul 29 07:41:37 PM PDT 24
Peak memory 242236 kb
Host smart-832cd254-ee9c-478b-b237-d6f70088db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110179927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2110179927
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1300329706
Short name T899
Test name
Test status
Simulation time 1326097227 ps
CPU time 19.34 seconds
Started Jul 29 07:41:17 PM PDT 24
Finished Jul 29 07:41:36 PM PDT 24
Peak memory 248636 kb
Host smart-36adabfb-e0b2-4797-ab77-505d250dd336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300329706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1300329706
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2769138981
Short name T356
Test name
Test status
Simulation time 4244758312 ps
CPU time 13.46 seconds
Started Jul 29 07:41:20 PM PDT 24
Finished Jul 29 07:41:34 PM PDT 24
Peak memory 242616 kb
Host smart-0771f79c-4537-422d-ad5a-6269174eb6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769138981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2769138981
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.2048297061
Short name T1025
Test name
Test status
Simulation time 2494545472 ps
CPU time 6.33 seconds
Started Jul 29 07:41:17 PM PDT 24
Finished Jul 29 07:41:23 PM PDT 24
Peak memory 242440 kb
Host smart-86c454c1-d037-452a-b698-6dfc5cb39675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048297061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2048297061
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.4248475880
Short name T827
Test name
Test status
Simulation time 11796537746 ps
CPU time 95.03 seconds
Started Jul 29 07:41:24 PM PDT 24
Finished Jul 29 07:42:59 PM PDT 24
Peak memory 258524 kb
Host smart-9c7cb46b-c0cc-441f-a972-1f030ae56370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248475880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.4248475880
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.9847039
Short name T383
Test name
Test status
Simulation time 18512445410 ps
CPU time 25.36 seconds
Started Jul 29 07:41:24 PM PDT 24
Finished Jul 29 07:41:50 PM PDT 24
Peak memory 242288 kb
Host smart-95a1ca8b-b0f8-4484-b07f-6b628e316b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9847039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.9847039
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.861405734
Short name T399
Test name
Test status
Simulation time 259450961 ps
CPU time 3.92 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:28 PM PDT 24
Peak memory 242132 kb
Host smart-24a067da-4349-4ae0-b23a-4998b5aa9b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861405734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.861405734
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3594707261
Short name T156
Test name
Test status
Simulation time 706587926 ps
CPU time 13.12 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 241900 kb
Host smart-030fb640-bf4c-45f6-ba40-a2bd980bfe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594707261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3594707261
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3738530969
Short name T1021
Test name
Test status
Simulation time 1603325747 ps
CPU time 4.66 seconds
Started Jul 29 07:48:16 PM PDT 24
Finished Jul 29 07:48:21 PM PDT 24
Peak memory 242216 kb
Host smart-45f7dd2a-32d4-42fc-84d2-7e0e157e961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738530969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3738530969
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.545738719
Short name T1020
Test name
Test status
Simulation time 626508399 ps
CPU time 17.05 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:36 PM PDT 24
Peak memory 241912 kb
Host smart-075e8ad3-f2eb-4f66-881a-aefd49f1f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545738719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.545738719
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1956394918
Short name T588
Test name
Test status
Simulation time 296079053 ps
CPU time 4.19 seconds
Started Jul 29 07:48:11 PM PDT 24
Finished Jul 29 07:48:15 PM PDT 24
Peak memory 242040 kb
Host smart-14844cbf-c80f-4730-b53c-9ba3a4f36102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956394918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1956394918
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.730584641
Short name T919
Test name
Test status
Simulation time 102056857 ps
CPU time 2.98 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:22 PM PDT 24
Peak memory 241824 kb
Host smart-cda39bfe-226c-4ef2-9221-f03660a8a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730584641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.730584641
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3545520657
Short name T438
Test name
Test status
Simulation time 246247469 ps
CPU time 4.7 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 242024 kb
Host smart-6c22f0e1-8663-4d44-8cae-2de7f779c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545520657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3545520657
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.475739827
Short name T1101
Test name
Test status
Simulation time 92605474 ps
CPU time 3.33 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:22 PM PDT 24
Peak memory 247508 kb
Host smart-aade5dd6-c59b-40ec-9949-bc5e5cec7984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475739827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.475739827
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.1412238555
Short name T594
Test name
Test status
Simulation time 106508367 ps
CPU time 3.7 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242428 kb
Host smart-4702f70e-b7d7-45ba-9c27-07f53dccf59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412238555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1412238555
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.1716384912
Short name T986
Test name
Test status
Simulation time 419063802 ps
CPU time 5.06 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 242292 kb
Host smart-4863f511-5a3f-47a6-a167-100d43034a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716384912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1716384912
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3219552540
Short name T248
Test name
Test status
Simulation time 1469334653 ps
CPU time 12.58 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 241820 kb
Host smart-a9a574c9-f4ac-4b3f-9c90-aeac8eb4d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219552540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3219552540
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.1643076033
Short name T687
Test name
Test status
Simulation time 463391208 ps
CPU time 5.28 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242420 kb
Host smart-138344c7-13f2-453d-8ba2-3215df41aa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643076033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1643076033
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2364358750
Short name T484
Test name
Test status
Simulation time 7632331229 ps
CPU time 24.1 seconds
Started Jul 29 07:48:11 PM PDT 24
Finished Jul 29 07:48:35 PM PDT 24
Peak memory 242500 kb
Host smart-e4009a05-8b01-4d32-a64e-9d0dbc33508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364358750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2364358750
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.959501254
Short name T756
Test name
Test status
Simulation time 380112949 ps
CPU time 4.13 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:22 PM PDT 24
Peak memory 242296 kb
Host smart-9002a3fd-cae5-4a5e-bf71-009c41ea3603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959501254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.959501254
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3031293087
Short name T955
Test name
Test status
Simulation time 4571127791 ps
CPU time 12.52 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 242356 kb
Host smart-89d535e2-051a-41ed-8b29-b2eee5584d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031293087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3031293087
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.4114881083
Short name T574
Test name
Test status
Simulation time 2363797591 ps
CPU time 6.63 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:31 PM PDT 24
Peak memory 242232 kb
Host smart-4e963bdc-8841-40dc-941f-4956ded140af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114881083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.4114881083
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3957815626
Short name T414
Test name
Test status
Simulation time 4151378229 ps
CPU time 8.98 seconds
Started Jul 29 07:48:14 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242484 kb
Host smart-862a5ab3-5889-4bc8-b50c-c76f64d61617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957815626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3957815626
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.1260876556
Short name T826
Test name
Test status
Simulation time 2313807651 ps
CPU time 4.54 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 242232 kb
Host smart-0735022a-0eb6-4699-8255-bc922c1807ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260876556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1260876556
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.2042276799
Short name T859
Test name
Test status
Simulation time 327307126 ps
CPU time 4.21 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242148 kb
Host smart-47f95d74-e322-4bba-800e-a96cb314624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042276799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2042276799
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.461442391
Short name T492
Test name
Test status
Simulation time 618665561 ps
CPU time 1.78 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:41:34 PM PDT 24
Peak memory 240468 kb
Host smart-bf25d290-36cd-495a-a78a-e6ccf8aabf98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461442391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.461442391
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.518407168
Short name T1098
Test name
Test status
Simulation time 3258845974 ps
CPU time 7.65 seconds
Started Jul 29 07:41:27 PM PDT 24
Finished Jul 29 07:41:35 PM PDT 24
Peak memory 241872 kb
Host smart-85594f53-537c-48ae-8949-29a2c797f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518407168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.518407168
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.1274475158
Short name T220
Test name
Test status
Simulation time 295920895 ps
CPU time 18.04 seconds
Started Jul 29 07:41:24 PM PDT 24
Finished Jul 29 07:41:42 PM PDT 24
Peak memory 242340 kb
Host smart-689b5f2b-9c6a-4226-b8d5-8c59cc171fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274475158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1274475158
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.3815605311
Short name T363
Test name
Test status
Simulation time 1940292960 ps
CPU time 15.5 seconds
Started Jul 29 07:41:23 PM PDT 24
Finished Jul 29 07:41:39 PM PDT 24
Peak memory 242108 kb
Host smart-a2d18e11-2aca-418d-bd5b-1e99c53b30c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815605311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3815605311
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1638506336
Short name T1121
Test name
Test status
Simulation time 1900143901 ps
CPU time 5.59 seconds
Started Jul 29 07:41:27 PM PDT 24
Finished Jul 29 07:41:32 PM PDT 24
Peak memory 241908 kb
Host smart-a0f386f8-4cad-474e-a38b-59df1f8efb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638506336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1638506336
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.3570351914
Short name T643
Test name
Test status
Simulation time 2058736793 ps
CPU time 3.75 seconds
Started Jul 29 07:41:24 PM PDT 24
Finished Jul 29 07:41:28 PM PDT 24
Peak memory 241972 kb
Host smart-703c5ffd-9aae-4380-bd89-a4d383b148dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570351914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3570351914
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.1439104983
Short name T938
Test name
Test status
Simulation time 966724647 ps
CPU time 18.56 seconds
Started Jul 29 07:41:24 PM PDT 24
Finished Jul 29 07:41:43 PM PDT 24
Peak memory 242392 kb
Host smart-42a961ed-83b5-4b54-873d-7b7cbf688b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439104983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1439104983
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1043464771
Short name T417
Test name
Test status
Simulation time 197797280 ps
CPU time 5.86 seconds
Started Jul 29 07:41:25 PM PDT 24
Finished Jul 29 07:41:31 PM PDT 24
Peak memory 242236 kb
Host smart-0ff85973-4e42-4837-940a-1d4c12fea6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043464771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1043464771
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.3067175395
Short name T636
Test name
Test status
Simulation time 385327169 ps
CPU time 10.05 seconds
Started Jul 29 07:41:25 PM PDT 24
Finished Jul 29 07:41:35 PM PDT 24
Peak memory 248468 kb
Host smart-cddaa1cf-d745-4dba-824e-0f523dcafa32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067175395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.3067175395
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2208209979
Short name T520
Test name
Test status
Simulation time 1694019437 ps
CPU time 4.57 seconds
Started Jul 29 07:41:25 PM PDT 24
Finished Jul 29 07:41:30 PM PDT 24
Peak memory 242388 kb
Host smart-d669ab85-ec5b-4d66-b866-809cfb0fb3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208209979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2208209979
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.3457036308
Short name T22
Test name
Test status
Simulation time 134150479831 ps
CPU time 1229.14 seconds
Started Jul 29 07:41:26 PM PDT 24
Finished Jul 29 08:01:56 PM PDT 24
Peak memory 328952 kb
Host smart-2af6ffe9-0567-46cf-9468-e82aebe4711c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457036308 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.3457036308
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1139724989
Short name T1159
Test name
Test status
Simulation time 9093194505 ps
CPU time 14.92 seconds
Started Jul 29 07:41:25 PM PDT 24
Finished Jul 29 07:41:40 PM PDT 24
Peak memory 242132 kb
Host smart-579b7725-c7be-4762-a81f-c4558a870232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139724989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1139724989
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.4157688846
Short name T1039
Test name
Test status
Simulation time 2577964983 ps
CPU time 5.81 seconds
Started Jul 29 07:48:23 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242212 kb
Host smart-38c5a1c8-8b6d-449a-aeb2-2720f4c7bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157688846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.4157688846
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.806059668
Short name T805
Test name
Test status
Simulation time 633772041 ps
CPU time 10.63 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:30 PM PDT 24
Peak memory 242428 kb
Host smart-8fef2282-7803-4ad0-8908-5be80be7e07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806059668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.806059668
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2396814395
Short name T973
Test name
Test status
Simulation time 250810549 ps
CPU time 5 seconds
Started Jul 29 07:48:14 PM PDT 24
Finished Jul 29 07:48:19 PM PDT 24
Peak memory 242044 kb
Host smart-99911b94-3873-41ce-980a-263a63fb5904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396814395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2396814395
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.2799937610
Short name T551
Test name
Test status
Simulation time 414616655 ps
CPU time 7.33 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:26 PM PDT 24
Peak memory 241904 kb
Host smart-05851e4f-a9b8-4e96-9bf5-0700585c2b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799937610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2799937610
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.934152074
Short name T731
Test name
Test status
Simulation time 223167104 ps
CPU time 5.47 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:25 PM PDT 24
Peak memory 241892 kb
Host smart-2acd456c-282a-40f2-9e81-c54a71b91550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934152074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.934152074
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.600374382
Short name T1137
Test name
Test status
Simulation time 2180464750 ps
CPU time 7.24 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 242028 kb
Host smart-c975869b-c3ab-4ff3-97ff-645a70fdfc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600374382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.600374382
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.454253617
Short name T1123
Test name
Test status
Simulation time 698952572 ps
CPU time 9.08 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:39 PM PDT 24
Peak memory 242076 kb
Host smart-b312d52a-46a2-4b2d-bf30-c54ec4e48a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454253617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.454253617
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.2690213043
Short name T837
Test name
Test status
Simulation time 1804416546 ps
CPU time 6.01 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 242288 kb
Host smart-b7a90cc0-edd8-444a-98cc-cfa19d855c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690213043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2690213043
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1309502677
Short name T838
Test name
Test status
Simulation time 527581403 ps
CPU time 9.12 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 241900 kb
Host smart-8ea93b40-a236-4faa-8649-28c09dd2de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309502677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1309502677
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3425956678
Short name T881
Test name
Test status
Simulation time 216757686 ps
CPU time 3.52 seconds
Started Jul 29 07:48:21 PM PDT 24
Finished Jul 29 07:48:25 PM PDT 24
Peak memory 242056 kb
Host smart-56ef8a9b-0eea-4441-a6a5-bb315ca6c734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425956678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3425956678
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.2715389953
Short name T1041
Test name
Test status
Simulation time 353477050 ps
CPU time 5.49 seconds
Started Jul 29 07:48:22 PM PDT 24
Finished Jul 29 07:48:28 PM PDT 24
Peak memory 242240 kb
Host smart-75d3460f-c47b-4463-91d0-a3dc23437fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715389953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2715389953
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.209263518
Short name T566
Test name
Test status
Simulation time 328819374 ps
CPU time 3.77 seconds
Started Jul 29 07:48:32 PM PDT 24
Finished Jul 29 07:48:36 PM PDT 24
Peak memory 242272 kb
Host smart-d335f8b4-9807-4273-aaed-4e89b520a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209263518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.209263518
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.1902902867
Short name T620
Test name
Test status
Simulation time 254820255 ps
CPU time 2.67 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:21 PM PDT 24
Peak memory 242360 kb
Host smart-6cc7efc2-4cea-4929-a3b5-8a230e74345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902902867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1902902867
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.1381608370
Short name T483
Test name
Test status
Simulation time 2007357048 ps
CPU time 4.37 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 241984 kb
Host smart-8c730a35-f8c9-410a-8078-a5587706918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381608370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1381608370
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.124824306
Short name T1038
Test name
Test status
Simulation time 4150982299 ps
CPU time 9.32 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:39 PM PDT 24
Peak memory 242148 kb
Host smart-56117e59-fceb-4c9b-985a-344b375bb600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124824306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.124824306
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.267173887
Short name T965
Test name
Test status
Simulation time 445688595 ps
CPU time 4.82 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:35 PM PDT 24
Peak memory 241996 kb
Host smart-386b522e-2dab-4775-8821-6c50158c6354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267173887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.267173887
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.998286416
Short name T790
Test name
Test status
Simulation time 357728140 ps
CPU time 8.96 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242144 kb
Host smart-0eaced10-3f46-43a8-9aa0-b8bf4123124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998286416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.998286416
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2064769635
Short name T262
Test name
Test status
Simulation time 2365975214 ps
CPU time 21.97 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:53 PM PDT 24
Peak memory 242016 kb
Host smart-3612a121-caeb-4608-9634-c38a6eb62051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064769635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2064769635
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.625375785
Short name T987
Test name
Test status
Simulation time 124593916 ps
CPU time 2.08 seconds
Started Jul 29 07:41:37 PM PDT 24
Finished Jul 29 07:41:39 PM PDT 24
Peak memory 240388 kb
Host smart-eff13782-64d9-4d19-aaa4-b41ce61a7a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625375785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.625375785
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.546328790
Short name T1075
Test name
Test status
Simulation time 7226634642 ps
CPU time 22.26 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:56 PM PDT 24
Peak memory 244156 kb
Host smart-3b9a4145-c7e1-4f85-8ea4-9542ad55b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546328790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.546328790
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.4156062360
Short name T87
Test name
Test status
Simulation time 745128420 ps
CPU time 25.57 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:59 PM PDT 24
Peak memory 242624 kb
Host smart-3d8a27fd-2e46-428c-bdb7-1a34ad6c8b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156062360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.4156062360
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.621592014
Short name T1147
Test name
Test status
Simulation time 6965756153 ps
CPU time 30.54 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:42:03 PM PDT 24
Peak memory 242804 kb
Host smart-86f8b70f-8fd6-4215-b1b3-017894ef8479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621592014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.621592014
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.4222748761
Short name T32
Test name
Test status
Simulation time 1799189157 ps
CPU time 5.74 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:40 PM PDT 24
Peak memory 242008 kb
Host smart-10f4daab-0a1e-4328-bb61-642e055622d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222748761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.4222748761
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.205991932
Short name T610
Test name
Test status
Simulation time 1926869149 ps
CPU time 21.4 seconds
Started Jul 29 07:41:35 PM PDT 24
Finished Jul 29 07:41:57 PM PDT 24
Peak memory 244344 kb
Host smart-07747fcc-6422-429d-8b7f-eab9f6b0bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205991932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.205991932
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3516227673
Short name T92
Test name
Test status
Simulation time 181166621 ps
CPU time 4.24 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:41:37 PM PDT 24
Peak memory 242384 kb
Host smart-67fb8220-4531-4a3d-a149-6cc4812d416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516227673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3516227673
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1374337695
Short name T1040
Test name
Test status
Simulation time 739325942 ps
CPU time 12.74 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 242484 kb
Host smart-1ccee168-63ab-4cc9-a73c-e100c5129ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374337695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1374337695
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.609539380
Short name T325
Test name
Test status
Simulation time 160485595 ps
CPU time 5.03 seconds
Started Jul 29 07:41:37 PM PDT 24
Finished Jul 29 07:41:42 PM PDT 24
Peak memory 242052 kb
Host smart-71ffb6b1-bf2c-4a2a-8c59-f76279990b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609539380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.609539380
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.4040138610
Short name T568
Test name
Test status
Simulation time 2253500491 ps
CPU time 7.7 seconds
Started Jul 29 07:41:33 PM PDT 24
Finished Jul 29 07:41:41 PM PDT 24
Peak memory 242040 kb
Host smart-22f67022-e18e-4bed-8ebf-e23a82becc01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040138610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.4040138610
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.2891175023
Short name T1030
Test name
Test status
Simulation time 3765617156 ps
CPU time 11.65 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 242244 kb
Host smart-a8a1e30f-ecaf-4613-a46e-cf2888a45d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891175023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2891175023
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.2185167871
Short name T569
Test name
Test status
Simulation time 57437075350 ps
CPU time 697.48 seconds
Started Jul 29 07:41:33 PM PDT 24
Finished Jul 29 07:53:11 PM PDT 24
Peak memory 265232 kb
Host smart-dcd2f4a1-8aef-4630-8330-2bed0e7c5baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185167871 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.2185167871
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3185095837
Short name T283
Test name
Test status
Simulation time 4284768317 ps
CPU time 25.53 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:59 PM PDT 24
Peak memory 241996 kb
Host smart-27fea5bf-cf4b-4a7c-9220-554fc2cb7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185095837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3185095837
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2746681306
Short name T668
Test name
Test status
Simulation time 381177299 ps
CPU time 3.97 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 242236 kb
Host smart-07e36984-605a-4b46-b7a1-8b30a99f39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746681306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2746681306
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2931626824
Short name T990
Test name
Test status
Simulation time 113611859 ps
CPU time 4.72 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:25 PM PDT 24
Peak memory 242344 kb
Host smart-aacc9d89-e2f4-4bfe-954e-00c0b895210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931626824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2931626824
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.1237429963
Short name T56
Test name
Test status
Simulation time 221640067 ps
CPU time 4.3 seconds
Started Jul 29 07:48:25 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242232 kb
Host smart-9941fbbd-b0d0-44f8-9002-95ac53002b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237429963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1237429963
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.2099130358
Short name T104
Test name
Test status
Simulation time 326644673 ps
CPU time 9.45 seconds
Started Jul 29 07:48:25 PM PDT 24
Finished Jul 29 07:48:35 PM PDT 24
Peak memory 242012 kb
Host smart-177cdd65-09aa-4be5-ad2e-c0cb78560d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099130358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.2099130358
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.896185476
Short name T187
Test name
Test status
Simulation time 1678449010 ps
CPU time 5.19 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:36 PM PDT 24
Peak memory 242372 kb
Host smart-6f199648-d23a-43da-b177-a30a63faa267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896185476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.896185476
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.566181458
Short name T877
Test name
Test status
Simulation time 260523588 ps
CPU time 7.64 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 242244 kb
Host smart-9b73cdc6-1fad-45a7-b39e-c3e7680f7415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566181458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.566181458
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.1664777837
Short name T605
Test name
Test status
Simulation time 300667834 ps
CPU time 4.5 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:25 PM PDT 24
Peak memory 242004 kb
Host smart-a4888372-7afb-4e7b-8bb6-6568a367de77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664777837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1664777837
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.556730272
Short name T682
Test name
Test status
Simulation time 386282333 ps
CPU time 9.64 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242428 kb
Host smart-a072a8ce-929f-4598-97d9-88cdfb0e42f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556730272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.556730272
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.3180524215
Short name T578
Test name
Test status
Simulation time 104785614 ps
CPU time 4.13 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242240 kb
Host smart-9adad99a-ab9c-4f9e-9b87-19f4db32540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180524215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3180524215
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2213467829
Short name T450
Test name
Test status
Simulation time 495445494 ps
CPU time 13.08 seconds
Started Jul 29 07:48:22 PM PDT 24
Finished Jul 29 07:48:36 PM PDT 24
Peak memory 242060 kb
Host smart-2cf5b7c7-6fba-49d2-a449-eb7ee1199d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213467829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2213467829
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2795634512
Short name T489
Test name
Test status
Simulation time 1889926304 ps
CPU time 5.97 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:36 PM PDT 24
Peak memory 242256 kb
Host smart-a54e0233-d703-4886-9569-9f375435599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795634512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2795634512
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2636252512
Short name T330
Test name
Test status
Simulation time 3843606326 ps
CPU time 18.47 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 241900 kb
Host smart-ac522725-0b43-4496-a43c-2f423fa69508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636252512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2636252512
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.848198346
Short name T590
Test name
Test status
Simulation time 139503710 ps
CPU time 3.39 seconds
Started Jul 29 07:48:32 PM PDT 24
Finished Jul 29 07:48:35 PM PDT 24
Peak memory 242272 kb
Host smart-3ab66e5e-75f6-4a9f-a5cd-2f6f53c46c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848198346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.848198346
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.3024596197
Short name T254
Test name
Test status
Simulation time 337215094 ps
CPU time 8.89 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:28 PM PDT 24
Peak memory 241892 kb
Host smart-283b69be-5612-4439-836b-98c4dcf2af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024596197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.3024596197
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.1494409252
Short name T957
Test name
Test status
Simulation time 1776718464 ps
CPU time 4.3 seconds
Started Jul 29 07:48:21 PM PDT 24
Finished Jul 29 07:48:26 PM PDT 24
Peak memory 241960 kb
Host smart-1fc27b8c-bc8e-4ed2-9ba4-640b34ce3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494409252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1494409252
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.107090353
Short name T1132
Test name
Test status
Simulation time 1929330954 ps
CPU time 5.79 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:26 PM PDT 24
Peak memory 242144 kb
Host smart-f612e7f1-b51f-452e-8048-3c29c63502e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107090353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.107090353
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2559603032
Short name T451
Test name
Test status
Simulation time 403760857 ps
CPU time 11.88 seconds
Started Jul 29 07:48:22 PM PDT 24
Finished Jul 29 07:48:34 PM PDT 24
Peak memory 241980 kb
Host smart-431772dc-878c-43c6-a457-1736ee7eab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559603032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2559603032
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2772925493
Short name T650
Test name
Test status
Simulation time 153527045 ps
CPU time 3.29 seconds
Started Jul 29 07:48:20 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242024 kb
Host smart-b43c24aa-a29c-4c50-ad82-958e8f4ccb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772925493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2772925493
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1667722074
Short name T207
Test name
Test status
Simulation time 207792157 ps
CPU time 11 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 241972 kb
Host smart-8de7900f-00ba-4d51-b55e-8f044debb928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667722074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1667722074
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.2644887571
Short name T236
Test name
Test status
Simulation time 54543476 ps
CPU time 1.84 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:43 PM PDT 24
Peak memory 240372 kb
Host smart-945fb57a-373d-4986-94d0-2d54d0280a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644887571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2644887571
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.641710123
Short name T125
Test name
Test status
Simulation time 213734097 ps
CPU time 5.99 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:48 PM PDT 24
Peak memory 248732 kb
Host smart-7df2fa28-8087-406e-813a-57d88d82d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641710123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.641710123
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.857099177
Short name T908
Test name
Test status
Simulation time 788396644 ps
CPU time 21.66 seconds
Started Jul 29 07:41:37 PM PDT 24
Finished Jul 29 07:41:59 PM PDT 24
Peak memory 241948 kb
Host smart-3de1068d-dddb-4e42-bfc6-ec7bf11b3756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857099177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.857099177
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2991664553
Short name T775
Test name
Test status
Simulation time 7896077015 ps
CPU time 11.84 seconds
Started Jul 29 07:41:34 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 242900 kb
Host smart-9e1f83ba-b510-4f02-aff1-e2dec5b9780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991664553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2991664553
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.643335058
Short name T732
Test name
Test status
Simulation time 2088047760 ps
CPU time 7.35 seconds
Started Jul 29 07:41:33 PM PDT 24
Finished Jul 29 07:41:41 PM PDT 24
Peak memory 241996 kb
Host smart-802d6d2d-9c6c-477e-bcb4-d88d7f1347de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643335058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.643335058
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1267965151
Short name T155
Test name
Test status
Simulation time 1706092065 ps
CPU time 22.74 seconds
Started Jul 29 07:41:44 PM PDT 24
Finished Jul 29 07:42:07 PM PDT 24
Peak memory 248564 kb
Host smart-4820e757-a89b-44ce-8d36-3626ce59285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267965151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1267965151
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.818912746
Short name T786
Test name
Test status
Simulation time 7443807100 ps
CPU time 19.16 seconds
Started Jul 29 07:41:43 PM PDT 24
Finished Jul 29 07:42:02 PM PDT 24
Peak memory 242124 kb
Host smart-06fdfe6e-289a-40b1-a141-18fb7f27f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818912746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.818912746
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.901281991
Short name T1139
Test name
Test status
Simulation time 407532643 ps
CPU time 6.96 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:41:39 PM PDT 24
Peak memory 242236 kb
Host smart-061c04ed-d460-4a79-bb7b-4c42441be272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901281991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.901281991
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2189556680
Short name T591
Test name
Test status
Simulation time 409852271 ps
CPU time 7.48 seconds
Started Jul 29 07:41:33 PM PDT 24
Finished Jul 29 07:41:41 PM PDT 24
Peak memory 241916 kb
Host smart-6f706487-2d55-4438-911b-f86fbd728bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189556680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2189556680
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.1800008943
Short name T359
Test name
Test status
Simulation time 4023005638 ps
CPU time 13.62 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:55 PM PDT 24
Peak memory 242608 kb
Host smart-d75886ef-c6e4-4304-8a8b-25ad7a79257d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800008943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1800008943
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.2024028639
Short name T765
Test name
Test status
Simulation time 127724501 ps
CPU time 3.66 seconds
Started Jul 29 07:41:32 PM PDT 24
Finished Jul 29 07:41:36 PM PDT 24
Peak memory 248628 kb
Host smart-13fdb5f3-63c5-4160-ad51-6ebbdb2c64e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024028639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2024028639
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1863809350
Short name T529
Test name
Test status
Simulation time 10133833541 ps
CPU time 79.14 seconds
Started Jul 29 07:41:40 PM PDT 24
Finished Jul 29 07:42:59 PM PDT 24
Peak memory 247368 kb
Host smart-f8107560-468d-47b0-ba06-8bc177021f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863809350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1863809350
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.3921175105
Short name T449
Test name
Test status
Simulation time 354444873 ps
CPU time 4.53 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 242224 kb
Host smart-3b4a2aea-153b-4990-aa1b-690b95c93342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921175105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3921175105
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.298714628
Short name T454
Test name
Test status
Simulation time 92034593 ps
CPU time 3.32 seconds
Started Jul 29 07:48:25 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242064 kb
Host smart-550486b8-76f5-470c-960b-601c843aaa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298714628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.298714628
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.4051004953
Short name T623
Test name
Test status
Simulation time 8014724038 ps
CPU time 25.8 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:56 PM PDT 24
Peak memory 242096 kb
Host smart-0f9a8a44-c7c2-49dd-a01c-b2ec7e63776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051004953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.4051004953
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.4217121772
Short name T608
Test name
Test status
Simulation time 485966753 ps
CPU time 13.7 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:43 PM PDT 24
Peak memory 242412 kb
Host smart-c0c55d8c-ea6e-4687-8be5-f74a31fef654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217121772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.4217121772
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3528113495
Short name T638
Test name
Test status
Simulation time 140824587 ps
CPU time 4.05 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:34 PM PDT 24
Peak memory 242340 kb
Host smart-caaadb3b-88f3-4934-a178-264a14d7d83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528113495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3528113495
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1348658810
Short name T780
Test name
Test status
Simulation time 194198646 ps
CPU time 4.95 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 241936 kb
Host smart-13a7c9bd-df34-49ed-9ada-95e605b72fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348658810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1348658810
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2349679522
Short name T644
Test name
Test status
Simulation time 2442328017 ps
CPU time 7.54 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241992 kb
Host smart-7d48efa0-5da1-4af2-9ce9-9e8bf18824f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349679522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2349679522
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.2242510643
Short name T197
Test name
Test status
Simulation time 5368391593 ps
CPU time 12.84 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 242020 kb
Host smart-97c8f305-98e3-443f-8912-649d98511830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242510643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2242510643
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.2210309
Short name T954
Test name
Test status
Simulation time 109157347 ps
CPU time 3.73 seconds
Started Jul 29 07:48:22 PM PDT 24
Finished Jul 29 07:48:25 PM PDT 24
Peak memory 241988 kb
Host smart-4bea4962-c4a4-45f6-9f0b-1a3cb2b09e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2210309
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.819485931
Short name T169
Test name
Test status
Simulation time 599412333 ps
CPU time 5.5 seconds
Started Jul 29 07:48:30 PM PDT 24
Finished Jul 29 07:48:35 PM PDT 24
Peak memory 247324 kb
Host smart-5aac44fe-968d-4199-9056-e110ce1d2367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819485931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.819485931
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.4163516856
Short name T611
Test name
Test status
Simulation time 110744862 ps
CPU time 3.11 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 241860 kb
Host smart-913c663d-6c93-43ae-9280-ea7f302534a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163516856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.4163516856
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.2243351618
Short name T1186
Test name
Test status
Simulation time 453205383 ps
CPU time 4.78 seconds
Started Jul 29 07:48:27 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 241900 kb
Host smart-4de2aec3-58b8-491d-9c2f-d38f16fe7185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243351618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2243351618
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2399983720
Short name T729
Test name
Test status
Simulation time 116456393 ps
CPU time 4.11 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:34 PM PDT 24
Peak memory 242460 kb
Host smart-7677389d-ecc9-4cff-8349-a2d93932dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399983720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2399983720
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.294171562
Short name T1166
Test name
Test status
Simulation time 250450094 ps
CPU time 6.16 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 242012 kb
Host smart-8ec113d1-a449-4d94-a489-38df5608c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294171562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.294171562
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.1982243695
Short name T424
Test name
Test status
Simulation time 168747596 ps
CPU time 4.54 seconds
Started Jul 29 07:48:29 PM PDT 24
Finished Jul 29 07:48:34 PM PDT 24
Peak memory 242092 kb
Host smart-b4cc3d09-5120-4c5d-bc69-3517a69834db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982243695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1982243695
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.3563687551
Short name T846
Test name
Test status
Simulation time 418683031 ps
CPU time 8.69 seconds
Started Jul 29 07:48:33 PM PDT 24
Finished Jul 29 07:48:42 PM PDT 24
Peak memory 242072 kb
Host smart-0d3824cc-0abb-4e04-8eb7-f08785b6260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563687551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3563687551
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.4135003284
Short name T445
Test name
Test status
Simulation time 148937535 ps
CPU time 4.88 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:42 PM PDT 24
Peak memory 242148 kb
Host smart-7b132556-6c04-43e6-9f1b-5deec4102c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135003284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.4135003284
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.1397172059
Short name T1194
Test name
Test status
Simulation time 206834517 ps
CPU time 6.15 seconds
Started Jul 29 07:48:32 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241960 kb
Host smart-28674caa-a4e6-4b22-8b7e-05753bcd846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397172059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1397172059
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3399018069
Short name T1032
Test name
Test status
Simulation time 111699958 ps
CPU time 3.93 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 242392 kb
Host smart-8927feb7-f1a1-4865-958e-19dbabadc495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399018069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3399018069
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1620047658
Short name T865
Test name
Test status
Simulation time 1023560475 ps
CPU time 10.39 seconds
Started Jul 29 07:48:35 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 242436 kb
Host smart-a62085d5-c456-4a1f-bf7e-aaf37dca2e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620047658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1620047658
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2129849409
Short name T409
Test name
Test status
Simulation time 812308900 ps
CPU time 2.34 seconds
Started Jul 29 07:41:44 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 240680 kb
Host smart-c923b112-cc43-4a4f-bb87-3c57e33d9bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129849409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2129849409
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.4016467802
Short name T239
Test name
Test status
Simulation time 2099519833 ps
CPU time 14.54 seconds
Started Jul 29 07:41:43 PM PDT 24
Finished Jul 29 07:41:58 PM PDT 24
Peak memory 248592 kb
Host smart-63fefa0e-9d7d-4c4d-9511-aebc5266ebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016467802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.4016467802
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.4254647338
Short name T1074
Test name
Test status
Simulation time 2672914278 ps
CPU time 41.81 seconds
Started Jul 29 07:41:42 PM PDT 24
Finished Jul 29 07:42:24 PM PDT 24
Peak memory 251656 kb
Host smart-c4c18666-94bf-4d0b-afcd-fab4da535300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254647338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.4254647338
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.473021728
Short name T100
Test name
Test status
Simulation time 11656458434 ps
CPU time 21.99 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:42:03 PM PDT 24
Peak memory 243128 kb
Host smart-b37ee310-5362-426b-9350-62b1f0bca65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473021728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.473021728
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.2631476529
Short name T523
Test name
Test status
Simulation time 130824907 ps
CPU time 3.6 seconds
Started Jul 29 07:41:40 PM PDT 24
Finished Jul 29 07:41:44 PM PDT 24
Peak memory 241972 kb
Host smart-4ed0aac3-1ada-4e82-860e-07d08481b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631476529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2631476529
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.2567752300
Short name T897
Test name
Test status
Simulation time 3379181887 ps
CPU time 42.02 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:42:23 PM PDT 24
Peak memory 264460 kb
Host smart-306d64c3-cb44-475d-9432-f0eb1385d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567752300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.2567752300
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.2077689354
Short name T622
Test name
Test status
Simulation time 938675787 ps
CPU time 14.52 seconds
Started Jul 29 07:41:40 PM PDT 24
Finished Jul 29 07:41:55 PM PDT 24
Peak memory 242408 kb
Host smart-3c9286a2-e019-4091-8032-4b86053bec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077689354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2077689354
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.1800739173
Short name T1126
Test name
Test status
Simulation time 322229718 ps
CPU time 4.9 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 242004 kb
Host smart-3b35a660-f95e-401f-a963-8d5e890f4ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800739173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1800739173
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.1281338473
Short name T1035
Test name
Test status
Simulation time 392377281 ps
CPU time 5.48 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:47 PM PDT 24
Peak memory 248676 kb
Host smart-d75eb4de-f968-4c3b-8d35-d2e4dea72ca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281338473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1281338473
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.1263287791
Short name T408
Test name
Test status
Simulation time 171987665 ps
CPU time 3.75 seconds
Started Jul 29 07:41:42 PM PDT 24
Finished Jul 29 07:41:46 PM PDT 24
Peak memory 241944 kb
Host smart-8414f0e8-1a02-4a41-8bf3-9b4cb197ad5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263287791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1263287791
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3715081823
Short name T233
Test name
Test status
Simulation time 257591450 ps
CPU time 8.27 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:49 PM PDT 24
Peak memory 241916 kb
Host smart-7bfd14e8-8fcc-4e27-a297-47e4692940c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715081823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3715081823
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.1443903787
Short name T628
Test name
Test status
Simulation time 23843139918 ps
CPU time 69.94 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 256920 kb
Host smart-edc4ca56-b186-4d44-ba0c-5971a70a5260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443903787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.1443903787
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3712758422
Short name T676
Test name
Test status
Simulation time 3854829169 ps
CPU time 19.99 seconds
Started Jul 29 07:41:40 PM PDT 24
Finished Jul 29 07:42:00 PM PDT 24
Peak memory 242140 kb
Host smart-98da2c8e-43fa-4eb2-a137-60718649b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712758422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3712758422
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.901619604
Short name T1028
Test name
Test status
Simulation time 1614430315 ps
CPU time 5.44 seconds
Started Jul 29 07:48:40 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 242252 kb
Host smart-83ca2512-0adc-4410-93f7-e85a86ee0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901619604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.901619604
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.224479869
Short name T264
Test name
Test status
Simulation time 127675064 ps
CPU time 4.68 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:39 PM PDT 24
Peak memory 241968 kb
Host smart-5fbd1c51-08b2-4b70-9107-98dc49e1433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224479869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.224479869
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.2882160069
Short name T810
Test name
Test status
Simulation time 580941344 ps
CPU time 5.23 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 242140 kb
Host smart-418b63e9-d8be-4595-8772-091af6a28d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882160069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2882160069
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2357073236
Short name T934
Test name
Test status
Simulation time 433386732 ps
CPU time 4.52 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242008 kb
Host smart-11605b16-80cb-432a-8bd3-a1ab0254e17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357073236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2357073236
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.3323702949
Short name T853
Test name
Test status
Simulation time 154924910 ps
CPU time 3.89 seconds
Started Jul 29 07:48:39 PM PDT 24
Finished Jul 29 07:48:43 PM PDT 24
Peak memory 242152 kb
Host smart-d1d39ab1-56cb-4d7f-bdec-5b11c059049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323702949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3323702949
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.3291490103
Short name T705
Test name
Test status
Simulation time 6041602628 ps
CPU time 14.62 seconds
Started Jul 29 07:48:33 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242268 kb
Host smart-28a72bdc-a5ce-449d-945f-3d902009e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291490103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3291490103
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.512173430
Short name T850
Test name
Test status
Simulation time 4043018117 ps
CPU time 18.51 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:52 PM PDT 24
Peak memory 241956 kb
Host smart-b2afdfe7-a48d-4a6c-9a10-dc2e2d12c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512173430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.512173430
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2376955303
Short name T190
Test name
Test status
Simulation time 558043511 ps
CPU time 3.62 seconds
Started Jul 29 07:48:41 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 241968 kb
Host smart-845868a2-21ef-4e36-8f4a-49e7421652dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376955303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2376955303
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2357251176
Short name T711
Test name
Test status
Simulation time 3677020479 ps
CPU time 14.23 seconds
Started Jul 29 07:48:33 PM PDT 24
Finished Jul 29 07:48:47 PM PDT 24
Peak memory 242088 kb
Host smart-5e18c55b-a27d-4568-8907-1bda23c53556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357251176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2357251176
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2939148213
Short name T53
Test name
Test status
Simulation time 264609667 ps
CPU time 4.45 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 242080 kb
Host smart-4d148a2d-d8ab-47ff-b29e-70986a795212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939148213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2939148213
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3173511527
Short name T797
Test name
Test status
Simulation time 461438871 ps
CPU time 5.81 seconds
Started Jul 29 07:48:32 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 242252 kb
Host smart-7ac96de3-3d9c-44f2-a31d-094155db712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173511527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3173511527
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1588394962
Short name T515
Test name
Test status
Simulation time 106877988 ps
CPU time 2.8 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242444 kb
Host smart-df4e9e23-4ff7-4805-b714-adace1066155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588394962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1588394962
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2998822287
Short name T1179
Test name
Test status
Simulation time 194409020 ps
CPU time 5.55 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242356 kb
Host smart-cff333f5-0f10-4f33-b082-d789d77856be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998822287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2998822287
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.4106382437
Short name T36
Test name
Test status
Simulation time 577126124 ps
CPU time 4.25 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242384 kb
Host smart-3c8e170c-ff3c-4ffa-b5cd-946e8e8112e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106382437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.4106382437
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.53209722
Short name T8
Test name
Test status
Simulation time 534353928 ps
CPU time 6.01 seconds
Started Jul 29 07:48:31 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 242508 kb
Host smart-dcb6b664-721c-4cd7-b54a-72942f3d443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53209722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.53209722
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.4026592936
Short name T50
Test name
Test status
Simulation time 129082434 ps
CPU time 3.54 seconds
Started Jul 29 07:48:33 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 242400 kb
Host smart-828c4452-0e07-4221-bec1-6a76ee3fa348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026592936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.4026592936
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.2528738000
Short name T1069
Test name
Test status
Simulation time 242173033 ps
CPU time 4.73 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 241876 kb
Host smart-4753fc39-3a39-4d73-a00c-b842023f6a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528738000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2528738000
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1690799189
Short name T222
Test name
Test status
Simulation time 170474815 ps
CPU time 3.87 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 242116 kb
Host smart-1f564480-620b-41e6-9f93-0185d62aa960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690799189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1690799189
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.988928494
Short name T675
Test name
Test status
Simulation time 169830719 ps
CPU time 7.3 seconds
Started Jul 29 07:48:35 PM PDT 24
Finished Jul 29 07:48:43 PM PDT 24
Peak memory 242372 kb
Host smart-c387979a-0438-40ed-88ca-b77be40f2f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988928494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.988928494
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3014578972
Short name T657
Test name
Test status
Simulation time 177032919 ps
CPU time 1.87 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:41:55 PM PDT 24
Peak memory 240716 kb
Host smart-660ead19-8444-4358-b259-560e224ccf48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014578972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3014578972
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.821063421
Short name T118
Test name
Test status
Simulation time 669464758 ps
CPU time 8.8 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:42:01 PM PDT 24
Peak memory 248668 kb
Host smart-073c67ab-a609-4c8f-b35b-ea5069fd8366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821063421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.821063421
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.3550030533
Short name T333
Test name
Test status
Simulation time 1405010626 ps
CPU time 17.29 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:42:10 PM PDT 24
Peak memory 241976 kb
Host smart-d172afee-168f-48b0-80e8-a0af930e2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550030533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3550030533
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.508315083
Short name T1054
Test name
Test status
Simulation time 654311266 ps
CPU time 4.68 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:41:58 PM PDT 24
Peak memory 242360 kb
Host smart-44d1a75d-5e0f-4a1e-9a02-9b8b6be2a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508315083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.508315083
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.4097584569
Short name T586
Test name
Test status
Simulation time 139245189 ps
CPU time 3.71 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:41:56 PM PDT 24
Peak memory 242220 kb
Host smart-5e5149c2-73f5-4d95-9f85-2ef09e459509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097584569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.4097584569
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.3887112529
Short name T1044
Test name
Test status
Simulation time 719599463 ps
CPU time 9.46 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:42:01 PM PDT 24
Peak memory 242216 kb
Host smart-b0fcb497-d359-4be4-a157-02e10cf58e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887112529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3887112529
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.1566504014
Short name T854
Test name
Test status
Simulation time 125518604 ps
CPU time 4.95 seconds
Started Jul 29 07:41:55 PM PDT 24
Finished Jul 29 07:42:00 PM PDT 24
Peak memory 242024 kb
Host smart-eedefbc3-7b61-48fc-812b-376343c40a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566504014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.1566504014
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3988051665
Short name T370
Test name
Test status
Simulation time 980154274 ps
CPU time 17.52 seconds
Started Jul 29 07:41:54 PM PDT 24
Finished Jul 29 07:42:11 PM PDT 24
Peak memory 242080 kb
Host smart-8da59da3-cd25-476b-aefc-a8aa1a8efd00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988051665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3988051665
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.4117742487
Short name T502
Test name
Test status
Simulation time 115319150 ps
CPU time 4.49 seconds
Started Jul 29 07:41:51 PM PDT 24
Finished Jul 29 07:41:56 PM PDT 24
Peak memory 241984 kb
Host smart-2dce531a-f068-426b-ba4d-2a10046de399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117742487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.4117742487
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2745994466
Short name T498
Test name
Test status
Simulation time 928287637 ps
CPU time 6.81 seconds
Started Jul 29 07:41:41 PM PDT 24
Finished Jul 29 07:41:47 PM PDT 24
Peak memory 241916 kb
Host smart-af95d29a-0d22-43d5-803f-efa33a420a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745994466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2745994466
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3945124007
Short name T227
Test name
Test status
Simulation time 78774056387 ps
CPU time 708.58 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:53:41 PM PDT 24
Peak memory 391892 kb
Host smart-c753f5dc-18e0-4990-872f-2b50872afd38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945124007 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.3945124007
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.1948649985
Short name T619
Test name
Test status
Simulation time 2203134160 ps
CPU time 18.88 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:42:11 PM PDT 24
Peak memory 242180 kb
Host smart-d64d0e76-8092-49c6-be13-cde8874a6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948649985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.1948649985
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.4199176542
Short name T126
Test name
Test status
Simulation time 126614578 ps
CPU time 3.64 seconds
Started Jul 29 07:48:35 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241952 kb
Host smart-6a02f3d6-b2b5-4015-8434-84110a1de219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199176542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4199176542
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2606844626
Short name T1171
Test name
Test status
Simulation time 212478768 ps
CPU time 4.1 seconds
Started Jul 29 07:48:28 PM PDT 24
Finished Jul 29 07:48:32 PM PDT 24
Peak memory 241896 kb
Host smart-db908f4b-1f81-4719-b035-b0b3b660483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606844626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2606844626
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3011602050
Short name T727
Test name
Test status
Simulation time 194089938 ps
CPU time 4 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 242084 kb
Host smart-a83c7135-374f-4958-b5b2-0d985701bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011602050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3011602050
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.2943085242
Short name T809
Test name
Test status
Simulation time 249771701 ps
CPU time 14.21 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:51 PM PDT 24
Peak memory 241948 kb
Host smart-42f43043-b82d-4e16-9ff0-8b9cfa8a29cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943085242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2943085242
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.4097798011
Short name T54
Test name
Test status
Simulation time 463289328 ps
CPU time 5.38 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 242124 kb
Host smart-6c2a54c6-245e-440b-b251-88d5ab8f53d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097798011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.4097798011
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3101105542
Short name T577
Test name
Test status
Simulation time 920835675 ps
CPU time 12.78 seconds
Started Jul 29 07:48:32 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 242224 kb
Host smart-486c0d9a-e0f7-4b19-9d82-fe89613bcbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101105542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3101105542
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.1363322396
Short name T983
Test name
Test status
Simulation time 309204383 ps
CPU time 4.46 seconds
Started Jul 29 07:48:33 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241960 kb
Host smart-68d87b85-e765-418e-8514-6c50ad0acd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363322396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1363322396
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.1207495718
Short name T651
Test name
Test status
Simulation time 797921325 ps
CPU time 4.74 seconds
Started Jul 29 07:48:40 PM PDT 24
Finished Jul 29 07:48:44 PM PDT 24
Peak memory 242040 kb
Host smart-9d4ad667-902a-4725-8043-1fd36833edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207495718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1207495718
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1116636030
Short name T175
Test name
Test status
Simulation time 800385791 ps
CPU time 10.63 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242220 kb
Host smart-51b142de-1986-4dc5-adf3-5b3358a50298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116636030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1116636030
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.1271100944
Short name T552
Test name
Test status
Simulation time 220918053 ps
CPU time 3.2 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241924 kb
Host smart-a58cbc8b-0767-4773-8473-1709ce81fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271100944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1271100944
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.4281703652
Short name T329
Test name
Test status
Simulation time 110395232 ps
CPU time 3.34 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 241948 kb
Host smart-873cbca4-598e-4014-9cad-d609d9223864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281703652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.4281703652
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3759935161
Short name T168
Test name
Test status
Simulation time 501253749 ps
CPU time 4.41 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 242428 kb
Host smart-7c704371-2adf-452e-bcc5-998a48d9e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759935161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3759935161
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.1189581458
Short name T690
Test name
Test status
Simulation time 123924028 ps
CPU time 4.03 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241980 kb
Host smart-fb875c19-0785-4fbf-9c06-8a6c666468c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189581458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1189581458
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3189696824
Short name T1134
Test name
Test status
Simulation time 169996190 ps
CPU time 4.21 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 242104 kb
Host smart-3d5e6967-8a71-41ce-bc3a-c1f1b45a6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189696824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3189696824
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.122893171
Short name T1087
Test name
Test status
Simulation time 319768965 ps
CPU time 7.92 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:42 PM PDT 24
Peak memory 241972 kb
Host smart-24c2de24-5cf3-4cbc-a352-4413c8915e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122893171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.122893171
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1868014176
Short name T1133
Test name
Test status
Simulation time 263468706 ps
CPU time 4.15 seconds
Started Jul 29 07:48:33 PM PDT 24
Finished Jul 29 07:48:38 PM PDT 24
Peak memory 241980 kb
Host smart-9186d8d6-ad25-4ad5-8708-11f96f435310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868014176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1868014176
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3402778236
Short name T892
Test name
Test status
Simulation time 117176619 ps
CPU time 4.38 seconds
Started Jul 29 07:48:36 PM PDT 24
Finished Jul 29 07:48:40 PM PDT 24
Peak memory 242440 kb
Host smart-3b48039c-bb78-4d9c-a036-c3926088f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402778236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3402778236
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.195784567
Short name T661
Test name
Test status
Simulation time 211455131 ps
CPU time 4.26 seconds
Started Jul 29 07:48:34 PM PDT 24
Finished Jul 29 07:48:39 PM PDT 24
Peak memory 242164 kb
Host smart-d54e933a-2e67-4d43-a22a-8674fc7a6d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195784567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.195784567
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1399839510
Short name T1003
Test name
Test status
Simulation time 7888707885 ps
CPU time 16.24 seconds
Started Jul 29 07:48:32 PM PDT 24
Finished Jul 29 07:48:49 PM PDT 24
Peak memory 242432 kb
Host smart-04b4080a-c409-47d3-a6d4-77785079a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399839510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1399839510
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.3991924275
Short name T873
Test name
Test status
Simulation time 96945025 ps
CPU time 1.93 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:41:55 PM PDT 24
Peak memory 240652 kb
Host smart-4c360cb6-3187-4e9e-85b8-1b06e83e1df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991924275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3991924275
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.2326252589
Short name T52
Test name
Test status
Simulation time 357509969 ps
CPU time 7.32 seconds
Started Jul 29 07:41:54 PM PDT 24
Finished Jul 29 07:42:01 PM PDT 24
Peak memory 242352 kb
Host smart-35e707ee-fcd4-4525-ab30-95448f3f8d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326252589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2326252589
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1469208110
Short name T161
Test name
Test status
Simulation time 4316102049 ps
CPU time 30.09 seconds
Started Jul 29 07:41:54 PM PDT 24
Finished Jul 29 07:42:24 PM PDT 24
Peak memory 243048 kb
Host smart-fdfac7d2-cc41-4f9e-be3a-d2184495b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469208110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1469208110
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.277897762
Short name T1051
Test name
Test status
Simulation time 829766891 ps
CPU time 18.94 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:42:11 PM PDT 24
Peak memory 248572 kb
Host smart-211b08dc-c511-4c36-bcc9-2fb5af9098f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277897762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.277897762
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2357493350
Short name T123
Test name
Test status
Simulation time 360843889 ps
CPU time 3.26 seconds
Started Jul 29 07:41:55 PM PDT 24
Finished Jul 29 07:41:58 PM PDT 24
Peak memory 242180 kb
Host smart-0af52294-4cd0-4e94-87a3-d284d3d42597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357493350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2357493350
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.918294106
Short name T177
Test name
Test status
Simulation time 255789944 ps
CPU time 11.44 seconds
Started Jul 29 07:41:54 PM PDT 24
Finished Jul 29 07:42:05 PM PDT 24
Peak memory 242156 kb
Host smart-9a9e2637-32f7-458a-ad2f-6faa5950a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918294106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.918294106
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.2162829049
Short name T144
Test name
Test status
Simulation time 890123927 ps
CPU time 13.26 seconds
Started Jul 29 07:41:54 PM PDT 24
Finished Jul 29 07:42:07 PM PDT 24
Peak memory 242292 kb
Host smart-c627667f-0019-4a12-973f-1ff59873b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162829049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2162829049
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.1866808947
Short name T991
Test name
Test status
Simulation time 7090816043 ps
CPU time 23.58 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:42:15 PM PDT 24
Peak memory 242084 kb
Host smart-715bd7ff-98d4-40f2-9c2d-84fb49b3dcda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866808947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1866808947
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.181027685
Short name T360
Test name
Test status
Simulation time 1333580345 ps
CPU time 10.4 seconds
Started Jul 29 07:41:55 PM PDT 24
Finished Jul 29 07:42:06 PM PDT 24
Peak memory 242076 kb
Host smart-ace96af0-a781-44ea-9216-bfc3eed924b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181027685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.181027685
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2174480827
Short name T939
Test name
Test status
Simulation time 339684980 ps
CPU time 4.94 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:41:58 PM PDT 24
Peak memory 241972 kb
Host smart-28c8b2d5-4a0a-457d-aa66-c2c4881dc8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174480827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2174480827
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3676526034
Short name T840
Test name
Test status
Simulation time 2355351449 ps
CPU time 50.7 seconds
Started Jul 29 07:41:52 PM PDT 24
Finished Jul 29 07:42:43 PM PDT 24
Peak memory 248716 kb
Host smart-3354bcb6-d978-4642-8361-02b5e922bfe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676526034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3676526034
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1286612152
Short name T173
Test name
Test status
Simulation time 104181495296 ps
CPU time 1049.58 seconds
Started Jul 29 07:41:54 PM PDT 24
Finished Jul 29 07:59:24 PM PDT 24
Peak memory 259484 kb
Host smart-be5357ef-4246-4c84-a4ac-17f849c8bcc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286612152 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.1286612152
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2646369379
Short name T418
Test name
Test status
Simulation time 123789142 ps
CPU time 3.87 seconds
Started Jul 29 07:41:53 PM PDT 24
Finished Jul 29 07:41:57 PM PDT 24
Peak memory 242164 kb
Host smart-e1033a62-f971-42f0-9489-5987ad5a99cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646369379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2646369379
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.2642474324
Short name T186
Test name
Test status
Simulation time 430692175 ps
CPU time 4.38 seconds
Started Jul 29 07:48:40 PM PDT 24
Finished Jul 29 07:48:44 PM PDT 24
Peak memory 242224 kb
Host smart-751aa9c3-2143-4809-a889-c36284874f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642474324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2642474324
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2170250764
Short name T130
Test name
Test status
Simulation time 352174122 ps
CPU time 10.49 seconds
Started Jul 29 07:48:37 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242480 kb
Host smart-0d19ab93-9f6c-4a1c-9a8a-0a8577985996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170250764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2170250764
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.744121128
Short name T981
Test name
Test status
Simulation time 133133867 ps
CPU time 3.76 seconds
Started Jul 29 07:48:43 PM PDT 24
Finished Jul 29 07:48:47 PM PDT 24
Peak memory 242256 kb
Host smart-121cc348-b385-44af-a8f0-e1d53facf1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744121128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.744121128
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3414675545
Short name T251
Test name
Test status
Simulation time 1720197144 ps
CPU time 13.11 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:49:03 PM PDT 24
Peak memory 241856 kb
Host smart-5637f312-ee6b-4080-8316-44405f71d5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414675545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3414675545
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.2600739514
Short name T219
Test name
Test status
Simulation time 307369518 ps
CPU time 3.27 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 242312 kb
Host smart-a49876a8-7cac-44fa-9df4-767ccb5f4118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600739514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2600739514
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.674045629
Short name T1148
Test name
Test status
Simulation time 384983708 ps
CPU time 5.39 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:51 PM PDT 24
Peak memory 242072 kb
Host smart-41f82a50-6b98-4452-bb98-3e4fc725e86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674045629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.674045629
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.798875171
Short name T869
Test name
Test status
Simulation time 248037937 ps
CPU time 3.8 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:48:53 PM PDT 24
Peak memory 242252 kb
Host smart-7bdfa9ac-9a2e-40d1-b32f-11dc50bc0794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798875171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.798875171
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.576790917
Short name T784
Test name
Test status
Simulation time 171409629 ps
CPU time 8.79 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:48:59 PM PDT 24
Peak memory 241876 kb
Host smart-649f60f2-6721-4758-b2ee-62cc446f5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576790917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.576790917
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2174387691
Short name T1008
Test name
Test status
Simulation time 199964226 ps
CPU time 4.68 seconds
Started Jul 29 07:48:41 PM PDT 24
Finished Jul 29 07:48:46 PM PDT 24
Peak memory 241996 kb
Host smart-c849b210-0481-4c27-a557-d9015f8d908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174387691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2174387691
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.4292345414
Short name T1078
Test name
Test status
Simulation time 130595949 ps
CPU time 3.81 seconds
Started Jul 29 07:48:46 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 242088 kb
Host smart-b9cafeb9-2b9e-429f-b52f-592230528c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292345414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4292345414
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2196376339
Short name T1182
Test name
Test status
Simulation time 538014380 ps
CPU time 3.92 seconds
Started Jul 29 07:48:43 PM PDT 24
Finished Jul 29 07:48:47 PM PDT 24
Peak memory 242172 kb
Host smart-195cc2d3-66d3-4f1c-8218-27b126f2bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196376339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2196376339
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.252318472
Short name T821
Test name
Test status
Simulation time 380737372 ps
CPU time 8.12 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 242088 kb
Host smart-de51697d-e3b8-4885-9a49-70ca0a1f1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252318472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.252318472
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.4275823344
Short name T988
Test name
Test status
Simulation time 157794671 ps
CPU time 4.11 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:49 PM PDT 24
Peak memory 242012 kb
Host smart-11a325dd-edf0-4cfa-bfe2-927dd85be653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275823344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4275823344
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2567343645
Short name T958
Test name
Test status
Simulation time 205843590 ps
CPU time 4.64 seconds
Started Jul 29 07:48:43 PM PDT 24
Finished Jul 29 07:48:47 PM PDT 24
Peak memory 241884 kb
Host smart-8c5ee1fa-deb4-40a8-9227-747b278c9aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567343645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2567343645
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.1135964328
Short name T581
Test name
Test status
Simulation time 271335372 ps
CPU time 4.02 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:49 PM PDT 24
Peak memory 242368 kb
Host smart-8eaaf527-a3ad-44fc-936f-2898dea69eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135964328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1135964328
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.4277631530
Short name T250
Test name
Test status
Simulation time 353597857 ps
CPU time 9.32 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:52 PM PDT 24
Peak memory 242368 kb
Host smart-66d683ac-bac7-4e20-acff-b1dece3cd14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277631530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.4277631530
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3069892734
Short name T1001
Test name
Test status
Simulation time 107872381 ps
CPU time 4.58 seconds
Started Jul 29 07:48:51 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 241708 kb
Host smart-f0361cc3-ca2b-4ab6-bdb4-648361566e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069892734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3069892734
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.207744470
Short name T462
Test name
Test status
Simulation time 1953126290 ps
CPU time 9.65 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 242208 kb
Host smart-5b09f907-c8d2-4cde-950b-9ff74646087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207744470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.207744470
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.1994764685
Short name T755
Test name
Test status
Simulation time 1890076116 ps
CPU time 5.09 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242316 kb
Host smart-a57d3cd5-2274-4e0f-a690-18ee28b1467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994764685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.1994764685
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2901104187
Short name T495
Test name
Test status
Simulation time 200416471 ps
CPU time 4.98 seconds
Started Jul 29 07:48:46 PM PDT 24
Finished Jul 29 07:48:51 PM PDT 24
Peak memory 241904 kb
Host smart-22ceb7fd-dc82-4d9e-803e-b7c6f3333626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901104187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2901104187
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.552235094
Short name T413
Test name
Test status
Simulation time 54782725 ps
CPU time 1.85 seconds
Started Jul 29 07:42:08 PM PDT 24
Finished Jul 29 07:42:10 PM PDT 24
Peak memory 240500 kb
Host smart-b7bfa826-26f6-427a-83de-61bf51784ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552235094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.552235094
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.789252504
Short name T40
Test name
Test status
Simulation time 13224646407 ps
CPU time 36.51 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:40 PM PDT 24
Peak memory 243420 kb
Host smart-9f59fc70-e28d-4f80-ad29-5e18b78f52eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789252504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.789252504
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.2545064758
Short name T1146
Test name
Test status
Simulation time 338054718 ps
CPU time 20.09 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:42:26 PM PDT 24
Peak memory 241976 kb
Host smart-ab54b2b2-91e4-45d0-883d-0368110496e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545064758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2545064758
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.232455144
Short name T1122
Test name
Test status
Simulation time 431019031 ps
CPU time 7.22 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:13 PM PDT 24
Peak memory 242116 kb
Host smart-eaf4a70d-f79f-4bf6-ab6e-82df54e40e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232455144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.232455144
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.2208597935
Short name T550
Test name
Test status
Simulation time 127362199 ps
CPU time 4.76 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:10 PM PDT 24
Peak memory 241976 kb
Host smart-9d528aa5-a73f-4d1b-9867-c84744eac86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208597935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2208597935
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1731380283
Short name T439
Test name
Test status
Simulation time 3349154497 ps
CPU time 7.52 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:13 PM PDT 24
Peak memory 243716 kb
Host smart-b16cf812-6027-4013-960b-964b53588591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731380283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1731380283
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.522426515
Short name T1043
Test name
Test status
Simulation time 1350835332 ps
CPU time 28.55 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:33 PM PDT 24
Peak memory 242300 kb
Host smart-dcda6303-2f94-4b57-abeb-6afa9d8ffc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522426515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.522426515
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.4211588003
Short name T1017
Test name
Test status
Simulation time 437741671 ps
CPU time 5 seconds
Started Jul 29 07:42:07 PM PDT 24
Finished Jul 29 07:42:12 PM PDT 24
Peak memory 241896 kb
Host smart-67a35b11-5526-436e-83a9-a58759a25add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211588003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.4211588003
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.2084374635
Short name T105
Test name
Test status
Simulation time 1636445450 ps
CPU time 12.72 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:18 PM PDT 24
Peak memory 241916 kb
Host smart-37228ee0-df15-4ab4-a10e-bee0eb0a8f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084374635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2084374635
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.3969587313
Short name T844
Test name
Test status
Simulation time 134647065 ps
CPU time 4.56 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:10 PM PDT 24
Peak memory 248556 kb
Host smart-cba5086a-6a8b-42a8-90ef-3dcb47a5ef7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969587313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3969587313
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3990518280
Short name T530
Test name
Test status
Simulation time 626821273 ps
CPU time 6.71 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:12 PM PDT 24
Peak memory 241968 kb
Host smart-1294024e-2d83-48b2-96ce-d552994e9ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990518280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3990518280
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.265683418
Short name T726
Test name
Test status
Simulation time 10877597676 ps
CPU time 68.63 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:43:15 PM PDT 24
Peak memory 248648 kb
Host smart-846392c5-5f3d-4311-8e69-65bff321a613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265683418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.
265683418
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.3502573152
Short name T841
Test name
Test status
Simulation time 260637999 ps
CPU time 5.99 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:42:12 PM PDT 24
Peak memory 241976 kb
Host smart-ddc41e58-4ff8-400b-a000-8339a660690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502573152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3502573152
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.2415614974
Short name T62
Test name
Test status
Simulation time 136939717 ps
CPU time 3.66 seconds
Started Jul 29 07:48:41 PM PDT 24
Finished Jul 29 07:48:44 PM PDT 24
Peak memory 242196 kb
Host smart-ad3fb38e-7691-4aa1-8f8b-44dae6e230ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415614974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2415614974
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1419509861
Short name T1180
Test name
Test status
Simulation time 3609238418 ps
CPU time 22.79 seconds
Started Jul 29 07:48:49 PM PDT 24
Finished Jul 29 07:49:12 PM PDT 24
Peak memory 242000 kb
Host smart-495a1339-dfd3-43b0-8eaf-8d6de9b180b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419509861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1419509861
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.4156668258
Short name T950
Test name
Test status
Simulation time 168089266 ps
CPU time 3.83 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 241932 kb
Host smart-1b9009ed-fbf2-4718-aea3-07aa952af895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156668258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.4156668258
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1172914637
Short name T147
Test name
Test status
Simulation time 4228732091 ps
CPU time 19.12 seconds
Started Jul 29 07:48:51 PM PDT 24
Finished Jul 29 07:49:10 PM PDT 24
Peak memory 242060 kb
Host smart-a59a420f-1103-4d24-ad52-b064a762158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172914637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1172914637
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2519334098
Short name T634
Test name
Test status
Simulation time 1725940476 ps
CPU time 4.18 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:46 PM PDT 24
Peak memory 241848 kb
Host smart-1e77818f-8078-4191-bef4-72741bc6fe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519334098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2519334098
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.829928396
Short name T767
Test name
Test status
Simulation time 128137822 ps
CPU time 5.19 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 241816 kb
Host smart-eae8c5e6-0462-4f16-ab65-e217597cd21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829928396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.829928396
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.3636470521
Short name T744
Test name
Test status
Simulation time 2065093865 ps
CPU time 7.14 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 242096 kb
Host smart-a57d0f28-e09d-4c15-88b6-83625baa1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636470521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3636470521
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1041255855
Short name T506
Test name
Test status
Simulation time 1213206838 ps
CPU time 4.14 seconds
Started Jul 29 07:48:46 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 241992 kb
Host smart-3fa8c3b6-886c-4dfb-8ece-c47dd168d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041255855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1041255855
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1593552506
Short name T654
Test name
Test status
Simulation time 96739887 ps
CPU time 3.13 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 241900 kb
Host smart-fb2a3f6b-969d-4221-b7cf-f53861e3a11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593552506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1593552506
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1563789080
Short name T868
Test name
Test status
Simulation time 2061888205 ps
CPU time 7.16 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:51 PM PDT 24
Peak memory 241944 kb
Host smart-67dec590-cead-4005-b232-265319b1ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563789080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1563789080
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1511745411
Short name T1096
Test name
Test status
Simulation time 116526666 ps
CPU time 3.17 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242168 kb
Host smart-d753a586-33e2-44b8-a3b7-f335209a188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511745411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1511745411
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2649942329
Short name T120
Test name
Test status
Simulation time 388423202 ps
CPU time 5.02 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 242052 kb
Host smart-a6f29196-209c-4393-95b6-e794543bb3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649942329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2649942329
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.520484428
Short name T213
Test name
Test status
Simulation time 146528143 ps
CPU time 3.57 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:46 PM PDT 24
Peak memory 242196 kb
Host smart-4ed9a971-a8cf-47aa-9650-bde539289021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520484428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.520484428
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1461893427
Short name T1158
Test name
Test status
Simulation time 434220806 ps
CPU time 5.9 seconds
Started Jul 29 07:48:46 PM PDT 24
Finished Jul 29 07:48:52 PM PDT 24
Peak memory 242260 kb
Host smart-dcfa0f83-cc05-4586-a2d8-b7ba75bddcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461893427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1461893427
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.2733416481
Short name T1097
Test name
Test status
Simulation time 1725502204 ps
CPU time 4.64 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:49 PM PDT 24
Peak memory 242360 kb
Host smart-26aaa3dc-5c25-4c1c-b6f2-13a56dbfed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733416481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.2733416481
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.3266949706
Short name T652
Test name
Test status
Simulation time 154169967 ps
CPU time 5.31 seconds
Started Jul 29 07:48:41 PM PDT 24
Finished Jul 29 07:48:47 PM PDT 24
Peak memory 241896 kb
Host smart-d18bfc19-b926-4b56-8e19-7a5b691abd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266949706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3266949706
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3650731635
Short name T1184
Test name
Test status
Simulation time 3245680538 ps
CPU time 13.35 seconds
Started Jul 29 07:48:51 PM PDT 24
Finished Jul 29 07:49:04 PM PDT 24
Peak memory 241952 kb
Host smart-786b60a5-0a9c-4f01-b3b0-22e3b9db9005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650731635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3650731635
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.15991319
Short name T946
Test name
Test status
Simulation time 150417349 ps
CPU time 3.85 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242040 kb
Host smart-5899c95b-e739-489e-9f8a-ca851963737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15991319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.15991319
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.3018835102
Short name T1155
Test name
Test status
Simulation time 986841921 ps
CPU time 8.46 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 241868 kb
Host smart-f3128a31-589e-43fb-8792-4fa7aec8144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018835102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3018835102
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3136181689
Short name T488
Test name
Test status
Simulation time 57070650 ps
CPU time 1.72 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:06 PM PDT 24
Peak memory 240468 kb
Host smart-b3afa391-c064-4bd1-afc6-2a544b638f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136181689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3136181689
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2093208624
Short name T29
Test name
Test status
Simulation time 1041195564 ps
CPU time 14.91 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:19 PM PDT 24
Peak memory 242340 kb
Host smart-027c467c-464c-44da-856a-72de45b96bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093208624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2093208624
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.504045374
Short name T970
Test name
Test status
Simulation time 3282465987 ps
CPU time 32.51 seconds
Started Jul 29 07:42:08 PM PDT 24
Finished Jul 29 07:42:40 PM PDT 24
Peak memory 245708 kb
Host smart-63f84a6a-6d3d-46c9-8dd0-385fd208ea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504045374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.504045374
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.3142474977
Short name T930
Test name
Test status
Simulation time 1402896453 ps
CPU time 27.58 seconds
Started Jul 29 07:42:07 PM PDT 24
Finished Jul 29 07:42:35 PM PDT 24
Peak memory 248572 kb
Host smart-d1ccd379-35ec-4908-9f65-a40e02492ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142474977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3142474977
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2785723933
Short name T956
Test name
Test status
Simulation time 156964071 ps
CPU time 4.74 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:10 PM PDT 24
Peak memory 241996 kb
Host smart-521a650a-c6cb-4462-9691-97ed07a4081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785723933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2785723933
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.4034653166
Short name T935
Test name
Test status
Simulation time 1773506912 ps
CPU time 25.72 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:42:31 PM PDT 24
Peak memory 246020 kb
Host smart-6ebc9c28-2f5e-4a74-a446-1513005f949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034653166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.4034653166
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.167148299
Short name T1031
Test name
Test status
Simulation time 338788332 ps
CPU time 9.71 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:42:16 PM PDT 24
Peak memory 242188 kb
Host smart-1cb7287b-5c03-47c1-87bd-f959359d30e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167148299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.167148299
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.3469500971
Short name T937
Test name
Test status
Simulation time 532973279 ps
CPU time 8.02 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:12 PM PDT 24
Peak memory 241672 kb
Host smart-14074c58-204b-4d88-bdb1-19382ab58df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469500971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3469500971
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.838563133
Short name T763
Test name
Test status
Simulation time 3827520714 ps
CPU time 12.97 seconds
Started Jul 29 07:42:08 PM PDT 24
Finished Jul 29 07:42:21 PM PDT 24
Peak memory 242056 kb
Host smart-bab2ab89-2ea5-4581-935b-0cb91583c78f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838563133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.838563133
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.50035486
Short name T406
Test name
Test status
Simulation time 4298616213 ps
CPU time 9.32 seconds
Started Jul 29 07:42:07 PM PDT 24
Finished Jul 29 07:42:16 PM PDT 24
Peak memory 242176 kb
Host smart-6cd23f3c-75be-4148-a1a7-8bc57061863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50035486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.50035486
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2305311618
Short name T482
Test name
Test status
Simulation time 115463288900 ps
CPU time 186.46 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:45:11 PM PDT 24
Peak memory 247352 kb
Host smart-4f1bd070-7c87-4098-bae3-386e2100bb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305311618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2305311618
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.4064862363
Short name T18
Test name
Test status
Simulation time 178362456242 ps
CPU time 999.97 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:58:46 PM PDT 24
Peak memory 257044 kb
Host smart-2479e630-9033-4cc7-8adb-225e7fe57170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064862363 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.4064862363
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1591666414
Short name T607
Test name
Test status
Simulation time 677944457 ps
CPU time 10.92 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:15 PM PDT 24
Peak memory 242224 kb
Host smart-959d000c-c5b2-4080-bb4f-561ae672dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591666414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1591666414
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.2724932111
Short name T205
Test name
Test status
Simulation time 271711212 ps
CPU time 7.19 seconds
Started Jul 29 07:48:46 PM PDT 24
Finished Jul 29 07:48:53 PM PDT 24
Peak memory 241976 kb
Host smart-cec33fd2-0812-4c16-9315-2f3c0cf5c4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724932111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2724932111
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.4288321413
Short name T779
Test name
Test status
Simulation time 1606899414 ps
CPU time 4.64 seconds
Started Jul 29 07:48:43 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242188 kb
Host smart-3579ec63-9479-45cf-ad29-d3f460b47bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288321413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.4288321413
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.1742655611
Short name T260
Test name
Test status
Simulation time 921181960 ps
CPU time 15.58 seconds
Started Jul 29 07:48:51 PM PDT 24
Finished Jul 29 07:49:07 PM PDT 24
Peak memory 241740 kb
Host smart-483cd319-bbf4-403b-a5d4-0cccabb22ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742655611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1742655611
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3574974051
Short name T1144
Test name
Test status
Simulation time 467662488 ps
CPU time 4.15 seconds
Started Jul 29 07:48:41 PM PDT 24
Finished Jul 29 07:48:45 PM PDT 24
Peak memory 242300 kb
Host smart-ef909dd4-1187-4525-82a9-5b8d2ed42d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574974051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3574974051
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.1111134099
Short name T386
Test name
Test status
Simulation time 293819540 ps
CPU time 4.13 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:49 PM PDT 24
Peak memory 241936 kb
Host smart-e5e4acf7-d296-4afc-8d82-07a5007375d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111134099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1111134099
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1785373980
Short name T1080
Test name
Test status
Simulation time 123102837 ps
CPU time 3.09 seconds
Started Jul 29 07:48:44 PM PDT 24
Finished Jul 29 07:48:48 PM PDT 24
Peak memory 242244 kb
Host smart-0c42318d-1c0e-49c2-94d7-7e9fe252932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785373980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1785373980
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.3093429444
Short name T129
Test name
Test status
Simulation time 175644662 ps
CPU time 7.71 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:53 PM PDT 24
Peak memory 241864 kb
Host smart-8a7db0ee-3121-4c55-80cf-b546a50f41c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093429444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3093429444
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.3965020111
Short name T1130
Test name
Test status
Simulation time 165612764 ps
CPU time 3.84 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:48:54 PM PDT 24
Peak memory 241900 kb
Host smart-e631cd0d-878a-4f40-bd10-e35075bf4cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965020111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3965020111
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.1298490294
Short name T1084
Test name
Test status
Simulation time 604313198 ps
CPU time 8.18 seconds
Started Jul 29 07:48:47 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 242400 kb
Host smart-560c302a-d425-4f81-a786-721aee65580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298490294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1298490294
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.1443551546
Short name T1174
Test name
Test status
Simulation time 1616482064 ps
CPU time 4.47 seconds
Started Jul 29 07:48:46 PM PDT 24
Finished Jul 29 07:48:50 PM PDT 24
Peak memory 242376 kb
Host smart-a947cc8d-63b5-454f-b1c0-d769ae279675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443551546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1443551546
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.4181540763
Short name T677
Test name
Test status
Simulation time 1104927417 ps
CPU time 15.03 seconds
Started Jul 29 07:48:43 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 241896 kb
Host smart-b027ef90-19c0-4b74-b031-03cfdf65dcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181540763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.4181540763
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.270838545
Short name T1142
Test name
Test status
Simulation time 1982311486 ps
CPU time 6.46 seconds
Started Jul 29 07:48:45 PM PDT 24
Finished Jul 29 07:48:52 PM PDT 24
Peak memory 242180 kb
Host smart-97540b79-c808-4e99-8e4a-719ad292c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270838545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.270838545
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2078825612
Short name T463
Test name
Test status
Simulation time 1713853805 ps
CPU time 7.57 seconds
Started Jul 29 07:48:43 PM PDT 24
Finished Jul 29 07:48:51 PM PDT 24
Peak memory 242200 kb
Host smart-85b41d64-2049-4fd3-bbf4-bb998b6781a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078825612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2078825612
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.409231559
Short name T83
Test name
Test status
Simulation time 1927493961 ps
CPU time 5.35 seconds
Started Jul 29 07:48:49 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 242296 kb
Host smart-34e7bab8-1ab7-4f03-899e-a1fb2cb1792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409231559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.409231559
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1940826381
Short name T9
Test name
Test status
Simulation time 3447727922 ps
CPU time 8.35 seconds
Started Jul 29 07:48:48 PM PDT 24
Finished Jul 29 07:48:56 PM PDT 24
Peak memory 242248 kb
Host smart-92817876-9c33-4250-9cda-a8ae3d4059fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940826381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1940826381
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1325051573
Short name T557
Test name
Test status
Simulation time 515984442 ps
CPU time 5.83 seconds
Started Jul 29 07:48:49 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 241920 kb
Host smart-e8419500-b134-4a6b-8f1a-862c64a88efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325051573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1325051573
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.4032339971
Short name T895
Test name
Test status
Simulation time 2150734855 ps
CPU time 10.55 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:49:01 PM PDT 24
Peak memory 242004 kb
Host smart-0743e7a2-6929-4cef-8ec9-fb5b9a402aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032339971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.4032339971
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.584208490
Short name T517
Test name
Test status
Simulation time 234256473 ps
CPU time 4.73 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 242292 kb
Host smart-9f92f234-404a-4226-bf58-9cb087967043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584208490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.584208490
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2558952906
Short name T691
Test name
Test status
Simulation time 134117967 ps
CPU time 4.94 seconds
Started Jul 29 07:48:47 PM PDT 24
Finished Jul 29 07:48:52 PM PDT 24
Peak memory 241876 kb
Host smart-b2a8cb60-1b26-49d9-a7ae-9a0f0c209629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558952906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2558952906
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.3027989545
Short name T1192
Test name
Test status
Simulation time 875691076 ps
CPU time 2.13 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:40:31 PM PDT 24
Peak memory 240548 kb
Host smart-300844b3-5556-4bb7-b6b2-1247e5782459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027989545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3027989545
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3727639199
Short name T842
Test name
Test status
Simulation time 595694632 ps
CPU time 16.68 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:43 PM PDT 24
Peak memory 242376 kb
Host smart-99d619e8-43b2-40fb-8b27-b358dca74c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727639199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3727639199
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.2092827236
Short name T317
Test name
Test status
Simulation time 442092880 ps
CPU time 10.13 seconds
Started Jul 29 07:40:24 PM PDT 24
Finished Jul 29 07:40:35 PM PDT 24
Peak memory 241872 kb
Host smart-2eb74da1-bd17-415a-80c6-8c879b796c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092827236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2092827236
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.1407983901
Short name T1082
Test name
Test status
Simulation time 3942954205 ps
CPU time 9.65 seconds
Started Jul 29 07:40:25 PM PDT 24
Finished Jul 29 07:40:35 PM PDT 24
Peak memory 242772 kb
Host smart-b6183434-5963-4b32-8bf9-66a6178f9a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407983901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1407983901
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.3900537570
Short name T1056
Test name
Test status
Simulation time 275720919 ps
CPU time 4.54 seconds
Started Jul 29 07:40:25 PM PDT 24
Finished Jul 29 07:40:30 PM PDT 24
Peak memory 242220 kb
Host smart-512c1439-6173-4681-aa5c-ec0ea475e175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900537570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3900537570
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1513055216
Short name T490
Test name
Test status
Simulation time 398768908 ps
CPU time 3.85 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:40:32 PM PDT 24
Peak memory 248584 kb
Host smart-2f99c937-26e7-4d5a-bd71-dd5a1b2ce1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513055216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1513055216
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1122176033
Short name T730
Test name
Test status
Simulation time 428997022 ps
CPU time 14.43 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:40 PM PDT 24
Peak memory 248632 kb
Host smart-96fc26f4-1718-4cca-ad15-dd7b51dff503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122176033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1122176033
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.622300738
Short name T637
Test name
Test status
Simulation time 184860151 ps
CPU time 3.65 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:30 PM PDT 24
Peak memory 242280 kb
Host smart-2a178340-7295-4d5f-8720-fe181505a401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622300738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.622300738
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.815968315
Short name T430
Test name
Test status
Simulation time 385739724 ps
CPU time 12.02 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:38 PM PDT 24
Peak memory 242164 kb
Host smart-48316bf6-41f5-4682-9cea-d8cb51acf0cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815968315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.815968315
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.652730304
Short name T89
Test name
Test status
Simulation time 290216488 ps
CPU time 9.66 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:40:37 PM PDT 24
Peak memory 242244 kb
Host smart-0ca709ab-d613-4f48-a363-6ec33d01d9d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652730304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.652730304
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.2671593629
Short name T23
Test name
Test status
Simulation time 39819783779 ps
CPU time 214.64 seconds
Started Jul 29 07:40:27 PM PDT 24
Finished Jul 29 07:44:02 PM PDT 24
Peak memory 266468 kb
Host smart-321c55a8-c4a5-4057-a1df-858098797fb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671593629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2671593629
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1216428277
Short name T695
Test name
Test status
Simulation time 513254286 ps
CPU time 12.27 seconds
Started Jul 29 07:40:25 PM PDT 24
Finished Jul 29 07:40:38 PM PDT 24
Peak memory 241996 kb
Host smart-dcf63121-9370-48e3-bbfc-101d476ef92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216428277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1216428277
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3861628167
Short name T201
Test name
Test status
Simulation time 517198742 ps
CPU time 8.97 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:35 PM PDT 24
Peak memory 242172 kb
Host smart-4c98b7a8-10ca-400c-8682-c8d5eceaf730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861628167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3861628167
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.4033752201
Short name T757
Test name
Test status
Simulation time 84691418 ps
CPU time 1.78 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:23 PM PDT 24
Peak memory 240520 kb
Host smart-9d8569bc-b4a9-485c-9557-79ae84922681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033752201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.4033752201
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.2098915482
Short name T31
Test name
Test status
Simulation time 839123747 ps
CPU time 12.77 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:18 PM PDT 24
Peak memory 242124 kb
Host smart-3b989491-b37a-4e43-89ed-0a8b84242290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098915482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2098915482
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2870539891
Short name T162
Test name
Test status
Simulation time 171596820 ps
CPU time 8.37 seconds
Started Jul 29 07:42:07 PM PDT 24
Finished Jul 29 07:42:15 PM PDT 24
Peak memory 241936 kb
Host smart-8029396e-cec4-450f-a4a5-b1c8cd0bf0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870539891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2870539891
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.2042046974
Short name T785
Test name
Test status
Simulation time 11271386080 ps
CPU time 25.4 seconds
Started Jul 29 07:42:06 PM PDT 24
Finished Jul 29 07:42:31 PM PDT 24
Peak memory 243028 kb
Host smart-9dca2914-6005-4fc0-987d-96a448020d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042046974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2042046974
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.1961830252
Short name T1107
Test name
Test status
Simulation time 426412489 ps
CPU time 3.39 seconds
Started Jul 29 07:42:05 PM PDT 24
Finished Jul 29 07:42:09 PM PDT 24
Peak memory 242132 kb
Host smart-7f40b589-0f34-40d1-b7f3-0daaa325a16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961830252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1961830252
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.2481836273
Short name T1141
Test name
Test status
Simulation time 4007634771 ps
CPU time 32.68 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:37 PM PDT 24
Peak memory 256912 kb
Host smart-b9b27fb4-5f01-4f7c-8154-1dafdd092b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481836273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2481836273
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.273666522
Short name T792
Test name
Test status
Simulation time 1014287529 ps
CPU time 20.55 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:42:44 PM PDT 24
Peak memory 248684 kb
Host smart-76af91fb-e3a8-4ea3-845f-cbf44eb0e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273666522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.273666522
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.772141245
Short name T542
Test name
Test status
Simulation time 4180756379 ps
CPU time 11.86 seconds
Started Jul 29 07:42:04 PM PDT 24
Finished Jul 29 07:42:16 PM PDT 24
Peak memory 241992 kb
Host smart-aede3681-2fd8-47e5-9d93-f3a3914ce712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772141245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.772141245
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3926747489
Short name T1033
Test name
Test status
Simulation time 229001678 ps
CPU time 5.62 seconds
Started Jul 29 07:42:07 PM PDT 24
Finished Jul 29 07:42:12 PM PDT 24
Peak memory 248444 kb
Host smart-acd2a6b6-ada9-481b-b173-f895c3dbade6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926747489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3926747489
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.1333962713
Short name T712
Test name
Test status
Simulation time 482444225 ps
CPU time 9.51 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:30 PM PDT 24
Peak memory 242040 kb
Host smart-477fff9a-405b-4b5f-9c58-8a017e9caf91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333962713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1333962713
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.2781671610
Short name T1071
Test name
Test status
Simulation time 89461839 ps
CPU time 3.28 seconds
Started Jul 29 07:42:28 PM PDT 24
Finished Jul 29 07:42:32 PM PDT 24
Peak memory 241884 kb
Host smart-18bd3821-b11c-415f-888b-eeb224063549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781671610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2781671610
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.973681991
Short name T614
Test name
Test status
Simulation time 73320129246 ps
CPU time 222.81 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:46:03 PM PDT 24
Peak memory 268644 kb
Host smart-863a91dd-8e8d-4dd6-bd86-d8b8e76225b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973681991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
973681991
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.3546084737
Short name T940
Test name
Test status
Simulation time 4128787409 ps
CPU time 27.87 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 242500 kb
Host smart-f8d9f10e-adc3-4fd2-b25e-016a5c17d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546084737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3546084737
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3895230854
Short name T891
Test name
Test status
Simulation time 162900708 ps
CPU time 3.18 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:48:59 PM PDT 24
Peak memory 242004 kb
Host smart-8b4f32b2-29e8-4000-98ba-0c2f04b27d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895230854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3895230854
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.734005287
Short name T476
Test name
Test status
Simulation time 254189382 ps
CPU time 3.57 seconds
Started Jul 29 07:48:48 PM PDT 24
Finished Jul 29 07:48:51 PM PDT 24
Peak memory 242020 kb
Host smart-f05c4bdf-baa2-4b33-ac48-2b565acfd2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734005287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.734005287
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.3999333953
Short name T942
Test name
Test status
Simulation time 251320521 ps
CPU time 3.85 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 241972 kb
Host smart-a6c242e5-d278-40a0-995b-13ddf1e7e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999333953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3999333953
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.2030466606
Short name T392
Test name
Test status
Simulation time 185185020 ps
CPU time 4.79 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:01 PM PDT 24
Peak memory 242244 kb
Host smart-8806a82c-74f0-4a4e-9b31-818431a6476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030466606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2030466606
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.95590109
Short name T822
Test name
Test status
Simulation time 157771390 ps
CPU time 4.13 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 242180 kb
Host smart-89a0311c-11f5-44d1-a02f-6bad7f0cdfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95590109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.95590109
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2218937299
Short name T559
Test name
Test status
Simulation time 146483241 ps
CPU time 4.25 seconds
Started Jul 29 07:48:42 PM PDT 24
Finished Jul 29 07:48:47 PM PDT 24
Peak memory 241924 kb
Host smart-901e68e9-49d9-4964-aded-677deac95384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218937299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2218937299
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.1148686257
Short name T214
Test name
Test status
Simulation time 135653352 ps
CPU time 3.53 seconds
Started Jul 29 07:48:52 PM PDT 24
Finished Jul 29 07:48:56 PM PDT 24
Peak memory 241996 kb
Host smart-6264a1c7-3a87-4820-96bb-b45a4eaceec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148686257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1148686257
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.1698185260
Short name T1162
Test name
Test status
Simulation time 254466595 ps
CPU time 3.79 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242096 kb
Host smart-6e0ce4a6-2ff1-4ea7-8452-4542bae8cc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698185260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1698185260
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1562848534
Short name T964
Test name
Test status
Simulation time 79037770 ps
CPU time 1.61 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:22 PM PDT 24
Peak memory 240308 kb
Host smart-a11c41a0-db18-4d49-aa14-96cedf1d68bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562848534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1562848534
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.4000907622
Short name T856
Test name
Test status
Simulation time 1161391534 ps
CPU time 16.86 seconds
Started Jul 29 07:42:19 PM PDT 24
Finished Jul 29 07:42:37 PM PDT 24
Peak memory 242600 kb
Host smart-16ce3d0c-4af9-4254-8b2b-0e5b4f8da9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000907622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.4000907622
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3629129675
Short name T694
Test name
Test status
Simulation time 342697718 ps
CPU time 22.48 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:44 PM PDT 24
Peak memory 241920 kb
Host smart-fb5b7d87-e65e-4673-a520-d039d72370fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629129675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3629129675
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.919418515
Short name T633
Test name
Test status
Simulation time 1829081577 ps
CPU time 14.11 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:36 PM PDT 24
Peak memory 242368 kb
Host smart-da16e87e-1db6-405b-87b1-bd42893adcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919418515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.919418515
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1020816330
Short name T791
Test name
Test status
Simulation time 217056615 ps
CPU time 3.66 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:24 PM PDT 24
Peak memory 242312 kb
Host smart-adff9b73-f2be-4153-9803-0310077286b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020816330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1020816330
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.1916702250
Short name T1024
Test name
Test status
Simulation time 13740463598 ps
CPU time 42.24 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:43:03 PM PDT 24
Peak memory 248716 kb
Host smart-75c9a69f-bc47-4634-a195-24fac2488a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916702250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1916702250
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.4246563327
Short name T916
Test name
Test status
Simulation time 470284630 ps
CPU time 10.01 seconds
Started Jul 29 07:42:19 PM PDT 24
Finished Jul 29 07:42:29 PM PDT 24
Peak memory 242160 kb
Host smart-8e638bd2-1891-461b-9716-b54d8facb95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246563327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.4246563327
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3410610191
Short name T829
Test name
Test status
Simulation time 679885911 ps
CPU time 18.15 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 242288 kb
Host smart-d062080b-369a-4297-aa2c-0569e79e33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410610191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3410610191
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.3040034875
Short name T715
Test name
Test status
Simulation time 420940418 ps
CPU time 2.98 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:25 PM PDT 24
Peak memory 248156 kb
Host smart-6a8f58bd-302a-4474-9c2a-8dfc7385541e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040034875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3040034875
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.4166051594
Short name T863
Test name
Test status
Simulation time 687868551 ps
CPU time 5.8 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:42:29 PM PDT 24
Peak memory 242036 kb
Host smart-904d8600-5cb2-419f-b860-ca624e07a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166051594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.4166051594
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.681867839
Short name T1177
Test name
Test status
Simulation time 300758296614 ps
CPU time 1766.67 seconds
Started Jul 29 07:42:18 PM PDT 24
Finished Jul 29 08:11:45 PM PDT 24
Peak memory 420368 kb
Host smart-6549dff9-d4ad-4820-bda5-088d48173dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681867839 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.681867839
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.2848748411
Short name T972
Test name
Test status
Simulation time 2738236375 ps
CPU time 26.19 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:46 PM PDT 24
Peak memory 242304 kb
Host smart-3041aeb5-3d7e-42b9-8a3d-b05dd8fe39eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848748411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2848748411
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1477825646
Short name T670
Test name
Test status
Simulation time 110520223 ps
CPU time 3.69 seconds
Started Jul 29 07:49:03 PM PDT 24
Finished Jul 29 07:49:06 PM PDT 24
Peak memory 242300 kb
Host smart-113c62e0-8a26-4d9d-84f6-edddfab33316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477825646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1477825646
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.3466312719
Short name T949
Test name
Test status
Simulation time 163249761 ps
CPU time 4.09 seconds
Started Jul 29 07:48:58 PM PDT 24
Finished Jul 29 07:49:02 PM PDT 24
Peak memory 242208 kb
Host smart-55411bd8-8ffb-4b75-8330-641ee7043446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466312719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3466312719
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.805831762
Short name T741
Test name
Test status
Simulation time 1547625047 ps
CPU time 6.58 seconds
Started Jul 29 07:48:57 PM PDT 24
Finished Jul 29 07:49:04 PM PDT 24
Peak memory 242320 kb
Host smart-20dcb41d-ea0f-400f-9dbd-38e70089bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805831762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.805831762
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1320924529
Short name T662
Test name
Test status
Simulation time 636127781 ps
CPU time 4.95 seconds
Started Jul 29 07:48:55 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 241988 kb
Host smart-8198d6d0-4728-4ed8-b2c6-a0d988e094c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320924529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1320924529
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.71967836
Short name T978
Test name
Test status
Simulation time 1985470563 ps
CPU time 4.56 seconds
Started Jul 29 07:48:58 PM PDT 24
Finished Jul 29 07:49:02 PM PDT 24
Peak memory 242384 kb
Host smart-ea8cec6a-b0f0-46cb-a9af-7d2da43f3ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71967836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.71967836
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.2463491986
Short name T503
Test name
Test status
Simulation time 158537156 ps
CPU time 5.57 seconds
Started Jul 29 07:48:54 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 241972 kb
Host smart-18adfa99-a902-4dbf-a68d-d62e280b3dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463491986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2463491986
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2941636118
Short name T116
Test name
Test status
Simulation time 281547233 ps
CPU time 3.79 seconds
Started Jul 29 07:48:54 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242056 kb
Host smart-662f217f-cb64-422e-8a4e-b980cfa687f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941636118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2941636118
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3174919910
Short name T500
Test name
Test status
Simulation time 1973141073 ps
CPU time 4.63 seconds
Started Jul 29 07:49:03 PM PDT 24
Finished Jul 29 07:49:08 PM PDT 24
Peak memory 242496 kb
Host smart-7803b06c-e0dc-4bab-a356-384e57803bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174919910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3174919910
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2009033632
Short name T831
Test name
Test status
Simulation time 1503849916 ps
CPU time 5.31 seconds
Started Jul 29 07:48:52 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 242336 kb
Host smart-832bd962-6292-4c4e-b723-194f76cf0b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009033632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2009033632
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.1769381994
Short name T963
Test name
Test status
Simulation time 41947077 ps
CPU time 1.61 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:42:24 PM PDT 24
Peak memory 240660 kb
Host smart-0a5bb634-fb23-473d-ab06-36ea9bc088c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769381994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1769381994
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.196001870
Short name T78
Test name
Test status
Simulation time 1466705858 ps
CPU time 23.04 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:45 PM PDT 24
Peak memory 248624 kb
Host smart-8124c161-6f04-4df2-a69b-4f8fb1b7aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196001870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.196001870
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1791576929
Short name T526
Test name
Test status
Simulation time 5821623006 ps
CPU time 33.32 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:42:56 PM PDT 24
Peak memory 241940 kb
Host smart-4654501c-8040-47e0-b54c-aa215c3af5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791576929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1791576929
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.496183651
Short name T112
Test name
Test status
Simulation time 1388092880 ps
CPU time 16.1 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:37 PM PDT 24
Peak memory 241924 kb
Host smart-dbe80858-7e77-4cb2-bc4a-8c3f8859893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496183651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.496183651
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.4034281125
Short name T597
Test name
Test status
Simulation time 140173415 ps
CPU time 4.06 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:26 PM PDT 24
Peak memory 242060 kb
Host smart-ffcbf371-4835-4c27-a837-0219203b67f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034281125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.4034281125
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3747210215
Short name T101
Test name
Test status
Simulation time 378332594 ps
CPU time 11.54 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:33 PM PDT 24
Peak memory 242388 kb
Host smart-02910193-b5b5-4a0b-8b3b-48871e004c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747210215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3747210215
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.465550512
Short name T507
Test name
Test status
Simulation time 2419460273 ps
CPU time 6.58 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:27 PM PDT 24
Peak memory 242416 kb
Host smart-e62d925d-f81c-4575-b431-a85a3b6440eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465550512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.465550512
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1177904713
Short name T932
Test name
Test status
Simulation time 3220739390 ps
CPU time 29.05 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:50 PM PDT 24
Peak memory 241988 kb
Host smart-438f8e5d-7d66-40e3-954b-903d30b2d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177904713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1177904713
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.3166914357
Short name T426
Test name
Test status
Simulation time 568847577 ps
CPU time 6.69 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:27 PM PDT 24
Peak memory 242172 kb
Host smart-fc27e8a6-dc1c-471a-a67d-6850257d3a09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166914357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3166914357
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1074413059
Short name T920
Test name
Test status
Simulation time 494600647 ps
CPU time 5.49 seconds
Started Jul 29 07:42:23 PM PDT 24
Finished Jul 29 07:42:28 PM PDT 24
Peak memory 248552 kb
Host smart-ebadad49-2aa3-4c25-b0e5-150243d35f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074413059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1074413059
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.2332588418
Short name T798
Test name
Test status
Simulation time 690468681 ps
CPU time 10.35 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:33 PM PDT 24
Peak memory 242304 kb
Host smart-fccea1a2-6e40-4fd6-9bb7-28fd62e6b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332588418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2332588418
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.3831772482
Short name T131
Test name
Test status
Simulation time 1822659122 ps
CPU time 13.61 seconds
Started Jul 29 07:42:19 PM PDT 24
Finished Jul 29 07:42:33 PM PDT 24
Peak memory 241960 kb
Host smart-03502be0-8fe7-4ac6-a7c4-dc8d3751d824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831772482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.3831772482
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3344007905
Short name T385
Test name
Test status
Simulation time 69855884698 ps
CPU time 1406.47 seconds
Started Jul 29 07:42:18 PM PDT 24
Finished Jul 29 08:05:45 PM PDT 24
Peak memory 282584 kb
Host smart-d20ff76a-fb2a-4979-ad7b-e5d45ec0138c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344007905 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.3344007905
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.1333699055
Short name T497
Test name
Test status
Simulation time 5763400221 ps
CPU time 37.27 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:58 PM PDT 24
Peak memory 242000 kb
Host smart-45c55eb3-6ae5-4d60-8bd0-b7fd5215f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333699055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1333699055
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.635205374
Short name T164
Test name
Test status
Simulation time 1779040647 ps
CPU time 5.86 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:02 PM PDT 24
Peak memory 242164 kb
Host smart-82fc9d15-d675-41b2-8607-024eb71c19d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635205374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.635205374
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.1580415186
Short name T60
Test name
Test status
Simulation time 281437140 ps
CPU time 3.87 seconds
Started Jul 29 07:48:54 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 242164 kb
Host smart-d4abff46-ce56-4ed9-8bfb-d566f5892328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580415186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1580415186
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.362493260
Short name T977
Test name
Test status
Simulation time 449175069 ps
CPU time 4.9 seconds
Started Jul 29 07:48:52 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242204 kb
Host smart-dfac6674-4364-4644-ade3-fcf9c2bc76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362493260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.362493260
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3015332831
Short name T1191
Test name
Test status
Simulation time 115305664 ps
CPU time 3.34 seconds
Started Jul 29 07:49:02 PM PDT 24
Finished Jul 29 07:49:05 PM PDT 24
Peak memory 242356 kb
Host smart-91aa0671-dbd6-41e8-9276-6ee0c429a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015332831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3015332831
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1785399236
Short name T1053
Test name
Test status
Simulation time 263778013 ps
CPU time 3.7 seconds
Started Jul 29 07:49:03 PM PDT 24
Finished Jul 29 07:49:06 PM PDT 24
Peak memory 242416 kb
Host smart-c25b5de6-8ee2-47c9-b513-f02319b01e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785399236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1785399236
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2671051352
Short name T545
Test name
Test status
Simulation time 198454677 ps
CPU time 4.92 seconds
Started Jul 29 07:48:59 PM PDT 24
Finished Jul 29 07:49:04 PM PDT 24
Peak memory 242180 kb
Host smart-615ba7ea-ad32-4076-838e-9d044389365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671051352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2671051352
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.4044891588
Short name T401
Test name
Test status
Simulation time 176209078 ps
CPU time 4.86 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 241996 kb
Host smart-12e786fd-eeae-40ca-8406-77db7a22bda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044891588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.4044891588
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2151327162
Short name T524
Test name
Test status
Simulation time 236370207 ps
CPU time 4.4 seconds
Started Jul 29 07:48:50 PM PDT 24
Finished Jul 29 07:48:55 PM PDT 24
Peak memory 242060 kb
Host smart-a300b765-53b1-432f-923d-b00394eeff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151327162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2151327162
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.553034697
Short name T913
Test name
Test status
Simulation time 119499516 ps
CPU time 3.16 seconds
Started Jul 29 07:48:55 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 242108 kb
Host smart-b3d06686-a8ff-4c69-95df-f24a2e996ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553034697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.553034697
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3322038911
Short name T411
Test name
Test status
Simulation time 151333900 ps
CPU time 1.8 seconds
Started Jul 29 07:42:35 PM PDT 24
Finished Jul 29 07:42:37 PM PDT 24
Peak memory 240440 kb
Host smart-68272ea0-b308-467d-a857-f99a21261863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322038911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3322038911
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2055085345
Short name T1164
Test name
Test status
Simulation time 1907443542 ps
CPU time 11.06 seconds
Started Jul 29 07:42:34 PM PDT 24
Finished Jul 29 07:42:45 PM PDT 24
Peak memory 242656 kb
Host smart-15288449-a39f-4931-b474-3d980bcffcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055085345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2055085345
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3634103748
Short name T1048
Test name
Test status
Simulation time 5812020008 ps
CPU time 46.74 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:43:19 PM PDT 24
Peak memory 249472 kb
Host smart-4a9d643c-4d3a-4692-8627-909673f9a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634103748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3634103748
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.3261492770
Short name T753
Test name
Test status
Simulation time 150848503 ps
CPU time 3.94 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:26 PM PDT 24
Peak memory 241824 kb
Host smart-c70e1da4-88e1-4021-bfc4-8ba19472c61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261492770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3261492770
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2164090869
Short name T180
Test name
Test status
Simulation time 271570110 ps
CPU time 3.3 seconds
Started Jul 29 07:42:21 PM PDT 24
Finished Jul 29 07:42:24 PM PDT 24
Peak memory 241848 kb
Host smart-55ab5a2c-4e69-4fa3-a31a-8f47ca3cdbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164090869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2164090869
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.2375305010
Short name T924
Test name
Test status
Simulation time 333372696 ps
CPU time 9.67 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:42:40 PM PDT 24
Peak memory 243168 kb
Host smart-9e14828b-de51-4a1c-a0fc-cc03ba634096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375305010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2375305010
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.2583907133
Short name T1105
Test name
Test status
Simulation time 641806428 ps
CPU time 6.95 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:42:37 PM PDT 24
Peak memory 242092 kb
Host smart-e1ea71cc-eb7b-4857-83cd-49c498ce4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583907133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2583907133
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2679953308
Short name T1175
Test name
Test status
Simulation time 3156839071 ps
CPU time 12.97 seconds
Started Jul 29 07:42:22 PM PDT 24
Finished Jul 29 07:42:35 PM PDT 24
Peak memory 241944 kb
Host smart-a9378974-0d65-48d5-bd6e-3dbbdb5a7c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679953308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2679953308
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.1308827834
Short name T124
Test name
Test status
Simulation time 5774424743 ps
CPU time 16.57 seconds
Started Jul 29 07:42:18 PM PDT 24
Finished Jul 29 07:42:35 PM PDT 24
Peak memory 248716 kb
Host smart-61fd1acd-4492-4954-9038-761a3a32d45a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308827834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1308827834
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.1275595732
Short name T355
Test name
Test status
Simulation time 113713435 ps
CPU time 4.15 seconds
Started Jul 29 07:42:35 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 241856 kb
Host smart-915aa3f5-40f4-4e8f-b84f-3125b6c8240a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1275595732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1275595732
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2130863547
Short name T318
Test name
Test status
Simulation time 666402288 ps
CPU time 5.17 seconds
Started Jul 29 07:42:20 PM PDT 24
Finished Jul 29 07:42:26 PM PDT 24
Peak memory 242284 kb
Host smart-5fdff689-a975-4412-b6b6-2d5f286d2861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130863547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2130863547
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.2215463733
Short name T880
Test name
Test status
Simulation time 49847212872 ps
CPU time 138.01 seconds
Started Jul 29 07:42:31 PM PDT 24
Finished Jul 29 07:44:49 PM PDT 24
Peak memory 261464 kb
Host smart-a6dccc3e-2c26-482f-86ca-ed897fb9ae0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215463733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.2215463733
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.661245402
Short name T522
Test name
Test status
Simulation time 2392301950 ps
CPU time 26.54 seconds
Started Jul 29 07:42:34 PM PDT 24
Finished Jul 29 07:43:00 PM PDT 24
Peak memory 242088 kb
Host smart-185fdb7b-0ce4-4b71-8c0c-67321340afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661245402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.661245402
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3141223231
Short name T1131
Test name
Test status
Simulation time 2204853348 ps
CPU time 7.72 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:03 PM PDT 24
Peak memory 242308 kb
Host smart-c673b2e9-3526-4c05-912b-0c7e42b9b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141223231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3141223231
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3659687586
Short name T909
Test name
Test status
Simulation time 436537076 ps
CPU time 3.55 seconds
Started Jul 29 07:49:02 PM PDT 24
Finished Jul 29 07:49:06 PM PDT 24
Peak memory 242288 kb
Host smart-208ef6b2-433b-4493-a9ff-775f53cf2628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659687586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3659687586
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3884290575
Short name T480
Test name
Test status
Simulation time 332227731 ps
CPU time 3.4 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242212 kb
Host smart-3693445e-dd50-4b5e-b047-f802aee3f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884290575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3884290575
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.462081098
Short name T230
Test name
Test status
Simulation time 222785083 ps
CPU time 4.02 seconds
Started Jul 29 07:48:57 PM PDT 24
Finished Jul 29 07:49:01 PM PDT 24
Peak memory 241916 kb
Host smart-f0ef7268-ad8e-4294-aae4-46a2583f8fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462081098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.462081098
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.1220663001
Short name T321
Test name
Test status
Simulation time 116196667 ps
CPU time 4.69 seconds
Started Jul 29 07:48:52 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242232 kb
Host smart-c947fd10-5276-4981-a90e-def3d92beed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220663001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1220663001
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.1356473833
Short name T457
Test name
Test status
Simulation time 191387651 ps
CPU time 3.91 seconds
Started Jul 29 07:48:55 PM PDT 24
Finished Jul 29 07:48:59 PM PDT 24
Peak memory 242008 kb
Host smart-033dd3b3-10a3-4713-866b-b6ac6d642c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356473833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1356473833
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.269667503
Short name T1102
Test name
Test status
Simulation time 119073806 ps
CPU time 4.09 seconds
Started Jul 29 07:48:54 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 242004 kb
Host smart-810540a3-c0fb-4809-9566-176780878fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269667503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.269667503
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.190860607
Short name T649
Test name
Test status
Simulation time 1589115059 ps
CPU time 4.34 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 241920 kb
Host smart-6989082a-3682-4ecf-8912-593f9df78a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190860607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.190860607
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2511736374
Short name T458
Test name
Test status
Simulation time 168175927 ps
CPU time 2.07 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:42:33 PM PDT 24
Peak memory 240416 kb
Host smart-88cd0651-ca9b-4e7e-93f6-42af72a4c4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511736374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2511736374
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.3130629571
Short name T71
Test name
Test status
Simulation time 1061598428 ps
CPU time 19.09 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:48 PM PDT 24
Peak memory 244392 kb
Host smart-c0c0fb71-48d0-42dd-9829-17ee48dd2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130629571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3130629571
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.203829020
Short name T1011
Test name
Test status
Simulation time 822921927 ps
CPU time 25.02 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:42:58 PM PDT 24
Peak memory 242016 kb
Host smart-29d17b14-ee41-4118-aa77-4195b30c3490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203829020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.203829020
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.588569023
Short name T902
Test name
Test status
Simulation time 1043161301 ps
CPU time 25.15 seconds
Started Jul 29 07:42:33 PM PDT 24
Finished Jul 29 07:42:59 PM PDT 24
Peak memory 242456 kb
Host smart-a89c314c-0d96-4dc0-811e-dcec081c3e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588569023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.588569023
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.355060598
Short name T121
Test name
Test status
Simulation time 147941761 ps
CPU time 3.76 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:33 PM PDT 24
Peak memory 242120 kb
Host smart-9bd0ea34-83aa-439c-9ae1-925b763695e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355060598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.355060598
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.751271378
Short name T680
Test name
Test status
Simulation time 8991363639 ps
CPU time 21.61 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 248556 kb
Host smart-6ca99b11-68ed-4386-9be5-2a65ef10d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751271378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.751271378
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1659653219
Short name T433
Test name
Test status
Simulation time 3598095616 ps
CPU time 9.74 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:42:42 PM PDT 24
Peak memory 242876 kb
Host smart-2c588090-d486-42f3-bee8-6b88d36c571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659653219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1659653219
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.955911849
Short name T373
Test name
Test status
Simulation time 599768702 ps
CPU time 17.95 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:42:48 PM PDT 24
Peak memory 242164 kb
Host smart-dfc2a94f-e533-4bda-9846-477bd4c7ac52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955911849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.955911849
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1330487310
Short name T814
Test name
Test status
Simulation time 269841310 ps
CPU time 9.82 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:42:40 PM PDT 24
Peak memory 242008 kb
Host smart-2712cafb-f069-424a-b4c0-d5b8238f3e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330487310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1330487310
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1742037194
Short name T466
Test name
Test status
Simulation time 378034043 ps
CPU time 12.03 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:41 PM PDT 24
Peak memory 242168 kb
Host smart-8b7350e9-cf31-4c04-a3ce-9b6944a164c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742037194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1742037194
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.1597323409
Short name T768
Test name
Test status
Simulation time 45608279955 ps
CPU time 130.51 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:44:41 PM PDT 24
Peak memory 248584 kb
Host smart-b79ad3e1-e75d-4e89-ad29-6a89dd6aad6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597323409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.1597323409
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.699863121
Short name T135
Test name
Test status
Simulation time 392611243959 ps
CPU time 3104.94 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 08:34:18 PM PDT 24
Peak memory 584188 kb
Host smart-3925e721-58df-40ae-a4f1-ad9f38101940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699863121 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.699863121
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.1533366732
Short name T724
Test name
Test status
Simulation time 3004853066 ps
CPU time 26.87 seconds
Started Jul 29 07:42:31 PM PDT 24
Finished Jul 29 07:42:58 PM PDT 24
Peak memory 242920 kb
Host smart-120ba9ca-7c66-4af8-a8b5-af1140c14934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533366732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1533366732
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.3396454116
Short name T1015
Test name
Test status
Simulation time 97942404 ps
CPU time 4.25 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:58 PM PDT 24
Peak memory 241928 kb
Host smart-5c1bdb52-2651-4ff7-9c13-fe8ec4f6f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396454116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3396454116
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1099103539
Short name T817
Test name
Test status
Simulation time 491657176 ps
CPU time 5.39 seconds
Started Jul 29 07:48:54 PM PDT 24
Finished Jul 29 07:48:59 PM PDT 24
Peak memory 242228 kb
Host smart-0a8b658e-c013-4050-a987-1cc62a6e5aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099103539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1099103539
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.918052807
Short name T689
Test name
Test status
Simulation time 2602164578 ps
CPU time 7.81 seconds
Started Jul 29 07:48:55 PM PDT 24
Finished Jul 29 07:49:03 PM PDT 24
Peak memory 242196 kb
Host smart-85ec7439-77f8-4412-a6ba-d82ce68bee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918052807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.918052807
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.3840075440
Short name T28
Test name
Test status
Simulation time 278308246 ps
CPU time 4.64 seconds
Started Jul 29 07:48:55 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 241980 kb
Host smart-40d6de10-1aea-4d6a-a4b7-af5b68d830f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840075440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3840075440
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1761338031
Short name T1012
Test name
Test status
Simulation time 246556422 ps
CPU time 5.52 seconds
Started Jul 29 07:49:00 PM PDT 24
Finished Jul 29 07:49:05 PM PDT 24
Peak memory 242376 kb
Host smart-feda3174-49bc-45e4-94a4-b8df021dcc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761338031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1761338031
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2267765832
Short name T465
Test name
Test status
Simulation time 313034726 ps
CPU time 3.98 seconds
Started Jul 29 07:48:57 PM PDT 24
Finished Jul 29 07:49:01 PM PDT 24
Peak memory 242244 kb
Host smart-be324fca-13d3-450e-8cf1-540dff33f644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267765832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2267765832
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2337230760
Short name T947
Test name
Test status
Simulation time 2059881672 ps
CPU time 6 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:59 PM PDT 24
Peak memory 242008 kb
Host smart-70a197bc-485d-45e3-be77-5a07994e524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337230760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2337230760
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.389930667
Short name T153
Test name
Test status
Simulation time 109893303 ps
CPU time 4.27 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:01 PM PDT 24
Peak memory 242108 kb
Host smart-32525a14-4b7e-4033-8f35-2b770f355eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389930667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.389930667
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1875111923
Short name T1111
Test name
Test status
Simulation time 151973717 ps
CPU time 1.58 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:42:34 PM PDT 24
Peak memory 240436 kb
Host smart-8c5dba40-ca37-4f89-aa6b-6783b5dc1cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875111923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1875111923
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3695584013
Short name T115
Test name
Test status
Simulation time 2323089567 ps
CPU time 6.24 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 241996 kb
Host smart-1c237a33-a78b-41a7-9d64-dddce42a3215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695584013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3695584013
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1990628188
Short name T1070
Test name
Test status
Simulation time 934157936 ps
CPU time 14.28 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:42:46 PM PDT 24
Peak memory 242392 kb
Host smart-53c05389-04b8-45ad-a087-88588b4c2bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990628188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1990628188
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.4150891108
Short name T427
Test name
Test status
Simulation time 541107633 ps
CPU time 6.59 seconds
Started Jul 29 07:42:34 PM PDT 24
Finished Jul 29 07:42:40 PM PDT 24
Peak memory 241812 kb
Host smart-a3324cfe-6772-4978-8781-d8779af2664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150891108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4150891108
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3034089420
Short name T912
Test name
Test status
Simulation time 445371767 ps
CPU time 3.77 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:32 PM PDT 24
Peak memory 241964 kb
Host smart-650a1ceb-b57e-4a3f-84cd-26488bbf8b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034089420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3034089420
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.1039320293
Short name T499
Test name
Test status
Simulation time 178642917 ps
CPU time 3.77 seconds
Started Jul 29 07:42:35 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 242084 kb
Host smart-76095afb-e358-44d4-ae22-4f9d7f7ab0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039320293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1039320293
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.2110087171
Short name T423
Test name
Test status
Simulation time 465586210 ps
CPU time 12.48 seconds
Started Jul 29 07:42:35 PM PDT 24
Finished Jul 29 07:42:48 PM PDT 24
Peak memory 242160 kb
Host smart-5606c863-ce32-4f72-a213-a840b6407985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110087171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2110087171
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.3594153513
Short name T324
Test name
Test status
Simulation time 185762683 ps
CPU time 3.86 seconds
Started Jul 29 07:42:35 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 242256 kb
Host smart-73722f23-4b48-4318-b0a3-f2a4114131bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594153513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3594153513
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.570400778
Short name T374
Test name
Test status
Simulation time 1762751135 ps
CPU time 14.83 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:44 PM PDT 24
Peak memory 242344 kb
Host smart-fac3f157-4bae-4548-b299-083c6cd42b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570400778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.570400778
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.354855277
Short name T828
Test name
Test status
Simulation time 129305495 ps
CPU time 2.97 seconds
Started Jul 29 07:42:29 PM PDT 24
Finished Jul 29 07:42:32 PM PDT 24
Peak memory 241860 kb
Host smart-a91e3361-96aa-461e-bdf5-4c3a75dc1fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354855277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.354855277
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1321396422
Short name T794
Test name
Test status
Simulation time 1044137083 ps
CPU time 7.01 seconds
Started Jul 29 07:42:31 PM PDT 24
Finished Jul 29 07:42:38 PM PDT 24
Peak memory 242016 kb
Host smart-9f9d5042-f378-4199-9b1f-1aa5faf393e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321396422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1321396422
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3400668790
Short name T481
Test name
Test status
Simulation time 4283829091 ps
CPU time 63.75 seconds
Started Jul 29 07:42:32 PM PDT 24
Finished Jul 29 07:43:36 PM PDT 24
Peak memory 244468 kb
Host smart-fa1bb0f1-9deb-4484-9238-fa0a91568849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400668790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3400668790
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1508048507
Short name T696
Test name
Test status
Simulation time 29500254195 ps
CPU time 610.2 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:52:40 PM PDT 24
Peak memory 327200 kb
Host smart-d0ef923a-eab1-4843-886d-f4d9310d25cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508048507 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.1508048507
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2249728859
Short name T93
Test name
Test status
Simulation time 2242898232 ps
CPU time 26.98 seconds
Started Jul 29 07:42:33 PM PDT 24
Finished Jul 29 07:43:00 PM PDT 24
Peak memory 242548 kb
Host smart-f152d48c-481e-48a0-b014-91bb5715f6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249728859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2249728859
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.811208060
Short name T728
Test name
Test status
Simulation time 387442907 ps
CPU time 3.88 seconds
Started Jul 29 07:48:55 PM PDT 24
Finished Jul 29 07:48:59 PM PDT 24
Peak memory 242172 kb
Host smart-53ef52ef-cba8-402b-98c9-4fedbd6a85a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811208060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.811208060
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1435976826
Short name T914
Test name
Test status
Simulation time 119359112 ps
CPU time 4.11 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:00 PM PDT 24
Peak memory 242400 kb
Host smart-6fa9c8aa-d479-40a6-bb0e-94b0df574ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435976826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1435976826
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.1313677891
Short name T1109
Test name
Test status
Simulation time 104216233 ps
CPU time 4.09 seconds
Started Jul 29 07:48:58 PM PDT 24
Finished Jul 29 07:49:02 PM PDT 24
Peak memory 242392 kb
Host smart-6688296d-3339-4af4-a26f-c231ead3680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313677891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1313677891
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2851822578
Short name T747
Test name
Test status
Simulation time 108249925 ps
CPU time 3.89 seconds
Started Jul 29 07:48:53 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242064 kb
Host smart-2a9a0cf1-e5b4-4f39-a673-7546ac5a3941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851822578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2851822578
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2566082756
Short name T1023
Test name
Test status
Simulation time 1806537589 ps
CPU time 5.33 seconds
Started Jul 29 07:48:56 PM PDT 24
Finished Jul 29 07:49:02 PM PDT 24
Peak memory 242252 kb
Host smart-3e8c648b-6c77-4c2a-82f1-dac62aa87700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566082756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2566082756
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2489695449
Short name T221
Test name
Test status
Simulation time 424497089 ps
CPU time 4.05 seconds
Started Jul 29 07:48:59 PM PDT 24
Finished Jul 29 07:49:03 PM PDT 24
Peak memory 241980 kb
Host smart-5642a1b2-d93a-4224-9c27-e7c3047d3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489695449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2489695449
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.6094355
Short name T982
Test name
Test status
Simulation time 646659445 ps
CPU time 4.16 seconds
Started Jul 29 07:48:52 PM PDT 24
Finished Jul 29 07:48:57 PM PDT 24
Peak memory 242168 kb
Host smart-ff595b69-85a4-4395-b278-d49156326247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6094355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.6094355
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.867036118
Short name T770
Test name
Test status
Simulation time 133939918 ps
CPU time 4.05 seconds
Started Jul 29 07:49:17 PM PDT 24
Finished Jul 29 07:49:21 PM PDT 24
Peak memory 242312 kb
Host smart-ae0c8231-76da-44b2-9d57-74f4e04ee7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867036118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.867036118
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.2360429852
Short name T570
Test name
Test status
Simulation time 97692634 ps
CPU time 1.97 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:42:47 PM PDT 24
Peak memory 240436 kb
Host smart-32149ee2-99b8-46bf-b5bd-fd0a98158e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360429852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2360429852
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1803035597
Short name T713
Test name
Test status
Simulation time 17062879425 ps
CPU time 49.51 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:43:19 PM PDT 24
Peak memory 249244 kb
Host smart-362f2b76-11e6-4dbc-b578-8af3ebd1f2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803035597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1803035597
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.3105593660
Short name T647
Test name
Test status
Simulation time 179788156 ps
CPU time 7.51 seconds
Started Jul 29 07:42:33 PM PDT 24
Finished Jul 29 07:42:41 PM PDT 24
Peak memory 248612 kb
Host smart-bc917e84-10e5-47eb-a6e2-e76daafc4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105593660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3105593660
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.3284375833
Short name T641
Test name
Test status
Simulation time 619033720 ps
CPU time 4.94 seconds
Started Jul 29 07:42:30 PM PDT 24
Finished Jul 29 07:42:35 PM PDT 24
Peak memory 242164 kb
Host smart-324f940b-ac25-433f-9e3c-09dd33d0bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284375833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3284375833
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.320927759
Short name T648
Test name
Test status
Simulation time 476505809 ps
CPU time 10.01 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:42:55 PM PDT 24
Peak memory 242648 kb
Host smart-88f3a6a7-321f-4336-a764-504abc5f21fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320927759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.320927759
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2232868666
Short name T702
Test name
Test status
Simulation time 14892769455 ps
CPU time 38.52 seconds
Started Jul 29 07:42:44 PM PDT 24
Finished Jul 29 07:43:23 PM PDT 24
Peak memory 248648 kb
Host smart-4e4a8044-5ea8-4129-be83-2ed33501c189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232868666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2232868666
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.3278848562
Short name T1125
Test name
Test status
Simulation time 400932967 ps
CPU time 9.25 seconds
Started Jul 29 07:42:28 PM PDT 24
Finished Jul 29 07:42:38 PM PDT 24
Peak memory 241964 kb
Host smart-2b8874e1-78e3-48e1-b480-1cdb629684e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278848562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3278848562
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3905534037
Short name T441
Test name
Test status
Simulation time 713738867 ps
CPU time 6.74 seconds
Started Jul 29 07:42:35 PM PDT 24
Finished Jul 29 07:42:42 PM PDT 24
Peak memory 241980 kb
Host smart-ebc072c4-50d9-422b-a22e-d2c0a141cb7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905534037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3905534037
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.411090428
Short name T90
Test name
Test status
Simulation time 219636512 ps
CPU time 3.54 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 242100 kb
Host smart-b661419a-a75a-4f9c-a21e-fe271d655cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411090428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.411090428
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.3671749853
Short name T883
Test name
Test status
Simulation time 3695403717 ps
CPU time 5.15 seconds
Started Jul 29 07:42:34 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 242384 kb
Host smart-edd563b9-358d-406b-940f-48655ed5bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671749853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3671749853
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3752254862
Short name T626
Test name
Test status
Simulation time 24186135959 ps
CPU time 584.23 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:52:32 PM PDT 24
Peak memory 273396 kb
Host smart-edbeb239-e24a-4f22-9db7-6190455b42b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752254862 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3752254862
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.1528190066
Short name T531
Test name
Test status
Simulation time 252970823 ps
CPU time 5.54 seconds
Started Jul 29 07:42:50 PM PDT 24
Finished Jul 29 07:42:55 PM PDT 24
Peak memory 242188 kb
Host smart-1864a29c-5193-439f-9978-429cf43f1e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528190066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1528190066
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2577923323
Short name T525
Test name
Test status
Simulation time 145569756 ps
CPU time 4.45 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 242032 kb
Host smart-d68a10d9-c128-4ccf-82d0-feecd80ce02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577923323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2577923323
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.3255124932
Short name T211
Test name
Test status
Simulation time 227534214 ps
CPU time 3.93 seconds
Started Jul 29 07:49:11 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 242364 kb
Host smart-2543d0e5-18e8-4117-8f10-e52783b95a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255124932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3255124932
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.371245284
Short name T948
Test name
Test status
Simulation time 99957368 ps
CPU time 3.51 seconds
Started Jul 29 07:49:14 PM PDT 24
Finished Jul 29 07:49:17 PM PDT 24
Peak memory 242408 kb
Host smart-ea2fb65a-d24e-4d50-89c8-27ced0000da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371245284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.371245284
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.1926751680
Short name T612
Test name
Test status
Simulation time 103659402 ps
CPU time 3.73 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 242232 kb
Host smart-75bcec83-31c0-4c0c-bf3a-2b19a302c49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926751680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1926751680
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.89607512
Short name T2
Test name
Test status
Simulation time 104459686 ps
CPU time 4.31 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 242176 kb
Host smart-56eda619-a922-46f0-898c-b6ae2818299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89607512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.89607512
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1598415202
Short name T625
Test name
Test status
Simulation time 339046756 ps
CPU time 5.07 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 242384 kb
Host smart-8c678eb8-3612-4e31-b3c9-bd4d37d90041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598415202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1598415202
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.3270875314
Short name T48
Test name
Test status
Simulation time 151381933 ps
CPU time 3.75 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:13 PM PDT 24
Peak memory 242052 kb
Host smart-197f0230-1710-4a5a-a1fc-84cc285e6cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270875314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3270875314
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1816539742
Short name T707
Test name
Test status
Simulation time 127956028 ps
CPU time 4.44 seconds
Started Jul 29 07:49:08 PM PDT 24
Finished Jul 29 07:49:13 PM PDT 24
Peak memory 242092 kb
Host smart-cddd319a-f315-47bd-a57f-36f21d06012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816539742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1816539742
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3088066766
Short name T327
Test name
Test status
Simulation time 252665714 ps
CPU time 4.49 seconds
Started Jul 29 07:49:15 PM PDT 24
Finished Jul 29 07:49:19 PM PDT 24
Peak memory 242020 kb
Host smart-beb93490-777b-430f-9353-f6ffef1ba508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088066766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3088066766
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.2929710582
Short name T931
Test name
Test status
Simulation time 243273294 ps
CPU time 3.95 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:13 PM PDT 24
Peak memory 241996 kb
Host smart-a9d5e1fa-e54b-42fa-ba75-eb5c4a1dfe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929710582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2929710582
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2792344937
Short name T567
Test name
Test status
Simulation time 793656990 ps
CPU time 2.15 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:42:47 PM PDT 24
Peak memory 240352 kb
Host smart-a617fbb3-4dde-4090-b3f5-b42af637311e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792344937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2792344937
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.350682044
Short name T322
Test name
Test status
Simulation time 660281718 ps
CPU time 24.66 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:43:13 PM PDT 24
Peak memory 240852 kb
Host smart-5530fe0c-01d3-4b16-be5a-150e29eb56b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350682044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.350682044
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.3371229184
Short name T1138
Test name
Test status
Simulation time 690540821 ps
CPU time 10.58 seconds
Started Jul 29 07:42:44 PM PDT 24
Finished Jul 29 07:42:55 PM PDT 24
Peak memory 242088 kb
Host smart-77ff064c-9191-471c-9611-f1dafaf917cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371229184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3371229184
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1725328579
Short name T593
Test name
Test status
Simulation time 1669212510 ps
CPU time 4.82 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:42:53 PM PDT 24
Peak memory 242260 kb
Host smart-8c8e19fc-f01b-4191-812f-48ab99ecb934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725328579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1725328579
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.666409781
Short name T191
Test name
Test status
Simulation time 2108615439 ps
CPU time 45.61 seconds
Started Jul 29 07:42:50 PM PDT 24
Finished Jul 29 07:43:36 PM PDT 24
Peak memory 257244 kb
Host smart-1d7a51f1-65c6-42f3-88cc-0d927e7fdb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666409781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.666409781
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.3946789527
Short name T1050
Test name
Test status
Simulation time 958813216 ps
CPU time 25.55 seconds
Started Jul 29 07:42:46 PM PDT 24
Finished Jul 29 07:43:12 PM PDT 24
Peak memory 242396 kb
Host smart-b5ac15f9-257a-410c-8b95-a984a8047a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946789527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3946789527
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3111087615
Short name T918
Test name
Test status
Simulation time 344848546 ps
CPU time 6.97 seconds
Started Jul 29 07:42:44 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 241884 kb
Host smart-015c97ee-e229-4392-85f5-54b5187efda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111087615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3111087615
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.1646640646
Short name T722
Test name
Test status
Simulation time 787212771 ps
CPU time 7.63 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:42:55 PM PDT 24
Peak memory 242344 kb
Host smart-f239f9a8-3cdd-48b5-8b3c-a8d3bf6f1b8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646640646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1646640646
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.4052220416
Short name T352
Test name
Test status
Simulation time 1327367348 ps
CPU time 12.73 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:42:58 PM PDT 24
Peak memory 241932 kb
Host smart-ce885551-da14-4c82-b004-9d695458116d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052220416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.4052220416
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1043782136
Short name T890
Test name
Test status
Simulation time 3189380762 ps
CPU time 7.82 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:42:56 PM PDT 24
Peak memory 242024 kb
Host smart-bfc3b0bc-3bca-4eec-a590-c439d04e17c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043782136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1043782136
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.361913863
Short name T1172
Test name
Test status
Simulation time 91938685773 ps
CPU time 200.72 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:46:06 PM PDT 24
Peak memory 265032 kb
Host smart-e4e04940-814e-4caa-aec3-d43d3ef29300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361913863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.
361913863
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2533572473
Short name T314
Test name
Test status
Simulation time 352719883076 ps
CPU time 743.19 seconds
Started Jul 29 07:42:51 PM PDT 24
Finished Jul 29 07:55:14 PM PDT 24
Peak memory 325180 kb
Host smart-080f6918-cbe1-4f49-8a0e-6dcfb6220764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533572473 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.2533572473
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.2769615255
Short name T627
Test name
Test status
Simulation time 467837016 ps
CPU time 5.25 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:42:52 PM PDT 24
Peak memory 242036 kb
Host smart-8084e28e-1a61-43b8-91f0-0909e377152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769615255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2769615255
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.3121796138
Short name T195
Test name
Test status
Simulation time 217683356 ps
CPU time 4.12 seconds
Started Jul 29 07:49:17 PM PDT 24
Finished Jul 29 07:49:21 PM PDT 24
Peak memory 242244 kb
Host smart-e3f1a3e3-2ad5-41e4-8a70-ca9742e0d3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121796138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.3121796138
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2794652021
Short name T579
Test name
Test status
Simulation time 2006122640 ps
CPU time 6.58 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:17 PM PDT 24
Peak memory 242356 kb
Host smart-0e59ec6a-f1f7-4397-aaec-581e9e7f8e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794652021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2794652021
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.3532709819
Short name T774
Test name
Test status
Simulation time 197263290 ps
CPU time 4.4 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 241972 kb
Host smart-bfb14fc5-7a5d-485d-a408-b83dbd72d9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532709819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3532709819
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.2192332707
Short name T415
Test name
Test status
Simulation time 111422185 ps
CPU time 3.05 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 241976 kb
Host smart-5124035c-cdc6-4dca-8f24-17b402eb0025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192332707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2192332707
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3987410587
Short name T870
Test name
Test status
Simulation time 180525114 ps
CPU time 5.11 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 242320 kb
Host smart-a8b01943-5a8d-4c91-917b-7163c04552f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987410587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3987410587
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1986998733
Short name T472
Test name
Test status
Simulation time 144686917 ps
CPU time 4.1 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:13 PM PDT 24
Peak memory 242004 kb
Host smart-1a021841-f6ad-4cdb-ab22-1a6f8bc5f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986998733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1986998733
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.2342672795
Short name T46
Test name
Test status
Simulation time 2777205031 ps
CPU time 6.97 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:17 PM PDT 24
Peak memory 242064 kb
Host smart-554c6f4d-e657-4cab-84b7-9710864626eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342672795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2342672795
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.1579503930
Short name T444
Test name
Test status
Simulation time 1873177748 ps
CPU time 6.97 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:17 PM PDT 24
Peak memory 241984 kb
Host smart-1b11a49d-b0bd-4045-ac1f-6e2518a15a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579503930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1579503930
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3153223621
Short name T182
Test name
Test status
Simulation time 291528914 ps
CPU time 3.96 seconds
Started Jul 29 07:49:10 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 241964 kb
Host smart-e1f71de4-2099-4b13-b60b-45fd718694c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153223621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3153223621
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3008509800
Short name T1168
Test name
Test status
Simulation time 128319341 ps
CPU time 3.62 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 242204 kb
Host smart-efc5b07d-c51c-47f5-8ebe-5d9d3dd24dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008509800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3008509800
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3954527350
Short name T425
Test name
Test status
Simulation time 67403869 ps
CPU time 1.79 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:42:49 PM PDT 24
Peak memory 240420 kb
Host smart-f597cd79-fb31-40d2-966c-ef365768f93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954527350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3954527350
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.3588709915
Short name T541
Test name
Test status
Simulation time 2741051339 ps
CPU time 6.81 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:42:54 PM PDT 24
Peak memory 242692 kb
Host smart-6d27a206-6fbc-4b09-85b0-ad77dfbed21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588709915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3588709915
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3601719807
Short name T971
Test name
Test status
Simulation time 1285266750 ps
CPU time 24.48 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:43:09 PM PDT 24
Peak memory 242004 kb
Host smart-d7782385-171f-4f39-81d7-a82ee5daaf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601719807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3601719807
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.760196666
Short name T382
Test name
Test status
Simulation time 921292952 ps
CPU time 14.47 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:43:01 PM PDT 24
Peak memory 242316 kb
Host smart-f7a294de-5228-4559-9c48-5932278091f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760196666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.760196666
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.569641536
Short name T216
Test name
Test status
Simulation time 2100113676 ps
CPU time 5.56 seconds
Started Jul 29 07:42:46 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 242388 kb
Host smart-69956782-cba7-4069-84f6-9ea9de1156cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569641536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.569641536
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.945847638
Short name T334
Test name
Test status
Simulation time 6227977398 ps
CPU time 12.69 seconds
Started Jul 29 07:42:47 PM PDT 24
Finished Jul 29 07:43:00 PM PDT 24
Peak memory 242012 kb
Host smart-47da1b98-eadf-4ee3-a337-ca8b73456d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945847638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.945847638
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.2462517244
Short name T631
Test name
Test status
Simulation time 169957724 ps
CPU time 4.53 seconds
Started Jul 29 07:42:46 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 248632 kb
Host smart-ef054f6e-eacb-4df9-93a9-c1e0921c5fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462517244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2462517244
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1265121713
Short name T708
Test name
Test status
Simulation time 754431870 ps
CPU time 6.19 seconds
Started Jul 29 07:42:45 PM PDT 24
Finished Jul 29 07:42:51 PM PDT 24
Peak memory 242276 kb
Host smart-d26074cf-0564-48d7-8182-b0c4fea998a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265121713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1265121713
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.296551609
Short name T402
Test name
Test status
Simulation time 210840852 ps
CPU time 6.12 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:42:54 PM PDT 24
Peak memory 241888 kb
Host smart-cde3be4f-e25b-4fe3-87ed-a9d6efdc964b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296551609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.296551609
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.4008624007
Short name T323
Test name
Test status
Simulation time 3399011903 ps
CPU time 7.45 seconds
Started Jul 29 07:42:48 PM PDT 24
Finished Jul 29 07:42:56 PM PDT 24
Peak memory 241148 kb
Host smart-5e3dc937-8b41-4633-851e-55b648b693cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008624007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.4008624007
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.564278515
Short name T621
Test name
Test status
Simulation time 1230460086 ps
CPU time 8 seconds
Started Jul 29 07:42:51 PM PDT 24
Finished Jul 29 07:42:59 PM PDT 24
Peak memory 242100 kb
Host smart-08a04a45-8fc5-4cbb-abe9-3d371c9cecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564278515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.564278515
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.139492011
Short name T34
Test name
Test status
Simulation time 440750758 ps
CPU time 5.41 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 242240 kb
Host smart-949fef62-be77-43a2-b9de-44f47214b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139492011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.139492011
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.2821284598
Short name T653
Test name
Test status
Simulation time 114071772 ps
CPU time 3.67 seconds
Started Jul 29 07:49:28 PM PDT 24
Finished Jul 29 07:49:32 PM PDT 24
Peak memory 242000 kb
Host smart-f8c7b92f-bfe2-4dfc-96c8-d771b2ee5969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821284598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2821284598
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.1767700249
Short name T1005
Test name
Test status
Simulation time 2674144011 ps
CPU time 4.87 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:17 PM PDT 24
Peak memory 241968 kb
Host smart-10f9aa70-736e-4139-8208-22b04d8dfd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767700249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1767700249
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.2230932926
Short name T1073
Test name
Test status
Simulation time 298375915 ps
CPU time 3.93 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:13 PM PDT 24
Peak memory 242136 kb
Host smart-d1b0d610-a130-4d21-a192-9eb54082274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230932926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.2230932926
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.4062041448
Short name T922
Test name
Test status
Simulation time 2504611788 ps
CPU time 7.7 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:20 PM PDT 24
Peak memory 242220 kb
Host smart-ca40e7e0-5da8-4f75-b3ae-1cc0fe97d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062041448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.4062041448
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.1027809438
Short name T41
Test name
Test status
Simulation time 498244637 ps
CPU time 3.77 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:16 PM PDT 24
Peak memory 241976 kb
Host smart-dece132b-9443-48d1-8b75-1e2548d9c2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027809438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1027809438
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.305895516
Short name T560
Test name
Test status
Simulation time 129872990 ps
CPU time 3.83 seconds
Started Jul 29 07:49:11 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 242224 kb
Host smart-1af3f00e-35a4-4724-9956-8207df313c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305895516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.305895516
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.66261793
Short name T976
Test name
Test status
Simulation time 622339388 ps
CPU time 4.98 seconds
Started Jul 29 07:49:18 PM PDT 24
Finished Jul 29 07:49:23 PM PDT 24
Peak memory 242372 kb
Host smart-d211890f-979a-4bfc-9c28-6865ec67eedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66261793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.66261793
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2285760958
Short name T777
Test name
Test status
Simulation time 2086126963 ps
CPU time 5.29 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:14 PM PDT 24
Peak memory 241992 kb
Host smart-59e96651-2b5c-4a9d-91a8-481bc5242f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285760958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2285760958
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3387072006
Short name T534
Test name
Test status
Simulation time 138910656 ps
CPU time 1.58 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:42:58 PM PDT 24
Peak memory 240636 kb
Host smart-8da24dbc-3608-47f7-b15d-c7466b8d9905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387072006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3387072006
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.2761688938
Short name T326
Test name
Test status
Simulation time 1854681175 ps
CPU time 35.37 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:43:32 PM PDT 24
Peak memory 245860 kb
Host smart-effe8013-76ed-4c94-8a38-b781ab3222bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761688938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2761688938
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2970113997
Short name T133
Test name
Test status
Simulation time 2604127344 ps
CPU time 26.67 seconds
Started Jul 29 07:43:05 PM PDT 24
Finished Jul 29 07:43:31 PM PDT 24
Peak memory 242148 kb
Host smart-e54d54a3-52b5-4d50-aea0-521904910d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970113997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2970113997
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3168762361
Short name T1176
Test name
Test status
Simulation time 327679620 ps
CPU time 4.87 seconds
Started Jul 29 07:42:51 PM PDT 24
Finished Jul 29 07:42:56 PM PDT 24
Peak memory 241972 kb
Host smart-19fa69a6-687e-478a-a42d-1a7a5a9335f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168762361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3168762361
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.2011985010
Short name T1093
Test name
Test status
Simulation time 25329518450 ps
CPU time 39.42 seconds
Started Jul 29 07:43:00 PM PDT 24
Finished Jul 29 07:43:39 PM PDT 24
Peak memory 257728 kb
Host smart-5597e4ad-66b4-4e32-a914-0a5ff61f9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011985010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2011985010
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.4123592519
Short name T836
Test name
Test status
Simulation time 211572822 ps
CPU time 5.38 seconds
Started Jul 29 07:43:00 PM PDT 24
Finished Jul 29 07:43:05 PM PDT 24
Peak memory 242216 kb
Host smart-beaea8d7-d402-4836-9b11-738f1f88a916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123592519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4123592519
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.3475783345
Short name T143
Test name
Test status
Simulation time 122155109 ps
CPU time 4.47 seconds
Started Jul 29 07:42:55 PM PDT 24
Finished Jul 29 07:43:00 PM PDT 24
Peak memory 241936 kb
Host smart-01bc5fc5-59b5-40db-92fe-675dffc3ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475783345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.3475783345
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.928769967
Short name T1140
Test name
Test status
Simulation time 763420095 ps
CPU time 22.94 seconds
Started Jul 29 07:42:55 PM PDT 24
Finished Jul 29 07:43:18 PM PDT 24
Peak memory 242336 kb
Host smart-bca72837-427b-450f-9a3b-52e23c72b17a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928769967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.928769967
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.1261537150
Short name T866
Test name
Test status
Simulation time 169891726 ps
CPU time 5.03 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:01 PM PDT 24
Peak memory 241924 kb
Host smart-b09051a9-d31b-4ff5-bc34-0ab704521fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261537150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1261537150
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1230559498
Short name T749
Test name
Test status
Simulation time 1003673421 ps
CPU time 10.49 seconds
Started Jul 29 07:43:04 PM PDT 24
Finished Jul 29 07:43:15 PM PDT 24
Peak memory 242016 kb
Host smart-1b8a9d84-15e8-4501-90d7-0907f56148a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230559498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1230559498
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2221208801
Short name T812
Test name
Test status
Simulation time 41825427162 ps
CPU time 441.58 seconds
Started Jul 29 07:42:55 PM PDT 24
Finished Jul 29 07:50:17 PM PDT 24
Peak memory 295968 kb
Host smart-a57e9cb8-1ba4-4ddd-af38-c82edb119703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221208801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2221208801
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2589787599
Short name T762
Test name
Test status
Simulation time 162340893273 ps
CPU time 2217.73 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 08:19:56 PM PDT 24
Peak memory 694656 kb
Host smart-8fb46c76-f709-4d97-87eb-75dc73aebad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589787599 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.2589787599
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.3886227559
Short name T889
Test name
Test status
Simulation time 766404762 ps
CPU time 14.54 seconds
Started Jul 29 07:42:55 PM PDT 24
Finished Jul 29 07:43:09 PM PDT 24
Peak memory 242556 kb
Host smart-cde9b5a4-0355-4ab6-b08a-e37f4387958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886227559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3886227559
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.777710224
Short name T843
Test name
Test status
Simulation time 128715484 ps
CPU time 3.86 seconds
Started Jul 29 07:49:11 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 242232 kb
Host smart-e19301a8-5adf-4613-a17c-6748cc323377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777710224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.777710224
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.2434518319
Short name T188
Test name
Test status
Simulation time 126697664 ps
CPU time 3.15 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:15 PM PDT 24
Peak memory 242236 kb
Host smart-6c06c0c6-85f8-402e-9079-fd01432d34cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434518319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2434518319
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.399975385
Short name T556
Test name
Test status
Simulation time 289688525 ps
CPU time 4.72 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:16 PM PDT 24
Peak memory 242388 kb
Host smart-4bb1363c-0f88-4cd7-9197-e60a0a144265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399975385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.399975385
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3990081984
Short name T1009
Test name
Test status
Simulation time 376493479 ps
CPU time 3.76 seconds
Started Jul 29 07:49:09 PM PDT 24
Finished Jul 29 07:49:13 PM PDT 24
Peak memory 242156 kb
Host smart-c3b04ab6-f13e-4a0a-9167-16138ebd833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990081984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3990081984
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.664212060
Short name T910
Test name
Test status
Simulation time 364551782 ps
CPU time 4.18 seconds
Started Jul 29 07:49:12 PM PDT 24
Finished Jul 29 07:49:16 PM PDT 24
Peak memory 242284 kb
Host smart-7ad4334a-7925-4f00-a520-2aae1f506928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664212060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.664212060
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.783698780
Short name T665
Test name
Test status
Simulation time 346878217 ps
CPU time 3.66 seconds
Started Jul 29 07:49:13 PM PDT 24
Finished Jul 29 07:49:16 PM PDT 24
Peak memory 242048 kb
Host smart-500ad4ea-d344-4218-ac18-7cf55e89eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783698780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.783698780
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.2987273509
Short name T704
Test name
Test status
Simulation time 138764357 ps
CPU time 4.35 seconds
Started Jul 29 07:49:14 PM PDT 24
Finished Jul 29 07:49:19 PM PDT 24
Peak memory 242224 kb
Host smart-4bd15824-25ff-4ca7-8cd9-4c1575e4107a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987273509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2987273509
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3429128467
Short name T933
Test name
Test status
Simulation time 212626623 ps
CPU time 4.24 seconds
Started Jul 29 07:49:14 PM PDT 24
Finished Jul 29 07:49:19 PM PDT 24
Peak memory 242368 kb
Host smart-98ad96df-8abc-402c-9eb6-896cb42a26b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429128467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3429128467
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2250983659
Short name T176
Test name
Test status
Simulation time 191874358 ps
CPU time 4.35 seconds
Started Jul 29 07:49:19 PM PDT 24
Finished Jul 29 07:49:24 PM PDT 24
Peak memory 242116 kb
Host smart-8302e034-4a4c-4519-94c0-b302da9479f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250983659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2250983659
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2950630356
Short name T857
Test name
Test status
Simulation time 58528345 ps
CPU time 1.86 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:40:44 PM PDT 24
Peak memory 240288 kb
Host smart-f850aacf-f29d-4149-bfbb-83701f44070b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950630356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2950630356
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.1967984625
Short name T519
Test name
Test status
Simulation time 433532924 ps
CPU time 7.92 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:34 PM PDT 24
Peak memory 242152 kb
Host smart-3f74879e-914e-4a3a-b44d-c9181dd66cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967984625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1967984625
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.2556318169
Short name T911
Test name
Test status
Simulation time 348070054 ps
CPU time 9.07 seconds
Started Jul 29 07:40:40 PM PDT 24
Finished Jul 29 07:40:49 PM PDT 24
Peak memory 248440 kb
Host smart-47fb7eef-8048-4ea2-8add-18c79924d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556318169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2556318169
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3664796400
Short name T456
Test name
Test status
Simulation time 1576311508 ps
CPU time 31.93 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:41:00 PM PDT 24
Peak memory 242312 kb
Host smart-059927e3-5008-4927-9af4-68be1d67d2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664796400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3664796400
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.2723545546
Short name T174
Test name
Test status
Simulation time 1034920476 ps
CPU time 30.9 seconds
Started Jul 29 07:40:26 PM PDT 24
Finished Jul 29 07:40:57 PM PDT 24
Peak memory 242700 kb
Host smart-65339891-2514-4322-86db-efec105205ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723545546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2723545546
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1629887924
Short name T1135
Test name
Test status
Simulation time 1690816945 ps
CPU time 4.77 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:40:33 PM PDT 24
Peak memory 242216 kb
Host smart-9aeaf9f2-93f3-43fe-b905-a46f7dfd9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629887924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1629887924
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.4095354902
Short name T799
Test name
Test status
Simulation time 3621235000 ps
CPU time 29.76 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 246344 kb
Host smart-b3c74cb8-1c43-4bd5-bae6-57b869e38ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095354902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.4095354902
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3886057763
Short name T993
Test name
Test status
Simulation time 751408884 ps
CPU time 9.57 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:40:51 PM PDT 24
Peak memory 242108 kb
Host smart-d4a7410d-f179-406c-ae25-e34f6d15e36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886057763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3886057763
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.94640737
Short name T378
Test name
Test status
Simulation time 2249242933 ps
CPU time 21.03 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:40:49 PM PDT 24
Peak memory 248584 kb
Host smart-982379d8-4ea0-4aa4-a256-3c705d579ecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94640737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.94640737
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3947133618
Short name T1046
Test name
Test status
Simulation time 420970343 ps
CPU time 6.76 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:40:49 PM PDT 24
Peak memory 241940 kb
Host smart-220938ab-c6d6-4eea-b300-879cd86ebe7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947133618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3947133618
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1499309090
Short name T242
Test name
Test status
Simulation time 12528925169 ps
CPU time 185.13 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:43:46 PM PDT 24
Peak memory 270212 kb
Host smart-26d74516-feb4-4328-bc24-675407e8953c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499309090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1499309090
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.2426931140
Short name T1149
Test name
Test status
Simulation time 341754733 ps
CPU time 8.8 seconds
Started Jul 29 07:40:28 PM PDT 24
Finished Jul 29 07:40:37 PM PDT 24
Peak memory 241988 kb
Host smart-9d9df682-a2fa-4d0b-8b55-9737dc6ac8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426931140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2426931140
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.4013240284
Short name T146
Test name
Test status
Simulation time 20274435841 ps
CPU time 81.13 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:42:02 PM PDT 24
Peak memory 248652 kb
Host smart-23e60c77-a30f-4c96-bfd7-3d5a36da71a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013240284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
4013240284
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3860713901
Short name T7
Test name
Test status
Simulation time 2636744132656 ps
CPU time 3720.84 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 08:42:42 PM PDT 24
Peak memory 339092 kb
Host smart-aef850b5-e3bf-4be7-bd2a-e133db417a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860713901 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3860713901
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.570366859
Short name T1034
Test name
Test status
Simulation time 24710094323 ps
CPU time 37.92 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:41:21 PM PDT 24
Peak memory 243340 kb
Host smart-5a2e0dd1-5c88-49e5-aecc-199e6ac0ffad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570366859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.570366859
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.4286858605
Short name T864
Test name
Test status
Simulation time 748310263 ps
CPU time 1.75 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:42:58 PM PDT 24
Peak memory 240512 kb
Host smart-0a7c39c0-dd99-4b01-967f-20a90942380b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286858605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.4286858605
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1093386482
Short name T968
Test name
Test status
Simulation time 559609912 ps
CPU time 20.31 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:17 PM PDT 24
Peak memory 248672 kb
Host smart-cb506eb9-1978-45e3-9afa-99091be52e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093386482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1093386482
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.4087055604
Short name T961
Test name
Test status
Simulation time 2617053188 ps
CPU time 18.17 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 07:43:16 PM PDT 24
Peak memory 242064 kb
Host smart-b7657400-f183-4761-a323-14ab037751a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087055604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.4087055604
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.639618507
Short name T888
Test name
Test status
Simulation time 1650829350 ps
CPU time 19.58 seconds
Started Jul 29 07:43:00 PM PDT 24
Finished Jul 29 07:43:19 PM PDT 24
Peak memory 241736 kb
Host smart-d13e15ac-9783-478b-b601-db57cfb013b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639618507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.639618507
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.434222255
Short name T721
Test name
Test status
Simulation time 137090215 ps
CPU time 3.53 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:00 PM PDT 24
Peak memory 241928 kb
Host smart-f4deac0f-54c6-4cb9-9ed1-79b8590b19bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434222255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.434222255
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2096361076
Short name T165
Test name
Test status
Simulation time 2065390716 ps
CPU time 27.58 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 07:43:25 PM PDT 24
Peak memory 248668 kb
Host smart-2778808b-5b6b-413e-8aad-3a0ed093e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096361076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2096361076
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.240580167
Short name T547
Test name
Test status
Simulation time 2384610781 ps
CPU time 32.6 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:28 PM PDT 24
Peak memory 248624 kb
Host smart-18522b88-41d0-4632-81b5-746a1c62b5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240580167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.240580167
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.1327728423
Short name T215
Test name
Test status
Simulation time 430708660 ps
CPU time 12.67 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 07:43:10 PM PDT 24
Peak memory 242236 kb
Host smart-cd724788-2865-4384-9f7a-cbd47b2d70e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327728423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1327728423
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.2728569773
Short name T380
Test name
Test status
Simulation time 5674797259 ps
CPU time 22.25 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:19 PM PDT 24
Peak memory 242036 kb
Host smart-1ba92604-eece-4b5e-9217-c875db05aa93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728569773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.2728569773
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3556318221
Short name T354
Test name
Test status
Simulation time 515248090 ps
CPU time 9.46 seconds
Started Jul 29 07:43:04 PM PDT 24
Finished Jul 29 07:43:13 PM PDT 24
Peak memory 242052 kb
Host smart-04a94a06-3710-4353-80a4-02fc42ba697b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556318221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3556318221
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.1148465060
Short name T598
Test name
Test status
Simulation time 1534335247 ps
CPU time 10.82 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:43:08 PM PDT 24
Peak memory 248572 kb
Host smart-c3b8f825-73ab-4ee5-a38e-26376f8d2205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148465060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1148465060
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.1093307565
Short name T630
Test name
Test status
Simulation time 55937370264 ps
CPU time 70.52 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:44:07 PM PDT 24
Peak memory 243020 kb
Host smart-76e9a33f-ef09-4702-95b7-34d0c430bf7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093307565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.1093307565
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2474981310
Short name T801
Test name
Test status
Simulation time 2236005695 ps
CPU time 70.57 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 07:44:08 PM PDT 24
Peak memory 254424 kb
Host smart-1f4c7da6-4667-4d7f-8898-ac2c14b2b0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474981310 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2474981310
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.1273695620
Short name T735
Test name
Test status
Simulation time 2726990193 ps
CPU time 42.72 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:39 PM PDT 24
Peak memory 242096 kb
Host smart-63f14408-74d5-4f30-8130-64b9745ff227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273695620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1273695620
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3535161399
Short name T448
Test name
Test status
Simulation time 234250937 ps
CPU time 2.2 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:42:59 PM PDT 24
Peak memory 240900 kb
Host smart-2f304f67-95a4-43d8-8b8a-6155d5c88c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535161399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3535161399
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.3686110805
Short name T1099
Test name
Test status
Simulation time 1839070513 ps
CPU time 27.95 seconds
Started Jul 29 07:43:02 PM PDT 24
Finished Jul 29 07:43:30 PM PDT 24
Peak memory 248496 kb
Host smart-96883dc2-478f-4e43-b032-7c1fc0334062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686110805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3686110805
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.2283845278
Short name T787
Test name
Test status
Simulation time 2640803664 ps
CPU time 19.94 seconds
Started Jul 29 07:43:02 PM PDT 24
Finished Jul 29 07:43:22 PM PDT 24
Peak memory 242436 kb
Host smart-7f2ede8a-e056-4a13-ad7c-f2bc324845e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283845278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2283845278
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.3340154056
Short name T98
Test name
Test status
Simulation time 2221941219 ps
CPU time 19.1 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 07:43:18 PM PDT 24
Peak memory 242160 kb
Host smart-38162714-596b-4704-9c6c-213e7da28622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340154056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3340154056
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.3491659569
Short name T442
Test name
Test status
Simulation time 225913060 ps
CPU time 5.59 seconds
Started Jul 29 07:42:59 PM PDT 24
Finished Jul 29 07:43:05 PM PDT 24
Peak memory 243048 kb
Host smart-e535c739-8941-4d8c-9944-4b0a83445b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491659569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3491659569
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.1291235473
Short name T539
Test name
Test status
Simulation time 7644995094 ps
CPU time 19.75 seconds
Started Jul 29 07:43:00 PM PDT 24
Finished Jul 29 07:43:20 PM PDT 24
Peak memory 248724 kb
Host smart-df5ffadc-ecde-4ec9-9bc4-aed47413512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291235473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1291235473
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.480747699
Short name T275
Test name
Test status
Simulation time 477977008 ps
CPU time 5.16 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:43:02 PM PDT 24
Peak memory 242032 kb
Host smart-d24e3042-c7ab-495c-a9f1-daf78b7601ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480747699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.480747699
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.3238833839
Short name T671
Test name
Test status
Simulation time 695839784 ps
CPU time 13.05 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:10 PM PDT 24
Peak memory 241984 kb
Host smart-890e08a4-4a0d-4a07-93c6-6d688de042f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238833839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3238833839
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.642102788
Short name T893
Test name
Test status
Simulation time 684182151 ps
CPU time 7.52 seconds
Started Jul 29 07:43:02 PM PDT 24
Finished Jul 29 07:43:10 PM PDT 24
Peak memory 242292 kb
Host smart-d62fe913-2b54-4e62-96fe-82246f5ac01a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642102788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.642102788
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.981740290
Short name T800
Test name
Test status
Simulation time 2140174045 ps
CPU time 19.07 seconds
Started Jul 29 07:42:58 PM PDT 24
Finished Jul 29 07:43:17 PM PDT 24
Peak memory 242344 kb
Host smart-a5f46128-a127-433a-9bf3-4efd142e9606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981740290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.981740290
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.78195957
Short name T599
Test name
Test status
Simulation time 38345180834 ps
CPU time 141.34 seconds
Started Jul 29 07:43:05 PM PDT 24
Finished Jul 29 07:45:26 PM PDT 24
Peak memory 246024 kb
Host smart-1dd49113-36a9-4eea-aade-e86fe1060ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78195957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.78195957
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.4280965211
Short name T37
Test name
Test status
Simulation time 70056216706 ps
CPU time 1330.68 seconds
Started Jul 29 07:43:01 PM PDT 24
Finished Jul 29 08:05:12 PM PDT 24
Peak memory 264892 kb
Host smart-6b266bc2-399a-4a0d-bf74-894db89b7691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280965211 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.4280965211
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.2051998108
Short name T683
Test name
Test status
Simulation time 111161697 ps
CPU time 3.17 seconds
Started Jul 29 07:42:56 PM PDT 24
Finished Jul 29 07:43:00 PM PDT 24
Peak memory 242080 kb
Host smart-a4cd3a58-6af5-4b7c-b0de-1220e015f12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051998108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2051998108
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2910532513
Short name T660
Test name
Test status
Simulation time 42469463 ps
CPU time 1.6 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:11 PM PDT 24
Peak memory 240292 kb
Host smart-c7322980-e0ec-4ba1-afa0-348f7e56f2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910532513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2910532513
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.3342201808
Short name T65
Test name
Test status
Simulation time 8444313873 ps
CPU time 16.32 seconds
Started Jul 29 07:43:07 PM PDT 24
Finished Jul 29 07:43:23 PM PDT 24
Peak memory 248656 kb
Host smart-0c48b989-2851-46be-a00c-17a1a6b4a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342201808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3342201808
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2434936210
Short name T984
Test name
Test status
Simulation time 2343683584 ps
CPU time 31.9 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:41 PM PDT 24
Peak memory 245516 kb
Host smart-87d11072-f9ea-4756-ba7e-c216ef9ae536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434936210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2434936210
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.470042619
Short name T885
Test name
Test status
Simulation time 15038446728 ps
CPU time 38.42 seconds
Started Jul 29 07:43:08 PM PDT 24
Finished Jul 29 07:43:47 PM PDT 24
Peak memory 242500 kb
Host smart-69b3bba2-42dd-475c-877c-ab98e4f26a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470042619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.470042619
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.3750782273
Short name T1061
Test name
Test status
Simulation time 221182319 ps
CPU time 4.35 seconds
Started Jul 29 07:42:57 PM PDT 24
Finished Jul 29 07:43:02 PM PDT 24
Peak memory 242236 kb
Host smart-7100021c-a9d7-4988-b1f5-acaf8479216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750782273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3750782273
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.645466988
Short name T959
Test name
Test status
Simulation time 372118345 ps
CPU time 13.2 seconds
Started Jul 29 07:43:11 PM PDT 24
Finished Jul 29 07:43:24 PM PDT 24
Peak memory 243488 kb
Host smart-7579a923-6efc-430e-8b88-06c3887aae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645466988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.645466988
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.2507542675
Short name T369
Test name
Test status
Simulation time 1832164914 ps
CPU time 22.87 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 07:43:33 PM PDT 24
Peak memory 241920 kb
Host smart-063553ba-12d5-44b6-a9df-6d8ef3fb1b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507542675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2507542675
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.4048795136
Short name T595
Test name
Test status
Simulation time 1189436645 ps
CPU time 3.04 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 07:43:13 PM PDT 24
Peak memory 242440 kb
Host smart-48b49c60-e74e-4628-9be6-36bb8e9d1a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048795136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.4048795136
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.3988918489
Short name T788
Test name
Test status
Simulation time 330739293 ps
CPU time 11.52 seconds
Started Jul 29 07:43:11 PM PDT 24
Finished Jul 29 07:43:23 PM PDT 24
Peak memory 241968 kb
Host smart-ad52c491-0eec-48c0-bead-f03e1900bc78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988918489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3988918489
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.2984485554
Short name T1029
Test name
Test status
Simulation time 452931348 ps
CPU time 6.12 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:15 PM PDT 24
Peak memory 242044 kb
Host smart-77c2f25a-bd28-4914-8cb2-13a332097e54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984485554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2984485554
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1210671312
Short name T394
Test name
Test status
Simulation time 818561587 ps
CPU time 6.34 seconds
Started Jul 29 07:43:02 PM PDT 24
Finished Jul 29 07:43:08 PM PDT 24
Peak memory 241840 kb
Host smart-53d0a2d1-4dfd-4b5c-8423-33f6fb62fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210671312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1210671312
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.199975215
Short name T640
Test name
Test status
Simulation time 12466955453 ps
CPU time 167.3 seconds
Started Jul 29 07:43:11 PM PDT 24
Finished Jul 29 07:45:59 PM PDT 24
Peak memory 256904 kb
Host smart-e1f50b4b-167f-4c18-90d5-97f0079b461a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199975215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
199975215
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.659949869
Short name T282
Test name
Test status
Simulation time 246649663434 ps
CPU time 3616.68 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 08:43:28 PM PDT 24
Peak memory 340560 kb
Host smart-26690ed9-2530-411b-a335-0869d17c220a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659949869 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.659949869
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.829270177
Short name T936
Test name
Test status
Simulation time 656953667 ps
CPU time 6.42 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:15 PM PDT 24
Peak memory 242000 kb
Host smart-745fc4df-9544-4677-a094-af5dec55896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829270177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.829270177
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3061111536
Short name T915
Test name
Test status
Simulation time 131097001 ps
CPU time 2.1 seconds
Started Jul 29 07:43:08 PM PDT 24
Finished Jul 29 07:43:10 PM PDT 24
Peak memory 240400 kb
Host smart-c2b78f30-795d-4b5c-9f0a-66598ffa1d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061111536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3061111536
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.726019708
Short name T967
Test name
Test status
Simulation time 1367544238 ps
CPU time 22.13 seconds
Started Jul 29 07:43:11 PM PDT 24
Finished Jul 29 07:43:33 PM PDT 24
Peak memory 242016 kb
Host smart-203e4d41-c377-4c67-b992-c53e2d93e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726019708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.726019708
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.293726999
Short name T700
Test name
Test status
Simulation time 280792750 ps
CPU time 7.12 seconds
Started Jul 29 07:43:11 PM PDT 24
Finished Jul 29 07:43:18 PM PDT 24
Peak memory 242156 kb
Host smart-4c5afe79-e580-4346-b165-7c875e23bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293726999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.293726999
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.864343264
Short name T1094
Test name
Test status
Simulation time 343881164 ps
CPU time 5.03 seconds
Started Jul 29 07:43:14 PM PDT 24
Finished Jul 29 07:43:19 PM PDT 24
Peak memory 242296 kb
Host smart-72a4411b-6268-4ed7-9b50-556417a539ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864343264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.864343264
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3501570472
Short name T736
Test name
Test status
Simulation time 1117258672 ps
CPU time 19.64 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 07:43:30 PM PDT 24
Peak memory 244388 kb
Host smart-0dd97c8f-9c1b-4259-a7cb-82119b46c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501570472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3501570472
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.1268353485
Short name T737
Test name
Test status
Simulation time 1719730831 ps
CPU time 24.5 seconds
Started Jul 29 07:43:08 PM PDT 24
Finished Jul 29 07:43:32 PM PDT 24
Peak memory 242224 kb
Host smart-d5c8fb01-b604-4072-a9d5-f868dc5b7457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268353485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.1268353485
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.1617208010
Short name T1037
Test name
Test status
Simulation time 195331432 ps
CPU time 9.53 seconds
Started Jul 29 07:43:08 PM PDT 24
Finished Jul 29 07:43:18 PM PDT 24
Peak memory 242092 kb
Host smart-f2266c90-0968-40b0-a977-094432e49cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617208010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.1617208010
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1876936091
Short name T328
Test name
Test status
Simulation time 170462310 ps
CPU time 5.64 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 07:43:15 PM PDT 24
Peak memory 242076 kb
Host smart-41e13774-c08f-473e-bf70-2f01af36c658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876936091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1876936091
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.2684224734
Short name T443
Test name
Test status
Simulation time 147629654 ps
CPU time 5.22 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 07:43:16 PM PDT 24
Peak memory 242116 kb
Host smart-34d5de28-861c-4e9d-b8f2-ceb955d9ebbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684224734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2684224734
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.92720832
Short name T111
Test name
Test status
Simulation time 174841595 ps
CPU time 5.64 seconds
Started Jul 29 07:43:12 PM PDT 24
Finished Jul 29 07:43:18 PM PDT 24
Peak memory 241988 kb
Host smart-d03acc2e-44c1-44ec-a2d2-c93eeaf7246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92720832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.92720832
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2119429220
Short name T1052
Test name
Test status
Simulation time 5426841372 ps
CPU time 91.46 seconds
Started Jul 29 07:43:12 PM PDT 24
Finished Jul 29 07:44:43 PM PDT 24
Peak memory 248524 kb
Host smart-9abfd060-5ecc-41c1-b93c-cc218c7f5ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119429220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2119429220
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.2057662826
Short name T96
Test name
Test status
Simulation time 1070680189 ps
CPU time 14.17 seconds
Started Jul 29 07:43:10 PM PDT 24
Finished Jul 29 07:43:25 PM PDT 24
Peak memory 242352 kb
Host smart-8ef96938-ab4d-4720-aa46-b963a5abe7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057662826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2057662826
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.2367146608
Short name T1103
Test name
Test status
Simulation time 66981201 ps
CPU time 2.03 seconds
Started Jul 29 07:43:20 PM PDT 24
Finished Jul 29 07:43:22 PM PDT 24
Peak memory 240436 kb
Host smart-d658a7b5-5037-4d61-b6fa-2b90d5fa6495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367146608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2367146608
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3465856866
Short name T1085
Test name
Test status
Simulation time 2666202294 ps
CPU time 28.62 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:50 PM PDT 24
Peak memory 244852 kb
Host smart-ce098e2c-972a-45be-9735-f5d498625f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465856866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3465856866
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.951011360
Short name T471
Test name
Test status
Simulation time 879373627 ps
CPU time 26.84 seconds
Started Jul 29 07:43:20 PM PDT 24
Finished Jul 29 07:43:47 PM PDT 24
Peak memory 242296 kb
Host smart-55e5ec5d-d595-49f9-b1df-3ec6c7b1e80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951011360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.951011360
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3470065299
Short name T528
Test name
Test status
Simulation time 2140310710 ps
CPU time 25.98 seconds
Started Jul 29 07:43:28 PM PDT 24
Finished Jul 29 07:43:54 PM PDT 24
Peak memory 242284 kb
Host smart-b16164c3-6cba-4164-850c-3cb84b74c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470065299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3470065299
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.3389719803
Short name T564
Test name
Test status
Simulation time 1716272616 ps
CPU time 3.91 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:13 PM PDT 24
Peak memory 242304 kb
Host smart-b9d343a2-bd7d-428d-86f3-e77764fec29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389719803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3389719803
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.65737238
Short name T335
Test name
Test status
Simulation time 3389878648 ps
CPU time 17.48 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:43:39 PM PDT 24
Peak memory 246348 kb
Host smart-1fa6f900-e4ff-4b30-9ce3-579fbc79ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65737238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.65737238
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.1396863508
Short name T511
Test name
Test status
Simulation time 705226358 ps
CPU time 15.08 seconds
Started Jul 29 07:43:24 PM PDT 24
Finished Jul 29 07:43:40 PM PDT 24
Peak memory 242284 kb
Host smart-4d7cc230-c77b-41f6-bcda-e2c0770976b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396863508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1396863508
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2050341262
Short name T1120
Test name
Test status
Simulation time 1496186534 ps
CPU time 5.82 seconds
Started Jul 29 07:43:27 PM PDT 24
Finished Jul 29 07:43:33 PM PDT 24
Peak memory 241996 kb
Host smart-1c955c41-7a7c-496f-8a5f-5d13c2741050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050341262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2050341262
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.896643081
Short name T764
Test name
Test status
Simulation time 586182207 ps
CPU time 15.34 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:36 PM PDT 24
Peak memory 241928 kb
Host smart-4caac228-8b9f-4f44-9ed6-b5b9ea76361a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896643081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.896643081
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.2791280916
Short name T592
Test name
Test status
Simulation time 400121860 ps
CPU time 9.19 seconds
Started Jul 29 07:43:09 PM PDT 24
Finished Jul 29 07:43:18 PM PDT 24
Peak memory 242276 kb
Host smart-3685baf9-c062-4261-9bb3-75ae1eeaf4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791280916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2791280916
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.1972332060
Short name T151
Test name
Test status
Simulation time 19249102230 ps
CPU time 159.12 seconds
Started Jul 29 07:43:24 PM PDT 24
Finished Jul 29 07:46:03 PM PDT 24
Peak memory 260932 kb
Host smart-1f59eff6-ba0c-4cd0-937c-a15a895b3518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972332060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.1972332060
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.2385081408
Short name T572
Test name
Test status
Simulation time 1562054199 ps
CPU time 21.23 seconds
Started Jul 29 07:43:23 PM PDT 24
Finished Jul 29 07:43:44 PM PDT 24
Peak memory 242220 kb
Host smart-d1b72aca-5106-40dc-a21f-836d3a4c1068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385081408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.2385081408
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2684096840
Short name T997
Test name
Test status
Simulation time 821708892 ps
CPU time 2.36 seconds
Started Jul 29 07:43:20 PM PDT 24
Finished Jul 29 07:43:22 PM PDT 24
Peak memory 240440 kb
Host smart-67c92bf8-611e-4146-a967-1a54634f0ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684096840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2684096840
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.4293602453
Short name T73
Test name
Test status
Simulation time 685741853 ps
CPU time 27.61 seconds
Started Jul 29 07:43:27 PM PDT 24
Finished Jul 29 07:43:55 PM PDT 24
Peak memory 242592 kb
Host smart-01239095-9b71-458f-8032-6b8c28baddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293602453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.4293602453
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1056840404
Short name T558
Test name
Test status
Simulation time 2668933033 ps
CPU time 25.45 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:46 PM PDT 24
Peak memory 242144 kb
Host smart-a079089c-54b1-47ab-8023-d392109414cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056840404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1056840404
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.228879901
Short name T874
Test name
Test status
Simulation time 10005469874 ps
CPU time 22.39 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:43:44 PM PDT 24
Peak memory 243220 kb
Host smart-c27f1ec3-57f5-462b-b9e1-2929be48e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228879901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.228879901
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1823712246
Short name T998
Test name
Test status
Simulation time 129612446 ps
CPU time 3.88 seconds
Started Jul 29 07:43:23 PM PDT 24
Finished Jul 29 07:43:27 PM PDT 24
Peak memory 242244 kb
Host smart-d3802aed-bc28-4540-91af-6681c4a147fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823712246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1823712246
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.1430220579
Short name T858
Test name
Test status
Simulation time 2600449538 ps
CPU time 24.25 seconds
Started Jul 29 07:43:28 PM PDT 24
Finished Jul 29 07:43:52 PM PDT 24
Peak memory 242144 kb
Host smart-540a84da-3a4f-4a98-ab90-6711753ab572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430220579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1430220579
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1221632924
Short name T835
Test name
Test status
Simulation time 1029644157 ps
CPU time 22.81 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:43:45 PM PDT 24
Peak memory 242280 kb
Host smart-930ddf8a-5659-4603-8d07-9c0e96b3e757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221632924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1221632924
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.1007022073
Short name T752
Test name
Test status
Simulation time 228477978 ps
CPU time 5.06 seconds
Started Jul 29 07:43:25 PM PDT 24
Finished Jul 29 07:43:30 PM PDT 24
Peak memory 242020 kb
Host smart-21f7973a-9aa3-44bd-bf7a-cc90a572e8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007022073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1007022073
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.53243985
Short name T1058
Test name
Test status
Simulation time 582590727 ps
CPU time 8.23 seconds
Started Jul 29 07:43:25 PM PDT 24
Finished Jul 29 07:43:34 PM PDT 24
Peak memory 242028 kb
Host smart-1b0cbfa0-6d90-436e-b249-7902388841bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53243985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.53243985
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.1569941179
Short name T351
Test name
Test status
Simulation time 276475455 ps
CPU time 7.28 seconds
Started Jul 29 07:43:23 PM PDT 24
Finished Jul 29 07:43:30 PM PDT 24
Peak memory 242264 kb
Host smart-bcfdc822-ffdb-45db-b839-5b9927bbe14c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569941179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1569941179
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3389725233
Short name T393
Test name
Test status
Simulation time 1409773008 ps
CPU time 7.83 seconds
Started Jul 29 07:43:23 PM PDT 24
Finished Jul 29 07:43:31 PM PDT 24
Peak memory 242344 kb
Host smart-cf0b26a6-7a4a-4d81-b937-7cc569f980a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389725233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3389725233
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.3233405592
Short name T673
Test name
Test status
Simulation time 8274691382 ps
CPU time 164.1 seconds
Started Jul 29 07:43:20 PM PDT 24
Finished Jul 29 07:46:04 PM PDT 24
Peak memory 264812 kb
Host smart-02fccf44-d499-4cce-8f07-a343b78e4465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233405592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.3233405592
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1853232984
Short name T1119
Test name
Test status
Simulation time 1003756973263 ps
CPU time 1443.48 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 08:07:25 PM PDT 24
Peak memory 262544 kb
Host smart-cffd7e71-45f2-4077-b7aa-4dd1bf47d4a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853232984 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.1853232984
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.2225795390
Short name T992
Test name
Test status
Simulation time 2641100078 ps
CPU time 20.41 seconds
Started Jul 29 07:43:26 PM PDT 24
Finished Jul 29 07:43:47 PM PDT 24
Peak memory 242364 kb
Host smart-19fd216f-4618-490e-ab2b-736bf0742e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225795390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2225795390
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.714097546
Short name T478
Test name
Test status
Simulation time 55377945 ps
CPU time 1.78 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:23 PM PDT 24
Peak memory 240444 kb
Host smart-7a8d2fa2-f77d-4d8c-9cb8-9d57b44ffde4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714097546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.714097546
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.221789482
Short name T1193
Test name
Test status
Simulation time 1728003547 ps
CPU time 25.73 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:47 PM PDT 24
Peak memory 243660 kb
Host smart-8035ee45-d744-44a1-9d87-0781aea27873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221789482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.221789482
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2000447126
Short name T464
Test name
Test status
Simulation time 267337745 ps
CPU time 7.18 seconds
Started Jul 29 07:43:20 PM PDT 24
Finished Jul 29 07:43:28 PM PDT 24
Peak memory 241972 kb
Host smart-6fb8e576-74db-4f0b-89c4-d193bc212e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000447126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2000447126
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.1451660518
Short name T543
Test name
Test status
Simulation time 126821893 ps
CPU time 4.33 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:43:27 PM PDT 24
Peak memory 242180 kb
Host smart-6016ffb1-257e-4d05-b704-5777b3893333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451660518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1451660518
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1305836043
Short name T452
Test name
Test status
Simulation time 2982847747 ps
CPU time 41.47 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:44:03 PM PDT 24
Peak memory 248724 kb
Host smart-caa16a54-bfdf-4b0f-8d9e-ec570e668e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305836043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1305836043
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.4073357745
Short name T387
Test name
Test status
Simulation time 4115987385 ps
CPU time 26.33 seconds
Started Jul 29 07:43:26 PM PDT 24
Finished Jul 29 07:43:52 PM PDT 24
Peak memory 241964 kb
Host smart-de068d6e-c4c4-419f-a1c4-e2853b23aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073357745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.4073357745
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3354275046
Short name T245
Test name
Test status
Simulation time 378142492 ps
CPU time 3.33 seconds
Started Jul 29 07:43:20 PM PDT 24
Finished Jul 29 07:43:24 PM PDT 24
Peak memory 246996 kb
Host smart-0337bf27-b60e-4ced-ad68-edafc5ca55ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354275046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3354275046
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.324523193
Short name T1004
Test name
Test status
Simulation time 634611138 ps
CPU time 11.89 seconds
Started Jul 29 07:43:25 PM PDT 24
Finished Jul 29 07:43:37 PM PDT 24
Peak memory 242044 kb
Host smart-0aa4f90f-1e2b-49b2-9db3-38e100dd90cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324523193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.324523193
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.3855295035
Short name T228
Test name
Test status
Simulation time 298606307 ps
CPU time 4.24 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:26 PM PDT 24
Peak memory 241952 kb
Host smart-fcf77a56-b49f-4cd2-add8-3c5a488841bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855295035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3855295035
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.392923604
Short name T200
Test name
Test status
Simulation time 5397994575 ps
CPU time 16.58 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:43:39 PM PDT 24
Peak memory 242080 kb
Host smart-4d911494-b7b3-49d0-9635-17148c616149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392923604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.392923604
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.988129810
Short name T91
Test name
Test status
Simulation time 38023559293 ps
CPU time 285.56 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:48:07 PM PDT 24
Peak memory 277352 kb
Host smart-97aa8ae0-ded1-455c-8d24-f823097b173a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988129810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
988129810
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3142412819
Short name T664
Test name
Test status
Simulation time 39435202179 ps
CPU time 1158.91 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 08:02:40 PM PDT 24
Peak memory 382168 kb
Host smart-31bbd782-affb-4af4-92ef-ee1a8fd5485e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142412819 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.3142412819
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.3859383074
Short name T1068
Test name
Test status
Simulation time 2814254826 ps
CPU time 28.54 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:50 PM PDT 24
Peak memory 242964 kb
Host smart-ad74e455-b6b2-4cf2-8c47-34ce6ec88ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859383074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3859383074
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2164430648
Short name T198
Test name
Test status
Simulation time 743552954 ps
CPU time 1.76 seconds
Started Jul 29 07:43:30 PM PDT 24
Finished Jul 29 07:43:32 PM PDT 24
Peak memory 240436 kb
Host smart-45d370b5-354f-4f48-9d86-923fb94fc50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164430648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2164430648
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3553178026
Short name T42
Test name
Test status
Simulation time 487759403 ps
CPU time 10.85 seconds
Started Jul 29 07:43:27 PM PDT 24
Finished Jul 29 07:43:38 PM PDT 24
Peak memory 242252 kb
Host smart-6c965398-8015-43b1-b250-4e9ec12e159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553178026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3553178026
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.3994571755
Short name T160
Test name
Test status
Simulation time 848060978 ps
CPU time 25.88 seconds
Started Jul 29 07:43:23 PM PDT 24
Finished Jul 29 07:43:49 PM PDT 24
Peak memory 242020 kb
Host smart-fda5c9a1-7448-4386-b03c-66f12274b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994571755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3994571755
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.3583539306
Short name T847
Test name
Test status
Simulation time 424524301 ps
CPU time 8.58 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:30 PM PDT 24
Peak memory 242416 kb
Host smart-458f6352-ac7b-4f59-851c-fc15752cf94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583539306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3583539306
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.1843738182
Short name T782
Test name
Test status
Simulation time 128371336 ps
CPU time 3.66 seconds
Started Jul 29 07:43:19 PM PDT 24
Finished Jul 29 07:43:23 PM PDT 24
Peak memory 242172 kb
Host smart-c0af1c2a-a7df-43ae-bc33-c20c14de9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843738182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1843738182
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.796482718
Short name T615
Test name
Test status
Simulation time 2050505749 ps
CPU time 9.58 seconds
Started Jul 29 07:43:22 PM PDT 24
Finished Jul 29 07:43:32 PM PDT 24
Peak memory 248560 kb
Host smart-a23b8d3f-6afe-4b8b-b1df-c05cefc3557f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796482718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.796482718
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.2085573797
Short name T1188
Test name
Test status
Simulation time 2654795017 ps
CPU time 31.28 seconds
Started Jul 29 07:43:31 PM PDT 24
Finished Jul 29 07:44:03 PM PDT 24
Peak memory 241984 kb
Host smart-5bb4e645-e84d-4758-9b58-4825d150f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085573797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2085573797
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2720237607
Short name T179
Test name
Test status
Simulation time 408090343 ps
CPU time 16.48 seconds
Started Jul 29 07:43:27 PM PDT 24
Finished Jul 29 07:43:43 PM PDT 24
Peak memory 242300 kb
Host smart-fd35edca-c196-4f6e-8334-af83b295ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720237607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2720237607
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.3018029451
Short name T999
Test name
Test status
Simulation time 439498031 ps
CPU time 13.04 seconds
Started Jul 29 07:43:21 PM PDT 24
Finished Jul 29 07:43:34 PM PDT 24
Peak memory 242028 kb
Host smart-a1ba6a66-9d55-41c3-822e-36a3c1feb136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018029451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3018029451
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.4250660866
Short name T349
Test name
Test status
Simulation time 241816396 ps
CPU time 3.75 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:43:36 PM PDT 24
Peak memory 242016 kb
Host smart-bbcfd117-de6e-41e1-8299-ac7242e9bd7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250660866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.4250660866
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.3494274384
Short name T514
Test name
Test status
Simulation time 2948383242 ps
CPU time 6.91 seconds
Started Jul 29 07:43:25 PM PDT 24
Finished Jul 29 07:43:32 PM PDT 24
Peak memory 242352 kb
Host smart-2449e6b4-2d47-4230-b5c3-ed358d2f640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494274384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3494274384
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.1859383762
Short name T639
Test name
Test status
Simulation time 40986323469 ps
CPU time 155.94 seconds
Started Jul 29 07:43:30 PM PDT 24
Finished Jul 29 07:46:06 PM PDT 24
Peak memory 245512 kb
Host smart-84c9cb48-e651-4cac-97e5-5bcb494f5e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859383762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.1859383762
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1234035894
Short name T1150
Test name
Test status
Simulation time 11358558885 ps
CPU time 264.33 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 267400 kb
Host smart-564ffb2f-d6f7-4ac6-aa9e-31f247de960f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234035894 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.1234035894
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2255644621
Short name T1114
Test name
Test status
Simulation time 469935018 ps
CPU time 15.52 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:43:48 PM PDT 24
Peak memory 248624 kb
Host smart-88f207a8-3c38-4379-935f-30e7e93b8a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255644621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2255644621
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.2197152879
Short name T655
Test name
Test status
Simulation time 115504742 ps
CPU time 1.94 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:43:35 PM PDT 24
Peak memory 240332 kb
Host smart-6ec003be-e2ec-4a32-859a-c4cb0f83d743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197152879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2197152879
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.314142822
Short name T952
Test name
Test status
Simulation time 739382669 ps
CPU time 15.69 seconds
Started Jul 29 07:43:33 PM PDT 24
Finished Jul 29 07:43:49 PM PDT 24
Peak memory 242580 kb
Host smart-6d620a69-28f7-4525-ad58-76ed567cf12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314142822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.314142822
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2163067659
Short name T1006
Test name
Test status
Simulation time 695259708 ps
CPU time 21.49 seconds
Started Jul 29 07:43:34 PM PDT 24
Finished Jul 29 07:43:56 PM PDT 24
Peak memory 242112 kb
Host smart-1b2a0d4f-5ad6-48b0-bf7a-2e3cc130cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163067659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2163067659
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.1585457380
Short name T851
Test name
Test status
Simulation time 929141090 ps
CPU time 19.63 seconds
Started Jul 29 07:43:31 PM PDT 24
Finished Jul 29 07:43:51 PM PDT 24
Peak memory 242220 kb
Host smart-109f4489-d2de-4123-a8a7-2070e807379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585457380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1585457380
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.2082878279
Short name T548
Test name
Test status
Simulation time 125046693 ps
CPU time 4.85 seconds
Started Jul 29 07:43:33 PM PDT 24
Finished Jul 29 07:43:38 PM PDT 24
Peak memory 242240 kb
Host smart-58788b9a-da9c-49ef-a156-b8a9d4b8d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082878279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.2082878279
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1774500198
Short name T803
Test name
Test status
Simulation time 709597913 ps
CPU time 17.44 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:43:50 PM PDT 24
Peak memory 241960 kb
Host smart-8d54f783-c18e-41b0-ba29-87e6dc9cb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774500198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1774500198
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2659089870
Short name T1042
Test name
Test status
Simulation time 810083234 ps
CPU time 23.04 seconds
Started Jul 29 07:43:33 PM PDT 24
Finished Jul 29 07:43:56 PM PDT 24
Peak memory 241920 kb
Host smart-1dc2fce7-2a8a-421f-84c1-54c990d07c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659089870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2659089870
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.2552704649
Short name T6
Test name
Test status
Simulation time 809337828 ps
CPU time 21.2 seconds
Started Jul 29 07:43:31 PM PDT 24
Finished Jul 29 07:43:53 PM PDT 24
Peak memory 242048 kb
Host smart-4a1f4e24-9139-42ad-b9a0-b2969bd81c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552704649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2552704649
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3479157348
Short name T367
Test name
Test status
Simulation time 72817415987 ps
CPU time 339.16 seconds
Started Jul 29 07:43:31 PM PDT 24
Finished Jul 29 07:49:10 PM PDT 24
Peak memory 267472 kb
Host smart-85124051-df9b-4cc7-8cc0-b216a331eb97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479157348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3479157348
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.1069769437
Short name T1013
Test name
Test status
Simulation time 188605960594 ps
CPU time 1858.29 seconds
Started Jul 29 07:43:36 PM PDT 24
Finished Jul 29 08:14:34 PM PDT 24
Peak memory 365068 kb
Host smart-6df3aff8-53b7-468e-a9be-7895c5e44dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069769437 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.1069769437
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.12399815
Short name T875
Test name
Test status
Simulation time 439628881 ps
CPU time 6.28 seconds
Started Jul 29 07:43:30 PM PDT 24
Finished Jul 29 07:43:37 PM PDT 24
Peak memory 242024 kb
Host smart-d081786f-b860-41c3-a7f6-6b3e26ed1aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12399815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.12399815
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.2332136652
Short name T616
Test name
Test status
Simulation time 111652187 ps
CPU time 1.94 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:46 PM PDT 24
Peak memory 240368 kb
Host smart-5ebc07a8-072a-4716-8608-8cee7c7cd8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332136652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2332136652
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1912364122
Short name T717
Test name
Test status
Simulation time 663559708 ps
CPU time 9.44 seconds
Started Jul 29 07:43:29 PM PDT 24
Finished Jul 29 07:43:38 PM PDT 24
Peak memory 241988 kb
Host smart-f1f06655-6b28-48f2-91b9-5a298f31b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912364122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1912364122
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.2564337395
Short name T533
Test name
Test status
Simulation time 750405544 ps
CPU time 10.96 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:43:44 PM PDT 24
Peak memory 242492 kb
Host smart-d6eaea51-f3aa-406c-bf55-017f9f1c2490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564337395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2564337395
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1674176836
Short name T601
Test name
Test status
Simulation time 382083403 ps
CPU time 3.88 seconds
Started Jul 29 07:43:35 PM PDT 24
Finished Jul 29 07:43:39 PM PDT 24
Peak memory 242180 kb
Host smart-f997166d-5bcf-4750-bfed-b2691f6d2b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674176836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1674176836
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.850068836
Short name T646
Test name
Test status
Simulation time 1920323532 ps
CPU time 6.65 seconds
Started Jul 29 07:43:34 PM PDT 24
Finished Jul 29 07:43:40 PM PDT 24
Peak memory 242128 kb
Host smart-d24092d5-5e66-473e-8d94-c6eaf3a3c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850068836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.850068836
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.1407405915
Short name T681
Test name
Test status
Simulation time 1058594594 ps
CPU time 8.31 seconds
Started Jul 29 07:43:35 PM PDT 24
Finished Jul 29 07:43:44 PM PDT 24
Peak memory 241960 kb
Host smart-b0725f85-8dc9-4926-9548-31977cda9d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407405915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1407405915
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3333819586
Short name T421
Test name
Test status
Simulation time 259712952 ps
CPU time 6.45 seconds
Started Jul 29 07:43:30 PM PDT 24
Finished Jul 29 07:43:37 PM PDT 24
Peak memory 242348 kb
Host smart-fb7c6523-d766-4cea-a44f-cdf424006b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333819586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3333819586
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1060493991
Short name T1110
Test name
Test status
Simulation time 1458129307 ps
CPU time 15.09 seconds
Started Jul 29 07:43:32 PM PDT 24
Finished Jul 29 07:43:48 PM PDT 24
Peak memory 241956 kb
Host smart-d4491bf8-44bd-4fe4-9b06-f4bd7aad50e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060493991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1060493991
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.2521298735
Short name T113
Test name
Test status
Simulation time 471351367 ps
CPU time 6.82 seconds
Started Jul 29 07:43:31 PM PDT 24
Finished Jul 29 07:43:38 PM PDT 24
Peak memory 248584 kb
Host smart-2946dcc9-9f87-4343-82cb-299f876225fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521298735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.2521298735
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1443519568
Short name T609
Test name
Test status
Simulation time 394930843 ps
CPU time 5.88 seconds
Started Jul 29 07:43:36 PM PDT 24
Finished Jul 29 07:43:42 PM PDT 24
Peak memory 248584 kb
Host smart-4caf88c0-ebf2-42d3-963e-c8d63aa5b6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443519568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1443519568
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.544837123
Short name T1152
Test name
Test status
Simulation time 42226967702 ps
CPU time 108.88 seconds
Started Jul 29 07:43:35 PM PDT 24
Finished Jul 29 07:45:24 PM PDT 24
Peak memory 250800 kb
Host smart-b8482bd3-4dae-46f6-8698-595acbeb9e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544837123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.
544837123
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.1658972103
Short name T274
Test name
Test status
Simulation time 51965625170 ps
CPU time 1325.48 seconds
Started Jul 29 07:43:36 PM PDT 24
Finished Jul 29 08:05:42 PM PDT 24
Peak memory 265176 kb
Host smart-fecf7e80-46b9-4f11-85ef-369b31a2581a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658972103 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.1658972103
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.865293089
Short name T802
Test name
Test status
Simulation time 2956091388 ps
CPU time 18.39 seconds
Started Jul 29 07:43:34 PM PDT 24
Finished Jul 29 07:43:52 PM PDT 24
Peak memory 248660 kb
Host smart-d2d5b901-b23f-4263-9516-f39c7d45e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865293089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.865293089
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.205157382
Short name T486
Test name
Test status
Simulation time 713948719 ps
CPU time 1.97 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:40:43 PM PDT 24
Peak memory 240580 kb
Host smart-74d6174f-0246-445a-aa3f-dac2fcb89c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205157382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.205157382
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3763955242
Short name T1036
Test name
Test status
Simulation time 411260098 ps
CPU time 8.57 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:40:50 PM PDT 24
Peak memory 242352 kb
Host smart-ee8feff5-8689-461a-bf5b-2a512c493914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763955242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3763955242
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.2892723204
Short name T80
Test name
Test status
Simulation time 465929163 ps
CPU time 7.88 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:40:51 PM PDT 24
Peak memory 241972 kb
Host smart-1d756b4a-efe4-44cc-9a24-534a73959b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892723204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2892723204
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.2230908298
Short name T848
Test name
Test status
Simulation time 659419771 ps
CPU time 19.01 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:41:03 PM PDT 24
Peak memory 242004 kb
Host smart-ca6c9282-e044-4172-bf26-ce91bab6e503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230908298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2230908298
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.549276224
Short name T761
Test name
Test status
Simulation time 976653294 ps
CPU time 30.06 seconds
Started Jul 29 07:40:40 PM PDT 24
Finished Jul 29 07:41:10 PM PDT 24
Peak memory 242456 kb
Host smart-1849fa66-3782-41c9-8a10-ad56ab43f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549276224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.549276224
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.180542989
Short name T867
Test name
Test status
Simulation time 2293480348 ps
CPU time 6.26 seconds
Started Jul 29 07:40:41 PM PDT 24
Finished Jul 29 07:40:48 PM PDT 24
Peak memory 242084 kb
Host smart-2cc79eb9-3ad5-4e18-84fd-78546caaef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180542989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.180542989
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.2766600480
Short name T167
Test name
Test status
Simulation time 1192312698 ps
CPU time 21.39 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:41:03 PM PDT 24
Peak memory 245800 kb
Host smart-2c9e76eb-1ca1-4170-ad1c-1f2000eebc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766600480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2766600480
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3483062428
Short name T110
Test name
Test status
Simulation time 257343341 ps
CPU time 5.88 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:40:49 PM PDT 24
Peak memory 242000 kb
Host smart-f8449e92-7642-4a26-8284-e4d08730046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483062428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3483062428
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.4082205698
Short name T1027
Test name
Test status
Simulation time 1605467883 ps
CPU time 5.86 seconds
Started Jul 29 07:40:40 PM PDT 24
Finished Jul 29 07:40:46 PM PDT 24
Peak memory 242000 kb
Host smart-b4b3266e-116f-4e46-8d83-3aefc6dae386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082205698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4082205698
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1791208165
Short name T527
Test name
Test status
Simulation time 870031527 ps
CPU time 7.14 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:40:50 PM PDT 24
Peak memory 248680 kb
Host smart-c3899304-249a-4ab8-9ae1-ffdb2bc8f679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791208165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1791208165
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.4138304232
Short name T114
Test name
Test status
Simulation time 283940856 ps
CPU time 4.14 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:40:46 PM PDT 24
Peak memory 241948 kb
Host smart-bbe74aec-dc72-4e44-9a1d-2b54e271c3cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138304232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.4138304232
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.2068776485
Short name T238
Test name
Test status
Simulation time 6719596030 ps
CPU time 11.65 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:40:54 PM PDT 24
Peak memory 242060 kb
Host smart-a1cf7fde-13c7-446d-850f-73c6bc182563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068776485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2068776485
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.1370652258
Short name T320
Test name
Test status
Simulation time 46068769324 ps
CPU time 184.01 seconds
Started Jul 29 07:40:40 PM PDT 24
Finished Jul 29 07:43:44 PM PDT 24
Peak memory 264996 kb
Host smart-e08bdca8-fb52-4047-978e-1e61ac0eb90b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370652258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
1370652258
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1267767797
Short name T17
Test name
Test status
Simulation time 407072960967 ps
CPU time 1164.79 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 08:00:08 PM PDT 24
Peak memory 269792 kb
Host smart-382ecb13-4dc1-4c56-af7c-89fc1a618a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267767797 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1267767797
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.2875147419
Short name T904
Test name
Test status
Simulation time 3566935811 ps
CPU time 23.34 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:41:06 PM PDT 24
Peak memory 242676 kb
Host smart-d0ed2e62-1e08-4c3a-9137-c9ea6a28616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875147419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2875147419
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2772688383
Short name T960
Test name
Test status
Simulation time 99586253 ps
CPU time 1.78 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:46 PM PDT 24
Peak memory 240392 kb
Host smart-a40f2d03-d070-4bd4-a8e9-4a0e09787eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772688383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2772688383
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.2234414955
Short name T55
Test name
Test status
Simulation time 625229582 ps
CPU time 19.45 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:44:04 PM PDT 24
Peak memory 242172 kb
Host smart-8d1c65f1-e61d-4649-ac45-ec6c2f7c4191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234414955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2234414955
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.1459913617
Short name T565
Test name
Test status
Simulation time 227757253 ps
CPU time 10.71 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:55 PM PDT 24
Peak memory 242020 kb
Host smart-96c965ae-c1da-4ca9-ab14-1b5ea53c3a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459913617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1459913617
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.2525744878
Short name T772
Test name
Test status
Simulation time 7571151493 ps
CPU time 21.12 seconds
Started Jul 29 07:43:46 PM PDT 24
Finished Jul 29 07:44:08 PM PDT 24
Peak memory 243196 kb
Host smart-3082b7f9-e5f4-4e85-b60a-b344583eead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525744878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2525744878
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.3230409577
Short name T538
Test name
Test status
Simulation time 172320321 ps
CPU time 4.06 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:43:49 PM PDT 24
Peak memory 242048 kb
Host smart-cfe26c4c-0cae-40bf-98df-08c1bb4fd50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230409577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3230409577
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.90944308
Short name T1106
Test name
Test status
Simulation time 10497931183 ps
CPU time 24.1 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:44:08 PM PDT 24
Peak memory 248676 kb
Host smart-bee9cb2d-ba72-4c8c-96da-9d3e17e9edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90944308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.90944308
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1322124440
Short name T475
Test name
Test status
Simulation time 522903443 ps
CPU time 13.4 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:58 PM PDT 24
Peak memory 241964 kb
Host smart-35332fe3-d9ea-42d3-b32a-ad0031c9e880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322124440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1322124440
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.108912081
Short name T516
Test name
Test status
Simulation time 613941095 ps
CPU time 9.13 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:53 PM PDT 24
Peak memory 241952 kb
Host smart-f0532081-5c68-46b6-9538-4cf649a4f556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108912081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.108912081
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1299704903
Short name T535
Test name
Test status
Simulation time 1214924664 ps
CPU time 12.78 seconds
Started Jul 29 07:43:54 PM PDT 24
Finished Jul 29 07:44:07 PM PDT 24
Peak memory 242096 kb
Host smart-8d1ff72b-6b85-482d-9f98-4fd83f81d41a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299704903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1299704903
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.2626770264
Short name T1127
Test name
Test status
Simulation time 175208918 ps
CPU time 4.29 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:48 PM PDT 24
Peak memory 242364 kb
Host smart-e8252b12-6d46-4193-84c8-c38900e32abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626770264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2626770264
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.4189781384
Short name T742
Test name
Test status
Simulation time 232467911235 ps
CPU time 257.33 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:48:03 PM PDT 24
Peak memory 281480 kb
Host smart-68462221-f085-4c38-b3ef-09ce94885602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189781384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.4189781384
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.232251066
Short name T19
Test name
Test status
Simulation time 22132668329 ps
CPU time 471.12 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:51:35 PM PDT 24
Peak memory 257072 kb
Host smart-5a8d2d2c-3c3a-42f9-9c77-1adf4204e080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232251066 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.232251066
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2096723805
Short name T872
Test name
Test status
Simulation time 607590351 ps
CPU time 10.95 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:55 PM PDT 24
Peak memory 242116 kb
Host smart-0d3eb3aa-397b-47f3-a19e-a645a87ef229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096723805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2096723805
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.378243879
Short name T819
Test name
Test status
Simulation time 774167201 ps
CPU time 2.67 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:43:48 PM PDT 24
Peak memory 240484 kb
Host smart-c51e462a-0a41-4960-a15e-9a7da8f54578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378243879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.378243879
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1648394324
Short name T79
Test name
Test status
Simulation time 1929198056 ps
CPU time 16.23 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:44:00 PM PDT 24
Peak memory 248560 kb
Host smart-394209df-2493-440a-8a7b-3e524fe89d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648394324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1648394324
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.308672378
Short name T521
Test name
Test status
Simulation time 1706426845 ps
CPU time 29.67 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:44:14 PM PDT 24
Peak memory 245524 kb
Host smart-f777ac12-743b-4bcd-9216-fa9f3e70c98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308672378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.308672378
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.3523569595
Short name T740
Test name
Test status
Simulation time 2919164723 ps
CPU time 33.87 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:44:19 PM PDT 24
Peak memory 242868 kb
Host smart-7d454c84-68eb-4250-9890-b939ceb166bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523569595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3523569595
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.1383982514
Short name T1090
Test name
Test status
Simulation time 451224693 ps
CPU time 4.58 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:49 PM PDT 24
Peak memory 242184 kb
Host smart-e0f32298-4e4e-411d-a6f1-ec945bbb1ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383982514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1383982514
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2143251015
Short name T743
Test name
Test status
Simulation time 4690278780 ps
CPU time 32.25 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:44:16 PM PDT 24
Peak memory 248708 kb
Host smart-192912c2-109c-4063-9cba-ebedf80b16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143251015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2143251015
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.764599333
Short name T1077
Test name
Test status
Simulation time 1823888603 ps
CPU time 14.75 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:59 PM PDT 24
Peak memory 242312 kb
Host smart-3db32f51-3083-4ad1-a4d9-4894d5237391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764599333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.764599333
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.1179995779
Short name T509
Test name
Test status
Simulation time 471570134 ps
CPU time 4.07 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:48 PM PDT 24
Peak memory 242316 kb
Host smart-1172b9f5-0ab3-4c30-9ff3-6cb3945f4872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179995779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1179995779
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.577301906
Short name T580
Test name
Test status
Simulation time 5777246576 ps
CPU time 10.72 seconds
Started Jul 29 07:43:46 PM PDT 24
Finished Jul 29 07:43:56 PM PDT 24
Peak memory 248720 kb
Host smart-02756e3f-c1ab-49bb-868a-159492c0e3e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577301906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.577301906
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.996944571
Short name T553
Test name
Test status
Simulation time 2574665504 ps
CPU time 8.29 seconds
Started Jul 29 07:43:46 PM PDT 24
Finished Jul 29 07:43:54 PM PDT 24
Peak memory 242012 kb
Host smart-91d172f5-7c76-4cba-a2f7-8af25bae58a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996944571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.996944571
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.3819684174
Short name T1089
Test name
Test status
Simulation time 151168241 ps
CPU time 5.42 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:50 PM PDT 24
Peak memory 241960 kb
Host smart-7cebbbb6-6244-4860-9b6a-0299e65800f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819684174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3819684174
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3072201720
Short name T137
Test name
Test status
Simulation time 10408101216 ps
CPU time 235.46 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:47:38 PM PDT 24
Peak memory 265092 kb
Host smart-4280ed5f-2529-449d-a2a5-1b704cdb7859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072201720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3072201720
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2187801222
Short name T237
Test name
Test status
Simulation time 20972919213 ps
CPU time 393.85 seconds
Started Jul 29 07:43:46 PM PDT 24
Finished Jul 29 07:50:20 PM PDT 24
Peak memory 256956 kb
Host smart-b46e0661-6f3d-432d-b17b-0364d884bb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187801222 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2187801222
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.758941370
Short name T544
Test name
Test status
Simulation time 988742643 ps
CPU time 32.15 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:44:17 PM PDT 24
Peak memory 242508 kb
Host smart-ce8733c2-fcb4-4a7e-a971-583d449638e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758941370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.758941370
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2474634203
Short name T1104
Test name
Test status
Simulation time 211597311 ps
CPU time 2.02 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:27 PM PDT 24
Peak memory 240412 kb
Host smart-0b973223-e4ca-4f65-a39b-156b3324d811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474634203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2474634203
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.2440860920
Short name T1178
Test name
Test status
Simulation time 159447025 ps
CPU time 4.75 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:48 PM PDT 24
Peak memory 242528 kb
Host smart-fa0fd6f9-8080-423c-8d39-8789041f02d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440860920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2440860920
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.4234254053
Short name T172
Test name
Test status
Simulation time 911508875 ps
CPU time 12.74 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:43:58 PM PDT 24
Peak memory 242008 kb
Host smart-c7fb9c77-0cd3-46a0-9cc0-a08b750190df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234254053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.4234254053
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.2320389986
Short name T903
Test name
Test status
Simulation time 1584618133 ps
CPU time 32.32 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:44:17 PM PDT 24
Peak memory 248604 kb
Host smart-0b301b8c-47fb-4a48-9957-d131c1b8d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320389986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.2320389986
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2029956348
Short name T706
Test name
Test status
Simulation time 101054512 ps
CPU time 2.96 seconds
Started Jul 29 07:43:47 PM PDT 24
Finished Jul 29 07:43:50 PM PDT 24
Peak memory 242276 kb
Host smart-ec3f9321-57b0-47de-8e36-8e07769d5e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029956348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2029956348
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1547702173
Short name T86
Test name
Test status
Simulation time 7502816586 ps
CPU time 51.4 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:44:36 PM PDT 24
Peak memory 260004 kb
Host smart-91ed367d-b43d-40fa-8a4e-9a16a6208a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547702173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1547702173
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.939922478
Short name T710
Test name
Test status
Simulation time 3365530751 ps
CPU time 27.48 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:44:13 PM PDT 24
Peak memory 242076 kb
Host smart-3030ebfe-5b20-4ca0-87ea-c05c1df2d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939922478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.939922478
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1958627922
Short name T679
Test name
Test status
Simulation time 262344036 ps
CPU time 4.81 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:43:49 PM PDT 24
Peak memory 242344 kb
Host smart-50020a62-319b-46a8-bc48-914fead063d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958627922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1958627922
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1073317663
Short name T397
Test name
Test status
Simulation time 652523951 ps
CPU time 6.73 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 07:43:51 PM PDT 24
Peak memory 248644 kb
Host smart-09d5e8ac-f147-4a6a-8b6d-249aab00a2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073317663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1073317663
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.1430877053
Short name T1161
Test name
Test status
Simulation time 346029665 ps
CPU time 7.77 seconds
Started Jul 29 07:43:43 PM PDT 24
Finished Jul 29 07:43:50 PM PDT 24
Peak memory 241944 kb
Host smart-5a4d3153-d5e6-4418-8ad2-7b504d4d7dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430877053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1430877053
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.3262939357
Short name T617
Test name
Test status
Simulation time 649507973 ps
CPU time 5.12 seconds
Started Jul 29 07:43:46 PM PDT 24
Finished Jul 29 07:43:52 PM PDT 24
Peak memory 242160 kb
Host smart-8f92ffc6-35f3-4ab8-98b9-fbf509a42504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262939357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3262939357
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.26797381
Short name T311
Test name
Test status
Simulation time 1898160084 ps
CPU time 30.14 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:44:15 PM PDT 24
Peak memory 256824 kb
Host smart-8a4649b2-24da-4460-ba5a-6a8309432de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.26797381
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.1642704803
Short name T773
Test name
Test status
Simulation time 668857149372 ps
CPU time 1504.2 seconds
Started Jul 29 07:43:44 PM PDT 24
Finished Jul 29 08:08:49 PM PDT 24
Peak memory 276436 kb
Host smart-427c2a20-dba9-4478-b46b-dc6031682b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642704803 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.1642704803
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.1615374973
Short name T470
Test name
Test status
Simulation time 2602093967 ps
CPU time 27.93 seconds
Started Jul 29 07:43:45 PM PDT 24
Finished Jul 29 07:44:13 PM PDT 24
Peak memory 242068 kb
Host smart-2c020510-7349-4aa8-8ea0-e04f171e2248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615374973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1615374973
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3881601358
Short name T945
Test name
Test status
Simulation time 316316902 ps
CPU time 2.68 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:27 PM PDT 24
Peak memory 240480 kb
Host smart-54869c03-a44c-4e0d-bb9a-e12901b8e379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881601358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3881601358
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1307658048
Short name T69
Test name
Test status
Simulation time 4023117537 ps
CPU time 31.3 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 244332 kb
Host smart-90783a48-cf35-4212-8356-e7fa0423a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307658048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1307658048
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.1456731351
Short name T685
Test name
Test status
Simulation time 1019156592 ps
CPU time 21.37 seconds
Started Jul 29 07:47:23 PM PDT 24
Finished Jul 29 07:47:44 PM PDT 24
Peak memory 241924 kb
Host smart-36e4526c-2c6d-4ac5-be1f-d86e350de0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456731351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1456731351
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.1113224584
Short name T364
Test name
Test status
Simulation time 1161922202 ps
CPU time 20.8 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:45 PM PDT 24
Peak memory 241968 kb
Host smart-9e15a3e6-a450-483a-aa71-cdbb9b9e7af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113224584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1113224584
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1993951306
Short name T807
Test name
Test status
Simulation time 102794296 ps
CPU time 3.39 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:27 PM PDT 24
Peak memory 241992 kb
Host smart-5d147193-7b62-4699-9752-b0dd0f537356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993951306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1993951306
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.536186579
Short name T953
Test name
Test status
Simulation time 13748894141 ps
CPU time 41.22 seconds
Started Jul 29 07:47:26 PM PDT 24
Finished Jul 29 07:48:07 PM PDT 24
Peak memory 248712 kb
Host smart-73c6620a-c509-4ace-8018-e9eb5dec8db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536186579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.536186579
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.4261598367
Short name T440
Test name
Test status
Simulation time 1535761031 ps
CPU time 34.97 seconds
Started Jul 29 07:47:27 PM PDT 24
Finished Jul 29 07:48:02 PM PDT 24
Peak memory 242184 kb
Host smart-fff5ea48-5ca2-47c2-9e24-21cad38b3373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261598367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.4261598367
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3020539971
Short name T461
Test name
Test status
Simulation time 121429913 ps
CPU time 4.73 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:29 PM PDT 24
Peak memory 241936 kb
Host smart-cc06d04d-ca9b-4152-a670-da1c7bf9f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020539971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3020539971
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2223747382
Short name T372
Test name
Test status
Simulation time 9327606288 ps
CPU time 21.36 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:47 PM PDT 24
Peak memory 248728 kb
Host smart-eaa9bfb0-ce2a-4f54-bd06-3fad9b813dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223747382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2223747382
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.667955577
Short name T224
Test name
Test status
Simulation time 248180062 ps
CPU time 8.56 seconds
Started Jul 29 07:47:27 PM PDT 24
Finished Jul 29 07:47:36 PM PDT 24
Peak memory 248560 kb
Host smart-06fec2dc-5a35-415c-91c9-439981533263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667955577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.667955577
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.1625256471
Short name T1066
Test name
Test status
Simulation time 426572193 ps
CPU time 4.22 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:28 PM PDT 24
Peak memory 242116 kb
Host smart-acda6309-b66a-4d87-b0bb-67e83856a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625256471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1625256471
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3166485184
Short name T316
Test name
Test status
Simulation time 335767884358 ps
CPU time 944.85 seconds
Started Jul 29 07:47:23 PM PDT 24
Finished Jul 29 08:03:08 PM PDT 24
Peak memory 297084 kb
Host smart-ac16ec97-d874-4edd-9aba-6873c9464165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166485184 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3166485184
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1171362816
Short name T1124
Test name
Test status
Simulation time 577584794 ps
CPU time 12.1 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:38 PM PDT 24
Peak memory 242032 kb
Host smart-6ff665e7-b8af-4894-a6c9-750f6ead8c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171362816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1171362816
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3695148101
Short name T1047
Test name
Test status
Simulation time 70330299 ps
CPU time 2.08 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:26 PM PDT 24
Peak memory 240356 kb
Host smart-d1c8fe45-5731-4b02-b215-1f0ef24b278b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695148101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3695148101
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1567173700
Short name T555
Test name
Test status
Simulation time 125495555 ps
CPU time 5.16 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:29 PM PDT 24
Peak memory 241956 kb
Host smart-7dafa152-3256-41b2-9aaf-bc3a39ad3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567173700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1567173700
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1490800011
Short name T966
Test name
Test status
Simulation time 2961066995 ps
CPU time 41.62 seconds
Started Jul 29 07:47:22 PM PDT 24
Finished Jul 29 07:48:04 PM PDT 24
Peak memory 250472 kb
Host smart-9562d402-0abe-43c2-b817-22fc89350dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490800011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1490800011
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.4198394078
Short name T376
Test name
Test status
Simulation time 335582475 ps
CPU time 11.71 seconds
Started Jul 29 07:47:21 PM PDT 24
Finished Jul 29 07:47:33 PM PDT 24
Peak memory 242024 kb
Host smart-6a85e138-da4e-48e5-aa89-e24e8582f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198394078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.4198394078
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.588666050
Short name T122
Test name
Test status
Simulation time 229770996 ps
CPU time 3.46 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:29 PM PDT 24
Peak memory 242180 kb
Host smart-8d420bc5-0be4-4527-98f7-b6ff98ccd27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588666050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.588666050
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2847702955
Short name T951
Test name
Test status
Simulation time 1461772337 ps
CPU time 16.56 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:41 PM PDT 24
Peak memory 243600 kb
Host smart-27af5c89-654a-4a34-9a28-eddf23965e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847702955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2847702955
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.834513351
Short name T818
Test name
Test status
Simulation time 673633240 ps
CPU time 7.71 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:32 PM PDT 24
Peak memory 248620 kb
Host smart-93153263-767d-4a08-8ef0-eb9a98df8c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834513351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.834513351
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.4239170951
Short name T750
Test name
Test status
Simulation time 216168094 ps
CPU time 4.42 seconds
Started Jul 29 07:47:27 PM PDT 24
Finished Jul 29 07:47:32 PM PDT 24
Peak memory 241916 kb
Host smart-dff8b886-6c55-4be2-b4f8-f82d9d6a95d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239170951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.4239170951
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2380246740
Short name T166
Test name
Test status
Simulation time 4338747358 ps
CPU time 14.03 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:38 PM PDT 24
Peak memory 242232 kb
Host smart-693314ec-d948-45c6-b024-53b499ae2a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380246740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2380246740
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.27113032
Short name T962
Test name
Test status
Simulation time 3079789893 ps
CPU time 7.33 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:32 PM PDT 24
Peak memory 242344 kb
Host smart-3729aff3-e54e-46e6-9352-b4019a8e373e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27113032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.27113032
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.3314499808
Short name T1076
Test name
Test status
Simulation time 7910569219 ps
CPU time 11.22 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:35 PM PDT 24
Peak memory 241800 kb
Host smart-64262a7b-1ed8-476e-958a-ab5b373bb27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314499808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3314499808
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1611755850
Short name T281
Test name
Test status
Simulation time 107218795030 ps
CPU time 1221.32 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 08:07:46 PM PDT 24
Peak memory 334532 kb
Host smart-a888a11d-601a-4aea-ba79-561fe1831cf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611755850 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.1611755850
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.4265339587
Short name T368
Test name
Test status
Simulation time 6899659987 ps
CPU time 15.45 seconds
Started Jul 29 07:47:24 PM PDT 24
Finished Jul 29 07:47:40 PM PDT 24
Peak memory 243416 kb
Host smart-ed862b33-82f3-44ae-9bbc-22de2b37f134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265339587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.4265339587
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3200771087
Short name T1086
Test name
Test status
Simulation time 49011814 ps
CPU time 1.57 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:38 PM PDT 24
Peak memory 240596 kb
Host smart-d4e48b4c-113d-4b2f-b052-4b0ed57fa1c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200771087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3200771087
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.2328870099
Short name T39
Test name
Test status
Simulation time 397944061 ps
CPU time 9.68 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:47 PM PDT 24
Peak memory 242508 kb
Host smart-5f9e0536-7df2-496d-91a1-a3939c04717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328870099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2328870099
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.968006462
Short name T1019
Test name
Test status
Simulation time 677323329 ps
CPU time 17.57 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 242188 kb
Host smart-6b70533d-cc78-4eaf-93cd-cded6792a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968006462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.968006462
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1083579875
Short name T95
Test name
Test status
Simulation time 1070310693 ps
CPU time 17.77 seconds
Started Jul 29 07:47:36 PM PDT 24
Finished Jul 29 07:47:54 PM PDT 24
Peak memory 242084 kb
Host smart-c611a94e-62e8-464d-b4a0-8f391bba20b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083579875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1083579875
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.2904543348
Short name T193
Test name
Test status
Simulation time 3453861582 ps
CPU time 26 seconds
Started Jul 29 07:47:44 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 244092 kb
Host smart-f811e4df-2fe4-49ad-901a-ffc3924963ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904543348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2904543348
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.2784193491
Short name T686
Test name
Test status
Simulation time 283746549 ps
CPU time 6.03 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:44 PM PDT 24
Peak memory 242088 kb
Host smart-bd732d2c-33d2-4b29-86ef-3ac1d5c4ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784193491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2784193491
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1899405207
Short name T152
Test name
Test status
Simulation time 207807536 ps
CPU time 11.39 seconds
Started Jul 29 07:47:25 PM PDT 24
Finished Jul 29 07:47:36 PM PDT 24
Peak memory 242344 kb
Host smart-de74e779-027a-4ec2-9b55-a9bc89bc91d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899405207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1899405207
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.3590627559
Short name T377
Test name
Test status
Simulation time 2851136311 ps
CPU time 23.05 seconds
Started Jul 29 07:47:23 PM PDT 24
Finished Jul 29 07:47:46 PM PDT 24
Peak memory 242276 kb
Host smart-facf93a5-69a2-4272-ac62-20e12bb7143f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590627559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3590627559
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1365574756
Short name T583
Test name
Test status
Simulation time 308500782 ps
CPU time 4.17 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:41 PM PDT 24
Peak memory 241868 kb
Host smart-8c108c3e-eb87-4007-ab3f-a034c74edc71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365574756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1365574756
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.4261262737
Short name T573
Test name
Test status
Simulation time 3061800317 ps
CPU time 6.47 seconds
Started Jul 29 07:47:22 PM PDT 24
Finished Jul 29 07:47:28 PM PDT 24
Peak memory 248636 kb
Host smart-58a22d46-7b55-49d9-a5d4-daf181503aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261262737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.4261262737
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1152108689
Short name T1113
Test name
Test status
Simulation time 504773594 ps
CPU time 10.92 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:49 PM PDT 24
Peak memory 242412 kb
Host smart-9f22da78-bbcb-469d-ab3c-f0ba124087ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152108689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1152108689
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1385206312
Short name T855
Test name
Test status
Simulation time 81487259 ps
CPU time 1.54 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:42 PM PDT 24
Peak memory 240456 kb
Host smart-b17875ea-2c88-4e62-bb3d-d1580e743cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385206312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1385206312
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2160919905
Short name T585
Test name
Test status
Simulation time 2394410014 ps
CPU time 17.87 seconds
Started Jul 29 07:47:41 PM PDT 24
Finished Jul 29 07:47:59 PM PDT 24
Peak memory 242804 kb
Host smart-154fc2f1-d208-446f-8f60-f376a7d9cb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160919905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2160919905
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2562308637
Short name T493
Test name
Test status
Simulation time 1561336652 ps
CPU time 24.21 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:48:02 PM PDT 24
Peak memory 241952 kb
Host smart-58da466a-b329-45aa-8f47-6ffc29238cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562308637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2562308637
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1008828927
Short name T1160
Test name
Test status
Simulation time 742426033 ps
CPU time 7.42 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:45 PM PDT 24
Peak memory 241880 kb
Host smart-594b0f96-a67c-426f-9198-986df8e4e390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008828927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1008828927
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.3557748099
Short name T1170
Test name
Test status
Simulation time 392407974 ps
CPU time 4.06 seconds
Started Jul 29 07:47:41 PM PDT 24
Finished Jul 29 07:47:46 PM PDT 24
Peak memory 242256 kb
Host smart-5b673ee5-4b2e-4fce-aaea-f88a9620e7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557748099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3557748099
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.1244150585
Short name T1095
Test name
Test status
Simulation time 2518444872 ps
CPU time 13.45 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:53 PM PDT 24
Peak memory 248564 kb
Host smart-59e008d8-ddfe-414e-b213-131cc7437d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244150585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1244150585
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.328678597
Short name T549
Test name
Test status
Simulation time 3913221959 ps
CPU time 26.42 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:48:04 PM PDT 24
Peak memory 242332 kb
Host smart-8df9609e-4d9b-4232-a35e-cfde44bc0188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328678597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.328678597
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.2946113261
Short name T261
Test name
Test status
Simulation time 745812929 ps
CPU time 6.38 seconds
Started Jul 29 07:47:45 PM PDT 24
Finished Jul 29 07:47:51 PM PDT 24
Peak memory 241936 kb
Host smart-55733f08-e085-4fa6-ad1c-0471f23e5eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946113261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2946113261
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3712601674
Short name T501
Test name
Test status
Simulation time 9582658604 ps
CPU time 28.09 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:48:06 PM PDT 24
Peak memory 242076 kb
Host smart-90b96d1b-64f3-4d0a-995f-65d058d99f01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712601674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3712601674
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2628948030
Short name T109
Test name
Test status
Simulation time 439761405 ps
CPU time 7.09 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:44 PM PDT 24
Peak memory 242324 kb
Host smart-dd13d421-6530-402a-93e6-61e987b46fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628948030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2628948030
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3347192220
Short name T532
Test name
Test status
Simulation time 215248130 ps
CPU time 4.79 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:44 PM PDT 24
Peak memory 248580 kb
Host smart-9c3984dc-56ca-4b55-9634-39981b5bf199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347192220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3347192220
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.664771244
Short name T887
Test name
Test status
Simulation time 27667161433 ps
CPU time 211.08 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:51:09 PM PDT 24
Peak memory 256928 kb
Host smart-fff9fcb8-4663-4ca5-b74e-4bf0a42e9ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664771244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
664771244
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3903772426
Short name T758
Test name
Test status
Simulation time 38764819386 ps
CPU time 499.93 seconds
Started Jul 29 07:47:34 PM PDT 24
Finished Jul 29 07:55:54 PM PDT 24
Peak memory 248816 kb
Host smart-36e97ceb-1af3-4983-a0f6-5093408cc69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903772426 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3903772426
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.1112551570
Short name T718
Test name
Test status
Simulation time 1643984829 ps
CPU time 34.65 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:48:15 PM PDT 24
Peak memory 242512 kb
Host smart-50ac733a-6bd1-4a17-b8ce-31eb9743be52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112551570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1112551570
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.261974976
Short name T852
Test name
Test status
Simulation time 739144298 ps
CPU time 2.13 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:40 PM PDT 24
Peak memory 240864 kb
Host smart-4a19c91a-22ed-4c91-a88e-23bf1a68649f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261974976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.261974976
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.2201794508
Short name T436
Test name
Test status
Simulation time 453222815 ps
CPU time 10.28 seconds
Started Jul 29 07:47:41 PM PDT 24
Finished Jul 29 07:47:51 PM PDT 24
Peak memory 241928 kb
Host smart-4a2c3535-9ff5-4efa-9657-b4eecdbe3e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201794508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2201794508
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.2169455318
Short name T575
Test name
Test status
Simulation time 399536244 ps
CPU time 14.18 seconds
Started Jul 29 07:47:39 PM PDT 24
Finished Jul 29 07:47:54 PM PDT 24
Peak memory 242376 kb
Host smart-840eb226-186f-4580-9303-0b777bae0f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169455318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2169455318
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.4156111721
Short name T576
Test name
Test status
Simulation time 707859040 ps
CPU time 4.58 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:42 PM PDT 24
Peak memory 242440 kb
Host smart-db956e43-2e72-4565-a933-4a0ae378c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156111721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.4156111721
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2484843413
Short name T1000
Test name
Test status
Simulation time 2005001202 ps
CPU time 17.54 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 247264 kb
Host smart-47eecf0e-ce86-4c84-ac32-9d8de6f5a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484843413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2484843413
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.748920203
Short name T259
Test name
Test status
Simulation time 396666084 ps
CPU time 10.72 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:48 PM PDT 24
Peak memory 242416 kb
Host smart-38d5f17d-5e95-433f-b949-1704c1582983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748920203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.748920203
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.151080548
Short name T518
Test name
Test status
Simulation time 757647803 ps
CPU time 11.37 seconds
Started Jul 29 07:47:35 PM PDT 24
Finished Jul 29 07:47:46 PM PDT 24
Peak memory 242072 kb
Host smart-47a35b2b-f4db-4864-b8f8-b6536cfba880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151080548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.151080548
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1515097871
Short name T1072
Test name
Test status
Simulation time 2845013736 ps
CPU time 24.83 seconds
Started Jul 29 07:47:36 PM PDT 24
Finished Jul 29 07:48:01 PM PDT 24
Peak memory 242056 kb
Host smart-a49bebce-a0de-4b55-a57c-309b1df71476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515097871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1515097871
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.2989519157
Short name T350
Test name
Test status
Simulation time 280914446 ps
CPU time 5.05 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:45 PM PDT 24
Peak memory 241940 kb
Host smart-9631bfab-ec5a-4007-9c4b-e94fac859d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989519157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2989519157
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.2024410397
Short name T716
Test name
Test status
Simulation time 1767679847 ps
CPU time 5.53 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:43 PM PDT 24
Peak memory 241808 kb
Host smart-4122e79b-b709-4b0f-8e16-0e6af8002419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024410397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.2024410397
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.755104879
Short name T901
Test name
Test status
Simulation time 8293736401 ps
CPU time 103.27 seconds
Started Jul 29 07:47:41 PM PDT 24
Finished Jul 29 07:49:24 PM PDT 24
Peak memory 252480 kb
Host smart-00c14b53-3fb6-4e3a-8319-78db9205d08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755104879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.
755104879
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2717861164
Short name T284
Test name
Test status
Simulation time 103766608111 ps
CPU time 1271.92 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 08:08:50 PM PDT 24
Peak memory 294556 kb
Host smart-d040f22f-cc2f-491f-b7c7-890167c3e920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717861164 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.2717861164
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.647869064
Short name T766
Test name
Test status
Simulation time 5764504571 ps
CPU time 37.84 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:48:16 PM PDT 24
Peak memory 248636 kb
Host smart-718adee9-5e35-46e2-820b-795102e1a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647869064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.647869064
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2645070684
Short name T906
Test name
Test status
Simulation time 86744877 ps
CPU time 1.51 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:41 PM PDT 24
Peak memory 240796 kb
Host smart-31f33fa6-6bfa-4156-9a87-c8c0a63d0f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645070684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2645070684
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1308429151
Short name T1163
Test name
Test status
Simulation time 1313167962 ps
CPU time 12.31 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:53 PM PDT 24
Peak memory 242032 kb
Host smart-131428c5-ea13-4021-bb6d-4a79eb87ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308429151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1308429151
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.1782343153
Short name T446
Test name
Test status
Simulation time 1822906339 ps
CPU time 18.42 seconds
Started Jul 29 07:47:39 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 241972 kb
Host smart-190b68e6-4871-4a4c-8001-cbc008962ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782343153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1782343153
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.313455564
Short name T435
Test name
Test status
Simulation time 811978580 ps
CPU time 11.66 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:49 PM PDT 24
Peak memory 248620 kb
Host smart-e57a0aff-a738-4ff3-8f9d-c7e08964a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313455564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.313455564
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2959987034
Short name T815
Test name
Test status
Simulation time 2630332774 ps
CPU time 6.06 seconds
Started Jul 29 07:47:39 PM PDT 24
Finished Jul 29 07:47:46 PM PDT 24
Peak memory 241976 kb
Host smart-55c145fa-a0b2-4e63-b8fe-46dfa3af149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959987034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2959987034
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1095898500
Short name T209
Test name
Test status
Simulation time 699418832 ps
CPU time 17.25 seconds
Started Jul 29 07:47:39 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 242212 kb
Host smart-41194b30-725b-4f32-8912-82aacf8313d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095898500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1095898500
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.3972253227
Short name T606
Test name
Test status
Simulation time 359313574 ps
CPU time 6.28 seconds
Started Jul 29 07:47:36 PM PDT 24
Finished Jul 29 07:47:42 PM PDT 24
Peak memory 248548 kb
Host smart-3be5fad5-b781-4361-b39d-320e0615df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972253227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3972253227
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.309527889
Short name T925
Test name
Test status
Simulation time 1128182598 ps
CPU time 10.48 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:47 PM PDT 24
Peak memory 242424 kb
Host smart-3083aa88-9526-455d-8681-b12e0d064daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309527889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.309527889
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.906175919
Short name T365
Test name
Test status
Simulation time 794754472 ps
CPU time 17.99 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 248668 kb
Host smart-b7843bf4-988d-44a1-93b8-26892e74b844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906175919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.906175919
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.669584198
Short name T1010
Test name
Test status
Simulation time 1527336867 ps
CPU time 5.1 seconds
Started Jul 29 07:47:36 PM PDT 24
Finished Jul 29 07:47:41 PM PDT 24
Peak memory 247900 kb
Host smart-88c80807-ed88-44bc-a538-68e71bc9133c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669584198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.669584198
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.4045448778
Short name T921
Test name
Test status
Simulation time 781531000 ps
CPU time 5.04 seconds
Started Jul 29 07:47:41 PM PDT 24
Finished Jul 29 07:47:46 PM PDT 24
Peak memory 242032 kb
Host smart-7a37cf10-e58c-4777-946e-a542b531ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045448778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.4045448778
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.3915054417
Short name T659
Test name
Test status
Simulation time 2675222625 ps
CPU time 18.68 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 243928 kb
Host smart-7db1d655-1a04-44cd-b2f1-ca5335cf457f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915054417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.3915054417
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.3700103629
Short name T725
Test name
Test status
Simulation time 12632167515 ps
CPU time 20.86 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:59 PM PDT 24
Peak memory 242536 kb
Host smart-d19ab86b-d583-4eaa-b7cc-59495b44fd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700103629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.3700103629
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.347470207
Short name T811
Test name
Test status
Simulation time 48737567 ps
CPU time 1.63 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:39 PM PDT 24
Peak memory 240820 kb
Host smart-0750c26c-9111-495d-92c0-6cff73197d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347470207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.347470207
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3219808926
Short name T420
Test name
Test status
Simulation time 117799209 ps
CPU time 3.62 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:44 PM PDT 24
Peak memory 241912 kb
Host smart-9d2b6cc0-e4b0-4853-91bf-0f2769786899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219808926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3219808926
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.3285563598
Short name T820
Test name
Test status
Simulation time 1512003960 ps
CPU time 22.09 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:48:00 PM PDT 24
Peak memory 241992 kb
Host smart-4829c99d-6363-4c99-b220-e54ae84d99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285563598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3285563598
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.319554954
Short name T896
Test name
Test status
Simulation time 1677720055 ps
CPU time 16.77 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 248692 kb
Host smart-1bfa9f28-e7d2-4b82-a7e1-f1b88902da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319554954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.319554954
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.1687228096
Short name T898
Test name
Test status
Simulation time 113140901 ps
CPU time 4.1 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:47:42 PM PDT 24
Peak memory 242388 kb
Host smart-0cc231da-728e-4d6d-959d-bc3431d2c9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687228096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1687228096
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.3818381545
Short name T212
Test name
Test status
Simulation time 1281409980 ps
CPU time 14.07 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 245916 kb
Host smart-b5dd9043-bbfe-4057-9eb0-0ce70a61fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818381545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3818381545
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3083535774
Short name T1067
Test name
Test status
Simulation time 2078558369 ps
CPU time 24.81 seconds
Started Jul 29 07:47:38 PM PDT 24
Finished Jul 29 07:48:03 PM PDT 24
Peak memory 242152 kb
Host smart-d282b0f6-85b6-4bed-8aba-0f8bdd14935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083535774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3083535774
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1150720275
Short name T825
Test name
Test status
Simulation time 1402198802 ps
CPU time 21.44 seconds
Started Jul 29 07:47:35 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 248644 kb
Host smart-ef6194c4-dd5a-4725-bed4-7a7f4243aa8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150720275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1150720275
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.210299873
Short name T746
Test name
Test status
Simulation time 134513093 ps
CPU time 6.15 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 07:47:46 PM PDT 24
Peak memory 241928 kb
Host smart-769317da-6edf-46a1-99ee-24bee4bbc7d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210299873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.210299873
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.3932359826
Short name T941
Test name
Test status
Simulation time 188015694 ps
CPU time 4.17 seconds
Started Jul 29 07:47:41 PM PDT 24
Finished Jul 29 07:47:45 PM PDT 24
Peak memory 242088 kb
Host smart-c4437568-e8b5-4f25-b89a-1b5b5b1300f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932359826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3932359826
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1370189644
Short name T154
Test name
Test status
Simulation time 1003554628469 ps
CPU time 1855.39 seconds
Started Jul 29 07:47:40 PM PDT 24
Finished Jul 29 08:18:36 PM PDT 24
Peak memory 363172 kb
Host smart-8c9533ed-0f23-4dcc-8014-47f9b7533816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370189644 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.1370189644
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.108994907
Short name T366
Test name
Test status
Simulation time 3926771843 ps
CPU time 33.79 seconds
Started Jul 29 07:47:37 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242492 kb
Host smart-c59d1120-64c4-485f-b264-214c695a2f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108994907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.108994907
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.764630475
Short name T907
Test name
Test status
Simulation time 112228792 ps
CPU time 1.83 seconds
Started Jul 29 07:40:56 PM PDT 24
Finished Jul 29 07:40:58 PM PDT 24
Peak memory 240440 kb
Host smart-95be3cd7-3401-4633-a060-2689728ceacc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764630475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.764630475
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.3884088256
Short name T669
Test name
Test status
Simulation time 376038766 ps
CPU time 4.88 seconds
Started Jul 29 07:40:45 PM PDT 24
Finished Jul 29 07:40:50 PM PDT 24
Peak memory 242308 kb
Host smart-6b26e8af-ab4e-445f-8baf-b070f2638c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884088256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3884088256
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.4140731436
Short name T692
Test name
Test status
Simulation time 4326084279 ps
CPU time 8.37 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:40:59 PM PDT 24
Peak memory 242396 kb
Host smart-53f348e6-4956-4c05-894b-765b7957a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140731436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.4140731436
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.4096855914
Short name T760
Test name
Test status
Simulation time 1249194466 ps
CPU time 20.58 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:41:12 PM PDT 24
Peak memory 241932 kb
Host smart-c90d2ab8-f6a4-441d-98ab-08617bd84b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096855914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.4096855914
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.338316991
Short name T693
Test name
Test status
Simulation time 1484726219 ps
CPU time 18.61 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:41:02 PM PDT 24
Peak memory 242112 kb
Host smart-44004abd-bac0-4063-bc7c-f7461cbc107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338316991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.338316991
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3533710467
Short name T1145
Test name
Test status
Simulation time 351302261 ps
CPU time 4.03 seconds
Started Jul 29 07:40:42 PM PDT 24
Finished Jul 29 07:40:46 PM PDT 24
Peak memory 242264 kb
Host smart-6f109fcf-2fa9-41bf-88b6-034f0bdc5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533710467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3533710467
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2406428010
Short name T554
Test name
Test status
Simulation time 1430300479 ps
CPU time 42.79 seconds
Started Jul 29 07:40:57 PM PDT 24
Finished Jul 29 07:41:40 PM PDT 24
Peak memory 246132 kb
Host smart-7a1948fc-6386-40e5-b8c5-24672636d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406428010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2406428010
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.330979998
Short name T428
Test name
Test status
Simulation time 418624172 ps
CPU time 16.36 seconds
Started Jul 29 07:40:50 PM PDT 24
Finished Jul 29 07:41:06 PM PDT 24
Peak memory 242364 kb
Host smart-1b758e73-9acf-4aa6-aff7-c5c691bae515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330979998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.330979998
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.4031689357
Short name T720
Test name
Test status
Simulation time 455103916 ps
CPU time 4.72 seconds
Started Jul 29 07:40:40 PM PDT 24
Finished Jul 29 07:40:45 PM PDT 24
Peak memory 242320 kb
Host smart-4d43f2c0-4ad8-4c4b-84a1-da6275cc55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031689357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4031689357
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1090646861
Short name T1088
Test name
Test status
Simulation time 2676331523 ps
CPU time 24.47 seconds
Started Jul 29 07:40:45 PM PDT 24
Finished Jul 29 07:41:09 PM PDT 24
Peak memory 248668 kb
Host smart-08732a40-bcda-499b-99b4-9f567fed51fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090646861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1090646861
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3052698863
Short name T969
Test name
Test status
Simulation time 2170638873 ps
CPU time 7.26 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:40:58 PM PDT 24
Peak memory 242280 kb
Host smart-624f0d70-1bbc-49c9-ab8d-1eed7a598abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052698863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3052698863
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.1843520889
Short name T410
Test name
Test status
Simulation time 222685595 ps
CPU time 3.56 seconds
Started Jul 29 07:40:43 PM PDT 24
Finished Jul 29 07:40:47 PM PDT 24
Peak memory 242028 kb
Host smart-be065a12-c585-4c84-b288-68712be1945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843520889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1843520889
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3798864983
Short name T613
Test name
Test status
Simulation time 3312427522 ps
CPU time 5.98 seconds
Started Jul 29 07:41:00 PM PDT 24
Finished Jul 29 07:41:06 PM PDT 24
Peak memory 242412 kb
Host smart-94c04674-cb11-4653-a76b-a519a3e73f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798864983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3798864983
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.1406032939
Short name T469
Test name
Test status
Simulation time 670831624 ps
CPU time 5.61 seconds
Started Jul 29 07:47:39 PM PDT 24
Finished Jul 29 07:47:45 PM PDT 24
Peak memory 242116 kb
Host smart-b2e3d8a5-c514-49c9-8988-ed5f846c57cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406032939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1406032939
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2513460341
Short name T145
Test name
Test status
Simulation time 367561757 ps
CPU time 10.55 seconds
Started Jul 29 07:47:45 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 241836 kb
Host smart-f3f2ab1f-9d5a-43de-9b35-1adcde09cdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513460341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2513460341
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1931348097
Short name T678
Test name
Test status
Simulation time 252340077557 ps
CPU time 1707.98 seconds
Started Jul 29 07:47:46 PM PDT 24
Finished Jul 29 08:16:14 PM PDT 24
Peak memory 498820 kb
Host smart-b9b68eb0-8e88-4992-bbe9-ce053d650af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931348097 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.1931348097
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.1309385423
Short name T624
Test name
Test status
Simulation time 168019954 ps
CPU time 4.72 seconds
Started Jul 29 07:47:47 PM PDT 24
Finished Jul 29 07:47:51 PM PDT 24
Peak memory 241988 kb
Host smart-325fe175-0bd8-4243-8283-b9ab8a4551e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309385423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1309385423
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2284156248
Short name T407
Test name
Test status
Simulation time 2358135193 ps
CPU time 26.56 seconds
Started Jul 29 07:47:47 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 242320 kb
Host smart-45d1ff1c-a016-45db-b8af-ff6237ec3257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284156248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2284156248
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.805459074
Short name T862
Test name
Test status
Simulation time 41649356725 ps
CPU time 479.6 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:55:54 PM PDT 24
Peak memory 280284 kb
Host smart-d98f9feb-b171-4d23-8ee6-e2000e06d4ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805459074 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.805459074
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3425677621
Short name T1065
Test name
Test status
Simulation time 2787714398 ps
CPU time 22.09 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 242348 kb
Host smart-bb92f703-3879-45e1-95ff-ddf208a65c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425677621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3425677621
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3943330327
Short name T279
Test name
Test status
Simulation time 139900678297 ps
CPU time 1498.27 seconds
Started Jul 29 07:47:52 PM PDT 24
Finished Jul 29 08:12:50 PM PDT 24
Peak memory 314136 kb
Host smart-c7b656bd-c592-4dd6-8b6c-45dc060554e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943330327 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.3943330327
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.1740825396
Short name T119
Test name
Test status
Simulation time 1698148838 ps
CPU time 5.4 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:47:59 PM PDT 24
Peak memory 242184 kb
Host smart-72360518-6097-4525-aa47-342b9e3b7120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740825396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1740825396
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3330797122
Short name T1049
Test name
Test status
Simulation time 835384838 ps
CPU time 11.72 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:48:06 PM PDT 24
Peak memory 241928 kb
Host smart-b0baec2d-addc-4818-a871-c3e6c4c83832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330797122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3330797122
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.2136907802
Short name T738
Test name
Test status
Simulation time 44750254443 ps
CPU time 831.45 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 08:01:44 PM PDT 24
Peak memory 256948 kb
Host smart-f4d48ba6-66ab-48cf-8d35-bc0a1e84891f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136907802 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.2136907802
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3862933996
Short name T396
Test name
Test status
Simulation time 308438595 ps
CPU time 3.95 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 242288 kb
Host smart-d7a2b2ae-68a5-477b-a88d-c1df870a8c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862933996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3862933996
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.2210324193
Short name T361
Test name
Test status
Simulation time 828724213 ps
CPU time 5.81 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 242256 kb
Host smart-cfceaee4-dc56-4e5a-9929-9c5226162741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210324193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2210324193
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.2448349355
Short name T995
Test name
Test status
Simulation time 32136874752 ps
CPU time 734.81 seconds
Started Jul 29 07:47:56 PM PDT 24
Finished Jul 29 08:00:11 PM PDT 24
Peak memory 297928 kb
Host smart-e57344e4-2b1e-4e64-9efd-dc8342923988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448349355 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.2448349355
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1685226128
Short name T12
Test name
Test status
Simulation time 572337188 ps
CPU time 4.28 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 241836 kb
Host smart-435a2b3c-6138-4312-90cb-e217191972ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685226128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1685226128
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.4194824774
Short name T331
Test name
Test status
Simulation time 178571189 ps
CPU time 4.64 seconds
Started Jul 29 07:47:48 PM PDT 24
Finished Jul 29 07:47:52 PM PDT 24
Peak memory 242272 kb
Host smart-0726145b-c74b-4222-b06a-a1719876fc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194824774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.4194824774
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.687102254
Short name T1156
Test name
Test status
Simulation time 1567660313 ps
CPU time 7.02 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:48:00 PM PDT 24
Peak memory 242180 kb
Host smart-9a12f775-71d5-4c19-b5e0-0141f32998c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687102254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.687102254
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.3162161847
Short name T1112
Test name
Test status
Simulation time 749229047 ps
CPU time 15.68 seconds
Started Jul 29 07:47:55 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 241752 kb
Host smart-16348bd8-d207-464b-a6ce-f765487fdbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162161847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.3162161847
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.3842159367
Short name T1026
Test name
Test status
Simulation time 202183093 ps
CPU time 3.35 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 242148 kb
Host smart-e53a838f-192b-4cf5-a5ad-9aecbfaa5052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842159367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3842159367
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.97859045
Short name T771
Test name
Test status
Simulation time 216035448 ps
CPU time 4.76 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 242400 kb
Host smart-f256e538-6dab-4aab-888f-9ebb0def92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97859045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.97859045
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.1609914611
Short name T362
Test name
Test status
Simulation time 211354772410 ps
CPU time 1669.35 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 08:15:43 PM PDT 24
Peak memory 476212 kb
Host smart-e5c5880a-1573-466d-86cb-04992d79d72d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609914611 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.1609914611
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.2178176719
Short name T88
Test name
Test status
Simulation time 2101126489 ps
CPU time 4.55 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 242348 kb
Host smart-29a06602-cada-4687-accb-b6f0af177ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178176719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2178176719
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1729525752
Short name T141
Test name
Test status
Simulation time 555846469 ps
CPU time 7.03 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 242332 kb
Host smart-dc9b7c80-7a58-4c55-aa67-c511d6ffcf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729525752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1729525752
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.1955447120
Short name T562
Test name
Test status
Simulation time 124739295 ps
CPU time 3.66 seconds
Started Jul 29 07:47:57 PM PDT 24
Finished Jul 29 07:48:01 PM PDT 24
Peak memory 242440 kb
Host smart-518b29bf-22d2-433d-aa97-32d1bba6d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955447120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1955447120
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1550324900
Short name T487
Test name
Test status
Simulation time 89510800 ps
CPU time 3.43 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 241864 kb
Host smart-19271401-fe94-482a-82b6-f5869451e564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550324900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1550324900
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3329728675
Short name T139
Test name
Test status
Simulation time 281207502589 ps
CPU time 535.36 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:56:49 PM PDT 24
Peak memory 257056 kb
Host smart-1313c3a0-ed60-42da-983d-13d72b1f30bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329728675 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3329728675
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1740875460
Short name T1092
Test name
Test status
Simulation time 87846282 ps
CPU time 1.48 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:40:52 PM PDT 24
Peak memory 240332 kb
Host smart-b9f718f6-ee1a-487b-99bb-ae3ce1413e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740875460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1740875460
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.4221384257
Short name T371
Test name
Test status
Simulation time 6394754403 ps
CPU time 41.58 seconds
Started Jul 29 07:40:57 PM PDT 24
Finished Jul 29 07:41:38 PM PDT 24
Peak memory 242816 kb
Host smart-ec505389-1162-473b-b682-bf5850e170d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221384257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.4221384257
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.182106031
Short name T44
Test name
Test status
Simulation time 6834464660 ps
CPU time 41.17 seconds
Started Jul 29 07:40:52 PM PDT 24
Finished Jul 29 07:41:33 PM PDT 24
Peak memory 244768 kb
Host smart-3a05908c-8538-4806-a15e-cbd38cce5c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182106031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.182106031
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1008261391
Short name T663
Test name
Test status
Simulation time 231733372 ps
CPU time 13.15 seconds
Started Jul 29 07:40:52 PM PDT 24
Finished Jul 29 07:41:06 PM PDT 24
Peak memory 242348 kb
Host smart-dfb45d16-a399-4e29-8dfa-526701721e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008261391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1008261391
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.521957936
Short name T878
Test name
Test status
Simulation time 349514380 ps
CPU time 8.02 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:40:59 PM PDT 24
Peak memory 242280 kb
Host smart-75e08cad-5e3b-48e3-8c7d-3c71ea40b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521957936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.521957936
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.670765488
Short name T513
Test name
Test status
Simulation time 352691184 ps
CPU time 4.5 seconds
Started Jul 29 07:40:58 PM PDT 24
Finished Jul 29 07:41:03 PM PDT 24
Peak memory 242112 kb
Host smart-e03761dc-b511-4e0f-bee5-7d4951b9b034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670765488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.670765488
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.507980871
Short name T703
Test name
Test status
Simulation time 179494593 ps
CPU time 4.36 seconds
Started Jul 29 07:40:52 PM PDT 24
Finished Jul 29 07:40:56 PM PDT 24
Peak memory 247160 kb
Host smart-ad6e8f10-cfd0-4c74-a78a-c4592408c2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507980871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.507980871
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.3816586345
Short name T806
Test name
Test status
Simulation time 2167036018 ps
CPU time 7.21 seconds
Started Jul 29 07:40:56 PM PDT 24
Finished Jul 29 07:41:03 PM PDT 24
Peak memory 242256 kb
Host smart-5de3a6a7-9fdd-41fc-af6d-a3249b7e42ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816586345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.3816586345
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.3043647933
Short name T688
Test name
Test status
Simulation time 321323173 ps
CPU time 3.55 seconds
Started Jul 29 07:40:50 PM PDT 24
Finished Jul 29 07:40:53 PM PDT 24
Peak memory 242108 kb
Host smart-fbac5855-5c27-4d6d-8eff-21a3d56e8f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043647933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3043647933
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.2473168681
Short name T479
Test name
Test status
Simulation time 467717460 ps
CPU time 13.04 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:41:04 PM PDT 24
Peak memory 241996 kb
Host smart-b0a1a395-c4d6-49d2-a530-d9a385592057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473168681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2473168681
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3614988242
Short name T357
Test name
Test status
Simulation time 1076999437 ps
CPU time 10.79 seconds
Started Jul 29 07:40:59 PM PDT 24
Finished Jul 29 07:41:10 PM PDT 24
Peak memory 242456 kb
Host smart-6f0a95f2-a5ae-45ee-bf59-93448542626d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614988242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3614988242
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.794577132
Short name T979
Test name
Test status
Simulation time 522950120 ps
CPU time 9.31 seconds
Started Jul 29 07:40:51 PM PDT 24
Finished Jul 29 07:41:01 PM PDT 24
Peak memory 242036 kb
Host smart-c58ca89b-8754-492b-8a39-582c72844d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794577132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.794577132
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.497445433
Short name T824
Test name
Test status
Simulation time 2127091608 ps
CPU time 44.45 seconds
Started Jul 29 07:40:58 PM PDT 24
Finished Jul 29 07:41:43 PM PDT 24
Peak memory 248684 kb
Host smart-bedb61f2-0065-4fd4-9f79-97c37194dca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497445433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.497445433
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3166225851
Short name T1183
Test name
Test status
Simulation time 70028047538 ps
CPU time 512.05 seconds
Started Jul 29 07:40:59 PM PDT 24
Finished Jul 29 07:49:31 PM PDT 24
Peak memory 281696 kb
Host smart-c26c177b-8f88-4c48-b103-fda25a5536b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166225851 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.3166225851
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.1902007356
Short name T894
Test name
Test status
Simulation time 2030269752 ps
CPU time 19.43 seconds
Started Jul 29 07:40:59 PM PDT 24
Finished Jul 29 07:41:19 PM PDT 24
Peak memory 242540 kb
Host smart-1039d67d-22aa-4b05-95c7-e242de1cd735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902007356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1902007356
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.674765612
Short name T1083
Test name
Test status
Simulation time 102122710 ps
CPU time 3.8 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 242248 kb
Host smart-f3ba4881-8ffa-4050-82b9-14a5151e7638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674765612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.674765612
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1382786371
Short name T860
Test name
Test status
Simulation time 329360154 ps
CPU time 14.9 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:48:05 PM PDT 24
Peak memory 241924 kb
Host smart-574a8d0a-37f4-4ecd-b59f-58ce74babc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382786371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1382786371
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2564083745
Short name T496
Test name
Test status
Simulation time 323332172307 ps
CPU time 625.95 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:58:17 PM PDT 24
Peak memory 326652 kb
Host smart-a30a3f27-6937-4be9-8fa1-f5800dfe6097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564083745 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.2564083745
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2653620780
Short name T1167
Test name
Test status
Simulation time 349419111 ps
CPU time 3.16 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 242312 kb
Host smart-ecd81c73-6597-48da-b68b-44f50b606945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653620780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2653620780
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3196895666
Short name T546
Test name
Test status
Simulation time 76269432621 ps
CPU time 645.18 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:58:36 PM PDT 24
Peak memory 263780 kb
Host smart-2761f1c3-1ae6-4dd7-83ab-69d2ff0b3539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196895666 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3196895666
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2553401090
Short name T795
Test name
Test status
Simulation time 184060519 ps
CPU time 4.56 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 241880 kb
Host smart-9ed4d4e5-1bf1-422d-a548-9a255c8ee227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553401090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2553401090
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3947963285
Short name T845
Test name
Test status
Simulation time 986821031 ps
CPU time 12.13 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:48:04 PM PDT 24
Peak memory 241812 kb
Host smart-39be0df8-1f02-400f-9b03-dd626a711a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947963285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3947963285
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.745610037
Short name T943
Test name
Test status
Simulation time 33198393877 ps
CPU time 721.31 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:59:52 PM PDT 24
Peak memory 296924 kb
Host smart-bf8bcc7c-8501-49fd-b95f-3f6899babc01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745610037 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.745610037
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2206969624
Short name T422
Test name
Test status
Simulation time 113560933 ps
CPU time 4.08 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 242272 kb
Host smart-9859d987-cb88-4d9d-9a9b-f0762c8273e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206969624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2206969624
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.1834769178
Short name T1169
Test name
Test status
Simulation time 597685222 ps
CPU time 7.95 seconds
Started Jul 29 07:47:51 PM PDT 24
Finished Jul 29 07:47:59 PM PDT 24
Peak memory 242044 kb
Host smart-52644143-64f1-4ab4-b56e-6bb57c3fb746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834769178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1834769178
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2046113924
Short name T1002
Test name
Test status
Simulation time 18368466422 ps
CPU time 519.66 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:56:33 PM PDT 24
Peak memory 314336 kb
Host smart-6496f791-5fb8-47f6-80ba-d42858b9bf28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046113924 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.2046113924
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.2739390145
Short name T134
Test name
Test status
Simulation time 192838753 ps
CPU time 3.86 seconds
Started Jul 29 07:47:52 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 242248 kb
Host smart-c105a116-90c6-44db-8c26-3a38b637181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739390145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2739390145
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1284601662
Short name T240
Test name
Test status
Simulation time 290756085 ps
CPU time 3.45 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 241932 kb
Host smart-b66b89fe-3ef7-4656-8b06-eba0775f9fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284601662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1284601662
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.3125644227
Short name T1129
Test name
Test status
Simulation time 234120230 ps
CPU time 3.4 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:47:54 PM PDT 24
Peak memory 242084 kb
Host smart-3a68a20f-9469-4112-aa04-46d682104016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125644227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3125644227
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1081334899
Short name T701
Test name
Test status
Simulation time 219851604 ps
CPU time 4.8 seconds
Started Jul 29 07:47:52 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 241916 kb
Host smart-2d2da33e-3526-4557-b452-7eff313bcaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081334899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1081334899
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.504892399
Short name T315
Test name
Test status
Simulation time 200596459119 ps
CPU time 1330 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 08:10:00 PM PDT 24
Peak memory 265188 kb
Host smart-7f5e4f42-7db2-43c6-93dc-2dd61912ca29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504892399 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.504892399
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.3599445248
Short name T658
Test name
Test status
Simulation time 135288523 ps
CPU time 3.62 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 241948 kb
Host smart-dd7fff02-4ca1-4ae4-84de-6227b231f1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599445248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3599445248
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2976587206
Short name T582
Test name
Test status
Simulation time 185763924 ps
CPU time 5.78 seconds
Started Jul 29 07:47:49 PM PDT 24
Finished Jul 29 07:47:55 PM PDT 24
Peak memory 242236 kb
Host smart-4c0ca927-9dd6-4030-beef-5a192b5d3264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976587206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2976587206
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.4240400426
Short name T391
Test name
Test status
Simulation time 326729377587 ps
CPU time 2577.35 seconds
Started Jul 29 07:47:49 PM PDT 24
Finished Jul 29 08:30:47 PM PDT 24
Peak memory 272328 kb
Host smart-ac261c70-0fc8-4054-8a77-9d242261e8d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240400426 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.4240400426
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.4011090697
Short name T793
Test name
Test status
Simulation time 201505377 ps
CPU time 4.51 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 241988 kb
Host smart-cba48d37-97c6-4251-90f2-bd52e773b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011090697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.4011090697
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.839932569
Short name T434
Test name
Test status
Simulation time 190151138 ps
CPU time 4.56 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:47:54 PM PDT 24
Peak memory 241940 kb
Host smart-2cc5503c-74ae-494d-b4ee-8f80b0b4effd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839932569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.839932569
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.2370051624
Short name T183
Test name
Test status
Simulation time 256220705 ps
CPU time 3.8 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 242068 kb
Host smart-373aa166-cd87-4aa2-b058-a1d614205d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370051624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2370051624
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1728665087
Short name T1136
Test name
Test status
Simulation time 471079917 ps
CPU time 15.96 seconds
Started Jul 29 07:47:57 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 241932 kb
Host smart-31ee33da-6391-44b8-94a4-8e0a2d81f21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728665087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1728665087
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.2756026970
Short name T255
Test name
Test status
Simulation time 270761205299 ps
CPU time 709.56 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:59:40 PM PDT 24
Peak memory 263544 kb
Host smart-ffe40693-3567-444b-8d72-3662f34d6b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756026970 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.2756026970
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.4102589668
Short name T917
Test name
Test status
Simulation time 1500544248 ps
CPU time 3.64 seconds
Started Jul 29 07:47:48 PM PDT 24
Finished Jul 29 07:47:52 PM PDT 24
Peak memory 241968 kb
Host smart-61527ace-69ba-4144-b4fd-990c723e50e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102589668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.4102589668
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2533646308
Short name T974
Test name
Test status
Simulation time 811854027 ps
CPU time 17.78 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 241836 kb
Host smart-c79a3fcb-16a4-46a3-8ba5-f735c4f1cf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533646308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2533646308
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.461132528
Short name T225
Test name
Test status
Simulation time 161463603342 ps
CPU time 1453.59 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 08:12:07 PM PDT 24
Peak memory 479160 kb
Host smart-4a33bfae-210e-456d-8e73-e049987b28a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461132528 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.461132528
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.2663615444
Short name T171
Test name
Test status
Simulation time 48726541 ps
CPU time 1.66 seconds
Started Jul 29 07:40:58 PM PDT 24
Finished Jul 29 07:41:00 PM PDT 24
Peak memory 240520 kb
Host smart-02665704-b0e8-4177-b539-ec309bbe2742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663615444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2663615444
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.1140482459
Short name T789
Test name
Test status
Simulation time 1349987272 ps
CPU time 25.85 seconds
Started Jul 29 07:40:57 PM PDT 24
Finished Jul 29 07:41:23 PM PDT 24
Peak memory 242256 kb
Host smart-f334916d-8f71-43d4-95e7-90db82fe97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140482459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1140482459
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.3707210289
Short name T117
Test name
Test status
Simulation time 1730427789 ps
CPU time 21.49 seconds
Started Jul 29 07:41:00 PM PDT 24
Finished Jul 29 07:41:21 PM PDT 24
Peak memory 244256 kb
Host smart-d751faf2-31d3-4db4-b1c0-e29f6c401291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707210289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3707210289
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2970891197
Short name T319
Test name
Test status
Simulation time 1421550024 ps
CPU time 19.78 seconds
Started Jul 29 07:40:57 PM PDT 24
Finished Jul 29 07:41:17 PM PDT 24
Peak memory 241964 kb
Host smart-482869e2-6cdb-475f-8743-3aeeebce1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970891197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2970891197
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.2066619777
Short name T106
Test name
Test status
Simulation time 1403540901 ps
CPU time 20.88 seconds
Started Jul 29 07:40:56 PM PDT 24
Finished Jul 29 07:41:17 PM PDT 24
Peak memory 242128 kb
Host smart-4f283af7-7cac-43bf-914d-0c554055c5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066619777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2066619777
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1849009160
Short name T72
Test name
Test status
Simulation time 2210503479 ps
CPU time 6.76 seconds
Started Jul 29 07:41:02 PM PDT 24
Finished Jul 29 07:41:08 PM PDT 24
Peak memory 242236 kb
Host smart-7bdaa3a1-b772-431b-82d6-2dbb4ef0cceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849009160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1849009160
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2783066542
Short name T336
Test name
Test status
Simulation time 704127873 ps
CPU time 12.2 seconds
Started Jul 29 07:40:56 PM PDT 24
Finished Jul 29 07:41:09 PM PDT 24
Peak memory 242516 kb
Host smart-ce4c8528-5299-4eb2-9046-5e88267c3bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783066542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2783066542
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.1590109216
Short name T769
Test name
Test status
Simulation time 717680994 ps
CPU time 16.39 seconds
Started Jul 29 07:41:02 PM PDT 24
Finished Jul 29 07:41:18 PM PDT 24
Peak memory 242188 kb
Host smart-2a2e222b-766d-4885-9462-8a5e2bcdd949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590109216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1590109216
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2407350126
Short name T246
Test name
Test status
Simulation time 9941706991 ps
CPU time 25.03 seconds
Started Jul 29 07:40:59 PM PDT 24
Finished Jul 29 07:41:24 PM PDT 24
Peak memory 242344 kb
Host smart-b42e9d5b-d8c9-49ed-b015-fb4f0bb34f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407350126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2407350126
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.169726094
Short name T235
Test name
Test status
Simulation time 666900810 ps
CPU time 17.98 seconds
Started Jul 29 07:40:59 PM PDT 24
Finished Jul 29 07:41:17 PM PDT 24
Peak memory 242116 kb
Host smart-d34e5a7c-8f30-4a16-982f-bcb9329709f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169726094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.169726094
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2291925342
Short name T1118
Test name
Test status
Simulation time 3722953262 ps
CPU time 7.77 seconds
Started Jul 29 07:40:56 PM PDT 24
Finished Jul 29 07:41:04 PM PDT 24
Peak memory 241908 kb
Host smart-e94312c4-98dc-4323-a361-04d8a11020b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291925342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2291925342
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1339816249
Short name T804
Test name
Test status
Simulation time 254792033 ps
CPU time 4.8 seconds
Started Jul 29 07:40:59 PM PDT 24
Finished Jul 29 07:41:04 PM PDT 24
Peak memory 242288 kb
Host smart-fead43f1-3af8-44e3-a259-a76e327d376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339816249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1339816249
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.1993154970
Short name T629
Test name
Test status
Simulation time 744528274 ps
CPU time 9.82 seconds
Started Jul 29 07:40:55 PM PDT 24
Finished Jul 29 07:41:06 PM PDT 24
Peak memory 242124 kb
Host smart-4888c0be-b18a-44a6-bf6c-1f83739d3ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993154970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
1993154970
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2516557620
Short name T132
Test name
Test status
Simulation time 156618186353 ps
CPU time 2121.47 seconds
Started Jul 29 07:40:57 PM PDT 24
Finished Jul 29 08:16:19 PM PDT 24
Peak memory 312824 kb
Host smart-0ce2c329-a0b3-414a-acda-e14107bf342d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516557620 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2516557620
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.150397440
Short name T1173
Test name
Test status
Simulation time 239808550 ps
CPU time 4.14 seconds
Started Jul 29 07:41:02 PM PDT 24
Finished Jul 29 07:41:06 PM PDT 24
Peak memory 241976 kb
Host smart-2a5897e7-431f-4db3-8b69-55f4e62a6e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150397440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.150397440
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3252064861
Short name T57
Test name
Test status
Simulation time 261082845 ps
CPU time 3.85 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:57 PM PDT 24
Peak memory 242176 kb
Host smart-5a843851-70e0-45fc-9385-600de9f2a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252064861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3252064861
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3306971801
Short name T460
Test name
Test status
Simulation time 1113313566 ps
CPU time 16.21 seconds
Started Jul 29 07:47:49 PM PDT 24
Finished Jul 29 07:48:05 PM PDT 24
Peak memory 242268 kb
Host smart-3746d9cd-4c9e-43e8-beb4-8b03e79c7f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306971801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3306971801
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3456968590
Short name T280
Test name
Test status
Simulation time 59132457802 ps
CPU time 1300.09 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 08:09:34 PM PDT 24
Peak memory 260912 kb
Host smart-8198e547-94f8-4f0b-a303-9d2f8d5c86b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456968590 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.3456968590
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.955709137
Short name T231
Test name
Test status
Simulation time 106497657 ps
CPU time 3.25 seconds
Started Jul 29 07:47:52 PM PDT 24
Finished Jul 29 07:47:56 PM PDT 24
Peak memory 241836 kb
Host smart-6cbe41f7-687a-4aaa-a787-e01c9f34c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955709137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.955709137
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.912293585
Short name T178
Test name
Test status
Simulation time 1109653091 ps
CPU time 22.81 seconds
Started Jul 29 07:47:57 PM PDT 24
Finished Jul 29 07:48:20 PM PDT 24
Peak memory 241804 kb
Host smart-720650d6-aac3-4b98-9e83-e1afa2c582dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912293585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.912293585
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.3821263140
Short name T14
Test name
Test status
Simulation time 30245813924 ps
CPU time 531.86 seconds
Started Jul 29 07:47:50 PM PDT 24
Finished Jul 29 07:56:42 PM PDT 24
Peak memory 303560 kb
Host smart-0941bc7d-1c91-44f8-902c-d7c1463547da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821263140 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.3821263140
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3826713950
Short name T1108
Test name
Test status
Simulation time 396747883 ps
CPU time 4.53 seconds
Started Jul 29 07:47:53 PM PDT 24
Finished Jul 29 07:47:58 PM PDT 24
Peak memory 242324 kb
Host smart-6ecc9c03-45d7-47a6-9163-388d3dd9263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826713950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3826713950
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.2235364744
Short name T600
Test name
Test status
Simulation time 262441264 ps
CPU time 15.58 seconds
Started Jul 29 07:47:54 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 241668 kb
Host smart-2764a561-fd02-4948-9b2e-e53998b7c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235364744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2235364744
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1674558083
Short name T537
Test name
Test status
Simulation time 118718790699 ps
CPU time 1639.61 seconds
Started Jul 29 07:47:49 PM PDT 24
Finished Jul 29 08:15:09 PM PDT 24
Peak memory 273336 kb
Host smart-98859ac1-0c05-48ff-ba09-23c853a28786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674558083 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1674558083
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.2746913981
Short name T1181
Test name
Test status
Simulation time 121922370 ps
CPU time 3.3 seconds
Started Jul 29 07:47:49 PM PDT 24
Finished Jul 29 07:47:53 PM PDT 24
Peak memory 242220 kb
Host smart-ba6ddd99-a7e0-49be-b9b7-a2d52569e4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746913981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2746913981
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3323196217
Short name T923
Test name
Test status
Simulation time 436179644 ps
CPU time 4.84 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:12 PM PDT 24
Peak memory 242076 kb
Host smart-fb24fa18-1c4e-46e3-ade2-244715a75399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323196217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3323196217
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.1751051047
Short name T1091
Test name
Test status
Simulation time 95618305593 ps
CPU time 586.81 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:57:51 PM PDT 24
Peak memory 258680 kb
Host smart-9d136041-5aa8-4efc-8e81-67044c01c96a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751051047 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.1751051047
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.2887769938
Short name T184
Test name
Test status
Simulation time 504592427 ps
CPU time 4.08 seconds
Started Jul 29 07:48:02 PM PDT 24
Finished Jul 29 07:48:06 PM PDT 24
Peak memory 241492 kb
Host smart-6ddaefca-15ee-4ef8-babd-d9956aac062a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887769938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2887769938
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1628749013
Short name T455
Test name
Test status
Simulation time 11660742582 ps
CPU time 29.5 seconds
Started Jul 29 07:48:03 PM PDT 24
Finished Jul 29 07:48:33 PM PDT 24
Peak memory 242336 kb
Host smart-b7ea61f4-c114-446a-bf4d-0659e9cb2cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628749013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1628749013
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1439691551
Short name T698
Test name
Test status
Simulation time 32015102378 ps
CPU time 814.63 seconds
Started Jul 29 07:47:59 PM PDT 24
Finished Jul 29 08:01:34 PM PDT 24
Peak memory 313888 kb
Host smart-111f5cc2-b58a-4934-a789-9ea3c44a6097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439691551 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1439691551
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.2974892672
Short name T485
Test name
Test status
Simulation time 436756185 ps
CPU time 4.02 seconds
Started Jul 29 07:47:59 PM PDT 24
Finished Jul 29 07:48:04 PM PDT 24
Peak memory 242364 kb
Host smart-29b740eb-326e-4667-b9df-d272110458f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974892672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2974892672
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2102051350
Short name T944
Test name
Test status
Simulation time 313216500 ps
CPU time 15.81 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:48:20 PM PDT 24
Peak memory 241952 kb
Host smart-206dd27c-8c75-4516-b8b4-e00d2ad2c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102051350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2102051350
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2631049913
Short name T1018
Test name
Test status
Simulation time 285001387 ps
CPU time 3.98 seconds
Started Jul 29 07:48:02 PM PDT 24
Finished Jul 29 07:48:06 PM PDT 24
Peak memory 241420 kb
Host smart-6ee25117-c99f-43e2-be86-cbd69a10b871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631049913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2631049913
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.770298671
Short name T1128
Test name
Test status
Simulation time 846048721 ps
CPU time 6.22 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:12 PM PDT 24
Peak memory 241928 kb
Host smart-9d3f541f-3bac-4f8d-b250-c02e770a63e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770298671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.770298671
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1123849675
Short name T253
Test name
Test status
Simulation time 199616075095 ps
CPU time 2176.56 seconds
Started Jul 29 07:48:02 PM PDT 24
Finished Jul 29 08:24:19 PM PDT 24
Peak memory 330936 kb
Host smart-6ac9e4bf-451e-43f7-a0cf-7e964ba2b59e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123849675 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1123849675
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1237081449
Short name T468
Test name
Test status
Simulation time 4357578532 ps
CPU time 18.17 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:24 PM PDT 24
Peak memory 242004 kb
Host smart-8b87548e-9304-4f00-b5f5-5c9c79b4c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237081449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1237081449
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.182641121
Short name T645
Test name
Test status
Simulation time 257097305 ps
CPU time 3.41 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 242292 kb
Host smart-a0f29f34-9989-4cf2-aa02-64e88c77cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182641121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.182641121
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3963533165
Short name T1016
Test name
Test status
Simulation time 167248983 ps
CPU time 4.5 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 241896 kb
Host smart-2c689cc2-ed61-4e7d-9a10-f6ba751b5966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963533165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3963533165
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1003302129
Short name T278
Test name
Test status
Simulation time 548283558756 ps
CPU time 1871.42 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 08:19:21 PM PDT 24
Peak memory 391632 kb
Host smart-bca499e2-ef76-4f39-8689-ec536bb4fd12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003302129 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.1003302129
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.926587863
Short name T697
Test name
Test status
Simulation time 203287705 ps
CPU time 3.89 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:09 PM PDT 24
Peak memory 242268 kb
Host smart-cb9ad9e7-5a61-4eb8-abb7-2fe3139b831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926587863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.926587863
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.2128757217
Short name T667
Test name
Test status
Simulation time 97735745 ps
CPU time 2.9 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:48:07 PM PDT 24
Peak memory 241844 kb
Host smart-28a84c6d-d382-4d96-8392-901ae9b074d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128757217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2128757217
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.3334960297
Short name T276
Test name
Test status
Simulation time 29072690866 ps
CPU time 581.53 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:57:46 PM PDT 24
Peak memory 256780 kb
Host smart-ef001def-03c6-40c2-a30d-021ab2c88dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334960297 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.3334960297
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.2568392918
Short name T170
Test name
Test status
Simulation time 90452593 ps
CPU time 1.82 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:08 PM PDT 24
Peak memory 240360 kb
Host smart-980e6b48-945b-4f0e-9198-3322a3f83487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568392918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.2568392918
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.757830378
Short name T839
Test name
Test status
Simulation time 388086212 ps
CPU time 6.94 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:13 PM PDT 24
Peak memory 242072 kb
Host smart-21686a95-1b52-4aef-9f38-cb120bf4a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757830378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.757830378
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.463842701
Short name T882
Test name
Test status
Simulation time 218415469 ps
CPU time 7.48 seconds
Started Jul 29 07:41:05 PM PDT 24
Finished Jul 29 07:41:12 PM PDT 24
Peak memory 242300 kb
Host smart-00e9308a-8087-4956-8a7d-0ef2483a28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463842701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.463842701
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1513571272
Short name T642
Test name
Test status
Simulation time 2102061372 ps
CPU time 22.58 seconds
Started Jul 29 07:41:07 PM PDT 24
Finished Jul 29 07:41:29 PM PDT 24
Peak memory 241964 kb
Host smart-dd51d504-9a42-4e46-bf99-7c154d9527ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513571272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1513571272
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.3289765387
Short name T1100
Test name
Test status
Simulation time 369780190 ps
CPU time 8.05 seconds
Started Jul 29 07:41:04 PM PDT 24
Finished Jul 29 07:41:12 PM PDT 24
Peak memory 242024 kb
Host smart-b37a3dc8-f734-4ab4-9026-4d74f697571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289765387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3289765387
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3150323190
Short name T879
Test name
Test status
Simulation time 2014169339 ps
CPU time 6.64 seconds
Started Jul 29 07:41:07 PM PDT 24
Finished Jul 29 07:41:13 PM PDT 24
Peak memory 242344 kb
Host smart-94925ca8-78b7-4527-aea9-f6067fac140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150323190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3150323190
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.3886629041
Short name T157
Test name
Test status
Simulation time 1304142682 ps
CPU time 17.26 seconds
Started Jul 29 07:41:05 PM PDT 24
Finished Jul 29 07:41:22 PM PDT 24
Peak memory 247372 kb
Host smart-46b05dfe-5744-4a5d-b9aa-afd018a6a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886629041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3886629041
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.928103935
Short name T734
Test name
Test status
Simulation time 482358180 ps
CPU time 18.57 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:25 PM PDT 24
Peak memory 242360 kb
Host smart-77e282c8-8e7c-4ae1-bafd-5ac54281a0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928103935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.928103935
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.4209885616
Short name T781
Test name
Test status
Simulation time 177336949 ps
CPU time 5.38 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 242184 kb
Host smart-8149d9d0-6b73-4cfe-ab4f-1368811ed005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209885616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.4209885616
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.4122595162
Short name T508
Test name
Test status
Simulation time 506444801 ps
CPU time 10.85 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:17 PM PDT 24
Peak memory 242248 kb
Host smart-f226b90c-2e48-4925-b827-5c834cfdd491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122595162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.4122595162
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.1089728217
Short name T1185
Test name
Test status
Simulation time 182869091 ps
CPU time 5.23 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 241968 kb
Host smart-7e924d8a-d959-4ae6-affc-d29b785f5898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089728217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1089728217
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3123095242
Short name T1151
Test name
Test status
Simulation time 1056025992943 ps
CPU time 2209.93 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 08:17:56 PM PDT 24
Peak memory 297448 kb
Host smart-db4cc962-c2b1-4937-a81b-b9f80b6990db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123095242 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3123095242
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.403539409
Short name T241
Test name
Test status
Simulation time 12910654893 ps
CPU time 24.3 seconds
Started Jul 29 07:41:05 PM PDT 24
Finished Jul 29 07:41:30 PM PDT 24
Peak memory 248616 kb
Host smart-9fb711a5-e89d-4687-9ecc-3e9fde2644f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403539409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.403539409
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3575045022
Short name T1117
Test name
Test status
Simulation time 136540007 ps
CPU time 3.75 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:09 PM PDT 24
Peak memory 242012 kb
Host smart-bf1edf76-ef9d-4db6-a46d-b6bb21acb035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575045022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3575045022
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.216520034
Short name T196
Test name
Test status
Simulation time 927543587 ps
CPU time 15.75 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:22 PM PDT 24
Peak memory 241844 kb
Host smart-c50e4de2-f753-4cd4-9898-74938dfa42c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216520034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.216520034
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.24386355
Short name T312
Test name
Test status
Simulation time 169071508133 ps
CPU time 1384.26 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 08:11:14 PM PDT 24
Peak memory 329496 kb
Host smart-f9788b4d-4289-4d7f-9a95-5a71f226a7b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386355 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.24386355
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.2432405805
Short name T33
Test name
Test status
Simulation time 124183537 ps
CPU time 4.77 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242228 kb
Host smart-2f43702f-9c9e-4ded-9d47-c630fec651fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432405805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2432405805
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.1716783287
Short name T980
Test name
Test status
Simulation time 235129954 ps
CPU time 5.89 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 241728 kb
Host smart-ee11e9bf-dc0b-48c4-8e50-e3a0e05a3d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716783287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1716783287
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.374768442
Short name T996
Test name
Test status
Simulation time 401665294 ps
CPU time 4.82 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242100 kb
Host smart-cd9f3a6b-97f8-41c5-a8be-581b63e5bbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374768442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.374768442
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.12451572
Short name T1007
Test name
Test status
Simulation time 119162598 ps
CPU time 5.09 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242000 kb
Host smart-4e9f941d-c4cc-4169-b89d-9dbff55b7bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12451572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.12451572
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.203393873
Short name T21
Test name
Test status
Simulation time 134114876817 ps
CPU time 1799.62 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 08:18:04 PM PDT 24
Peak memory 311564 kb
Host smart-065bad91-ab50-4201-9a6a-3d5edf5d9bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203393873 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.203393873
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.2535219350
Short name T194
Test name
Test status
Simulation time 190193329 ps
CPU time 4.87 seconds
Started Jul 29 07:48:08 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 241976 kb
Host smart-6e20531b-97eb-476a-a362-84bf60b98f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535219350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2535219350
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.929727958
Short name T403
Test name
Test status
Simulation time 401761788 ps
CPU time 10.08 seconds
Started Jul 29 07:48:03 PM PDT 24
Finished Jul 29 07:48:14 PM PDT 24
Peak memory 241792 kb
Host smart-139eae9e-7ac6-4f60-8b03-4572362c72fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929727958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.929727958
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1427341860
Short name T989
Test name
Test status
Simulation time 92166496985 ps
CPU time 577.65 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:57:42 PM PDT 24
Peak memory 314312 kb
Host smart-423dd990-1bb0-42ff-b37b-909de4d2f8f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427341860 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.1427341860
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.65704624
Short name T232
Test name
Test status
Simulation time 142579977 ps
CPU time 5.27 seconds
Started Jul 29 07:48:03 PM PDT 24
Finished Jul 29 07:48:08 PM PDT 24
Peak memory 241952 kb
Host smart-0a4f7328-0065-4b80-8bef-ba8d6bea36b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65704624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.65704624
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2464114750
Short name T491
Test name
Test status
Simulation time 219390519005 ps
CPU time 577.59 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:57:42 PM PDT 24
Peak memory 339112 kb
Host smart-abe30048-5a4b-47b8-ba5c-9aee21f68eeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464114750 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.2464114750
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.279122459
Short name T229
Test name
Test status
Simulation time 1641787466 ps
CPU time 4.92 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242408 kb
Host smart-17687262-8f84-46e0-9100-ea4a0759fcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279122459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.279122459
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1166981739
Short name T199
Test name
Test status
Simulation time 632350944 ps
CPU time 8.05 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:14 PM PDT 24
Peak memory 242284 kb
Host smart-f409f16e-1f36-4193-8b97-21594e9a8e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166981739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1166981739
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4053933979
Short name T309
Test name
Test status
Simulation time 85140504925 ps
CPU time 1655.13 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 08:15:41 PM PDT 24
Peak memory 363492 kb
Host smart-a0c471fb-955f-48b8-b7e6-cee0d27fad69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053933979 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.4053933979
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2479787596
Short name T1190
Test name
Test status
Simulation time 389095800 ps
CPU time 4.32 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 242156 kb
Host smart-e9339212-ab4c-454d-8b77-96a8504c94e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479787596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2479787596
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.1722344443
Short name T467
Test name
Test status
Simulation time 201867568 ps
CPU time 7.14 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:14 PM PDT 24
Peak memory 242204 kb
Host smart-1f132500-e0c9-4f6e-8a7e-442ea7a314f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722344443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1722344443
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.3059411855
Short name T388
Test name
Test status
Simulation time 22406402676 ps
CPU time 662.21 seconds
Started Jul 29 07:48:02 PM PDT 24
Finished Jul 29 07:59:04 PM PDT 24
Peak memory 258976 kb
Host smart-7bb772b8-62f3-4ae7-b592-6edee3913285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059411855 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.3059411855
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.1862656926
Short name T1045
Test name
Test status
Simulation time 550590768 ps
CPU time 4.24 seconds
Started Jul 29 07:48:02 PM PDT 24
Finished Jul 29 07:48:06 PM PDT 24
Peak memory 242140 kb
Host smart-450730fe-ba01-4f63-b153-cb3a4f38ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862656926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1862656926
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1357558874
Short name T1060
Test name
Test status
Simulation time 1651002323 ps
CPU time 5.78 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 241876 kb
Host smart-ab28be92-e2c9-426f-afc0-ca4bf98eac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357558874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1357558874
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.4143662515
Short name T748
Test name
Test status
Simulation time 555826623166 ps
CPU time 952.79 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 08:03:57 PM PDT 24
Peak memory 399972 kb
Host smart-107e601b-b657-45eb-8757-88b21987fcf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143662515 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.4143662515
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.2855275461
Short name T754
Test name
Test status
Simulation time 467049792 ps
CPU time 4.53 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 242132 kb
Host smart-93fc0068-121d-4c9e-9274-b822b97e200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855275461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2855275461
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3227499922
Short name T926
Test name
Test status
Simulation time 202000101 ps
CPU time 3.83 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:12 PM PDT 24
Peak memory 242352 kb
Host smart-0a3b2790-542f-4e3a-ade2-195a3264e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227499922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3227499922
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3133076659
Short name T310
Test name
Test status
Simulation time 63433679478 ps
CPU time 686.22 seconds
Started Jul 29 07:48:01 PM PDT 24
Finished Jul 29 07:59:27 PM PDT 24
Peak memory 256976 kb
Host smart-5b224347-fa7a-4b62-a847-42164bb6f898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133076659 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3133076659
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.2290287264
Short name T431
Test name
Test status
Simulation time 2112991305 ps
CPU time 3.97 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:09 PM PDT 24
Peak memory 242328 kb
Host smart-08755dce-aba1-4e8d-9054-640dd4dde7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290287264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2290287264
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3157195884
Short name T1115
Test name
Test status
Simulation time 451429415 ps
CPU time 6.86 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:14 PM PDT 24
Peak memory 242144 kb
Host smart-a477ed26-f6d8-4f68-85c8-e8deb0e8d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157195884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3157195884
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3652492873
Short name T149
Test name
Test status
Simulation time 126804603324 ps
CPU time 2575.02 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 08:30:59 PM PDT 24
Peak memory 284000 kb
Host smart-f7bb39b5-109f-45d0-97d1-784983a8122c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652492873 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3652492873
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.2389858871
Short name T103
Test name
Test status
Simulation time 803395879 ps
CPU time 2.01 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:13 PM PDT 24
Peak memory 240580 kb
Host smart-a6f5b1b4-aefc-4f45-8f5b-5525e12cab57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389858871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2389858871
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.2523558146
Short name T656
Test name
Test status
Simulation time 680754354 ps
CPU time 8.91 seconds
Started Jul 29 07:41:05 PM PDT 24
Finished Jul 29 07:41:14 PM PDT 24
Peak memory 242040 kb
Host smart-26850c2b-e414-4533-8581-2840aac0a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523558146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2523558146
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.122467167
Short name T58
Test name
Test status
Simulation time 5111157923 ps
CPU time 30.73 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:42 PM PDT 24
Peak memory 242080 kb
Host smart-b9bc48cc-44b9-4cc7-aab1-503fa36fdeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122467167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.122467167
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.967815544
Short name T849
Test name
Test status
Simulation time 660046979 ps
CPU time 13.54 seconds
Started Jul 29 07:41:13 PM PDT 24
Finished Jul 29 07:41:27 PM PDT 24
Peak memory 242056 kb
Host smart-0677108d-3fad-4157-b6aa-83c7b677f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967815544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.967815544
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2277166824
Short name T783
Test name
Test status
Simulation time 775334067 ps
CPU time 8.8 seconds
Started Jul 29 07:41:20 PM PDT 24
Finished Jul 29 07:41:29 PM PDT 24
Peak memory 242272 kb
Host smart-b129ef6d-80f3-4d16-943f-9851b3619a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277166824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2277166824
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1582391891
Short name T561
Test name
Test status
Simulation time 179883858 ps
CPU time 3.89 seconds
Started Jul 29 07:41:07 PM PDT 24
Finished Jul 29 07:41:11 PM PDT 24
Peak memory 241976 kb
Host smart-fb9965f7-713f-41b4-8c12-63b5aa550c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582391891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1582391891
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.1219768656
Short name T432
Test name
Test status
Simulation time 267186621 ps
CPU time 5.86 seconds
Started Jul 29 07:41:20 PM PDT 24
Finished Jul 29 07:41:26 PM PDT 24
Peak memory 242400 kb
Host smart-418eef6b-12f5-4076-abdd-4a456eab714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219768656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1219768656
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1688907864
Short name T375
Test name
Test status
Simulation time 2383317500 ps
CPU time 25.78 seconds
Started Jul 29 07:41:22 PM PDT 24
Finished Jul 29 07:41:48 PM PDT 24
Peak memory 242236 kb
Host smart-f5223376-7d1c-4dfe-80d7-684c623d1873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688907864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1688907864
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.2871638526
Short name T723
Test name
Test status
Simulation time 994015609 ps
CPU time 18.26 seconds
Started Jul 29 07:41:11 PM PDT 24
Finished Jul 29 07:41:30 PM PDT 24
Peak memory 241968 kb
Host smart-87262878-8c8a-41e5-91df-e42d1c0724a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871638526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2871638526
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2683677651
Short name T884
Test name
Test status
Simulation time 2970450776 ps
CPU time 27.27 seconds
Started Jul 29 07:41:13 PM PDT 24
Finished Jul 29 07:41:41 PM PDT 24
Peak memory 248676 kb
Host smart-3ec95ef7-9a1d-413e-898c-a5812159f4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683677651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2683677651
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.3679957766
Short name T353
Test name
Test status
Simulation time 599143796 ps
CPU time 5.5 seconds
Started Jul 29 07:41:12 PM PDT 24
Finished Jul 29 07:41:18 PM PDT 24
Peak memory 242368 kb
Host smart-da05e9bb-bfcd-4893-b594-35596fb2180f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679957766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3679957766
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3557136767
Short name T776
Test name
Test status
Simulation time 1430917077 ps
CPU time 13.98 seconds
Started Jul 29 07:41:06 PM PDT 24
Finished Jul 29 07:41:20 PM PDT 24
Peak memory 242148 kb
Host smart-579260de-f16b-4350-adad-661ce85a3112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557136767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3557136767
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.4259046590
Short name T1187
Test name
Test status
Simulation time 10619174021 ps
CPU time 104.25 seconds
Started Jul 29 07:41:21 PM PDT 24
Finished Jul 29 07:43:05 PM PDT 24
Peak memory 245512 kb
Host smart-5e80cd4c-596f-4119-b5a2-7c3b733089cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259046590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
4259046590
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3650393774
Short name T381
Test name
Test status
Simulation time 10712503601 ps
CPU time 182.48 seconds
Started Jul 29 07:41:21 PM PDT 24
Finished Jul 29 07:44:24 PM PDT 24
Peak memory 270820 kb
Host smart-e29b2978-bce7-4bb7-b222-fde4a1bc68f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650393774 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.3650393774
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1794617621
Short name T97
Test name
Test status
Simulation time 18516452212 ps
CPU time 36.45 seconds
Started Jul 29 07:41:13 PM PDT 24
Finished Jul 29 07:41:49 PM PDT 24
Peak memory 242976 kb
Host smart-f7f818a3-7b7f-4699-b1fb-c524ccc70bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794617621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1794617621
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.3372958528
Short name T830
Test name
Test status
Simulation time 1692842800 ps
CPU time 4.82 seconds
Started Jul 29 07:48:02 PM PDT 24
Finished Jul 29 07:48:07 PM PDT 24
Peak memory 242304 kb
Host smart-ac5d3d42-0efd-4779-8540-10c19c3d6979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372958528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3372958528
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3111460558
Short name T1055
Test name
Test status
Simulation time 453967824 ps
CPU time 5.54 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 242408 kb
Host smart-7c0f9863-63b3-4c0d-9210-7a96589de7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111460558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3111460558
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2847306516
Short name T285
Test name
Test status
Simulation time 337015094036 ps
CPU time 4524.83 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 09:03:30 PM PDT 24
Peak memory 299412 kb
Host smart-0779409c-575e-4f5f-9eaa-fae495ca00eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847306516 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.2847306516
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3144276075
Short name T674
Test name
Test status
Simulation time 202168341 ps
CPU time 4.74 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:12 PM PDT 24
Peak memory 242156 kb
Host smart-2fb53439-cad2-4cc3-a741-38906ba07d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144276075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3144276075
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.219438786
Short name T150
Test name
Test status
Simulation time 3440577957 ps
CPU time 7.72 seconds
Started Jul 29 07:48:06 PM PDT 24
Finished Jul 29 07:48:14 PM PDT 24
Peak memory 242004 kb
Host smart-7bd9bf1b-7c07-4c24-9397-069ce8d3edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219438786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.219438786
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2746283547
Short name T759
Test name
Test status
Simulation time 47935837225 ps
CPU time 1303.19 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 08:09:50 PM PDT 24
Peak memory 408112 kb
Host smart-d94b7f67-b687-40d6-98b5-8d360eb71c33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746283547 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2746283547
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2858338000
Short name T739
Test name
Test status
Simulation time 175785704 ps
CPU time 4.91 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:48:10 PM PDT 24
Peak memory 242260 kb
Host smart-8ffba068-8da0-4321-a467-062d261d8f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858338000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2858338000
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.424736110
Short name T699
Test name
Test status
Simulation time 175085084 ps
CPU time 4.38 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:11 PM PDT 24
Peak memory 241808 kb
Host smart-f7d05346-4a1b-4104-bff1-c54f5db722cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424736110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.424736110
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2168568122
Short name T1143
Test name
Test status
Simulation time 289404969922 ps
CPU time 2029.15 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 08:21:58 PM PDT 24
Peak memory 281540 kb
Host smart-2e0d1460-1d71-430a-9b0e-96574d76815e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168568122 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.2168568122
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1305389488
Short name T185
Test name
Test status
Simulation time 502208970 ps
CPU time 4.16 seconds
Started Jul 29 07:48:04 PM PDT 24
Finished Jul 29 07:48:09 PM PDT 24
Peak memory 242176 kb
Host smart-7fbbb6b9-95a6-4d89-91f9-73b2a55f4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305389488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1305389488
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.3190812714
Short name T510
Test name
Test status
Simulation time 6484770474 ps
CPU time 18.76 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 07:48:28 PM PDT 24
Peak memory 241936 kb
Host smart-0b777713-d3d9-4370-95fd-d7c90dc03bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190812714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3190812714
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.943195000
Short name T929
Test name
Test status
Simulation time 159294045721 ps
CPU time 397.58 seconds
Started Jul 29 07:48:05 PM PDT 24
Finished Jul 29 07:54:43 PM PDT 24
Peak memory 258408 kb
Host smart-c0af1bc5-6e15-4bce-ad67-3fd444cda248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943195000 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.943195000
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1300390246
Short name T49
Test name
Test status
Simulation time 2693564862 ps
CPU time 7.36 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 07:48:17 PM PDT 24
Peak memory 242276 kb
Host smart-fe2ef614-383a-41da-8b9e-391cc574dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300390246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1300390246
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.810221319
Short name T252
Test name
Test status
Simulation time 7215980321 ps
CPU time 17.07 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:37 PM PDT 24
Peak memory 241984 kb
Host smart-09e8b0bd-2566-460c-a6c8-d8111d1b6f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810221319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.810221319
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2985432059
Short name T563
Test name
Test status
Simulation time 138787502771 ps
CPU time 1540.79 seconds
Started Jul 29 07:48:17 PM PDT 24
Finished Jul 29 08:13:58 PM PDT 24
Peak memory 306212 kb
Host smart-8a87d9fe-0be6-4b71-85cd-8c31b6d7a4d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985432059 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2985432059
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1711328717
Short name T210
Test name
Test status
Simulation time 105406066 ps
CPU time 3.86 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 242272 kb
Host smart-07d98331-a256-4d01-9812-fd52c8f1bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711328717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1711328717
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.1829992156
Short name T540
Test name
Test status
Simulation time 603770419 ps
CPU time 4.81 seconds
Started Jul 29 07:48:07 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 241916 kb
Host smart-dcd2e995-beaa-4925-94f6-a60401b2d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829992156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1829992156
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1357853479
Short name T313
Test name
Test status
Simulation time 293874705441 ps
CPU time 459.38 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 07:55:49 PM PDT 24
Peak memory 256960 kb
Host smart-508ce5f4-53a2-45dc-8c3e-38326eff621a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357853479 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1357853479
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.3922697289
Short name T604
Test name
Test status
Simulation time 1833153667 ps
CPU time 4.03 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 242420 kb
Host smart-7cfd815e-8e9e-4d22-899d-57d945b9f8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922697289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3922697289
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.4199161218
Short name T684
Test name
Test status
Simulation time 527918916 ps
CPU time 5.42 seconds
Started Jul 29 07:48:08 PM PDT 24
Finished Jul 29 07:48:13 PM PDT 24
Peak memory 241872 kb
Host smart-9c99bbb2-9a5f-46e9-a66b-a94deb11f755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199161218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.4199161218
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.4025920746
Short name T389
Test name
Test status
Simulation time 83546980955 ps
CPU time 1277.67 seconds
Started Jul 29 07:48:16 PM PDT 24
Finished Jul 29 08:09:34 PM PDT 24
Peak memory 292524 kb
Host smart-6db6b4b9-d855-4cd7-9739-49f266c6e94e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025920746 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.4025920746
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.178643828
Short name T928
Test name
Test status
Simulation time 120297472 ps
CPU time 4.27 seconds
Started Jul 29 07:48:15 PM PDT 24
Finished Jul 29 07:48:20 PM PDT 24
Peak memory 241944 kb
Host smart-18df3d83-5ed3-42b5-a91a-58fc022fdcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178643828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.178643828
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.3782259544
Short name T419
Test name
Test status
Simulation time 168112547 ps
CPU time 5 seconds
Started Jul 29 07:48:18 PM PDT 24
Finished Jul 29 07:48:23 PM PDT 24
Peak memory 241964 kb
Host smart-c8bd3777-29ea-48a1-a4e1-10956f82f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782259544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3782259544
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3115692898
Short name T384
Test name
Test status
Simulation time 78577160845 ps
CPU time 1534.85 seconds
Started Jul 29 07:48:09 PM PDT 24
Finished Jul 29 08:13:44 PM PDT 24
Peak memory 530232 kb
Host smart-854a9fd4-5032-49b5-a041-031dbeef44a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115692898 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3115692898
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2484140870
Short name T1059
Test name
Test status
Simulation time 198201906 ps
CPU time 4.25 seconds
Started Jul 29 07:48:24 PM PDT 24
Finished Jul 29 07:48:29 PM PDT 24
Peak memory 242160 kb
Host smart-9ccb5662-1151-4db1-a971-854c0fdfd9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484140870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2484140870
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2164985596
Short name T778
Test name
Test status
Simulation time 716828057 ps
CPU time 21.58 seconds
Started Jul 29 07:48:19 PM PDT 24
Finished Jul 29 07:48:41 PM PDT 24
Peak memory 242504 kb
Host smart-4b5f44f4-5f86-45c5-a336-04737854e3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164985596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2164985596
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2473171163
Short name T905
Test name
Test status
Simulation time 309260888553 ps
CPU time 2913.58 seconds
Started Jul 29 07:48:08 PM PDT 24
Finished Jul 29 08:36:42 PM PDT 24
Peak memory 687024 kb
Host smart-af4646d5-4e2e-4a1f-8804-ac918c2d6a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473171163 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.2473171163
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.134231306
Short name T504
Test name
Test status
Simulation time 316758708 ps
CPU time 4.23 seconds
Started Jul 29 07:48:15 PM PDT 24
Finished Jul 29 07:48:19 PM PDT 24
Peak memory 242432 kb
Host smart-1a701045-1c6b-475d-a7fb-96a1bcffd7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134231306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.134231306
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3466683873
Short name T429
Test name
Test status
Simulation time 520197450 ps
CPU time 14.72 seconds
Started Jul 29 07:48:11 PM PDT 24
Finished Jul 29 07:48:25 PM PDT 24
Peak memory 242020 kb
Host smart-66bb5064-b891-481f-8643-3d3d3815e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466683873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3466683873
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3760499201
Short name T975
Test name
Test status
Simulation time 140150784675 ps
CPU time 1070.03 seconds
Started Jul 29 07:48:11 PM PDT 24
Finished Jul 29 08:06:01 PM PDT 24
Peak memory 350008 kb
Host smart-1ba3c47a-01be-4235-9ee3-ee3a50037069
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760499201 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.3760499201
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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