Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49849	1			T13	16		T9	654		T16	557
access_err	60721	1			T2	65		T3	40		T6	127
write_blank_err	407	1			T2	10		T8	2		T9	3
ecc_uncorr_err	66432	1			T2	46		T8	90		T9	1204
ecc_corr_err	1595	1			T2	1		T97	18		T50	23
no_err	95010	1			T2	59		T3	50		T6	110

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	862	1			T2	17		T8	5		T9	11
secret2	25581	1			T2	11		T3	10		T6	33
secret1	30692	1			T2	4		T3	10		T6	29
secret0	37802	1			T2	5		T3	8		T6	18
hw_cfg1	35076	1			T2	55		T3	11		T6	20
hw_cfg0	24912	1			T2	13		T3	8		T6	16
rot_creator_auth_state	21103	1			T2	21		T3	10		T6	24
rot_creator_auth_codesign	23296	1			T2	9		T3	15		T6	30
owner_sw_cfg	20941	1			T2	15		T3	1		T6	16
creator_sw_cfg	23304	1			T2	24		T6	28		T7	42
vendor_test	30445	1			T2	7		T3	17		T6	23

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3801	1			T16	124		T72	250		T98	257
fsm_err	secret1	6027	1			T206	234		T132	136		T133	144
fsm_err	secret0	3406	1			T129	69		T308	123		T131	186
fsm_err	hw_cfg1	3316	1			T9	106		T309	358		T130	71
fsm_err	hw_cfg0	5440	1			T16	433		T15	54		T18	21
fsm_err	rot_creator_auth_state	1955	1			T143	36		T310	200		T20	319
fsm_err	rot_creator_auth_codesign	4771	1			T13	16		T153	54		T226	161
fsm_err	owner_sw_cfg	2798	1			T9	548		T311	129		T312	109
fsm_err	creator_sw_cfg	5696	1			T97	35		T116	11		T313	401
fsm_err	vendor_test	12639	1			T65	391		T33	95		T15	202
access_err	life_cycle	862	1			T2	17		T8	5		T9	11
access_err	secret2	10888	1			T2	11		T3	9		T6	27
access_err	secret1	5208	1			T3	4		T6	24		T7	23
access_err	secret0	4309	1			T3	1		T6	12		T7	18
access_err	hw_cfg1	1233	1			T2	1		T6	6		T7	2
access_err	hw_cfg0	2074	1			T3	2		T6	4		T7	24
access_err	rot_creator_auth_state	5980	1			T2	9		T3	6		T6	6
access_err	rot_creator_auth_codesign	7896	1			T2	2		T3	7		T6	8
access_err	owner_sw_cfg	6946	1			T2	8		T6	13		T7	47
access_err	creator_sw_cfg	7816	1			T2	14		T6	17		T7	22
access_err	vendor_test	7509	1			T2	3		T3	11		T6	10
write_blank_err	secret2	15	1			T96	1		T306	1		T314	1
write_blank_err	secret1	26	1			T16	2		T14	1		T240	1
write_blank_err	secret0	54	1			T8	2		T9	2		T65	1
write_blank_err	hw_cfg1	70	1			T2	2		T16	1		T15	1
write_blank_err	hw_cfg0	14	1			T9	1		T218	1		T315	1
write_blank_err	rot_creator_auth_state	122	1			T2	5		T16	3		T306	2
write_blank_err	rot_creator_auth_codesign	37	1			T2	1		T16	2		T186	2
write_blank_err	owner_sw_cfg	30	1			T2	2		T306	1		T240	1
write_blank_err	creator_sw_cfg	17	1			T218	6		T316	1		T284	1
write_blank_err	vendor_test	22	1			T307	1		T18	1		T317	1
ecc_uncorr_err	secret2	5205	1			T96	252		T116	31		T306	85
ecc_uncorr_err	secret1	9329	1			T16	934		T97	41		T116	27
ecc_uncorr_err	secret0	20797	1			T8	90		T9	770		T65	606
ecc_uncorr_err	hw_cfg1	19157	1			T2	46		T16	387		T97	49
ecc_uncorr_err	hw_cfg0	4444	1			T9	434		T116	12		T198	122
ecc_uncorr_err	rot_creator_auth_state	4238	1			T97	49		T116	15		T198	66
ecc_uncorr_err	rot_creator_auth_codesign	967	1			T97	71		T153	55		T199	25
ecc_uncorr_err	owner_sw_cfg	1443	1			T198	220		T143	45		T197	33
ecc_uncorr_err	creator_sw_cfg	852	1			T142	47		T197	30		T285	31
ecc_corr_err	secret2	136	1			T33	8		T198	2		T27	1
ecc_corr_err	secret1	139	1			T97	3		T50	11		T116	1
ecc_corr_err	secret0	186	1			T97	5		T116	2		T33	1
ecc_corr_err	hw_cfg1	300	1			T2	1		T50	3		T116	5
ecc_corr_err	hw_cfg0	258	1			T97	2		T50	1		T116	1
ecc_corr_err	rot_creator_auth_state	117	1			T97	3		T116	1		T33	3
ecc_corr_err	rot_creator_auth_codesign	151	1			T97	2		T33	5		T70	3
ecc_corr_err	owner_sw_cfg	145	1			T70	11		T71	3		T198	1
ecc_corr_err	creator_sw_cfg	163	1			T97	3		T50	8		T116	2
no_err	secret2	5536	1			T3	1		T6	6		T7	4
no_err	secret1	9963	1			T2	4		T3	6		T6	5
no_err	secret0	9050	1			T2	5		T3	7		T6	6
no_err	hw_cfg1	11000	1			T2	5		T3	11		T6	14
no_err	hw_cfg0	12682	1			T2	13		T3	6		T6	12
no_err	rot_creator_auth_state	8691	1			T2	7		T3	4		T6	18
no_err	rot_creator_auth_codesign	9474	1			T2	6		T3	8		T6	22
no_err	owner_sw_cfg	9579	1			T2	5		T3	1		T6	3
no_err	creator_sw_cfg	8760	1			T2	10		T6	11		T7	20
no_err	vendor_test	10275	1			T2	4		T3	6		T6	13

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded