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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 9780 1 T1 7 T2 1 T3 3
true 16010 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10636 1 T1 7 T2 1 T3 3
true 16062 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T219 2 T387 2 T134 2
others[1] 88 1 T32 2 T36 2 T217 2
others[2] 94 1 T36 2 T94 2 T96 2
others[3] 86 1 T94 2 T58 2 T388 2
others[4] 78 1 T100 2 T219 2 T220 2
others[5] 102 1 T104 2 T126 2 T219 4
others[6] 78 1 T126 2 T184 2 T127 2
others[7] 104 1 T32 2 T37 2 T94 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T93 2 T94 2 T100 2
others[1] 58 1 T216 2 T217 2 T268 2
others[2] 90 1 T93 2 T104 2 T98 2
others[3] 70 1 T93 2 T216 2 T388 2
others[4] 90 1 T24 2 T127 2 T219 4
others[5] 84 1 T389 2 T220 2 T390 2
others[6] 94 1 T25 4 T63 2 T99 2
others[7] 76 1 T36 2 T216 2 T268 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T36 2 T58 2 T128 2
others[1] 80 1 T96 2 T98 4 T184 2
others[2] 98 1 T104 4 T128 2 T391 2
others[3] 86 1 T36 2 T95 2 T100 4
others[4] 66 1 T387 2 T392 2 T26 2
others[5] 94 1 T25 2 T36 2 T93 2
others[6] 86 1 T25 2 T219 2 T220 2
others[7] 94 1 T93 2 T132 2 T217 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 42 1 T389 6 T128 2 T134 2
others[1] 60 1 T104 2 T96 2 T100 2
others[2] 66 1 T25 2 T185 2 T388 2
others[3] 38 1 T393 2 T394 4 T395 2
others[4] 52 1 T37 2 T132 2 T128 2
others[5] 64 1 T95 2 T134 6 T260 2
others[6] 48 1 T388 2 T128 2 T134 2
others[7] 70 1 T184 2 T79 2 T268 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 82 1 T127 2 T71 2 T132 2
others[1] 98 1 T25 2 T95 2 T107 2
others[2] 80 1 T93 2 T96 2 T100 2
others[3] 90 1 T104 2 T134 6 T396 2
others[4] 82 1 T97 2 T216 4 T387 2
others[5] 74 1 T93 2 T219 2 T268 2
others[6] 92 1 T32 2 T37 2 T98 4
others[7] 110 1 T94 2 T216 2 T397 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 30 1 T99 2 T108 2 T398 2
others[1] 44 1 T93 2 T219 2 T220 2
others[2] 46 1 T287 2 T399 2 T28 2
others[3] 28 1 T219 4 T387 2 T400 2
others[4] 34 1 T99 2 T356 2 T121 2
others[5] 36 1 T24 2 T217 2 T387 2
others[6] 40 1 T216 2 T219 2 T220 2
others[7] 48 1 T127 2 T218 2 T255 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T25 4 T100 2 T185 2
others[1] 66 1 T220 2 T391 2 T268 2
others[2] 84 1 T97 2 T79 2 T217 2
others[3] 88 1 T4 2 T94 2 T98 2
others[4] 66 1 T98 2 T71 2 T388 2
others[5] 84 1 T37 2 T95 2 T97 2
others[6] 82 1 T96 2 T388 2 T268 2
others[7] 98 1 T24 2 T97 2 T98 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T104 2 T58 2 T79 2
others[1] 68 1 T25 2 T127 2 T71 2
others[2] 62 1 T24 2 T96 2 T98 2
others[3] 88 1 T24 2 T71 2 T388 2
others[4] 98 1 T36 2 T127 2 T389 2
others[5] 78 1 T104 2 T127 2 T216 2
others[6] 78 1 T217 2 T287 2 T260 2
others[7] 106 1 T126 2 T79 2 T217 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T388 2 T219 2 T255 2
others[1] 80 1 T25 2 T127 2 T391 2
others[2] 66 1 T79 2 T401 2 T130 4
others[3] 94 1 T219 2 T391 2 T387 2
others[4] 58 1 T25 2 T37 2 T93 2
others[5] 88 1 T95 2 T98 2 T127 2
others[6] 84 1 T24 2 T37 2 T217 2
others[7] 78 1 T97 2 T100 2 T268 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T25 2 T36 2 T96 2
others[1] 72 1 T97 2 T220 2 T402 2
others[2] 78 1 T37 2 T96 2 T389 2
others[3] 98 1 T93 4 T58 2 T100 2
others[4] 64 1 T104 2 T388 2 T219 4
others[5] 76 1 T37 2 T99 2 T71 2
others[6] 74 1 T96 2 T100 2 T217 2
others[7] 80 1 T132 2 T128 4 T403 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T24 2 T96 2 T404 2
others[1] 92 1 T25 2 T126 2 T96 2
others[2] 90 1 T36 2 T37 2 T104 2
others[3] 96 1 T94 2 T104 2 T219 2
others[4] 88 1 T98 2 T132 2 T405 2
others[5] 88 1 T97 2 T217 2 T219 2
others[6] 94 1 T25 2 T388 2 T220 2
others[7] 88 1 T32 2 T25 2 T98 2
false 13619 1 T1 8 T2 1 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 18 1 T11 1 T258 1 T256 1
others[1] 34 1 T12 1 T138 1 T148 1
others[2] 32 1 T12 1 T222 1 T219 2
others[3] 33 1 T9 1 T12 2 T222 1
others[4] 43 1 T8 1 T12 2 T110 1
others[5] 27 1 T9 1 T12 2 T222 3
others[6] 30 1 T11 1 T12 2 T256 1
others[7] 30 1 T392 2 T258 1 T256 2
false 13619 1 T1 8 T2 1 T3 4
true 2234 1 T7 1 T4 1 T8 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T9 1 T12 1 T110 1
others[1] 29 1 T12 1 T222 1 T406 2
others[2] 24 1 T12 1 T242 1 T222 1
others[3] 29 1 T11 1 T12 2 T258 1
others[4] 36 1 T12 3 T138 2 T242 1
others[5] 37 1 T8 1 T9 1 T11 1
others[6] 29 1 T12 1 T222 1 T360 1
others[7] 35 1 T222 1 T360 1 T256 1
false 11100 1 T1 7 T2 1 T3 4
true 18232 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T37 2 T128 2 T255 2
others[1] 80 1 T104 2 T97 4 T389 2
others[2] 102 1 T36 2 T94 2 T104 2
others[3] 96 1 T32 2 T58 2 T184 2
others[4] 88 1 T32 2 T36 2 T94 2
others[5] 74 1 T126 2 T217 2 T219 4
others[6] 96 1 T94 2 T58 2 T96 2
others[7] 96 1 T126 2 T388 2 T219 2
false 7620 1 T1 7 T2 1 T3 4
true 16126 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T25 2 T217 2 T128 2
others[1] 70 1 T36 2 T93 2 T219 2
others[2] 86 1 T104 2 T100 2 T216 2
others[3] 88 1 T93 2 T63 2 T99 2
others[4] 84 1 T24 2 T25 2 T216 2
others[5] 62 1 T94 2 T389 2 T391 2
others[6] 72 1 T98 2 T216 2 T388 2
others[7] 110 1 T93 2 T127 2 T217 2
false 6854 1 T1 7 T2 1 T3 3
true 15900 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T36 2 T71 2 T391 4
others[1] 80 1 T25 2 T104 2 T100 4
others[2] 72 1 T96 2 T98 2 T219 2
others[3] 120 1 T36 2 T93 2 T104 2
others[4] 78 1 T36 2 T217 2 T219 2
others[5] 54 1 T93 2 T95 2 T391 2
others[6] 82 1 T58 2 T219 4 T392 2
others[7] 98 1 T25 2 T96 2 T98 2
false 7150 1 T1 7 T2 1 T3 3
true 15900 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T12 1 T138 2 T242 1
others[1] 30 1 T9 1 T10 1 T126 2
others[2] 40 1 T8 1 T138 2 T148 1
others[3] 36 1 T9 1 T216 2 T132 2
others[4] 39 1 T8 1 T222 1 T360 1
others[5] 27 1 T12 1 T219 2 T406 1
others[6] 43 1 T11 1 T12 2 T110 1
others[7] 29 1 T9 2 T10 1 T97 2
false 11033 1 T1 7 T2 1 T3 4
true 18176 1 T1 11 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 50 1 T184 2 T128 2 T268 2
others[1] 50 1 T25 2 T100 2 T79 2
others[2] 50 1 T388 2 T389 2 T402 2
others[3] 42 1 T37 2 T134 2 T130 2
others[4] 50 1 T389 2 T134 2 T393 2
others[5] 60 1 T96 2 T130 4 T121 2
others[6] 68 1 T95 2 T128 4 T59 2
others[7] 70 1 T104 2 T132 2 T388 2
false 8761 1 T1 7 T2 1 T3 4
true 16108 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 25 1 T8 1 T12 2 T138 2
others[1] 28 1 T7 2 T9 1 T242 1
others[2] 40 1 T9 1 T11 1 T12 1
others[3] 29 1 T8 1 T12 1 T138 1
others[4] 38 1 T8 1 T9 1 T10 2
others[5] 33 1 T12 2 T138 1 T98 2
others[6] 26 1 T12 1 T242 1 T258 1
others[7] 58 1 T11 1 T12 2 T138 1
false 10979 1 T1 7 T2 1 T3 4
true 18108 1 T1 11 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 62 1 T104 2 T97 2 T401 2
others[1] 80 1 T397 2 T268 2 T402 2
others[2] 114 1 T32 2 T93 2 T58 2
others[3] 90 1 T100 2 T407 2 T130 2
others[4] 72 1 T95 2 T219 2 T391 2
others[5] 86 1 T127 2 T71 2 T219 2
others[6] 92 1 T96 2 T98 2 T216 6
others[7] 112 1 T25 2 T37 2 T93 2
false 7555 1 T1 7 T2 1 T3 4
true 16045 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T71 2 T222 1 T352 1
others[1] 22 1 T8 1 T12 1 T138 2
others[2] 22 1 T8 1 T12 1 T138 1
others[3] 38 1 T11 1 T148 1 T360 1
others[4] 41 1 T8 1 T9 1 T10 1
others[5] 30 1 T10 1 T360 1 T256 1
others[6] 33 1 T8 2 T9 1 T12 1
others[7] 48 1 T9 1 T12 2 T140 2
false 10932 1 T1 7 T2 1 T3 4
true 18133 1 T1 11 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 48 1 T93 2 T219 2 T108 2
others[1] 26 1 T219 2 T121 2 T408 2
others[2] 42 1 T99 2 T219 2 T268 2
others[3] 38 1 T99 2 T127 2 T255 4
others[4] 46 1 T216 2 T219 2 T400 2
others[5] 56 1 T218 2 T387 2 T130 2
others[6] 22 1 T217 2 T387 2 T409 2
others[7] 28 1 T24 2 T220 4 T410 2
false 9491 1 T1 7 T2 1 T3 4
true 16091 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T96 2 T97 2 T99 2
others[1] 90 1 T25 2 T97 2 T98 2
others[2] 74 1 T25 2 T98 2 T220 2
others[3] 90 1 T24 2 T95 2 T71 2
others[4] 70 1 T4 2 T37 2 T100 2
others[5] 88 1 T71 2 T217 2 T402 2
others[6] 58 1 T108 2 T268 2 T390 2
others[7] 88 1 T94 2 T97 2 T98 2
false 6972 1 T1 7 T2 1 T3 3
true 15905 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T71 2 T401 2 T411 2
others[1] 78 1 T25 2 T127 2 T108 2
others[2] 84 1 T24 2 T216 2 T388 2
others[3] 86 1 T104 2 T58 2 T79 2
others[4] 72 1 T127 2 T389 2 T387 2
others[5] 72 1 T24 2 T36 2 T126 2
others[6] 74 1 T127 2 T219 2 T108 2
others[7] 106 1 T104 2 T96 2 T98 2
false 6972 1 T1 7 T2 1 T3 3
true 15905 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T98 2 T100 2 T132 2
others[1] 76 1 T93 2 T220 2 T403 2
others[2] 90 1 T25 2 T37 2 T97 2
others[3] 82 1 T37 2 T217 2 T219 8
others[4] 66 1 T127 2 T391 2 T412 2
others[5] 66 1 T25 2 T388 2 T255 2
others[6] 84 1 T95 2 T79 2 T391 2
others[7] 82 1 T24 2 T127 2 T132 2
false 6324 1 T1 7 T2 1 T3 2
true 15888 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T104 2 T389 2 T403 2
others[1] 68 1 T37 2 T217 2 T388 2
others[2] 80 1 T93 2 T97 2 T388 2
others[3] 110 1 T96 2 T128 2 T255 2
others[4] 70 1 T97 2 T99 2 T100 2
others[5] 66 1 T36 2 T71 2 T132 4
others[6] 90 1 T25 2 T93 2 T96 4
others[7] 90 1 T37 2 T58 2 T219 4
false 6324 1 T1 7 T2 1 T3 2
true 15888 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T36 2 T93 2 T126 2
others[1] 44 1 T219 2 T268 2 T411 2
others[2] 42 1 T130 2 T400 2 T413 2
others[3] 68 1 T98 2 T127 2 T79 2
others[4] 76 1 T36 2 T96 2 T98 2
others[5] 54 1 T104 4 T97 2 T389 4
others[6] 58 1 T100 2 T216 2 T219 2
others[7] 62 1 T93 2 T100 2 T184 2
false 6735 1 T1 6 T2 1 T3 2
true 17208 1 T1 11 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 46 1 T96 2 T98 2 T108 2
others[1] 84 1 T94 2 T97 2 T127 4
others[2] 50 1 T36 2 T391 2 T402 2
others[3] 54 1 T37 2 T216 2 T219 2
others[4] 62 1 T36 4 T108 2 T402 2
others[5] 68 1 T93 2 T387 2 T411 2
others[6] 50 1 T97 2 T219 2 T268 2
others[7] 72 1 T126 2 T97 2 T100 2
false 6735 1 T1 6 T2 1 T3 2
true 17208 1 T1 11 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 46 1 T12 2 T222 1 T352 1
others[1] 29 1 T8 2 T9 1 T110 2
others[2] 25 1 T12 1 T138 1 T219 2
others[3] 30 1 T9 1 T222 1 T360 1
others[4] 39 1 T103 2 T9 1 T12 1
others[5] 41 1 T8 1 T9 1 T93 2
others[6] 35 1 T7 2 T242 1 T360 1
others[7] 37 1 T138 1 T242 1 T256 1
false 11173 1 T1 7 T2 1 T3 4
true 18316 1 T1 11 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T32 2 T36 2 T96 2
others[1] 90 1 T94 2 T97 2 T217 2
others[2] 70 1 T24 2 T25 2 T132 2
others[3] 88 1 T127 2 T219 2 T130 4
others[4] 104 1 T25 2 T104 2 T388 2
others[5] 82 1 T25 2 T96 2 T98 2
others[6] 76 1 T37 2 T126 2 T217 2
others[7] 96 1 T104 2 T98 2 T219 2
false 7595 1 T1 7 T2 1 T3 4
true 16093 1 T1 10 T2 1 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 39 1 T10 1 T12 1 T97 2
others[1] 34 1 T8 1 T12 1 T258 3
others[2] 25 1 T9 2 T138 1 T148 1
others[3] 45 1 T9 1 T138 1 T71 2
others[4] 37 1 T9 1 T12 1 T71 2
others[5] 24 1 T11 1 T12 2 T138 2
others[6] 38 1 T10 1 T126 2 T12 2
others[7] 38 1 T8 1 T12 1 T222 1
false 13619 1 T1 8 T2 1 T3 4
true 2224 1 T1 1 T6 1 T7 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%