Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49601	1			T1	29		T3	276		T7	104
access_err	62455	1			T1	9		T6	6		T7	7
write_blank_err	490	1			T1	6		T8	1		T18	6
ecc_uncorr_err	64085	1			T1	457		T17	266		T8	570
ecc_corr_err	1284	1			T17	3		T101	12		T103	3
no_err	90734	1			T1	117		T6	28		T7	14

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	721	1			T1	4		T18	6		T19	8
secret2	27786	1			T1	11		T6	3		T4	11
secret1	28674	1			T1	8		T7	107		T4	11
secret0	32692	1			T1	10		T6	2		T4	9
hw_cfg1	35609	1			T1	19		T4	8		T5	5
hw_cfg0	28013	1			T1	49		T6	8		T7	2
rot_creator_auth_state	20259	1			T1	469		T7	3		T4	13
rot_creator_auth_codesign	21563	1			T1	12		T6	7		T4	12
owner_sw_cfg	21122	1			T1	10		T6	3		T7	3
creator_sw_cfg	20636	1			T1	23		T3	276		T6	6
vendor_test	31574	1			T1	3		T6	5		T7	6

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	7126	1			T349	285		T222	83		T249	200
fsm_err	secret1	2719	1			T7	104		T197	51		T219	123
fsm_err	secret0	3127	1			T110	319		T197	54		T357	327
fsm_err	hw_cfg1	3494	1			T186	58		T11	46		T212	15
fsm_err	hw_cfg0	6063	1			T1	29		T9	129		T222	110
fsm_err	rot_creator_auth_state	2637	1			T103	34		T253	525		T12	58
fsm_err	rot_creator_auth_codesign	3649	1			T269	113		T196	61		T358	176
fsm_err	owner_sw_cfg	3024	1			T150	2		T140	60		T197	58
fsm_err	creator_sw_cfg	3250	1			T3	276		T17	71		T88	161
fsm_err	vendor_test	14512	1			T8	25		T73	6		T103	81
access_err	life_cycle	721	1			T1	4		T18	6		T19	8
access_err	secret2	10732	1			T6	3		T4	8		T8	16
access_err	secret1	5854	1			T8	2		T32	7		T24	3
access_err	secret0	4834	1			T1	1		T4	5		T25	19
access_err	hw_cfg1	1202	1			T1	1		T4	5		T8	3
access_err	hw_cfg0	2035	1			T4	2		T8	2		T32	1
access_err	rot_creator_auth_state	6056	1			T4	4		T8	23		T32	6
access_err	rot_creator_auth_codesign	7865	1			T1	3		T4	1		T8	17
access_err	owner_sw_cfg	7334	1			T6	1		T7	2		T4	6
access_err	creator_sw_cfg	8068	1			T7	1		T4	6		T8	20
access_err	vendor_test	7754	1			T6	2		T7	4		T4	3
write_blank_err	secret2	9	1			T8	1		T201	1		T352	1
write_blank_err	secret1	28	1			T19	1		T10	1		T247	1
write_blank_err	secret0	48	1			T91	1		T359	1		T242	1
write_blank_err	hw_cfg1	77	1			T18	2		T10	1		T90	1
write_blank_err	hw_cfg0	22	1			T360	1		T268	1		T361	1
write_blank_err	rot_creator_auth_state	170	1			T1	5		T18	4		T19	1
write_blank_err	rot_creator_auth_codesign	62	1			T1	1		T10	3		T11	3
write_blank_err	owner_sw_cfg	20	1			T11	1		T148	1		T258	6
write_blank_err	creator_sw_cfg	15	1			T361	3		T130	1		T160	1
write_blank_err	vendor_test	39	1			T91	1		T242	1		T268	1
ecc_uncorr_err	secret2	4420	1			T8	570		T101	34		T145	59
ecc_uncorr_err	secret1	10917	1			T19	62		T10	573		T202	24
ecc_uncorr_err	secret0	15945	1			T101	49		T103	77		T91	431
ecc_uncorr_err	hw_cfg1	19710	1			T17	66		T18	584		T10	146
ecc_uncorr_err	hw_cfg0	6985	1			T103	84		T360	665		T198	20
ecc_uncorr_err	rot_creator_auth_state	2776	1			T1	457		T17	68		T11	263
ecc_uncorr_err	rot_creator_auth_codesign	981	1			T17	68		T11	314		T150	5
ecc_uncorr_err	owner_sw_cfg	1576	1			T17	64		T103	39		T202	40
ecc_uncorr_err	creator_sw_cfg	775	1			T140	64		T180	24		T198	9
ecc_corr_err	secret2	54	1			T101	2		T58	5		T79	1
ecc_corr_err	secret1	110	1			T101	3		T63	3		T58	3
ecc_corr_err	secret0	122	1			T101	1		T63	2		T58	6
ecc_corr_err	hw_cfg1	288	1			T17	3		T18	1		T63	2
ecc_corr_err	hw_cfg0	234	1			T101	3		T103	2		T63	2
ecc_corr_err	rot_creator_auth_state	132	1			T103	1		T11	2		T187	2
ecc_corr_err	rot_creator_auth_codesign	88	1			T101	3		T58	4		T187	1
ecc_corr_err	owner_sw_cfg	123	1			T63	9		T187	4		T148	2
ecc_corr_err	creator_sw_cfg	133	1			T63	3		T58	7		T79	5
no_err	secret2	5445	1			T1	11		T4	3		T5	9
no_err	secret1	9046	1			T1	8		T7	3		T4	11
no_err	secret0	8616	1			T1	9		T6	2		T4	4
no_err	hw_cfg1	10838	1			T1	18		T4	3		T5	5
no_err	hw_cfg0	12674	1			T1	20		T6	8		T7	2
no_err	rot_creator_auth_state	8488	1			T1	7		T7	3		T4	9
no_err	rot_creator_auth_codesign	8918	1			T1	8		T6	7		T4	11
no_err	owner_sw_cfg	9045	1			T1	10		T6	2		T7	1
no_err	creator_sw_cfg	8395	1			T1	23		T6	6		T7	3
no_err	vendor_test	9269	1			T1	3		T6	3		T7	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded