Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

178776

1

T1

27

T2

553

T3

73

all_values[1]

178776

1

T1

27

T2

553

T3

73

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223770

1

T2

1105

T4

136

T5

383

auto[1]

133782

1

T1

54

T2

1

T3

146

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187535

1

T1

21

T2

652

T3

73

auto[1]

170017

1

T1

33

T2

454

T3

73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	37513	1			T2	226		T5	43		T7	77
all_values[0]	auto[0]	auto[1]	77495	1			T2	327		T5	145		T7	7
all_values[0]	auto[1]	auto[0]	19670	1			T4	175		T5	10		T7	67
all_values[0]	auto[1]	auto[1]	44098	1			T1	27		T3	73		T4	9
all_values[1]	auto[0]	auto[0]	77146	1			T2	425		T4	129		T5	180
all_values[1]	auto[0]	auto[1]	31616	1			T2	127		T4	7		T5	15
all_values[1]	auto[1]	auto[0]	53206	1			T1	21		T2	1		T3	73
all_values[1]	auto[1]	auto[1]	16808	1			T1	6		T4	1		T5	2